LT3070-1 5A, Low Noise, Programmable Output, 85mV Dropout Linear Regulator FEATURES DESCRIPTION Output Current: 5A Dropout Voltage: 85mV Typical nn Enable Function Soft-Starts the Reference nn Digitally Programmable V OUT : 0.8V to 1.8V nn Digital Output Margining: 1%, 3% or 5% nn Low Output Noise: 25V RMS (10Hz to 100kHz) nn Parallel Multiple Devices for 10A or More nn Precision Current Limit: 20% nn 1% Accuracy Over Line, Load and Temperature nn Stable with Low ESR Ceramic Output Capacitors (15F Minimum) nn High Frequency PSRR: 30dB at 1MHz nn VIOC Pin Controls Buck Converter to Maintain Low Power Dissipation and Optimize Efficiency nn PWRGD/UVLO/Thermal Shutdown Flag nn Current Limit with Foldback Protection nn Thermal Shutdown nn 28-Lead (4mm x 5mm x 0.75mm) QFN Package The LT(R)3070-1 is a low voltage, UltraFastTM transient response linear regulator. The device supplies up to 5A of output current with a typical dropout voltage of 85mV. A 0.01F reference bypass capacitor decreases output voltage noise to 25VRMS. The LT3070-1 EN pin controls the reference soft-start behavior in comparison to the LT3070 which controls the reference soft-start via the BIAS pin supply voltage. The LT3070-1's high bandwidth permits the use of low ESR ceramic capacitors, saving bulk capacitance and cost. The LT3070-1's features make it ideal for high performance FPGAs, microprocessors or sensitive communication supply applications. nn nn APPLICATIONS Output voltage is digitally selectable in 50mV increments over a 0.8V to 1.8V range. A margining function allows the user to adjust system output voltage in increments of 1%, 3% or 5%. The IC incorporates a unique tracking function to control a buck regulator powering the LT30701's input. This tracking function drives the buck regulator to maintain the LT3070-1's input voltage to VOUT + 300mV, minimizing power dissipation. FPGA and DSP Supplies ASIC and Microprocessor Supplies nn Servers and Storage Devices nn Post Buck Regulation and Supply Isolation Internal protection includes UVLO, reverse-current protection, precision current limiting with power foldback and thermal shutdown. The LT3070-1 regulator is available in a thermally enhanced 28-lead, 4mm x 5mm QFN package. nn nn All registered trademarks and trademarks are the property of their respective owners. TYPICAL APPLICATION Dropout Voltage 0.9V, 5A Regulator 50k VIN 1.2V PWRGD 2.2F IN 330F BIAS EN VO0 VO1 PWRGD SENSE LT3070-1 OUT VO2 2.2F* 4.7F* VOUT 0.9V 10F* 5A *X5R OR X7R CAPACITORS MARGSEL MARGTOL VIOC 1nF REF/BYP GND 0.01F 3070-1 TA01a DROPOUT VOLTAGE (mV) VBIAS 2.2V TO 3.6V 150 VIN = VOUT(NOMINAL) 120 90 VOUT = 1.8V VBIAS = 3.3V 60 VOUT = 0.8V VBIAS = 2.5V 30 0 0 1 3 4 5 2 OUTPUT CURRENT (A) 3070-1 TA01b Rev 0 Document Feedback For more information www.analog.com 1 LT3070-1 PIN CONFIGURATION IN, OUT...................................................... -0.3V to 3.3V BIAS.............................................................. -0.3V to 4V VO2, VO1, VO0 Inputs..................................... -0.3V to 4V MARGSEL, MARGTOL Input......................... -0.3V to 4V EN Input........................................................ -0.3V to 4V SENSE Input.................................................. -0.3V to 4V VIOC, PWRGD Outputs................................. -0.3V to 4V REF/BYP Output............................................ -0.3V to 4V Output Short-Circuit Duration.........................Indefinite Operating Junction Temperature (Note 2) LT3070-1E/LT3070-1I......................... -40C to 125C LT3070-1MP....................................... -55C to 125C Storage Temperature Range................... -65C to 150C VO0 VO1 VO2 GND BIAS EN TOP VIEW 28 27 26 25 24 23 VIOC 1 22 MARGTOL PWRGD 2 21 MARGSEL REF/BYP 3 20 GND GND 4 19 SENSE 29 GND IN 5 18 OUT IN 6 17 OUT IN 7 16 OUT IN 8 15 OUT GND GND GND GND 9 10 11 12 13 14 GND (Note 1) GND ABSOLUTE MAXIMUM RATINGS UFD PACKAGE 28-LEAD (4mm x 5mm) PLASTIC QFN TJMAX = 125C, JA = 30C/W TO 35C/W EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT3070EUFD-1#PBF LT3070EUFD-1#TRPBF 30701 28-Lead (4mm x 5mm) Plastic QFN -40C to 125C LT3070IUFD-1#PBF LT3070IUFD-1#TRPBF 30701 28-Lead (4mm x 5mm) Plastic QFN -40C to 125C LT3070MPUFD-1#PBF LT3070MPUFD-1#TRPBF 30701 28-Lead (4mm x 5mm) Plastic QFN -55C to 125C LEAD BASED FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT3070EUFD-1 LT3070EUFD-1#TR 30701 28-Lead (4mm x 5mm) Plastic QFN -40C to 125C LT3070IUFD-1 LT3070IUFD-1#TR 30701 28-Lead (4mm x 5mm) Plastic QFN -40C to 125C LT3070MPUFD-1 LT3070MPUFD-1#TR 30701 28-Lead (4mm x 5mm) Plastic QFN -55C to 125C Consult ADI Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. Rev 0 2 For more information www.analog.com LT3070-1 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. COUT = 15F (Note 9), VIN = VOUT + 0.3V (Note 5), VBIAS = 2.5V unless otherwise noted. PARAMETER CONDITIONS MIN IN Pin Voltage Range VIN VOUT + 150mV, IOUT= 5A l TYP 0.95 2.2 UNITS 3.0 V 3.6 V Regulated Output Voltage VOUT = 0.8V, 10mA IOUT 5A, 1.05V VIN 1.25V VOUT = 0.9V, 10mA IOUT 5A, 1.15V VIN 1.35V VOUT = 1V, 10mA IOUT 5A, 1.25V VIN 1.45V VOUT = 1.1V, 10mA IOUT 5A, 1.35V VIN 1.55V VOUT = 1.2V, 10mA IOUT 5A, 1.45V VIN 1.65V, VBIAS = 3.3V VOUT = 1.5V, 10mA IOUT 5A, 1.75V VIN 1.95V, VBIAS = 3.3V VOUT = 1.8V, 10mA IOUT 5A, 2.05V VIN 2.25V, VBIAS = 3.3V l l l l l l l 0.792 0.891 0.990 1.089 1.188 1.485 1.782 0.800 0.900 1.000 1.100 1.200 1.500 1.800 0.808 0.909 1.010 1.111 1.212 1.515 1.818 V V V V V V V Regulated Output Voltage Margining (Note 3) MARGTOL = 0V, MARGSEL = VBIAS MARGTOL = 0V, MARGSEL = 0V, IOUT = 10mA l l 0.8 -1.2 1 -1 1.2 -0.8 % % MARGTOL = FLOAT, MARGSEL = VBIAS MARGTOL = FLOAT, MARGSEL = 0V, IOUT = 10mA l l 2.7 -3.3 3 -3 3.3 -2.7 % % MARGTOL = VBIAS, MARGSEL= VBIAS MARGTOL = VBIAS, MARGSEL = 0V, IOUT = 10mA l l 4.6 -5.4 5 -5 5.4 -4.6 % % Line Regulation to VIN VOUT = 0.8V, VIN = 1.05V to 2.7V, VBIAS = 3.3V, IOUT = 10mA VOUT = 1.8V, VIN = 2.05V to 2.7V, VBIAS = 3.3V, IOUT = 10mA l l 1.0 1.0 mV mV Line Regulation to VBIAS VOUT = 0.8V, VBIAS = 2.2V to 3.6V, VIN = 1.1V, IOUT = 10mA VOUT = 1.8V, VBIAS = 3.25V to 3.6V, VIN = 2.1V, IOUT = 10mA l l 2.0 1.0 mV mV Load Regulation, IOUT = 10mA to 5A VBIAS = 2.5V, VIN = 1.05V, VOUT = 0.8V -1.5 -3.0 -5.5 mV mV -2 -4.0 -7.5 mV mV -2 -4.0 -7.5 mV mV -2.5 -5.0 -9.0 mV mV -3 -7.0 -13 mV mV 20 35 mV 50 65 85 mV mV 85 120 150 mV mV 50 300 65 400 A A BIAS Pin Voltage Range (Note 3) l MAX l VBIAS = 2.5V, VIN = 1.25V, VOUT = 1.0V l VBIAS = 3.3V, VIN = 1.45V, VOUT = 1.2V l VBIAS = 3.3V, VIN = 1.75V, VOUT = 1.5V l VBIAS = 3.3V, VIN = 2.05V, VOUT = 1.8V l Dropout Voltage, VIN = VOUT(NOMINAL) (Note 6) IOUT = 1A, VOUT = 1V l IOUT = 2.5A, VOUT = 1V l IOUT = 5A, VOUT = 1V l SENSE Pin Current VIN = 1.1V, VSENSE = 0.8V VBIAS = 3.3V, VIN = 2.1V, VSENSE = 1.8V l l 35 200 Rev 0 For more information www.analog.com 3 LT3070-1 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. COUT = 15F (Note 9), VIN = VOUT + 0.3V (Note 5), VBIAS = 2.5V unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX Ground Pin Current, VIN = 1.3V, VOUT = 1V IOUT = 10mA IOUT = 5A BIAS Pin Current in Nap Mode l l 0.65 0.9 1.1 1.35 1.8 2.3 mA mA EN = Low l 120 200 320 A BIAS Pin Current, VIN = 1.3V, VOUT = 1V IOUT = 10mA IOUT = 100mA IOUT = 500mA IOUT = 1A IOUT = 2.5A IOUT = 5A l l l l l l 0.75 1.25 2.0 2.6 3.5 4.5 1.08 1.8 3.0 3.8 5.2 6.9 1.5 2.4 4.0 5.0 7.0 10.0 mA mA mA mA mA mA Current Limit (Note 5) VIN - VOUT < 0.3V, VBIAS = 3.3V VIN - VOUT = 1.0V, VBIAS = 3.3V VIN - VOUT = 1.7V, VBIAS = 3.3V l l l 5.1 3.2 1.2 6.4 4.5 2.5 7.7 5.8 4.3 A A A Reverse Output Current (Note 8) VIN = 0V, VOUT = 1.8V l 300 450 A PWRGD VOUT Threshold Percentage of VOUT(NOMINAL), VOUT Rising Percentage of VOUT(NOMINAL), VOUT Falling l l 90 85 93 88 % % PWRGD VOL IPWRGD = 200A (Fault Condition) l 50 150 mV VBIAS Undervoltage Lockout VBIAS Rising VBIAS Falling l l 1.1 0.9 1.55 1.4 2.1 1.7 V V l 250 300 350 mV 160 170 235 255 310 340 A A 0.25 V VBIAS - 0.9 V VIN-VOUT Servo Voltage by VIOC VIOC Output Current VIN = VOUT(NOMINAL) + 150mV, Sourcing Out of the Pin VIN = VOUT(NOMINAL) + 450mV, Sinking Into the Pin l l VIL Input Threshold (Logic-0 State), VO2, VO1, VO0, MARGSEL, MARGTOL Input Falling l VIZ Input Range (Logic-Z State), VO2, VO1, VO0, MARGSEL, MARGTOL VIH Input Threshold (Logic-1 State), VO2, VO1, VO0, MARGSEL, MARGTOL Input Rising 87 82 l 0.75 l VBIAS - 0.25 Input Hysteresis (Both Thresholds), VO2, VO1, VO0, MARGSEL, MARGTOL UNITS V 60 mV Input Current High, VO2, VO1, VO0, MARGSEL, MARGTOL VIH = VBIAS = 2.5V, Current Flows Into Pin l 25 40 A Input Current Low, VO2, VO1, VO0, MARGSEL, MARGTOL VIL = 0V, VBIAS = 2.5V, Current Flows Out of Pin l 25 40 A EN Pin Threshold VOUT = Off to On, VBIAS = 2.5V VOUT = On to Off, VBIAS = 2.5V VOUT = Off to On, VBIAS =2.2V to 3.6V VOUT = On to Off, VBIAS =2.2V to 3.6V l l l l 1.4 V V V V VEN = VBIAS = 2.5V l EN Pin Logic High Current 0.9 0.56 * VBIAS 0.36 * VBIAS 2.5 4.0 6.5 A Rev 0 4 For more information www.analog.com LT3070-1 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. COUT = 15F (Note 9), VIN = VOUT + 0.3V (Note 5), VBIAS = 2.5V unless otherwise noted. PARAMETER CONDITIONS MIN TYP EN Pin Logic Low Current VEN = 0V VBIAS Ripple Rejection VBIAS = VOUT + 1.5VAVG, VRIPPLE =0.5VP-P , fRIPPLE = 120Hz, VIN - VOUT = 300mV, IOUT = 2.5A 75 dB VIN Ripple Rejection (Notes 3, 4, 5) VBIAS = 2.5V, VRIPPLE = 50mVP-P , fRIPPLE = 120Hz, VIN - VOUT = 300mV, IOUT = 2.5A 66 dB Reference Voltage Noise (REF/BYP Pin) CREF/BYP = 10nF, BW = 10Hz to 100kHz 10 VRMS Output Voltage Noise VOUT = 1V, IOUT = 5A, CREF/BYP = 10nF, COUT = 15F, BW = 10Hz to 100kHz 25 VRMS 0.1 l Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LT3070-1 regulators are tested and specified under pulse load conditions such that TJ TA. The LT3070-1E is 100% tested at TA = 25C. Performance at -40C and 125C is assured by design, characterization and correlation with statistical process controls. The LT3070-1I is guaranteed over the -40C to 125C operating junction temperature range. The LT3070-1MP is 100% tested and guaranteed over the -55C to 125C operating junction temperature range. Note 3: To maintain proper performance and regulation, the BIAS supply voltage must be higher than the IN supply voltage. For a given VOUT , the BIAS voltage must satisfy the following conditions: 2.2V VBIAS 3.6V and VBIAS (1.25 * VOUT + 1V). For VOUT 0.95V, the minimum BIAS voltage is limited to 2.2V. Note 4: Operating conditions are limited by maximum junction temperature. The regulated output voltage specification does not apply for all possible combinations of input voltage and output current. When operating at maximum output current, limit the input voltage range to VIN < VOUT + 500mV. MAX UNITS A Note 5: The LT3070-1 incorporates safe operating area protection circuitry. Current limit decreases as the VIN-VOUT voltage increases. Current limit foldback starts at VIN - VOUT > 500mV. See the Typical Performance Characteristics for a graph of Current Limit vs VIN - VOUT voltage. The current limit foldback feature is independent of the thermal shutdown circuity. Note 6: Dropout voltage, VDO, is the minimum input to output voltage differential at a specified output current. In dropout, the output voltage equals VIN - VDO. Note 7: GND pin current is tested with VIN = VOUT(NOMINAL) + 300mV and a current source load. VIOC is a buffered output determined by the value of VOUT as programmed by the VO2-VO0 pins. VIOC's output is independent of the margining function. Note 8: Reverse output current is tested with the IN pins grounded and the OUT + SENSE pins forced to the rated output voltage. This is measured as current into the OUT + SENSE pins. Note 9: Frequency Compensation: The LT3070-1 must be frequency compensated at its OUT pins with a minimum COUT of 15F configured as a cluster of (15x) 1F ceramic capacitors or as a graduated cluster of 10F/4.7F/2.2F ceramic capacitors of the same case size. Linear Technology only recommends X5R or X7R dielectric capacitors. Rev 0 For more information www.analog.com 5 LT3070-1 TYPICAL PERFORMANCE CHARACTERISTICS Dropout Voltage vs Temperature 30 VIN = VOUT(NOMINAL) TJ = 25C 25 120 VOUT = 1.8V VBIAS = 3.3V 60 VOUT = 0.8V VBIAS = 2.5V 30 0 VIN = VOUT(NOMINAL) IOUT = 1A 20 15 10 VOUT = 1.8V, VBIAS = 3.3V VOUT = 0.8V, VBIAS = 2.5V VOUT = 1.2V, VBIAS = 3.3V 5 0 1 3 4 2 OUTPUT CURRENT (A) 90 0 -75 -50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C) 5 Dropout Voltage vs Temperature 60 30 VOUT = 1.8V, VBIAS = 3.3V VOUT = 0.8V, VBIAS = 2.5V VOUT = 1.2V, VBIAS = 3.3V 30 20 0.808 160 140 120 100 80 60 40 0 OUT = 1.8V OUT = 1.5V OUT = 0.8V 2.2 2.4 2.6 2.8 3.0 3.2 BIAS VOLTAGE (V) 3.4 1.212 ILOAD = 10mA 0.802 0.800 0.798 0.796 0.794 0.792 -75 -50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C) 3.6 30701 G06 Output Voltage (1.5V) vs Temperature 1.515 ILOAD = 10mA 1.208 OUTPUT VOLTAGE (V) 1.006 1.002 1.000 0.998 0.996 0.994 ILOAD = 10mA 0.804 Output Voltage (1.2V) vs Temperature 1.004 VOUT = 1.8V, VBIAS = 3.3V VOUT = 0.8V, VBIAS = 2.5V VOUT = 1.2V, VBIAS = 3.3V 30701 G05 Output Voltage (1V) vs Temperature OUTPUT VOLTAGE (V) 40 0.806 30701 G04 1.008 50 Output Voltage (0.8V) vs Temperature Dropout Voltage vs VBIAS 20 0 -75 -50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C) 1.010 60 30701 G03 OUTPUT VOLTAGE (V) 90 70 0 -75 -50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C) IOUT = 5A 180 TJ = 25C DROPOUT VOLTAGE (mV) DROPOUT VOLTAGE (mV) 200 VIN = VOUT(NOMINAL) IOUT = 5A 120 80 30701 G02 30701 G01 150 VIN = VOUT(NOMINAL) IOUT = 2.5A 10 ILOAD = 10mA 1.510 OUTPUT VOLTAGE (V) 90 Dropout Voltage vs Temperature 100 DROPOUT VOLTAGE (mV) Dropout Voltage vs IOUT DROPOUT VOLTAGE (mV) DROPOUT VOLTAGE (mV) 150 1.204 1.200 1.196 1.505 1.500 1.495 1.192 1.490 1.188 -75 -50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C) 1.485 -75 -50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C) 0.992 0.990 -75 -50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C) 30701 G07 30701 G08 30701 G09 Rev 0 6 For more information www.analog.com LT3070-1 TYPICAL PERFORMANCE CHARACTERISTICS Output Voltage (1.8V) vs Temperature GND PIN CURRENT (mA) OUTPUT VOLTAGE (V) 1.806 1.802 1.798 1.794 1.790 2.0 1.5 1.0 VOUT = 1.8V, VBIAS = 3.3V VOUT = 1.2V, VBIAS = 3.3V VOUT = 0.8V, VBIAS = 2.5V 0.5 1.786 0 1.782 -75 -50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C) 0 1 10 100 50 2.5 8 7 VOUT = 1.8V VBIAS = 3.3V 6 VOUT = 0.8V VBIAS = 2.5V 5 4 3 2 0 0 1 3 4 2 OUTPUT CURRENT (A) 30701 G13 VBIAS = 2.5V ENABLE/DISABLE THRESHOLD (V) ENABLE PIN THRESHOLD (V) 4.0 1.6 1.4 1.2 1.0 0.8 2.0 VBIAS RISING 1.5 1.0 VBIAS FALLING 0.5 EN PIN RISING EN PIN FALLING 0.6 0.4 0.2 0 -75 -50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C) 30701 G16 0 -75 -50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C) 5 30701 G14 EN Pin Thresholds 1.8 30701 G12 1 0 -75 -50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C) 2.0 594 -75 -50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C) BIAS Pin Undervoltage Lockout Threshold VIN = VOUT + 300mV TJ = 25C 9 BIAS PIN CURRENT (mA) BIAS PIN CURRENT (A) VBIAS = 2.5V 350 VEN = 0V 150 598 BIAS Pin Current vs IOUT 400 200 600 30701 G11 BIAS Pin Current in Nap Mode 250 602 596 5 2 3 4 OUTPUT CURRENT (A) 30701 G10 300 CREF/BYP = 0.01F 604 REF/BYP VOLTAGE (mV) 2.5 1.810 606 VIN = VOUT + 300mV TJ = 25C UVLO THRESHOLD VOLTAGE (V) 1.814 3.0 ILOAD = 10mA Enable Pin Threshold and Hysteresis vs VBIAS TJ = -55C TO 125C 3.5 TYPICAL HYSTERESIS = 150mV 3.0 PWRGD Threshold Voltage 1.00 VBIAS 2.5 MAX ENABLE 2.0 TYP ENABLE 1.5 MIN DISABLE TYP DISABLE 1.0 0.5 0 30701 G15 PWRGD TRESHOLD VOLTAGE (V) 1.818 REF/BYP Pin Voltage vs Temperature GND Pin Current vs IOUT 2 2.5 3 4 3.5 BIAS VOLTAGE (V) 30701 G17 VBIAS = 2.5V VOUT = 1V 0.95 VOUT RISING 0.90 0.85 VOUT FALLING 0.80 -75 -50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C) 30701 G18 Rev 0 For more information www.analog.com 7 LT3070-1 TYPICAL PERFORMANCE CHARACTERISTICS 0.8 VBIAS = 2.5V IPWRGD = 200A 80 60 40 20 0.7 0.6 0.5 INPUT RISING LOGIC LOW TO Hi-Z INPUT FALLING LOGIC Hi-Z TO LOW 0.4 0.3 -75 -50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C) 0 25 50 75 100 125 150 TEMPERATURE (C) 30701 G19 2.7 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 2.6 Logic Pin Input Current, Low State 35 40 VLOGIC = VBIAS = 2.5V CURRENT FLOWS INTO THE PIN 30 25 20 15 10 5 0 -75 -50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C) VBIAS = 2.5V 35 VLOGIC = 0V CURRENT FLOWS OUT OF THE PIN 30 25 20 15 10 5 0 -75 -50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C) 30701 G23 30701 G22 SENSE Pin Current 30701 G24 Current Limit vs Temperature SENSE Pin Current 7.50 400 65 SENSE PIN CURRENT (A) VBIAS = 2.5V 60 VOUT = 0.8V CURRENT FLOWS INTO SENSE 55 50 45 40 35 INPUT FALLING LOGIC HIGH TO Hi-Z 30701 G21 LOGIC PIN INPUT CURRENT (A) 40 VEN = VBIAS = 2.5V 1.0 -75 -50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C) SENSE PIN CURRENT (A) INPUT RISING LOGIC Hi-Z TO HIGH Logic Pin Input Current, High State LOGIC PIN INPUT CURRENT (A) EN PIN LOGIC HIGH CURRENT (A) 5.5 2.8 30701 G20 EN Pin Logic High Current 6.0 2.9 VBIAS = 3.3V LOGIC Hi-Z TO HIGH THRESHOLD IS RELATIVE TO VBIAS VOLTAGE SEE APPLICATIONS INFORMATION FOR MORE DETAILS 2.5 -75 -50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C) VBIAS = 3.3V 375 VOUT = 1.8V CURRENT FLOWS INTO SENSE 350 7.25 VIN - VOUT(NOMINAL) = 300mV 7.00 CURRENT LIMIT (A) 0 -75 -50 -25 3.0 SEE APPLICATIONS INFORMATION FOR MORE DETAILS LOGIC INPUT THRESHOLD VOLTAGE (V) PWRGD VOL vs Temperature LOGIC INPUT THRESHOLD VOLTAGE (V) PWRGD VOL VOLTAGE (mV) 100 Logic Input Threshold Voltages Logic Hi-Z to High State Transitions Logic Input Threshold Voltages Logic Low to Hi-Z State Transitions 325 300 275 250 6.75 6.50 6.25 6.00 5.75 5.50 VOUT = 1.8V, VBIAS = 3.3V VOUT = 1.2V, VBIAS = 3.3V VOUT = 0.8V, VBIAS = 2.5V 30 225 5.25 25 -75 -50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C) 200 -75 -50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C) 5.00 -75 -50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C) 30701 G25 30701 G26 30701 G27 Rev 0 8 For more information www.analog.com LT3070-1 TYPICAL PERFORMANCE CHARACTERISTICS BIAS Pin Ripple Rejection VBIAS = 3.3V TJ = 25C 6 5 4 3 2 VOUT = 1.8V VOUT = 1.2V VOUT = 0.8V 0 0 80 70 60 50 40 30 20 10 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 IN-TO-OUT VOLTAGE DIFFERENTIAL (V) VBIAS = 2.5V + 500mVP-P VBIAS = 2.7V + 500mVP-P VBIAS = 3.3V + 500mVP-P 10 100 1k 10k 100k FREQUENCY (Hz) 120 110 100 1M 90 80 50 40 COUT = 117F COUT = 16.9F 100 1k 10k 100k FREQUENCY (Hz) 100 90 0 10M 80 120 50mVP-P RIPPLE ON VIN COUT = 16.9F VBIAS = 2.5V RIPPLE AT f = 10kHz TA = 25C 110 100 90 80 50 40 70 60 50 40 RIPPLE AT f = 100kHz 60 40 30 10M 50mVP-P RIPPLE ON VIN COUT = 16.9F VBIAS = 2.5V TA = 25C RIPPLE AT f = 10kHz RIPPLE AT f = 100kHz RIPPLE AT f = 1MHz 10 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 AVERAGE INPUT/OUTPUT DIFFERENTIAL (V) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 AVERAGE INPUT/OUTPUT DIFFERENTIAL (V) 30701 G33 IN Pin Ripple Rejection vs VIN - VOUT, 1V/2.5A 120 50mVP-P RIPPLE ON VIN COUT = 117F VBIAS = 2.5V TA = 25C 110 100 90 RIPPLE AT f = 10kHz RIPPLE AT f = 1MHz RIPPLE AT f = 100kHz 80 70 RIPPLE AT f = 1MHz 40 RIPPLE AT f = 100kHz 20 20 10 10 0 0 30701 G35 RIPPLE AT f = 10kHz 50 10 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 AVERAGE INPUT/OUTPUT DIFFERENTIAL (V) 50mVP-P RIPPLE ON VIN COUT = 117F VBIAS = 2.5V TA = 25C 60 20 30701 G34 1M 20 RIPPLE AT f = 1MHz 30 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 AVERAGE INPUT/OUTPUT DIFFERENTIAL (V) 1k 10k 100k FREQUENCY (Hz) 50 30 RIPPLE AT f = 1MHz 100 70 IN Pin Ripple Rejection vs VIN - VOUT, 1V/5A RIPPLE AT f = 100kHz 10 30701 G32 PSRR (dB) PSRR (dB) 90 10 60 30 100 50 20 80 70 110 60 IN Pin Ripple Rejection vs VIN - VOUT, 1V/1A 110 VOUT = 1V VIN = 1.3V + 50mVP-P RIPPLE VBIAS = 2.5V IOUT = 1A 120 50mVP-P RIPPLE ON VIN COUT = 16.9F VBIAS = 2.5V TA = 25C RIPPLE AT f = 10kHz 30701 G31 120 20 30701 G30 30 1M COUT = 117F COUT = 16.9F 30 IN Pin Ripple Rejection vs VIN - VOUT, 1V/2.5A 70 40 VOUT = 1V VIN = 1.3V + 50mVP-P RIPPLE VBIAS = 2.5V IOUT = 5A 10 40 0 10M PSRR (dB) 60 PSRR (dB) IN PIN RIPPLE REJECTION (dB) 70 0 50 IN Pin Ripple Rejection vs VIN - VOUT, 1V/5A 80 10 60 30701 G29 IN Pin Ripple Rejection 20 70 10 30701 G28 30 80 PSRR (dB) 1 IN Pin Ripple Rejection VIN = 1.3V VOUT = 1V IOUT = 5A COUT = 10F + 4.7F + 2.2F 90 BIAS PIN RIPPLE REJECTION (dB) 7 CURRENT LIMIT (A) 100 IN PIN RIPPLE REJECTION (dB) Current Limit vs VIN - VOUT 8 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 AVERAGE INPUT/OUTPUT DIFFERENTIAL (V) 30701 G36 Rev 0 For more information www.analog.com 9 LT3070-1 TYPICAL PERFORMANCE CHARACTERISTICS 110 100 90 50mVP-P RIPPLE ON VIN COUT = 117F VBIAS = 2.5V TA = 25C 80 PSRR (dB) 4.0 3.8 RIPPLE AT f = 10kHz 70 60 RIPPLE AT f = 1MHz 50 40 RIPPLE AT f = 100kHz 30 20 Minimum BIAS Voltage vs IOUT VOUT = 1.8V VOUT = 1.2V VOUT = 0.8V 3.4 3.2 3.0 2.8 2.6 2.4 10 0 IOUT = 5A 3.6 MINIMUM BIAS VOLTAGE (V) 120 Minimum BIAS Voltage vs Temperature 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 AVERAGE INPUT/OUTPUT DIFFERENTIAL (V) 30701 G37 3.6 VIN = VOUT(NOMINAL) + 300mV VOUT = -1%, TJ = 25C VOUT = 1.8V VOUT = 1.5V VOUT = 1.2V VOUT = 0.8V TO 1V 3.4 MINIMUM BIAS VOLTAGE (V) IN Pin Ripple Rejection vs VIN - VOUT, 1V/1A 3.2 3.0 2.8 2.6 2.4 2.2 2.2 2.0 -75 -50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C) 2.0 0 1 2 4 3 OUTPUT CURRENT (A) 30701 G39 30701 G38 Load Regulation Minimum BIAS Voltage vs VOUT IOUT = 5A TJ = 25C 3.0 LOAD REGULATION (mV) MINIMUM BIAS VOLTAGE (V) 3.2 2.8 2.6 2.4 2.2 -2 -4 -6 -8 2.0 1.8 0.7 0.9 Bias Voltage Line Regulation 800 0 1.5 1.1 1.3 OUTPUT VOLTAGE (V) 1.7 BIAS VOLTAGE LINE REGULATION (V) 3.4 VIN = VOUT(NOMINAL) + 300mV VBIAS = 3.3V IOUT = 100mA TO 5A VOUT = 0.8V VOUT = 1.2V VOUT = 1.8V 30701 G41 30701 G40 VBIAS = 2.2V TO 3.6V 700 VIN = 1.1V VOUT = 0.8V 600 IOUT = 10mA 500 400 300 200 100 0 -75 -50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C) -10 -75 -50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C) 1.9 5 30701 G42 Input Voltage Line Regulation INPUT VOLTAGE LINE REGULATION (V) BIAS VOLTAGE LINE REGULATION (V) 300 VBIAS = 3.25V TO 3.6V 300 VIN = 2.1V VOUT = 1.8V 200 IOUT = 10mA 100 0 -100 -200 -300 -400 -75 -50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C) 30701 G43 250 Input Voltage Line Regulation 300 VBIAS = 3.3V VIN = 1.05V TO 2.7V VOUT = 0.8V IOUT = 10mA INPUT VOLTAGE LINE REGULATION (V) Bias Voltage Line Regulation 400 200 150 100 50 0 -75 -50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C) 30701 G44 250 VBIAS = 3.3V VIN = 2.05V TO 2.7V VOUT = 1.8V IOUT = 10mA 200 150 100 50 0 -75 -50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C) 30701 G45 Rev 0 10 For more information www.analog.com LT3070-1 TYPICAL PERFORMANCE CHARACTERISTICS 0.1 0.01 0.001 100 80 VIN = VOUT(NOMINAL) + 300mV 70 VBIAS = 3.3V COUT = 16.9F 60 CREF/BYP = 10nF 10 100 1k 10k FREQUENCY (Hz) 100k 80 50 40 30 20 10 0 0.01 10 1n Input Voltage Line Transient Response 10n 100n 1 REF/BYP CAPACITOR (F) 10 Bias Voltage Line Transient Response VOUT 10mV/DIV VBIAS 200mV/DIV VIN = 1.3V VOUT = 1V IOUT = 5A COUT = 16.9F 30701 G50 20s/DIV VIN = 1.3V VBIAS = 2.5V VOUT = 1V IOUT = 5A COUT = 16.9F 20s/DIV 30701 G51 VIOC Amplifier Output Current vs Temperature 300 VBIAS = 2.5V VIOC AMPLIFIER OUTPUT CURRENT (A) VIOC IN-TO-OUT SERVO VOLTAGE (mV) 340 30 LT30701 G48 VIOC Amplifier IN-to-OUT Servo Voltage 350 40 0 0.1 1 OUTPUT CURRENT (A) VIN 50mV/DIV 30701 G49 50 10 VOUT 1mV/DIV 1ms/DIV 60 30701 G47 Output Noise (10Hz to 100kHz) VOUT = 1V IOUT = 5A COUT = 16.9F 70 20 VOUT = 1.8V VOUT = 1.2V VOUT = 0.8V 30701 G46 VOUT 100V/DIV COUT = 16.9F VOUT = 0.8V IL = 5A TJ = 25C 90 OUTPUT NOISE (uVRMS) VBIAS = 2.5V VOUT = 1V IOUT = 5A COUT = 16.9F CREF/BYP = 0.01F OUTPUT NOISE (VRMS) NOISE SPECTRAL DENSITY (V/Hz) 1.0 RMS Output Noise vs CREF/BYP RMS Output Noise vs Output Current Output Noise Spectral Density 330 320 310 300 290 280 270 260 250 -75 -50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C) 275 IVIOC SOURCING 250 IVIOC SINKING 225 200 175 150 -75 -50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C) 30701 G52 30701 G53 Rev 0 For more information www.analog.com 11 LT3070-1 TYPICAL PERFORMANCE CHARACTERISTICS Transient Load Response Transient Load Response VOUT 50mV/DIV AC-COUPLED VOUT 50mV/DIV AC-COUPLED IOUT 2A/DIV I = 500mA TO 5A IOUT 2A/DIV I = 500mA TO 5A 30701 G54 VOUT = 1V 20s/DIV COUT = 10F + 4.7F + 2.2F IOUT tRISE/tFALL = 100ns VOUT = 1V 20s/DIV COUT = 117F IOUT tRISE/tFALL = 100ns Transient Load Response 30701 G55 Transient Load Response VOUT 50mV/DIV AC-COUPLED VOUT 50mV/DIV AC-COUPLED IOUT 2A/DIV I = 500mA TO 5A IOUT 2A/DIV I = 500mA TO 5A 30701 G56 VOUT = 1V 20s/DIV COUT = 10F + 4.7F + 2.2F IOUT tRISE/tFALL = 1s VOUT = 1V 20s/DIV COUT = 117F IOUT tRISE/tFALL = 1s Output Voltage Start-Up Time vs CREF/BYP 30701 G57 EN Start-Up Response OUTPUT VOLTAGE START-UP TIME (ms) 100 10 TJ = 25C IL = 100mA SETTLING TO 1% IIN 100mA/DIV VOUT 500mV/DIV RL = 10 VREF 500mV/DIV CREF/BYP = 10nF 1 VEN 2V/DIV 0.1 0.01 100p 1n 10n 100n REF/BYP CAPACITOR (F) 1 CIN = 330F COUT = 16.9F VOUT = 1V 400s/DIV 30701 G59 LT30701 G58 Rev 0 12 For more information www.analog.com LT3070-1 PIN FUNCTIONS VIOC (Pin 1): Voltage for In-to-Out Control. The IC incorporates a unique tracking function to control a buck regulator powering the LT3070-1's input. The VIOC pin is the output of this tracking function that drives the buck regulator to maintain the LT3070-1's input voltage at VOUT + 300mV. This function maximizes efficiency and minimizes power dissipation. See the Applications Information section for more information on proper control of the buck regulator. PWRGD (Pin 2): Power Good. The PWRGD pin is an opendrain NMOS output that actively pulls low if any one of these fault modes is detected: * VOUT is less than 90% of VOUT(NOMINAL) on the rising edge of VOUT . * VOUT drops below 85% of VOUT(NOMINAL) for more than 25s. * Junction temperature typically exceeds 145C. * VBIAS is less than its undervoltage lockout threshold. * The OUT-to-IN reverse-current detector activates. See the Applications Information section for more information on PWRGD fault modes. REF/BYP (Pin 3): Reference Filter. The pin is the output of the bandgap reference and has an impedance of approximately 19k. This pin must not be externally loaded. Bypassing the REF/BYP pin to GND with a capacitor decreases output voltage noise and provides a soft-start function to the reference. ADI recommends the use of a high quality, low leakage capacitor. See the Applications Information section for more information on noise and output voltage margining considerations. GND (Pins 4, 9-14, 20, 26, 29): Ground. The exposed pad (Pin 29) of the QFN package is an electrical connection to GND. To ensure proper electrical and thermal performance, solder Pin 29 to the PCB ground and tie to all GND pins of the package. These GND pins are fused to the internal die attach paddle and the exposed pad to optimize heat sinking and thermal resistance characteristics. See the Applications Information section for thermal considerations and calculating junction temperature. IN (Pins 5, 6, 7, 8): Input Supply. These pins supply power to the high current pass transistor. Tie all IN pins together for proper performance. The LT3070-1 requires a bypass capacitor at IN to maintain stability and low input impedance over frequency. A 47F input bypass capacitor suffices for most battery and power plane impedances. Minimizing input trace inductance optimizes performance. Applications that operate with low VIN-VOUT differential voltages and that have large, fast load transients may require much higher input capacitor requirements to prevent the input supply from drooping and allowing the regulator to enter dropout. See the Applications Information section for more information on input capacitor requirements. OUT (Pins 15, 16, 17, 18): Output. These pins supply power to the load. Tie all OUT pins together for proper performance. A minimum output capacitance of 15F is required for stability. ADI recommends low ESR, X5R or X7R dielectric ceramic capacitors for best performance. A parallel ceramic capacitor combination of 10F + 4.7F + 2.2F or 15 1F ceramic capacitors in parallel provide excellent stability and load transient response. Large load transient applications require larger output capacitors to limit peak voltage transients. See the Applications Information section for more information on output capacitor requirements. SENSE (Pin 19): Kelvin Sense for OUT . The SENSE pin is the inverting input to the error amplifier. Optimum regulation is obtained when the SENSE pin is connected to the OUT pins of the regulator. In critical applications, the resistance (RP) of PCB traces between the regulator and the load cause small voltage drops, creating a load regulation error at the point of load. Connecting the SENSE pin at the load instead of directly to OUT eliminates this voltage error. Figure 1 illustrates this Kelvin-Sense connection method. Note that the voltage drop across the external PCB traces adds to the dropout voltage of the regulator. The SENSE pin input bias current depends on the selected output voltage. SENSE pin input current varies from 50A typically at VOUT = 0.8V to 300A typically at VOUT = 1.8V. Rev 0 For more information www.analog.com 13 LT3070-1 PIN FUNCTIONS + VBIAS EN BIAS SENSE IN VO2 + OUT LT3070-1 VO1 VIN RP PWRGD VO0 LOAD MARGSEL MARGTOL VIOC REF/BYP GND RP 30701 F01 Figure 1. Kelvin Sense Connection MARGSEL (Pin 21): Margining Enable and Polarity Selection. This three-state pin determines both the polarity and the active state of the margining function. The logic low threshold is less than 250mV referenced to GND and enables negative voltage margining. The logic high threshold is greater than VBIAS - 250mV and enables positive voltage margining. The voltage range between these two logic thresholds as set by a window comparator defines the logic Hi-Z state and disables the margining function. MARGTOL (Pin 22): Margining Tolerance. This threestate pin selects the absolute value of margining (1%, 3% or 5%) if enabled by the MARGSEL input. The logic low threshold is less than 250mV referenced to GND and enables either 1% change in VOUT depending on the state of the MARGSEL pin. The logic high threshold is greater than VBIAS - 250mV and enables either 5% change in VOUT depending on the state of the MARGSEL pin. The voltage range between these two logic thresholds as set by a window comparator defines the logic Hi-Z state and enables either 3% change in VOUT depending on the state of the MARGSEL pin. VO0, VO1 and VO2 (Pins 23, 24, 25): Output Voltage Select. These three-state pins combine to select a nominal output voltage from 0.8V to 1.8V in increments of 50mV. Output voltage is limited to 1.8V maximum by an internal override of VO1 when VO2 = high. The input logic low threshold is less than 250mV referenced to GND and the logic high threshold is greater than VBIAS - 250mV. The range between these two thresholds as set by a window comparator defines the logic Hi-Z state. See Table 1 in the Applications Information section that defines the VO2, VO1 and VO0 settings versus VOUT . BIAS (Pin 27): Bias Supply. This pin supplies current to the internal control circuitry and the output stage driving the pass transistor. The LT3070-1 requires a minimum 2.2F bypass capacitor for stability and proper operation. To ensure proper operation, the BIAS voltage must satisfy the following conditions: 2.2V VBIAS 3.6V and VBIAS (1.25 * VOUT + 1V). For VOUT 0.95V, the minimum BIAS voltage is limited to 2.2V. EN (Pin 28): Enable. This pin enables/disables the reference output and output power device. The internal reference and all support functions are active if VBIAS is above its UVLO threshold. Pulling EN low disables the REF/BYP pin current and the output pass transistor, putting the LT3070-1 into a low power nap mode. The maximum rising EN threshold is ratioed to 0.56 % of VBIAS and the minimum falling EN threshold is 0.36 % of VBIAS. Drive the EN pin with either a digital logic port or an open-collector NPN or an opendrain NMOS terminated with a pull-up resistor to VBIAS. The pull-up resistor must be less than 35k to meet the VIH condition of the EN pin. If unused, connect EN to BIAS. Rev 0 14 For more information www.analog.com LT3070-1 BLOCK DIAGRAM 27 BIAS IN 5-8 UVLO AND THERMAL SHUTDOWN + ISENSE REF/BYP - + EAMP BUF - OUT 15-18 LDO CORE SENSE DETECT VIOC + - 1 PWRGD 19 2 VOUT(NOM) + 300mV VREF GND 4,9-14,20,26,29 REF/BYP 600mV 3 PROGRAM CONTROL EN 28 VO2 VO1 VO0 MARGSEL MARGTOL 25 24 23 21 22 30701 BD LOGIC HIGH STATE EN 100k TO INTERNAL ENABLE SEE ENABLE THRESHOLD CURVE VBIAS - 0.25V + LOGIC Hi-Z STATE VBIAS VO2, VO1, VO0 MARGSEL OR MARGTOL - 100k VBIAS - 0.9V 100k 0.75V + - + - TO LOGIC HIGH IF IN > VBIAS - 0.25V HIGH IF IN < VBIAS - 0.9V AND IN > 0.75V HIGH IF IN < 0.25V LOGIC LOW STATE - 0.25V + Rev 0 For more information www.analog.com 15 LT3070-1 APPLICATIONS INFORMATION Introduction Current generation FPGA and ASIC processors place stringent demands on the power supplies that power the core, I/O and transceiver channels. These microprocessors may cycle load current from near zero to amps in tens of nanoseconds. Output voltage specifications, especially in the 1V range, require tight tolerances including transient response as part of the requirement. Some ASIC processors require only a single output voltage from which the core and I/O circuitry operate. Some high performance FPGA processors require separate power supply voltages for the processor core, the I/O, and the transceivers. Often, these supply voltages must be low noise and high bandwidth to achieve the lowest bit-error rates. These requirements mandate the need for very accurate, low noise, high current, very high speed regulator circuits that operate at low input and output voltages. The LT3070-1 is a low voltage, UltraFast transient response linear regulator. The device supplies up to 5A of output current with a typical dropout voltage of 85mV. A 0.01F reference bypass capacitor decreases output voltage noise to 25VRMS (BW = 10Hz to 100kHz). The LT3070-1's high bandwidth provides UltraFast transient response using low ESR ceramic output capacitors (15F minimum), saving bulk capacitance, PCB area and cost. The LT3070-1's features permit state-of-the-art linear regulator performance. The LT3070-1 is ideal for high performance FPGAs, microprocessors, sensitive communication supplies, and high current logic applications that also operate over low input and output voltages. Output voltage for the LT3070-1 is digitally selectable in 50mV increments over a 0.8V to 1.8V range. A margining function allows the user to adjust system output voltage in increments of 1%, 3% or 5%. The IC incorporates a unique tracking function, which if enabled by the user, controls an upsteam regulator powering the LT3070-1's input (see Figure 7). This tracking function drives the buck regulator to maintain the LT30701's input voltage to VOUT + 300mV. This input-to-output voltage control allows the user to change the regulator output voltage, and have the switching regulator powering the LT3070-1's input to track to the optimum input voltage with no component changes. 16 This combines the efficiency of a switching regulator with superior linear regulator response. It also permits thermal management of the system even with a maximum 5A output load. LT3070-1 internal protection includes input undervoltage lockout (UVLO), reverse-current protection, precision current limiting with power foldback and thermal shutdown. The LT3070-1 regulator is available in a thermally enhanced 28-lead, 4mm x 5mm QFN package. The LT3070-1's architecture drives an internal N-channel power MOSFET as a source follower. This configuration permits a user to obtain an extremely low dropout, UltraFast transient response regulator with excellent high frequency PSRR performance. The LT3070-1 achieves superior regulator bandwidth and transient load performance by eliminating expensive bulk tantalum or electrolytic capacitors in the most modern and demanding microprocessor applications. Users realize significant cost savings as all additional bulk capacitance is removed. The additional savings of insertion cost, purchasing/inventory cost and board space are readily apparent. Precision incremental output voltage control accommodates legacy and future microprocessor power supply voltages. Output capacitor networks simplify to direct parallel combinations of ceramic capacitors. Often, the high frequency ceramic decoupling capacitors required by these various FPGA and ASIC processors are sufficient to stabilize the system (see Stability and Output Capacitance section). This regulator design provides ample bandwidth and responds to transient load changes in a few hundred nanoseconds versus regulators that respond in many microseconds. The LT3070-1 also incorporates precision current limiting, enable/disable control of output voltage and integrated overvoltage and thermal shutdown protection. The LT30701's unique design combines the benefits of low dropout voltage, high functional integration, precision performance and UltraFast transient response, as well as providing significant cost savings on the output capacitance needed in fast load transient applications. As lower voltage applications become increasingly prevalent with higher frequency switching power supplies, the LT3070-1 offers superior regulation and an appreciable For more information www.analog.com Rev 0 LT3070-1 APPLICATIONS INFORMATION component cost savings. The LT3070-1 steps to the next level of performance for the latest generation FPGAs, DSPs and microprocessors. The simple versatility and benefits derived from these circuits exceed the power supply needs of today's high performance microprocessors. Programming Output Voltage Three tri-level input pins, VO2, VO1 and VO0, select the value of output voltage. Table 1 illustrates the 3-bit digital word to output voltage resulting from setting these pins high, low or allowing them to float. These pins may be tied high or low by either pin-strapping them to VBIAS or driving them with digital ports. Pins that float may either actually float or require logic that has Hi-Z output capability. This allows output voltage to be dynamically changed if necessary. Output voltage is selectable from a minimum of 0.8V to a maximum of 1.8V in increments of 50mV. The MSB, VO2, sets the pedestal voltage, and the LSB's, VO1 and VO0 increment VOUT . Output voltage is limited to 1.8V maximum by an internal override of VO1 (default to low) when VO2 = high. Table 1. VO2 to VO0 Settings vs Output Voltage VO2 VO1 VO0 VOUT(NOM) VO2 VO1 VO0 VOUT(NOM) 0 0 0 0.80V Z 0 1 1.35V 0 0 Z 0.85V Z Z 0 1.40V 0 0 1 0.90V Z Z Z 1.45V 0 Z 0 0.95V Z Z 1 1.50V 0 Z Z 1.00V Z 1 0 1.55V 0 Z 1 1.05V Z 1 Z 1.60V 0 1 0 1.10V Z 1 1 1.65V 0 1 Z 1.15V 1 X 0 1.70V 0 1 1 1.20V 1 X Z 1.75V Z 0 0 1.25V 1 X 1 1.80V Z 0 Z 1.30V X = Don't Care, 0 = Low, Z = Float, 1 = High The input logic low threshold is less than 250mV referenced to GND and the logic high threshold is greater than VBIAS - 250mV. The range between these two thresholds as set by a window comparator defines the logic Hi-Z state. REF/BYP--Voltage Reference This pin is the buffered output of the internal bandgap reference and has an output impedance of 19k. The design includes an internal compensation pole at fC = 4kHz. A 10nF REF/BYP capacitor to GND creates a lowpass pole at fLP = 840Hz. The 10nF capacitor decreases reference voltage noise to about 10VRMS and soft-starts the reference. The LT3070-1 soft-starts the reference voltage when the EN pin is toggled from low to high. In comparison, the LT3070 soft-starts only when turning the BIAS supply voltage on. Output voltage noise is the RMS sum of the reference voltage noise in addition to the amplifier noise. Curves for start-up time and output noise vs REF/BYP capacitance appear in the Typical Performance Characteristics section. The REF/BYP pin must not be DC loaded by anything except for applications that parallel other LT3070-1 regulators for higher output currents. Consult the Applications Section on Paralleling for further details. Output Voltage Margining Two tri-level input pins, MARGSEL (polarity) and MARGTOL (scale), select the polarity and amount of output voltage margining. Margining is programmable in increments of 1%, 3% and 5%. Margining is internally implemented as a scaling of the reference voltage. Table 2 illustrates the 2-bit digital word to output voltage margining resulting from setting these pins high, low or allowing them to float. These pins may be set high or low by either pin-strapping them to VBIAS or driving them with digital ports. Pins that float may either actually float or require logic that has "Hi-Z" output capability. This allows output voltage to be dynamically margined if necessary. The MARGSEL pin determines both the polarity and the active state of the margining function. The logic low threshold is less than 250mV referenced to GND and enables negative voltage margining. The logic high threshold is greater than VBIAS - 250mV and enables positive voltage margining. The voltage range between these two logic thresholds as set by a window comparator defines the logic Hi-Z state and disables the margining function. Rev 0 For more information www.analog.com 17 LT3070-1 APPLICATIONS INFORMATION The MARGTOL pin selects the absolute value of margining (1%, 3% or 5%) if enabled by the MARGSEL input. The logic low threshold is less than 250mV referenced to GND and enables either 1% change in VOUT depending on the state of the MARGSEL pin. The logic high threshold is greater than VBIAS - 250mV and enables either 5% change in VOUT depending on the state of the MARGSEL pin. The voltage range between these two logic thresholds as set by a window comparator defines the logic Hi-Z state and enables either 3% change in VOUT depending on the state of the MARGSEL pin. Table 2. Programming Margining MARGSEL 0 0 0 Z Z Z 1 1 1 MARGTOL 0 Z 1 0 Z 1 0 Z 1 % OF VOUT(NOM) -1 -3 -5 0 0 0 1 3 5 Enable Function--Turning On and Off The EN pin enables/disables the reference output and output power device. The LT3070-1's support functions remain active if VBIAS is above its UVLO threshold. Pulling the EN pin low puts the LT3070-1 into nap mode. In nap mode, the output is disabled and quiescent current decreases. Drive the EN pin with either a digital logic port or an opencollector NPN or an open-drain NMOS terminated with a pull-up resistor to VBIAS. The pull-up resistor must be less than 35k to meet the VIH condition of the EN pin. If unused, connect EN to BIAS. Input Undervoltage Lockout on BIAS Pin An internal undervoltage lockout (UVLO) comparator monitors the BIAS supply voltage. If VBIAS drops below the UVLO threshold, all functions shut down, the pass transistor is gated off and output current falls to zero. The typical BIAS pin UVLO threshold is 1.55V on the rising edge of VBIAS. The UVLO circuit incorporates about 150mV of hysteresis on the falling edge of VBIAS. High Efficiency Linear Regulator--Input-to-Output Voltage Control The VIOC (voltage input-to-output control) pin is a function to control a switching regulator and facilitate a design solution that maximizes system efficiency at high load currents and still provides low dropout voltage performance. The VIOC pin is the output of an integrated transconductance amplifier that sources and sinks about 250A of current. It typically regulates the output of most LTC(R) switching regulators or LTM(R) power modules, by sinking current from the ITH compensation node. The VIOC function controls a buck regulator powering the LT3070-1's input by maintaining the LT3070-1's input voltage to VOUT + 300mV. This 300mV VIN-VOUT differential voltage is chosen to provide fast transient response and good high frequency PSRR while minimizing power dissipation and maximizing efficiency. For example, 1.5V to 1.2V conversion and 1.3V to 1V conversion yield 1.5W maximum power dissipation at 5A full output current. Figure 2 depicts that the switcher's feedback resistor network sets the maximum switching regulator output voltage if the linear regulator is disabled. However, once the LT3070-1 is enabled, the VIOC feedback loop decreases the switching regulator output voltage back to VOUT + 300mV. Using the VIOC function creates a feedback loop between the LT3070-1 and the switching regulator. As such, the feedback loop must be frequency compensated for stability. Fortunately, the connection of VIOC to many ADI switching regulator ITH pins represents a high impedance characteristic which is the optimum circuit node to frequency compensate the feedback loop. Figure 2 illustrates the typical frequency compensation network used at the VIOC node to GND. The VIOC amplifier characteristics are: gm = 3.2mS, IOUT = 250A, BW = 10MHz. If the VIOC function is not used, terminate the VIOC pin to GND with a small capacitor (1000pF) to prevent oscillations. Rev 0 18 For more information www.analog.com LT3070-1 APPLICATIONS INFORMATION LT3070-1 IN OUT SWITCHING REGULATOR REF + - LOAD - + PWM FB VOUT + VREF 300mV VIOC REFERENCE ITH 30701 F02 Figure 2. VIOC Control Block Diagram PWRGD--Power Good PWRGD pin is an open-drain NMOS digital output that actively pulls low if any one of these fault modes is detected: * VOUT is less than 90% of VOUT(NOMINAL) on the rising edge of VOUT . * VOUT drops below 85% of VOUT(NOMINAL) for more than 25s. * VBIAS is less than its undervoltage lockout threshold. * The OUT-to-IN reverse-current detector activates. * Junction temperature exceeds 145C typically.* *The junction temperature detector is an early warning indicator that trips approximately 20C before thermal shutdown engages. Stability and Output Capacitance The LT3070-1's feedback loop requires an output capacitor for stability. Choose COUT carefully and mount it in close proximity to the LT3070-1's OUT and GND pins. Include wide routing planes for OUT and GND to minimize inductance. If possible, mount the regulator immediately adjacent to the application load to minimize distributed inductance for optimal load transient performance. Pointof-Load applications present the best case layout scenario for extracting full LT3070-1 performance. Low ESR, X5R or X7R ceramic chip capacitors are the ADI recommended choice for stabilizing the LT3070-1. Additional bulk capacitors distributed beyond the immediate decoupling capacitors are acceptable as their parasitic ESL and ESR, combined with the distributed PCB inductance isolates them from the primary compensation pole provided by the local surface mount ceramic capacitors. The LT3070-1 requires a minimum output capacitance of 15F for stability. ADI strongly recommends that the output capacitor network consist of several low value ceramic capacitors in parallel. Why Do Multiple, Small-Value Output Capacitors Connected in Parallel Work Better? The LT3070-1's unity-gain bandwidth with COUT of 15F is about 1MHz at its full-load current of 5A. Surface mounted MLCC capacitors have a self-resonance frequency of fR = 1/(2LC), which must be pushed to a frequency higher than the regulator bandwidth. Standard MLCC capacitors are acceptable. To keep the resonant frequency greater than 1MHz, the product 1/(2LC) must be greater than 1MHz. At this bandwidth, PCB vias can add significant inductance, thus the fundamental decoupling capacitors must be mounted on the same plane as the LT3070-1. Typical 0603 or 0805 case-size capacitors have an ESL of ~800pH and PCB mounting can contribute up to ~200pH. Thus, it becomes necessary to reduce the parasitic inductance by using a parallel capacitor combination. A Rev 0 For more information www.analog.com 19 LT3070-1 APPLICATIONS INFORMATION suitable methodology must control this paralleling as capacitors with the same self-resonant frequency, fR, will form a tank circuit that can induce ringing of their own accord. Small amounts of ESR (5m to 20m) have some benefit in dampening the resonant loop, but higher ESRs degrade the capacitor response to transient load steps with rise/fall times less than 1s. The most area efficient parallel capacitor combination is a graduated 4/2/1 scale of fR of the same case size. Under these conditions, the individual ESLs are relatively uniform, and the resonance peaks are deconstructively spread beyond the regulator bandwidth. The recommended parallel combination that approximates 15F is 10F + 4.7F + 2.2F. Capacitors with case sizes larger than 0805 have higher ESL and lower ESR (<5m). Therefore, more capacitors with smaller values (<10F) must be chosen. Users should consider new generation, low inductance capacitors to push out fR and maximize stability. Refer to the surface mount ceramic capacitor manufacturer's data sheets for capacitor specifications. Figure 3 illustrates an optimum PCB layout for the parallel output capacitor combination, but also illustrates the GND connection between the IN capacitor and the OUT capacitors to minimize the AC GND loop for fast load transients. This tight bypassing connection minimizes EMI and optimizes bypassing. Many of the applications in which the LT3070-1 excels, such as FPGA, ASIC processor or DSP supplies, typically require a high frequency decoupling capacitor network for the device being powered. This network generally consists of many low value ceramic capacitors in parallel. In some applications, this total value of capacitance may be close to LT3070-1 SENSE IN OUT GND Lo-Z INPUT LOAD PLANE 2.2F 47F 4.7F 10F the LT3070-1's minimum 15F capacitance requirement. This may reduce the required value of capacitance directly at the LT3070-1's output. Multiple low value capacitors in parallel present a favorable frequency characteristic that pushes many of the parasitic poles/zeroes beyond the LT3070-1's unity-gain crossover frequency. This technique illustrates the method that extracts the full bandwidth performance of the LT3070-1. Give additional consideration to the use of ceramic capacitors. Ceramic capacitors are manufactured with a variety of dielectrics, each with different behavior across temperature and applied voltage. The most common dielectrics used are specified with EIA temperature characteristic codes of Z5U, Y5V, X5R and X7R. The Z5U and Y5V dielectrics are good for providing high capacitances in a small package, but they tend to have strong voltage and temperature coefficients as shown in Figure 4 and Figure 5. When used with a 5V regulator, a 16V 10F Y5V capacitor can exhibit an effective value as low as 1F to 2F for the DC bias voltage applied and over the operating temperature range. The X5R and X7R dielectrics result in more stable characteristics and are more suitable for use as the output capacitor. The X7R type has better stability across temperature, while the X5R is less expensive and is available in higher values. Care still must be exercised when using X5R and X7R capacitors; the X5R and X7R codes only specify operating temperature range and maximum capacitance change over temperature. Capacitance change due to DC bias with X5R and X7R capacitors is better than Y5V and Z5U capacitors, but can still be significant enough to drop capacitor values below appropriate levels. Capacitor DC bias characteristics tend to improve as component case size increases, but expected capacitance at operating voltage should be verified. Voltage and temperature coefficients are not the only sources of problems. Some ceramic capacitors have a piezoelectric response. A piezoelectric device generates voltage across its terminals due to mechanical stress, similar to the way a piezoelectric microphone works. For a ceramic capacitor the stress can be induced by vibrations in the system or thermal transients. 30701 F03 Figure 3. Example PCB Layout Rev 0 20 For more information www.analog.com LT3070-1 APPLICATIONS INFORMATION 20 0 CHANGE IN VALUE (%) LT3070-1 back to the power supply ground), large input capacitors are required to avoid an unstable application. BOTH CAPACITORS ARE 16V, 1210 CASE SIZE, 10F X5R -20 -40 -60 Y5V -80 -100 0 2 10 12 4 8 6 DC BIAS VOLTAGE (V) 14 16 30701 F04 Figure 4. Ceramic Capacitor DC Bias Characteristics 40 CHANGE IN VALUE (%) 20 0 BOTH CAPACITORS ARE 16V, 1210 CASE SIZE, 10F X5R -20 -40 Y5V -60 -80 -100 -50 -25 50 25 75 0 TEMPERATURE (C) 100 125 30701 F05 Figure 5. Ceramic Capacitor Temperature Characteristics Stability and Input Capacitance The LT3070-1 is stable with a minimum capacitance of 47F connected to its IN pins. Use low ESR capacitors to minimize instantaneous voltage drops under large load transient conditions. Large VIN droops during large load transients may cause the regulator to enter dropout with corresponding degradation in load transient response. Increased values of input and output capacitance may be necessary depending on an application's requirements. Sufficient input capacitance is critical as the circuit is intentionally operated close to dropout to minimize power. Ideally, the output impedance of the supply that powers IN should be less than 10m to support a 5A load with large transients. In cases where wire is used to connect a power supply to the input of the LT3070-1 (and also from the ground of the This is due to the inductance of the wire forming an LC tank circuit with the input capacitor and not a result of the LT3070-1 being unstable. The self inductance, or isolated inductance, of a wire is directly proportional to its length. However, the diameter of a wire does not have a major influence on its self inductance. For example, one inch of 18-AWG, 0.04 inch diameter wire has 28nH of self inductance. The self inductance of a 2-AWG isolated wire with a diameter of 0.26 inch is about half the inductance of a 18-AWG wire. The overall self inductance of a wire can be reduced in two ways. One is to divide the current flowing towards the LT3070-1 between two parallel conductors which flows in the same direction in each. In this case, the farther the wires are placed apart from each other, the more inductance will be reduced, up to a 50% reduction when placed a few inches apart. Splitting the wires basically connects two equal inductors in parallel. However, when placed in close proximity from each other, mutual inductance is added to the overall self inductance of the wires. The most effective way to reduce overall inductance is to place the forward and return-current conductors (the wire for the input and the wire for the return ground) in very close proximity. Two 18-AWG wires separated by 0.05 inch reduce the overall self inductance to about one-fourth of a single isolated wire. If the LT3070-1 is powered by a battery mounted in close proximity with ground and power planes on the same circuit board, a 47F input capacitor is sufficient for stability. However, if the LT3070-1 is powered by a distant supply, use a low ESR, large value input capacitor on the order of 330F. As power supply output impedance varies, the minimum input capacitance needed for application stability also varies. Bias Pin Capacitance Requirements The BIAS pin supplies current to most of the internal control circuitry and the output stage driving the pass transistor. The LT3070-1 requires a minimum 2.2F bypass capacitor for stability and proper operation. To ensure proper operation, the BIAS voltage must satisfy the following conditions: 2.2V VBIAS 3.6V and VBIAS (1.25 * VOUT + 1V). For VOUT 0.95V, the minimum BIAS voltage is limited to 2.2V. Rev 0 For more information www.analog.com 21 LT3070-1 APPLICATIONS INFORMATION Load Regulation The LT3070-1 provides a Kelvin sense pin for VOUT, allowing the application to correct for parasitic package and PCB I-R drops. However, ADI recommends that the SENSE pin terminate in close proximity to the LT3070-1's OUT pins. This minimizes parasitic inductance and optimizes regulation. The LT3070-1 handles moderate levels of output line impedance, but excessive impedance between VOUT and COUT causes excessive phase shift in the feedback loop and adversely affects stability. to-output voltage. The LT3070-1 provides some output current at all values of input-to-output voltage up to the absolute maximum voltage rating. See the Current Limit vs VIN curve in the Typical Performance Characteristics. During start-up, after the BIAS voltage has cleared its UVLO threshold and VIN is increasing, output voltage increases at the rate of current limit charging COUT . Figure 1 in the Pin Functions section illustrates the KelvinSense connection method that eliminates voltage drops due to PCB trace resistance. However, note that the voltage drop across the external PCB traces adds to the dropout voltage of the regulator. The SENSE pin input bias current depends on the selected output voltage. SENSE pin input current varies from 50A typically at VOUT = 0.8V to 300A typically at VOUT = 1.8V. With a high input voltage, a problem can occur where the removal of an output short will not allow the output voltage to recover. Other regulators with current limit foldback also exhibit this phenomenon, so it is not unique to the LT3070-1. The load line for such a load may intersect the output current curve at two points: normal operation and the SOA restricted load current settings. A common situation is immediately after the removal of a short circuit, but with a static load 1A. In this situation, removal of the load or reduction of IOUT to <1A will clear this condition and allow VOUT to return to normal regulation. Short-Circuit and Overload Recovery Reverse Voltage Like many IC power regulators, the LT3070-1 has safe operating area (SOA) protection. The safe area protection decreases current limit as input-to-output voltage increases and keeps the power transistor inside a safe operating region for all values of input-to-output voltage up to the absolute maximum voltage rating. VBIAS must be above the UVLO threshold for any function. The LT3070-1 has a precision current limit specified at 20% that is active if VBIAS is above UVLO. The LT3070-1 incorporates a circuit that detects if VIN decreases below VOUT . This reverse-voltage detector has a typical threshold of about (VIN - VOUT) = -6mV. If the threshold is exceeded, this detector circuit turns off the drive to the internal NMOS pass transistor, thereby turning off the output. The output pulls low with the load current discharging the output capacitance. This circuit's intent is to limit and prevent back-feed current from OUT to IN if the input voltage collapses due to a fault or overload condition. It should be noted that a negative (-) reverse detection threshold implies that a small back-feed current can flow from VOUT to VIN, as long as the DUT is enabled. To guarantee shutdown the enable (EN) pin must be pulled low. Under conditions of maximum ILOAD and maximum VIN-VOUT the device's power dissipation peaks at about 3W. If ambient temperature is high enough, die junction temperature will exceed the 125C maximum operating temperature. If this occurs, the LT3070-1 relies on two additional thermal safety features. At about 145C, the PWRGD output pulls low providing an early warning of an impending thermal shutdown condition. At 165C typically, the LT3070-1's thermal shutdown engages and the output is shut down until the IC temperature falls below the thermal hysteresis limit. The SOA protection decreases current limit as the IN-to-OUT voltage increases and keeps the power dissipation at safe levels for all values of input- Thermal Considerations The LT3070-1's maximum rated junction temperature of 125C limits its power handling capability and is dominated by the output current multiplied by the input/output voltage differential: IOUT * (VIN - VOUT) Rev 0 22 For more information www.analog.com LT3070-1 APPLICATIONS INFORMATION The LT3070-1's internal power and thermal limiting circuitry protect it under overload conditions. For continuous normal load conditions, do not exceed the maximum junction temperature of 125C. Give careful consideration to all sources of thermal resistance from junction to ambient. This includes junction to case, case-to-heat sink interface, heat sink resistance or circuit board to ambient as the application dictates. Also, consider additional heat sources mounted in proximity to the LT3070-1. The LT3070-1 is a surface mount device and as such, heat sinking is accomplished by using the heat spreading capabilities of the PC board and its copper traces. Surface mount heat sinks and plated through-holes can also be used to spread the heat generated by power devices. Junction-to-case thermal resistance is specified from the IC junction to the bottom of the case directly below the die. This is the lowest resistance path for heat flow. Proper mounting is required to ensure the best possible thermal flow from this area of the package to the heat sinking material. Note that the exposed pad is electrically connected to GND. Calculating Junction Temperature Table 3 lists thermal resistance as a function of copper area in a fixed board size. All measurements were taken in still air on a 4-layer FR-4 board with 1 oz solid internal planes and 2 oz top/bottom external trace planes with a total board thickness of 1.6mm. PCB layers, copper weight, board layout and thermal vias affect the resultant thermal resistance. For further information on thermal resistance and high thermal conductivity test boards, refer to JEDEC standard JESD51, notably JESD51-12 and JESD51-7. Achieving low thermal resistance necessitates attention to detail and careful PCB layout. With the QFN package soldered to maximum copper area, the thermal resistance is 30C/W. So the junction temperature rise above ambient equals: Table 3. UFD Plastic Package, 28-Lead QFN COPPER AREA TOPSIDE* BACK SIDE BOARD AREA THERMAL RESISTANCE (JUNCTION-TO-AMBIENT) 2500mm2 2500mm2 2500mm2 30C/W 1000mm2 2500mm2 2500mm2 32C/W 225mm2 2500mm2 2500mm2 33C/W 100mm2 2500mm2 2500mm2 35C/W *Device is mounted on topside Example: Given an output voltage of 0.9V, an input voltage range of 1.2V 5%, a BIAS voltage of 2.5V, a maximum output current of 4A and a maximum ambient temperature of 50C, what will the maximum junction temperature be? The power dissipated by the device equals: IOUT(MAX) * (VIN(MAX) - VOUT) + (IBIAS - IGND) * VOUT + IGND * VBIAS where: IOUT(MAX) = 4A VIN(MAX) = 1.26V IBIAS at (IOUT = 4A, VBIAS = 2.5V) = 6.91mA IGND at (IOUT = 4A, VBIAS = 2.5V) = 0.87mA thus: P = 4A(1.26V - 0.9V) + (6.91mA - 0.87mA)0.9V + 0.87mA(2.5V) = 1.448W 1.448W at 30C/W = 43.44C The maximum junction temperature equals the maximum ambient temperature plus the maximum junction temperature rise above ambient or: TJMAX = 50C + 43.44C = 93.44C Applications that cannot support extensive PCB space for heat sinking the LT3070-1 require a derating of output current or increased airflow. Paralleling Devices for Higher IOUT Multiple LT3070-1s may be paralleled to obtain higher output current. This paralleling concept borrows from the scheme employed by the LT3080. To accomplish this paralleling, tie the REF/BYP pins of the paralleled regulators together. This effectively gives an averaged value of multiple 600mV reference voltage sources. Tie the OUT pins of the paralleled regulators to Rev 0 For more information www.analog.com 23 LT3070-1 APPLICATIONS INFORMATION the common load plane through a small piece of PC trace ballast or an actual surface mount sense resistor beyond the primary output capacitors of each regulator. The required ballast is dependent upon the application output voltage and peak load current. The recommended ballast is that value which contributes 1% to load regulation. For example, two LT3070-1 regulators configured to output 1V, sharing a 10A load require 2m of ballast at each output. The Kelvin SENSE pins connect to the regulator side of the ballast resistors to keep the individual control loops from conflicting with each other (see Figure 8 and Figure 9). Keep this ballast trace area free of solder to maintain a controlled resistance. Table 4 shows a simple guideline for PCB trace resistance as a function of weight and trace width. Table 4. PC Board Trace Resistance WEIGHT (Oz) 100 MIL WIDTH* 200 MIL WIDTH* 1 5.43 2.71 2 2.71 1.36 VIN 1.5V 50k PWRGD 2.2F IN 330F BIAS EN PWRGD SENSE OUT VO0 VO1 LT3070-1 VO2 NC MARGSEL NC MARGTOL VIOC 1nF The LT3070-1 offers numerous noise performance advantages. Each LDO has several sources of noise. An LDO's most critical noise source is the reference, followed by the LDO error amplifier. Traditional low noise regulators buffer the voltage reference out to an external pin (usually through a large value resistor) to allow for bypassing and noise reduction of reference noise. The LT3070-1 deviates from the traditional voltage reference by generating a low voltage VREF from a reference current into an internal resistor 19k. This intermediate impedance node (REF/BYP) facilitates external filtering directly. A 10nF filter capacitor minimizes reference noise to 10VRMS at the 600mV REF/BYP pin, equivalently a 17V contribution to output noise at VOUT = 1V. See the Typical Performance Characteristics for Noise vs Output Voltage performance as a function of CREF/BYP . This approach also accommodates reference sharing between LT3070-1 regulators that are hooked up in current sharing applications. The REF/BYP filter capacitor delays the initial power-up time by a factor of the RC time constant. VREF is disabled in nap mode, thus start-up time is well controlled coming out of nap mode (EN:LOHI), soft-starting the output. *Trace resistance is measured in milliohms/in VBIAS 2.5V TO 3.6V Quieting the Noise REF/BYP GND 2.2F* 4.7F* 10F* VOUT 1.2V 5A *X5R OR X7R CAPACITORS 0.01F 30701 F06 Figure 6. 1.5V to 1.2V Linear Regulator Rev 0 24 For more information www.analog.com LT3070-1 APPLICATIONS INFORMATION VBIAS 3.3V 47F 6.3V x3 1 50k SVIN NC PGOOD RUN PVIN PVIN SVIN TRACK SW PVIN SW PVIN SW PLLLPF SW CLKOUT VO0 VO2 NC MARGTOL NC MARGSEL 100F 6.3V x2 SVIN VIOC 10k 2.2F* LT3070-1 VO1 NC ITH NC PWRGD SENSE 2k 4.7nF VOUT 1V 5A 10F* OUT MGN ITHM MODE IN NC 20k VFB PGND CLKIN BIAS EN 1.3V/5A 47F BSEL PHMODE NC 0.2H SGND LTC3415EUHF NC PWRGD 2.2F 0.1F 4.7F* *X5R OR X7R CAPACITORS REF/BYP GND 0.01F 1nF SGND PGND PGND PGND PGND 30701 F07 PGND PGND NOTE: LTC3415 SWITCHER, 2MHz INTERNAL OSCILLATOR LTC3415 AND LT3070-1 ON SAME PCB POWER PLANE Figure 7. Regulator with VIOC Buck Control VBIAS 3.3V 47F 6.3V x3 50k 1 PWRGD 2.2F SVIN NC 0.1F PGOOD RUN NC PVIN PVIN SVIN TRACK SW PVIN SW PVIN SW PLLLPF SW CLKOUT LTC3415EUHF CLKIN MODE PGND PGND PGND PGND IN PWRGD SENSE NC VO0 NC VO1 2.2F* LT3070-1 ITH NC MARGTOL NC MARGSEL 15k 1% ITHM VIOC 17.5k 1% SGND EN P.O.L. 2 BIAS IN 47F RTRACE 3m CONTROLLED POWER PLANE 1V/8A 0.01F 2.2F PGND PGND NOTE: LTC3415 SWITCHER, 2MHz INTERNAL OSCILLATOR LTC3415 AND LT3070-1 x2 ON SAME PCB POWER PLANE 10F* P.O.L. 1 REF/BYP GND 1nF 100F 6.3V x2 4.7F* *X5R OR X7R CAPACITORS MGN NC VOUT 1V 3.5A OUT VO2 VFB PGND BIAS EN 1.3V/7A 47F BSEL PHMODE NC 0.2H SGND RTRACE 3m CONTROLLED PWRGD SENSE OUT NC VO0 NC VO1 LT3070-1 VO2 MARGTOL NC MARGSEL VIOC 4.7F* 10F* *X5R OR X7R CAPACITORS NC 1nF 2.2F* VOUT 1V 3.5A REF/BYP GND 0.01F 30701 F08 Figure 8. 1V, 7A Point-of-Load Current Sharing Regulators Rev 0 For more information www.analog.com 25 LT3070-1 APPLICATIONS INFORMATION 50k VIN 3.3V EN NC VO0 NC VO1 VO2 NC MARGTOL NC MARGSEL 1nF NC 10F 10F NC NC NC SW1 CLKIN1 CLKOUT1 CLKIN2 CLKOUT2 VIN1 VOUT1 SVIN1 MGN1 RUN1 FB1 PLLLPF1 ITH1 MODE1 ITHM1 PHMODE1 BSEL1 TRACK1 PGOOD1 LTM4616 VIN2 VOUT2 SVIN2 MGN2 RUN2 FB2 PLLLPF2 ITH2 MODE2 ITHM2 PHMODE2 BSEL2 TRACK2 PGOOD2 SW2 SGND1 GND1 VIN 3.3V NC EN 100F 6.3V X5R 10k NC NC 4.7nF VBUCK2 2.1V/8A VO1 VO2 NC MARGTOL NC MARGSEL VIOC EN VO0 4.7nF RTRACE 2.5m CONTROLLED P.O.L. 1 POWER PLANE 1V/7A 0.01F RTRACE 2.5m CONTROLLED PWRGD SENSE 10F* VOUT 1V 4A 10F* VOUT 1.8V 5A 10F* VOUT 1.5V 3A OUT 2.2F* 4.7F* *X5R OR X7R CAPACITORS REF/BYP GND BIAS 0.01F VO1 VO2 NC MARGTOL NC MARGSEL 1nF VIN 3.3V PWRGD SENSE LT3070-1 NC VIOC 2k 10F* *X5R OR X7R CAPACITORS LT3070-1 IN 20k 4.7F* 2.2F 47F 10k BIAS NC VIN 3.3V NC 2.2F* P.O.L. 2 VO0 1nF VOUT 1V 4A OUT REF/BYP GND NC NC NC SGND2 GND2 NOTE: THE TWO LTM4616 MODULE CHANNELS ARE INDEPENDENTLY CONTROLLED BY THE VIOC CONTROLS FROM THE LINEAR REGULATORS LT3070-1 IN 47F 2k 100F 6.3V X5R VIOC PWRGD SENSE 2.2F VBUCK1 1.3V/8A 20k BIAS IN 47F VIN 3.3V PWRGD 2.2F OUT 2.2F* 4.7F* *X5R OR X7R CAPACITORS REF/BYP GND 0.01F 2.2F EN BIAS IN 47F VO0 NC NC NC NC VO1 VO2 PWRGD SENSE LT3070-1 OUT MARGTOL 2.2F* 4.7F* *X5R OR X7R CAPACITORS MARGSEL VIOC 1nF REF/BYP GND 0.01F 30701 F09 Figure 9. Triple Output Supply Providing 1V, 8A and 1.8V, 5A and 1.5V, 3A Rev 0 26 For more information www.analog.com LT3070-1 PACKAGE DESCRIPTION UFD Package 28-Lead Plastic QFN (4mm x 5mm) (Reference LTC DWG # 05-08-1712 Rev C) 0.70 0.05 4.50 0.05 3.10 0.05 2.50 REF 2.65 0.05 3.65 0.05 PACKAGE OUTLINE 0.25 0.05 0.50 BSC 3.50 REF 4.10 0.05 5.50 0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 4.00 0.10 (2 SIDES) 0.75 0.05 R = 0.05 TYP PIN 1 NOTCH R = 0.20 OR 0.35 x 45 CHAMFER 2.50 REF R = 0.115 TYP 27 28 0.40 0.10 PIN 1 TOP MARK (NOTE 6) 1 2 5.00 0.10 (2 SIDES) 3.50 REF 3.65 0.10 2.65 0.10 (UFD28) QFN 0816 REV C 0.25 0.05 0.200 REF 0.50 BSC 0.00 - 0.05 BOTTOM VIEW--EXPOSED PAD NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGHD-3). 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE Rev 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license For is granted implication or otherwise under any patent or patent rights of Analog Devices. more by information www.analog.com 27 LT3070-1 TYPICAL APPLICATION 50k VBIAS 2.5V TO 3.6V VIN 1.5V PWRGD 2.2F BIAS IN 330F EN VO0 VO1 PWRGD SENSE LT3070-1 OUT VO2 NC MARGSEL NC MARGTOL VIOC 1nF REF/BYP GND 2.2F* 4.7F* 10F* VOUT 1.2V 5A *X5R OR X7R CAPACITORS 0.01F 30701 TA02 1.5V to 1.2V Linear Regulator RELATED PARTS PART DESCRIPTION COMMENTS LT1763 500mA, Low Noise LDO 300mV Dropout Voltage, Low Noise: 20VRMS, VIN: 1.8V to 20V, SO-8 Package LT1764/LT1764A 3A, Fast Transient Response, Low Noise LDO 340mV Dropout Voltage, Low Noise: 40VRMS, VIN: 2.7V to 20V, TO-220 and DD Packages "A" Version Stable Also with Ceramic Caps LT1963/LT1963A 1.5A Low Noise, Fast Transient Response LDO 340mV Dropout Voltage, Low Noise: 40VRMS, VIN: 2.5V to 20V, "A" Version Stable with Ceramic Caps, TO-220, DD, SOT-223 and SO-8 Packages LT1965 1.1A, Low Noise, Low Dropout Linear Regulator 290mV Dropout Voltage, Low Noise: 40VRMS, VIN: 1.8V to 20V, VOUT : 1.2V to 19.5V, Stable with Ceramic Caps, TO-220, DD-Pak, MSOP and 3mm x 3mm DFN Packages LT3021 500mA, Low Voltage, VLDOTM Linear Regulator VIN: 0.9V to 10V, Dropout Voltage = 160mV (Typ), Adjustable Output (VREF = VOUT(MIN) = 200mV), Fixed Output Voltages: 1.2V, 1.5V, 1.8V, Stable with Low ESR, Ceramic Output Capacitors 16-Pin DFN (5mm x 5mm) and 8-Lead SO Packages LT3080/LT3080-1 1.1A, Parallelable, Low Noise, Low Dropout Linear Regulator 300mV Dropout Voltage (2-Supply Operation), Low Noise: 40VRMS, VIN: 1.2V to 36V, VOUT: 0V to 35.7V, Current-Based Reference with 1 Resistor VOUT Set; Directly Parallelable (No Op Amp Required), Stable with Ceramic Caps, TO-220, SOT-223, MSOP-8 and 3mm x 3mm DFN-8 Packages; LT3080-1 has Integrated Internal Ballast Resistor LT3085 500mA, Parallelable, Low Noise, Low Dropout Linear Regulator 275mV Dropout Voltage (2-Supply Operation), Low Noise: 40VRMS, VIN: 1.2V to 36V, VOUT: 0V to 35.7V, Current-Based Reference with 1 Resistor VOUT Set; Directly Parallelable (No Op Amp Required), Stable with Ceramic Caps, MSOP-8 and 2mm x 3mm DFN-6 Packages LTC3025-1/ LTC3025-2 500mA Micropower VLDO Linear Regulator in 2mm x 2mm DFN VIN = 0.9V to 5.5V, Dropout Voltage: 75mV, Low Noise 80VRMS, Low IQ: 54A, Fixed Output: 1.2V (LTC3025-2); Adjustable Output Range: 0.4V to 3.6V (LTC3025-1) 2mm x 2mm 6-Lead DFN Package LTC3026 1.5A, Low Input Voltage VLDO Regulator VIN: 1.14V to 3.5V (Boost Enabled), 1.14V to 5.5V (with External 5V), VDO = 0.1V, IQ = 950A, Stable with 10F Ceramic Capacitors, 10-Lead MSOP and DFN-10 Packages LT3071 5A, Low Noise, Programmable Output, 85mV Dropout Linear VIN: 0.95V to 3V, VOUT: 0.8V to 1.8V in 50mV Increments, Low Regulator with Analog Margining Noise: 25VRMS, Stable with Ceramic Capacitors, 4mm x 5mm 28-Lead QFN Package Rev 0 28 D17101-0-9/18(0) www.analog.com For more information www.analog.com ANALOG DEVICES, INC. 2018