EMC4243-67-5 - Advanced Connection Technology Inc.

LT3070-1

Rev 0

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APPLICATIONS

n FPGA and DSP Supplies

n ASIC and Microprocessor Supplies

n Servers and Storage Devices

n Post Buck Regulation and Supply Isolation

TYPICAL APPLICATION

DESCRIPTION

5A, Low Noise, Programmable Output,

85mV Dropout Linear Regulator

The LT

3070-1 is a low voltage, UltraFast™ transient

response linear regulator. The device supplies up to 5A

of output current with a typical dropout voltage of 85mV.

A 0.01µF reference bypass capacitor decreases output

voltage noise to 25µVRMS. The LT3070-1 EN pin controls

the reference soft-start behavior in comparison to the

LT3070 which controls the reference soft-start via the

BIAS pin supply voltage. The LT3070-1’s high bandwidth

permits the use of low ESR ceramic capacitors, saving

bulk capacitance and cost. The LT3070-1’s features make

it ideal for high performance FPGAs, microprocessors or

sensitive communication supply applications.

Output voltage is digitally selectable in 50mV increments

over a 0.8V to 1.8V range. A margining function allows

the user to adjust system output voltage in increments of

±1%, ±3% or ±5%. The IC incorporates a unique tracking

function to control a buck regulator powering the LT3070-

1’s input. This tracking function drives the buck regulator

to maintain the LT3070-1’s input voltage to VOUT + 300mV,

minimizing power dissipation.

Internal protection includes UVLO, reverse-current protec-

tion, precision current limiting with power foldback and

thermal shutdown. The LT3070-1 regulator is available in

a thermally enhanced 28-lead, 4mm × 5mm QFN package.

0.9V, 5A Regulator

FEATURES

n Output Current: 5A

n Dropout Voltage: 85mV Typical

n Enable Function Soft-Starts the Reference

n Digitally Programmable VOUT

: 0.8V to 1.8V

n Digital Output Margining: ±1%, ±3% or ±5%

n Low Output Noise: 25µVRMS (10Hz to 100kHz)

n Parallel Multiple Devices for 10A or More

n Precision Current Limit: ±20%

n ±1% Accuracy Over Line, Load and Temperature

n Stable with Low ESR Ceramic Output Capacitors

(15µF Minimum)

n High Frequency PSRR: 30dB at 1MHz

n VIOC Pin Controls Buck Converter to Maintain Low

Power Dissipation and Optimize Efﬁciency

n PWRGD/UVLO/Thermal Shutdown Flag

n Current Limit with Foldback Protection

n Thermal Shutdown

n 28-Lead (4mm × 5mm × 0.75mm) QFN Package

Dropout Voltage

BIAS

50k

LT3070-1

VO0

VO1

330µF

2.2µF

2.2µF*

0.01µF1nF

4.7µF*

*X5R OR X7R CAPACITORS

3070-1 TA01a

10µF*

PWRGD

VOUT

0.9V

VO2

MARGSEL

MARGTOL

VIOC

SENSE

OUT

VBIAS

2.2V TO 3.6V

VIN

1.2V PWRGD

REF/BYP

GND

All registered trademarks and trademarks are the property of their respective owners.

OUTPUT CURRENT (A)

DROPOUT VOLTAGE (mV)

120

150

3070-1 TA01b

01235

VOUT = 1.8V

VBIAS = 3.3V

VOUT = 0.8V

VBIAS = 2.5V

VIN = VOUT(NOMINAL)

LT3070-1

Rev 0

For more information www.analog.com

IN, OUT ..................................................... –0.3V to 3.3V

BIAS ............................................................. –0.3V to 4V

VO2, VO1, VO0 Inputs .................................... –0.3V to 4V

MARGSEL, MARGTOL Input ........................ –0.3V to 4V

EN Input ....................................................... –0.3V to 4V

SENSE Input ................................................. –0.3V to 4V

VIOC, PWRGD Outputs ................................ –0.3V to 4V

REF/BYP Output ........................................... –0.3V to 4V

Output Short-Circuit Duration……...................Indefinite

Operating Junction Temperature (Note 2)

LT3070-1E/LT3070-1I ........................ –40°C to 125°C

LT3070-1MP ...................................... –55°C to 125°C

Storage Temperature Range .................. –65°C to 150°C

(Note 1)

9 10

TOP VIEW

GND

UFD PACKAGE

28-LEAD (4mm × 5mm) PLASTIC QFN

TJMAX = 125°C, θJA = 30°C/W TO 35°C/W

EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB

11 12 13

28 27 26 25 24

VIOC

PWRGD

REF/BYP

GND

MARGTOL

MARGSEL

GND

SENSE

OUT

BIAS

GND

VO2

VO1

VO0

GND

815

ORDER INFORMATION

PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LT3070EUFD-1#PBF LT3070EUFD-1#TRPBF 30701 28-Lead (4mm × 5mm) Plastic QFN –40°C to 125°C

LT3070IUFD-1#PBF LT3070IUFD-1#TRPBF 30701 28-Lead (4mm × 5mm) Plastic QFN –40°C to 125°C

LT3070MPUFD-1#PBF LT3070MPUFD-1#TRPBF 30701 28-Lead (4mm × 5mm) Plastic QFN –55°C to 125°C

LEAD BASED FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LT3070EUFD-1 LT3070EUFD-1#TR 30701 28-Lead (4mm × 5mm) Plastic QFN –40°C to 125°C

LT3070IUFD-1 LT3070IUFD-1#TR 30701 28-Lead (4mm × 5mm) Plastic QFN –40°C to 125°C

LT3070MPUFD-1 LT3070MPUFD-1#TR 30701 28-Lead (4mm × 5mm) Plastic QFN –55°C to 125°C

Consult ADI Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.

LT3070-1

Rev 0

For more information www.analog.com

ELECTRICAL CHARACTERISTICS

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. COUT = 15µF (Note 9), VIN = VOUT + 0.3V (Note 5), VBIAS = 2.5V unless

otherwise noted.

PARAMETER CONDITIONS MIN TYP MAX UNITS

IN Pin Voltage Range VIN ≥ VOUT + 150mV, IOUT= 5A l0.95 3.0 V

BIAS Pin Voltage Range (Note 3) l2.2 3.6 V

Regulated Output Voltage VOUT = 0.8V, 10mA ≤ IOUT ≤ 5A, 1.05V ≤ VIN ≤ 1.25V

VOUT = 0.9V, 10mA ≤ IOUT ≤ 5A, 1.15V ≤ VIN ≤ 1.35V

VOUT = 1V, 10mA ≤ IOUT ≤ 5A, 1.25V ≤ VIN ≤ 1.45V

VOUT = 1.1V, 10mA ≤ IOUT ≤ 5A, 1.35V ≤ VIN ≤ 1.55V

VOUT = 1.2V, 10mA ≤ IOUT ≤ 5A, 1.45V ≤ VIN ≤ 1.65V, VBIAS = 3.3V

VOUT = 1.5V, 10mA ≤ IOUT ≤ 5A, 1.75V ≤ VIN ≤ 1.95V, VBIAS = 3.3V

VOUT = 1.8V, 10mA ≤ IOUT ≤ 5A, 2.05V ≤ VIN ≤ 2.25V, VBIAS = 3.3V

0.792

0.891

0.990

1.089

1.188

1.485

1.782

0.800

0.900

1.000

1.100

1.200

1.500

1.800

0.808

0.909

1.010

1.111

1.212

1.515

1.818

Regulated Output Voltage Margining

(Note 3)

MARGTOL = 0V, MARGSEL = VBIAS

MARGTOL = 0V, MARGSEL = 0V, IOUT = 10mA

0.8

–1.2

–1

1.2

–0.8

MARGTOL = FLOAT, MARGSEL = VBIAS

MARGTOL = FLOAT, MARGSEL = 0V, IOUT = 10mA

2.7

–3.3

–3

3.3

–2.7

MARGTOL = VBIAS, MARGSEL= VBIAS

MARGTOL = VBIAS, MARGSEL = 0V, IOUT = 10mA

4.6

–5.4

–5

5.4

–4.6

Line Regulation to VIN VOUT = 0.8V, ∆VIN = 1.05V to 2.7V, VBIAS = 3.3V, IOUT = 10mA

VOUT = 1.8V, ∆VIN = 2.05V to 2.7V, VBIAS = 3.3V, IOUT = 10mA

1.0

Line Regulation to VBIAS VOUT = 0.8V, ∆VBIAS = 2.2V to 3.6V, VIN = 1.1V, IOUT = 10mA

VOUT = 1.8V, ∆VBIAS = 3.25V to 3.6V, VIN = 2.1V, IOUT = 10mA

2.0

1.0

Load Regulation,

∆IOUT = 10mA to 5A

VBIAS = 2.5V, VIN = 1.05V, VOUT = 0.8V

–1.5 –3.0

–5.5

VBIAS = 2.5V, VIN = 1.25V, VOUT = 1.0V

–2 –4.0

–7.5

VBIAS = 3.3V, VIN = 1.45V, VOUT = 1.2V

–2 –4.0

–7.5

VBIAS = 3.3V, VIN = 1.75V, VOUT = 1.5V

–2.5 –5.0

–9.0

VBIAS = 3.3V, VIN = 2.05V, VOUT = 1.8V

–3 –7.0

–13

Dropout Voltage,

VIN = VOUT(NOMINAL) (Note 6)

IOUT = 1A, VOUT = 1V l20 35 mV

IOUT = 2.5A, VOUT = 1V

50 65

IOUT = 5A, VOUT = 1V

85 120

150

SENSE Pin Current VIN = 1.1V, VSENSE = 0.8V

VBIAS = 3.3V, VIN = 2.1V, VSENSE = 1.8V

200

300

400

µA

LT3070-1

Rev 0

For more information www.analog.com

ELECTRICAL CHARACTERISTICS

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. COUT = 15µF (Note 9), VIN = VOUT + 0.3V (Note 5), VBIAS = 2.5V unless

otherwise noted.

PARAMETER CONDITIONS MIN TYP MAX UNITS

Ground Pin Current,

VIN = 1.3V, VOUT = 1V

IOUT = 10mA

IOUT = 5A

0.65

0.9

1.1

1.35

1.8

2.3

BIAS Pin Current in Nap Mode EN = Low l120 200 320 µA

BIAS Pin Current,

VIN = 1.3V, VOUT = 1V

IOUT = 10mA

IOUT = 100mA

IOUT = 500mA

IOUT = 1A

IOUT = 2.5A

IOUT = 5A

0.75

1.25

2.0

2.6

3.5

4.5

1.08

1.8

3.0

3.8

5.2

6.9

1.5

2.4

4.0

5.0

7.0

10.0

Current Limit (Note 5) VIN – VOUT < 0.3V, VBIAS = 3.3V

VIN – VOUT = 1.0V, VBIAS = 3.3V

VIN – VOUT = 1.7V, VBIAS = 3.3V

5.1

3.2

1.2

6.4

4.5

2.5

7.7

5.8

4.3

Reverse Output Current (Note 8) VIN = 0V, VOUT = 1.8V l300 450 µA

PWRGD VOUT Threshold Percentage of VOUT(NOMINAL), VOUT Rising

Percentage of VOUT(NOMINAL), VOUT Falling

PWRGD VOL IPWRGD = 200µA (Fault Condition) l50 150 mV

VBIAS Undervoltage Lockout VBIAS Rising

VBIAS Falling

1.1

0.9

1.55

1.4

2.1

1.7

VIN-VOUT Servo Voltage by VIOC l250 300 350 mV

VIOC Output Current VIN = VOUT(NOMINAL) + 150mV, Sourcing Out of the Pin

VIN = VOUT(NOMINAL) + 450mV, Sinking Into the Pin

160

170

235

255

310

340

µA

VIL Input Threshold (Logic-0 State),

VO2, VO1, VO0, MARGSEL, MARGTOL

Input Falling l0.25 V

VIZ Input Range (Logic-Z State),

VO2, VO1, VO0, MARGSEL, MARGTOL

l0.75 VBIAS – 0.9 V

VIH Input Threshold (Logic-1 State),

VO2, VO1, VO0, MARGSEL, MARGTOL

Input Rising lVBIAS – 0.25 V

Input Hysteresis (Both Thresholds),

VO2, VO1, VO0, MARGSEL, MARGTOL

60 mV

Input Current High,

VO2, VO1, VO0, MARGSEL, MARGTOL

VIH = VBIAS = 2.5V, Current Flows Into Pin l25 40 µA

Input Current Low,

VO2, VO1, VO0, MARGSEL, MARGTOL

VIL = 0V, VBIAS = 2.5V, Current Flows Out of Pin l25 40 µA

EN Pin Threshold VOUT = Off to On, VBIAS = 2.5V

VOUT = On to Off, VBIAS = 2.5V

VOUT = Off to On, VBIAS =2.2V to 3.6V

VOUT = On to Off, VBIAS =2.2V to 3.6V

0.9

0.36 • VBIAS

1.4

0.56 • VBIAS

EN Pin Logic High Current VEN = VBIAS = 2.5V l2.5 4.0 6.5 µA

LT3070-1

Rev 0

For more information www.analog.com

ELECTRICAL CHARACTERISTICS

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. COUT = 15µF (Note 9), VIN = VOUT + 0.3V (Note 5), VBIAS = 2.5V unless

otherwise noted.

PARAMETER CONDITIONS MIN TYP MAX UNITS

EN Pin Logic Low Current VEN = 0V l0.1 µA

VBIAS Ripple Rejection VBIAS = VOUT + 1.5VAVG, VRIPPLE =0.5VP-P , fRIPPLE = 120Hz,

VIN – VOUT = 300mV, IOUT = 2.5A

75 dB

VIN Ripple Rejection

(Notes 3, 4, 5)

VBIAS = 2.5V, VRIPPLE = 50mVP-P

, fRIPPLE = 120Hz,

VIN – VOUT = 300mV, IOUT = 2.5A

66 dB

Reference Voltage Noise

(REF/BYP Pin)

CREF/BYP = 10nF, BW = 10Hz to 100kHz 10 µVRMS

Output Voltage Noise VOUT = 1V, IOUT = 5A, CREF/BYP = 10nF, COUT = 15µF,

BW = 10Hz to 100kHz

25 µVRMS

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: The LT3070-1 regulators are tested and specified under pulse load

conditions such that TJ ≅ TA. The LT3070-1E is 100% tested at TA = 25°C.

Performance at –40°C and 125°C is assured by design, characterization

and correlation with statistical process controls. The LT3070-1I is

guaranteed over the –40°C to 125°C operating junction temperature range.

The LT3070-1MP is 100% tested and guaranteed over the –55°C to 125°C

operating junction temperature range.

Note 3: To maintain proper performance and regulation, the BIAS supply

voltage must be higher than the IN supply voltage. For a given VOUT

, the

BIAS voltage must satisfy the following conditions: 2.2V ≤ VBIAS ≤ 3.6V

and VBIAS ≥ (1.25 • VOUT + 1V). For VOUT ≤ 0.95V, the minimum BIAS

voltage is limited to 2.2V.

Note 4: Operating conditions are limited by maximum junction

temperature. The regulated output voltage specification does not apply

for all possible combinations of input voltage and output current. When

operating at maximum output current, limit the input voltage range to

VIN < VOUT + 500mV.

Note 5: The LT3070-1 incorporates safe operating area protection

circuitry. Current limit decreases as the VIN-VOUT voltage increases.

Current limit foldback starts at VIN – VOUT > 500mV. See the Typical

Performance Characteristics for a graph of Current Limit vs VIN – VOUT

voltage. The current limit foldback feature is independent of the thermal

shutdown circuity.

Note 6: Dropout voltage, VDO, is the minimum input to output voltage

differential at a specified output current. In dropout, the output voltage

equals VIN – VDO.

Note 7: GND pin current is tested with VIN = VOUT(NOMINAL) + 300mV and a

current source load. VIOC is a buffered output determined by the value of

VOUT as programmed by the VO2-VO0 pins. VIOC’s output is independent

of the margining function.

Note 8: Reverse output current is tested with the IN pins grounded and the

OUT + SENSE pins forced to the rated output voltage. This is measured as

current into the OUT + SENSE pins.

Note 9: Frequency Compensation: The LT3070-1 must be frequency

compensated at its OUT pins with a minimum COUT of 15µF configured

as a cluster of (15×) 1µF ceramic capacitors or as a graduated cluster

of 10µF/4.7µF/2.2µF ceramic capacitors of the same case size. Linear

Technology only recommends X5R or X7R dielectric capacitors.

LT3070-1

Rev 0

For more information www.analog.com

TYPICAL PERFORMANCE CHARACTERISTICS

Dropout Voltage vs VBIAS

Output Voltage (0.8V)

vs Temperature

Dropout Voltage vs IOUT Dropout Voltage vs Temperature

Dropout Voltage vs Temperature

OUTPUT CURRENT (A)

DROPOUT VOLTAGE (mV)

120

150

30701 G01

01235

VOUT = 1.8V

VBIAS = 3.3V

VOUT = 0.8V

VBIAS = 2.5V

VIN = VOUT(NOMINAL)

TJ = 25°C

TEMPERATURE (°C)

DROPOUT VOLTAGE (mV)

–25 25 75 125

30701 G02

175–50–75 0 50 100 150

VIN = VOUT(NOMINAL)

IOUT = 1A

VOUT = 1.8V, VBIAS = 3.3V

VOUT = 0.8V, VBIAS = 2.5V

VOUT = 1.2V, VBIAS = 3.3V

TEMPERATURE (°C)

–75

DROPOUT VOLTAGE (mV)

100

125

30701 G03

0–25–50 250 75 100 150

50 175

VIN = VOUT(NOMINAL)

IOUT = 2.5A

VOUT = 1.8V, VBIAS = 3.3V

VOUT = 0.8V, VBIAS = 2.5V

VOUT = 1.2V, VBIAS = 3.3V

TEMPERATURE (°C)

–75

OUTPUT VOLTAGE (V)

0.808

0.806

0.804

0.802

0.800

0.798

0.796

0.794

0.792 125

30701 G06

–25 25 75 175100–50 0 50 150

ILOAD = 10mA

BIAS VOLTAGE (V)

2.2

DROPOUT VOLTAGE (mV)

100

200

140

2.6 3.0 3.2

30701 G05

160

180

120

2.4 2.8 3.4 3.6

OUT = 1.8V

OUT = 1.5V

OUT = 0.8V

IOUT = 5A

TJ = 25°C

Output Voltage (1V)

vs Temperature

TEMPERATURE (°C)

–75

OUTPUT VOLTAGE (V)

1.002

1.006

1.010

125

30701 G07

0.998

0.994

1.000

1.004

1.008

0.996

0.992

0.990 –25–50 250 75 100 150

50 175

ILOAD = 10mA

Output Voltage (1.2V)

vs Temperature

TEMPERATURE (°C)

1.188

OUTPUT VOLTAGE (V)

1.196

1.204

1.212

1.192

1.200

1.208

–25 25 75 125

30701 G08

175–50–75 0 50 100 150

ILOAD = 10mA

Output Voltage (1.5V)

vs Temperature

TEMPERATURE (°C)

1.485

OUTPUT VOLTAGE (V)

1.495

1.505

1.515

1.490

1.500

1.510

–25 25 75 125

30701 G09

175–50–75 0 50 100 150

ILOAD = 10mA

TEMPERATURE (°C)

–75

DROPOUT VOLTAGE (mV)

120

150

125

30701 G04

0–50 –25 0 25 50 75 100 150 175

VIN = VOUT(NOMINAL)

IOUT = 5A

VOUT = 1.8V, VBIAS = 3.3V

VOUT = 0.8V, VBIAS = 2.5V

VOUT = 1.2V, VBIAS = 3.3V

LT3070-1

Rev 0

For more information www.analog.com

TYPICAL PERFORMANCE CHARACTERISTICS

BIAS Pin Current in Nap Mode BIAS Pin Current vs IOUT

GND Pin Current vs IOUT

REF/BYP Pin Voltage

vs Temperature

BIAS Pin Undervoltage Lockout

Threshold

Output Voltage (1.8V)

vs Temperature

TEMPERATURE (°C)

–75

1.782

OUTPUT VOLTAGE (V)

1.786

1.794

1.798

1.802

75 100 125 150

1.818

30701 G10

1.790

–50 –25 0 25 50 175

1.806

1.810

1.814

ILOAD = 10mA

OUTPUT CURRENT (A)

GND PIN CURRENT (mA)

0.5

1.0

1.5

2.0

2.5

3.0

1 2 3 4

30701 G11

VOUT = 1.8V, VBIAS = 3.3V

VOUT = 1.2V, VBIAS = 3.3V

VOUT = 0.8V, VBIAS = 2.5V

VIN = VOUT + 300mV

TJ = 25°C

TEMPERATURE (°C)

594

REF/BYP VOLTAGE (mV)

598

602

606

596

600

604

–25 25 75 125

30701 G12

175–50–75 0 50 100 150

CREF/BYP = 0.01µF

TEMPERATURE (°C)

–75

BIAS PIN CURRENT (µA)

400

350

300

250

200

150

100

0125

30701 G13

–25 25 75 175100–50 0 50 150

VBIAS = 2.5V

VEN = 0V

OUTPUT CURRENT (A)

BIAS PIN CURRENT (mA)

30701 G14

01235

VOUT = 1.8V

VBIAS = 3.3V

VOUT = 0.8V

VBIAS = 2.5V

VIN = VOUT + 300mV

TJ = 25°C

TEMPERATURE (°C)

–75

UVLO THRESHOLD VOLTAGE (V)

1.5

2.0

2.5

125

30701 G15

1.0

0.5

0–50 –25 0 25 50 75 100 150 175

VBIAS RISING

VBIAS FALLING

EN Pin Thresholds

Enable Pin Threshold and

Hysteresis vs VBIAS PWRGD Threshold Voltage

TEMPERATURE (°C)

–75

ENABLE PIN THRESHOLD (V)

1.2

1.6

2.0

125

30701 G16

0.8

0.4

1.0

1.4

1.8

0.6

0.2

0–25–50 250 75 100 150

50 175

VBIAS = 2.5V

EN PIN RISING

EN PIN FALLING

TEMPERATURE (°C)

–75

PWRGD TRESHOLD VOLTAGE (V)

0.90

0.95

125

30701 G18

0.85

0.80 –25 25 50 175

1.00

VOUT FALLING

–50 0150

100

VBIAS = 2.5V

VOUT = 1V

VOUT RISING

BIAS VOLTAGE (V)

ENABLE/DISABLE THRESHOLD (V)

2.0

2.5

3.0

30701 G17

1.5

1.0

02.5 33.5

0.5

4.0

3.5

MAX ENABLE

MIN DISABLE

TYP ENABLE

TYP DISABLE

TJ = –55°C TO 125°C

TYPICAL HYSTERESIS = 150mV

VBIAS

LT3070-1

Rev 0

For more information www.analog.com

TYPICAL PERFORMANCE CHARACTERISTICS

SENSE Pin Current

Logic Input Threshold Voltages

Logic Low to Hi-Z State Transitions

Logic Pin Input Current,

High State

EN Pin Logic High Current

TEMPERATURE (°C)

–75

LOGIC INPUT THRESHOLD VOLTAGE (V)

0.6

0.7

0.8

125

30701 G20

0.5

0.4

0.3 –50 –25 0 25 50 75 100 150 175

INPUT RISING

LOGIC LOW TO Hi-Z

INPUT FALLING

LOGIC Hi-Z TO LOW

SEE APPLICATIONS INFORMATION

FOR MORE DETAILS

Logic Input Threshold Voltages

Logic Hi-Z to High State Transitions

TEMPERATURE (°C)

–75

LOGIC INPUT THRESHOLD VOLTAGE (V)

2.8

2.9

3.0

125

30701 G21

2.7

2.6

2.5 –50 –25 0 25 50 75 100 150 175

INPUT FALLING

LOGIC HIGH TO Hi-Z

INPUT RISING

LOGIC Hi-Z TO HIGH

VBIAS = 3.3V

LOGIC Hi-Z TO HIGH THRESHOLD IS

RELATIVE TO VBIAS VOLTAGE

SEE APPLICATIONS INFORMATION

FOR MORE DETAILS

TEMPERATURE (°C)

–75

EN PIN LOGIC HIGH CURRENT (µA)

4.0

5.0

6.0

125

30701 G22

3.0

2.0

3.5

4.5

5.5

2.5

1.5

1.0 –25–50 250 75 100 150

50 175

VEN = VBIAS = 2.5V

TEMPERATURE (°C)

–75

LOGIC PIN INPUT CURRENT (µA)

0125

30701 G23

–25 25 75 175100–50 0 50 150

VLOGIC = VBIAS = 2.5V

CURRENT FLOWS INTO THE PIN

Logic Pin Input Current,

Low State

TEMPERATURE (°C)

–75

LOGIC PIN INPUT CURRENT (µA)

0125

30701 G24

–25 25 75 175100–50 0 50 150

VBIAS = 2.5V

VLOGIC = 0V

CURRENT FLOWS OUT OF THE PIN

TEMPERATURE (°C)

–75

SENSE PIN CURRENT (µA)

25 125

30701 G25

–25 25 75 175100–50 0 50 150

VBIAS = 2.5V

VOUT = 0.8V

CURRENT FLOWS INTO SENSE

SENSE Pin Current Current Limit vs Temperature

TEMPERATURE (°C)

–75

SENSE PIN CURRENT (µA)

400

375

350

325

300

275

250

225

200 125

30701 G26

–25 25 75 175100–50 0 50 150

VBIAS = 3.3V

VOUT = 1.8V

CURRENT FLOWS INTO SENSE

TEMPERATURE (°C)

–75

CURRENT LIMIT (A)

7.50

7.00

6.75

6.50

6.25

7.25

6.00

5.75

5.50

5.25

5.00 125

30701 G27

–25 25 75 175100–50 0 50 150

VIN – VOUT(NOMINAL) = 300mV

VOUT = 1.8V, VBIAS = 3.3V

VOUT = 1.2V, VBIAS = 3.3V

VOUT = 0.8V, VBIAS = 2.5V

PWRGD VOL vs Temperature

TEMPERATURE (°C)

–75

PWRGD VOL VOLTAGE (mV)

100

125

30701 G19

0–25 25 75

–50 050 100 150

VBIAS = 2.5V

IPWRGD = 200µA

LT3070-1

Rev 0

For more information www.analog.com

TYPICAL PERFORMANCE CHARACTERISTICS

BIAS Pin Ripple Rejection IN Pin Ripple RejectionCurrent Limit vs VIN – VOUT

IN-TO-OUT VOLTAGE DIFFERENTIAL (V)

CURRENT LIMIT (A)

2.00

30701 G28

00.50 1.00 1.50

0.25 0.75 1.25 1.75

VOUT = 1.8V

VOUT = 1.2V

VOUT = 0.8V

VBIAS = 3.3V

TJ = 25°C

FREQUENCY (Hz)

10 100

BIAS PIN RIPPLE REJECTION (dB)

1k 10k 100k 1M 10M

30701 G29

100

VBIAS = 2.5V + 500mVP-P

VBIAS = 2.7V + 500mVP-P

VBIAS = 3.3V + 500mVP-P

VIN = 1.3V

VOUT = 1V

IOUT = 5A

COUT = 10µF + 4.7µF + 2.2µF

FREQUENCY (Hz)

10 100

IN PIN RIPPLE REJECTION (dB)

1k 10k 100k 1M 10M

30701 G30

COUT = 117µF

COUT = 16.9µF

VOUT = 1V

VIN = 1.3V + 50mVP-P RIPPLE

VBIAS = 2.5V

IOUT = 1A

IN Pin Ripple Rejection

vs VIN – VOUT, 1V/5A

IN Pin Ripple Rejection

vs VIN – VOUT, 1V/2.5A

IN Pin Ripple Rejection

vs VIN – VOUT, 1V/1A

FREQUENCY (Hz)

10 100

IN PIN RIPPLE REJECTION (dB)

1k 10k 100k 1M 10M

30701 G31

COUT = 117µF

COUT = 16.9µF

VOUT = 1V

VIN = 1.3V + 50mVP-P RIPPLE

VBIAS = 2.5V

IOUT = 5A

AVERAGE INPUT/OUTPUT DIFFERENTIAL (V)

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

100

110

120

PSRR (dB)

30701 G32

50mVP-P RIPPLE ON V

OUT

= 16.9μF

BIAS

= 2.5V

= 25°C

RIPPLE AT f = 10kHz

RIPPLE AT f = 100kHz

RIPPLE AT f = 1MHz

AVERAGE INPUT/OUTPUT DIFFERENTIAL (V)

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

100

110

120

PSRR (dB)

30701 G33

50mVP-P RIPPLE ON V

OUT

= 16.9μF

BIAS

= 2.5V

= 25°C

RIPPLE AT f = 10kHz

RIPPLE AT f = 100kHz

RIPPLE AT f = 1MHz

AVERAGE INPUT/OUTPUT DIFFERENTIAL (V)

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

100

110

120

PSRR (dB)

30701 G34

50mVP-P RIPPLE ON V

OUT

= 16.9μF

BIAS

= 2.5V

= 25°C

RIPPLE AT f = 10kHz

RIPPLE AT f = 100kHz

RIPPLE AT f = 1MHz

AVERAGE INPUT/OUTPUT DIFFERENTIAL (V)

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

100

110

120

PSRR (dB)

30701 G35

50mVP-P RIPPLE ON V

OUT

= 117μF

BIAS

= 2.5V

= 25°C

RIPPLE AT f = 10kHz

RIPPLE AT f = 100kHz

RIPPLE AT f = 1MHz

AVERAGE INPUT/OUTPUT DIFFERENTIAL (V)

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

100

110

120

PSRR (dB)

30701 G36

50mVP-P RIPPLE ON V

OUT

= 117μF

BIAS

= 2.5V

= 25°C

RIPPLE AT f = 10kHz

RIPPLE AT f = 100kHz

RIPPLE AT f = 1MHz

IN Pin Ripple Rejection

vs VIN – VOUT, 1V/5A

IN Pin Ripple Rejection

vs VIN – VOUT, 1V/2.5A

LT3070-1

Rev 0

For more information www.analog.com

Input Voltage Line Regulation

TEMPERATURE (°C)

INPUT VOLTAGE LINE REGULATION (µV)

100

200

300

150

250

–25 25 75 125

30701 G45

175–50–75 0 50 100 150

VBIAS = 3.3V

VIN = 2.05V TO 2.7V

VOUT = 1.8V

IOUT = 10mA

Input Voltage Line Regulation

TEMPERATURE (°C)

INPUT VOLTAGE LINE REGULATION (µV)

100

200

300

150

250

–25 25 75 125

30701 G44

175–50–75 0 50 100 150

VBIAS = 3.3V

VIN = 1.05V TO 2.7V

VOUT = 0.8V

IOUT = 10mA

Bias Voltage Line Regulation

TEMPERATURE (°C)

–75

BIAS VOLTAGE LINE REGULATION (µV)

400

300

200

100

–100

–200

–300

–400 125

30701 G43

–25 25 75 175100–50 0 50 150

VBIAS = 3.25V TO 3.6V

VIN = 2.1V

VOUT = 1.8V

IOUT = 10mA

Minimum BIAS Voltage

vs Temperature

Minimum BIAS Voltage vs VOUT

TEMPERATURE (°C)

–75

MINIMUM BIAS VOLTAGE (V)

3.2

3.6

4.0

125

30701 G38

2.8

2.4

3.0

3.4

3.8

2.6

2.2

2.0 –25–50 250 75 100 150

50 175

IOUT = 5A VOUT = 1.8V

VOUT = 1.2V

VOUT = 0.8V

Minimum BIAS Voltage vs IOUT

OUTPUT CURRENT (A)

MINIMUM BIAS VOLTAGE (V)

2.6

2.8

3.0

30701 G39

2.4

2.2

2.0 1 2 4

3.2

3.4

3.6

VOUT = 1.8V

VOUT = 1.5V

VOUT = 1.2V

VOUT = 0.8V TO 1V

VIN = VOUT(NOMINAL) + 300mV

ΔVOUT = –1%, TJ = 25°C

OUTPUT VOLTAGE (V)

0.7

MINIMUM BIAS VOLTAGE (V)

3.4

3.2

3.0

2.8

2.6

2.4

2.2

2.0

1.8 1.5

30701 G40

0.9 1.1 1.3 1.91.7

IOUT = 5A

TJ = 25°C

Bias Voltage Line Regulation

TEMPERATURE (°C)

–75

BIAS VOLTAGE LINE REGULATION (µV)

800

700

600

500

400

300

200

100

0125

30701 G42

–25 25 75 175100–50 0 50 150

VBIAS = 2.2V TO 3.6V

VIN = 1.1V

VOUT = 0.8V

IOUT = 10mA

Load Regulation

TEMPERATURE (°C)

–75

LOAD REGULATION (mV)

–4

–2

125

30701 G41

–6

–8

–10 –50 –25 0 25 50 75 100 150 175

VIN = VOUT(NOMINAL) + 300mV

VBIAS = 3.3V

ΔIOUT = 100mA TO 5A

VOUT = 0.8V

VOUT = 1.2V

VOUT = 1.8V

TYPICAL PERFORMANCE CHARACTERISTICS

AVERAGE INPUT/OUTPUT DIFFERENTIAL (V)

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

100

110

120

PSRR (dB)

30701 G37

50mVP-P RIPPLE ON V

OUT

= 117μF

BIAS

= 2.5V

= 25°C

RIPPLE AT f = 10kHz

RIPPLE AT f = 100kHz

RIPPLE AT f = 1MHz

IN Pin Ripple Rejection

vs VIN – VOUT, 1V/1A

LT3070-1

Rev 0

For more information www.analog.com

TYPICAL PERFORMANCE CHARACTERISTICS

RMS Output Noise

vs Output Current

RMS Output Noise

vs CREF/BYP

Output Noise (10Hz to 100kHz)

Output Noise Spectral Density

Input Voltage Line Transient

Response

VIOC Amplifier Output Current

vs Temperature

Bias Voltage Line Transient

Response

VIOC Amplifier IN-to-OUT Servo

Voltage

FREQUENCY (Hz)

0.01

NOISE SPECTRAL DENSITY (µV/√

Hz)

0.1

10 1k 10k 100k

30701 G46

0.001 100

1.0 VBIAS = 2.5V

VOUT = 1V

IOUT = 5A

COUT = 16.9µF

CREF/BYP = 0.01µF

OUTPUT CURRENT (A)

0.01

OUTPUT NOISE (µVRMS)

0.1 1 10

30701 G47

VIN = VOUT(NOMINAL) + 300mV

VBIAS = 3.3V

COUT = 16.9µF

CREF/BYP = 10nF

VOUT = 1.8V

VOUT = 1.2V

VOUT = 0.8V

= 25°C

= 5A

OUT

= 0.8V

OUT

= 16.9µF

REF/BYP CAPACITOR (F)

10n

100n

1µ

10µ

100

OUTPUT NOISE (uV

RMS

)

LT30701 G48

VOUT

100µV/DIV

1ms/DIVVOUT = 1V

IOUT = 5A

COUT = 16.9µF

30701 G49

VOUT

1mV/DIV

VIN

50mV/DIV

20µs/DIVVIN = 1.3V

VOUT = 1V

IOUT = 5A

COUT = 16.9µF

30701 G50

VOUT

10mV/DIV

VBIAS

200mV/DIV

20µs/DIVVIN = 1.3V

VBIAS = 2.5V

VOUT = 1V

IOUT = 5A

COUT = 16.9µF

30701 G51

TEMPERATURE (°C)

–75

VIOC IN-TO-OUT SERVO VOLTAGE (mV)

310

330

350

125

30701 G52

290

270

300

320

340

280

260

250 –25–50 250 75 100 150

50 175

VBIAS = 2.5V

TEMPERATURE (°C)

150

VIOC AMPLIFIER OUTPUT CURRENT (µA)

200

250

300

175

225

275

–25 25 75 125

30701 G53

175–50–75 0 50 100 150

IVIOC SOURCING

IVIOC SINKING

LT3070-1

Rev 0

For more information www.analog.com

TYPICAL PERFORMANCE CHARACTERISTICS

VOUT

50mV/DIV

AC-COUPLED

IOUT

2A/DIV

∆I = 500mA

TO 5A

20µs/DIVVOUT = 1V

COUT = 117µF

IOUT tRISE/tFALL = 100ns

30701 G55

Transient Load Response

Transient Load Response Transient Load Response

VOUT

50mV/DIV

AC-COUPLED

IOUT

2A/DIV

∆I = 500mA

TO 5A

20µs/DIVVOUT = 1V

COUT = 10µF + 4.7µF + 2.2µF

IOUT tRISE/tFALL = 1µs

30701 G56

VOUT

50mV/DIV

AC-COUPLED

IOUT

2A/DIV

∆I = 500mA

TO 5A

20µs/DIVVOUT = 1V

COUT = 117µF

IOUT tRISE/tFALL = 1µs

30701 G57

Output Voltage Start-Up Time

vs CREF/BYP EN Start-Up Response

SETTLING TO 1%

= 100mA

= 25°C

REF/BYP CAPACITOR (F)

100p

10n

100n

1µ

0.01

0.1

100

OUTPUT VOLTAGE START–UP TIME (ms)

LT30701 G58

OUT

= 1V

OUT

= 16.9µF

= 330µF

400µs/DIV

OUT

500mV/DIV

= 10Ω

REF

500mV/DIV

REF/BYP

= 10nF

2V/DIV

100mA/DIV

30701 G59

Transient Load Response

VOUT

50mV/DIV

AC-COUPLED

IOUT

2A/DIV

∆I = 500mA

TO 5A

20µs/DIVVOUT = 1V

COUT = 10µF + 4.7µF + 2.2µF

IOUT tRISE/tFALL = 100ns

30701 G54

LT3070-1

Rev 0

For more information www.analog.com

PIN FUNCTIONS

VIOC (Pin 1): Voltage for In-to-Out Control. The IC incorpo-

rates a unique tracking function to control a buck regulator

powering the LT3070-1’s input. The VIOC pin is the output

of this tracking function that drives the buck regulator to

maintain the LT3070-1’s input voltage at VOUT + 300mV.

This function maximizes efficiency and minimizes power

dissipation. See the Applications Information section for

more information on proper control of the buck regulator.

PWRGD (Pin 2): Power Good. The PWRGD pin is an open-

drain NMOS output that actively pulls low if any one of

these fault modes is detected:

• VOUT is less than 90% of VOUT(NOMINAL) on the rising

edge of VOUT

• VOUT drops below 85% of VOUT(NOMINAL) for more than

25µs.

• Junction temperature typically exceeds 145°C.

• VBIAS is less than its undervoltage lockout threshold.

• The OUT-to-IN reverse-current detector activates.

See the Applications Information section for more infor-

mation on PWRGD fault modes.

REF/BYP (Pin 3): Reference Filter. The pin is the output

of the bandgap reference and has an impedance of ap-

proximately 19kΩ. This pin must not be externally loaded.

Bypassing the REF/BYP pin to GND with a capacitor

decreases output voltage noise and provides a soft-start

function to the reference. ADI recommends the use of a

high quality, low leakage capacitor. See the Applications

Information section for more information on noise and

output voltage margining considerations.

GND (Pins 4, 9-14, 20, 26, 29): Ground. The exposed pad

(Pin 29) of the QFN package is an electrical connection to

GND. To ensure proper electrical and thermal performance,

solder Pin 29 to the PCB ground and tie to all GND pins

of the package. These GND pins are fused to the internal

die attach paddle and the exposed pad to optimize heat

sinking and thermal resistance characteristics. See the Ap-

plications Information section for thermal considerations

and calculating junction temperature.

IN (Pins 5, 6, 7, 8): Input Supply. These pins supply

power to the high current pass transistor. Tie all IN pins

together for proper performance. The LT3070-1 requires

a bypass capacitor at IN to maintain stability and low input

impedance over frequency. A 47µF input bypass capacitor

suffices for most battery and power plane impedances.

Minimizing input trace inductance optimizes performance.

Applications that operate with low VIN-VOUT differential

voltages and that have large, fast load transients may require

much higher input capacitor requirements to prevent the

input supply from drooping and allowing the regulator to

enter dropout. See the Applications Information section

for more information on input capacitor requirements.

OUT (Pins 15, 16, 17, 18): Output. These pins supply

power to the load. Tie all OUT pins together for proper

performance. A minimum output capacitance of 15µF is

required for stability. ADI recommends low ESR, X5R or

X7R dielectric ceramic capacitors for best performance.

A parallel ceramic capacitor combination of 10µF + 4.7µF

+ 2.2µF or 15 1µF ceramic capacitors in parallel provide

excellent stability and load transient response. Large load

transient applications require larger output capacitors to

limit peak voltage transients. See the Applications Infor-

mation section for more information on output capacitor

requirements.

SENSE (Pin 19): Kelvin Sense for OUT . The SENSE pin is

the inverting input to the error amplifier. Optimum regu-

lation is obtained when the SENSE pin is connected to

the OUT pins of the regulator. In critical applications, the

resistance (RP) of PCB traces between the regulator and the

load cause small voltage drops, creating a load regulation

error at the point of load. Connecting the SENSE pin at

the load instead of directly to OUT eliminates this voltage

error. Figure 1 illustrates this Kelvin-Sense connection

method. Note that the voltage drop across the external

PCB traces adds to the dropout voltage of the regulator.

The SENSE pin input bias current depends on the selected

output voltage. SENSE pin input current varies from 50µA

typically at VOUT = 0.8V to 300µA typically at VOUT = 1.8V.

LT3070-1

Rev 0

For more information www.analog.com

PIN FUNCTIONS

MARGSEL (Pin 21): Margining Enable and Polarity Se-

lection. This three-state pin determines both the polarity

and the active state of the margining function. The logic

low threshold is less than 250mV referenced to GND and

enables negative voltage margining. The logic high thresh-

old is greater than VBIAS – 250mV and enables positive

voltage margining. The voltage range between these two

logic thresholds as set by a window comparator defines

the logic Hi-Z state and disables the margining function.

MARGTOL (Pin 22): Margining Tolerance. This three-

state pin selects the absolute value of margining (1%,

3% or 5%) if enabled by the MARGSEL input. The logic

low threshold is less than 250mV referenced to GND and

enables either ±1% change in VOUT depending on the state

of the MARGSEL pin. The logic high threshold is greater

than VBIAS – 250mV and enables either ±5% change in

VOUT depending on the state of the MARGSEL pin. The

voltage range between these two logic thresholds as set

by a window comparator defines the logic Hi-Z state and

enables either ±3% change in VOUT depending on the state

of the MARGSEL pin.

VO0, VO1 and VO2 (Pins 23, 24, 25): Output Voltage Se-

lect. These three-state pins combine to select a nominal

output voltage from 0.8V to 1.8V in increments of 50mV.

Output voltage is limited to 1.8V maximum by an internal

override of VO1 when VO2 = high. The input logic low

threshold is less than 250mV referenced to GND and the

logic high threshold is greater than VBIAS – 250mV. The

range between these two thresholds as set by a window

comparator defines the logic Hi-Z state. See Table 1 in the

Applications Information section that defines the VO2, VO1

and VO0 settings versus VOUT

BIAS (Pin 27): Bias Supply. This pin supplies current to

the internal control circuitry and the output stage driving

the pass transistor. The LT3070-1 requires a minimum

2.2µF bypass capacitor for stability and proper operation.

To ensure proper operation, the BIAS voltage must satisfy

the following conditions: 2.2V ≤ VBIAS ≤ 3.6V and VBIAS ≥

(1.25 • VOUT + 1V). For VOUT ≤ 0.95V, the minimum BIAS

voltage is limited to 2.2V.

EN (Pin 28): Enable. This pin enables/disables the reference

output and output power device. The internal reference and

all support functions are active if VBIAS is above its UVLO

threshold. Pulling EN low disables the REF/BYP pin current

and the output pass transistor, putting the LT3070-1 into

a low power nap mode. The maximum rising EN threshold

is ratioed to 0.56 % of VBIAS and the minimum falling EN

threshold is 0.36 % of VBIAS. Drive the EN pin with either

a digital logic port or an open-collector NPN or an open-

drain NMOS terminated with a pull-up resistor to VBIAS.

The pull-up resistor must be less than 35k to meet the VIH

condition of the EN pin. If unused, connect EN to BIAS.

BIAS

LT3070-1

VO2

VO1

VBIAS

VIN

VO0

MARGSEL

MARGTOL

VIOC

SENSE

OUT

PWRGD

REF/BYP

GND

RP30701 F01

LOAD

Figure 1. Kelvin Sense Connection

LT3070-1

Rev 0

For more information www.analog.com

BLOCK DIAGRAM

–

EAMP

REF/BYP

ISENSE

BUF

LDO CORE

OUT

SENSE

PWRGD

REF/BYP

600mV

30701 BD

VIOC

27 BIAS

5-8

VOUT(NOM) + 300mV

VO2

VO1

VO0

MARGSEL

MARGTOL

15-18

DETECT

VREF

PROGRAM CONTROL

UVLO AND

THERMAL

SHUTDOWN

–

GND

4,9-14,20,26,29

VBIAS – 0.25V

VBIAS – 0.9V

0.75V

100k

TO INTERNAL ENABLE

SEE ENABLE THRESHOLD

CURVE

VO2, VO1, VO0

MARGSEL OR

MARGTOL

0.25V

LOGIC HIGH STATE

LOGIC LOW STATE

LOGIC Hi-Z STATE

HIGH IF IN < VBIAS – 0.9V

AND IN > 0.75V

HIGH IF IN < 0.25V

TO LOGIC

HIGH IF IN > VBIAS – 0.25V

–

100k

VBIAS

LT3070-1

Rev 0

For more information www.analog.com

APPLICATIONS INFORMATION

Introduction

Current generation FPGA and ASIC processors place

stringent demands on the power supplies that power the

core, I/O and transceiver channels. These microprocessors

may cycle load current from near zero to amps in tens of

nanoseconds. Output voltage specifications, especially in

the 1V range, require tight tolerances including transient

response as part of the requirement. Some ASIC processors

require only a single output voltage from which the core

and I/O circuitry operate. Some high performance FPGA

processors require separate power supply voltages for the

processor core, the I/O, and the transceivers. Often, these

supply voltages must be low noise and high bandwidth

to achieve the lowest bit-error rates. These requirements

mandate the need for very accurate, low noise, high cur-

rent, very high speed regulator circuits that operate at low

input and output voltages.

The LT3070-1 is a low voltage, UltraFast transient response

linear regulator. The device supplies up to 5A of output

current with a typical dropout voltage of 85mV. A 0.01µF

reference bypass capacitor decreases output voltage noise

to 25µVRMS (BW = 10Hz to 100kHz). The LT3070-1’s high

bandwidth provides UltraFast transient response using low

ESR ceramic output capacitors (15µF minimum), saving

bulk capacitance, PCB area and cost.

The LT3070-1’s features permit state-of-the-art linear

regulator performance. The LT3070-1 is ideal for high

performance FPGAs, microprocessors, sensitive com-

munication supplies, and high current logic applications

that also operate over low input and output voltages.

Output voltage for the LT3070-1 is digitally selectable in

50mV increments over a 0.8V to 1.8V range. A margining

function allows the user to adjust system output voltage

in increments of ±1%, ±3% or ±5%.

The IC incorporates a unique tracking function, which if

enabled by the user, controls an upsteam regulator pow-

ering the LT3070-1’s input (see Figure 7). This tracking

function drives the buck regulator to maintain the LT3070-

1’s input voltage to VOUT + 300mV. This input-to-output

voltage control allows the user to change the regulator

output voltage, and have the switching regulator power-

ing the LT3070-1’s input to track to the optimum input

voltage with no component changes.

This combines the efficiency of a switching regulator

with superior linear regulator response. It also permits

thermal management of the system even with a maximum

5A output load.

LT3070-1 internal protection includes input undervoltage

lockout (UVLO), reverse-current protection, precision cur-

rent limiting with power foldback and thermal shutdown.

The LT3070-1 regulator is available in a thermally enhanced

28-lead, 4mm × 5mm QFN package.

The LT3070-1’s architecture drives an internal N-channel

power MOSFET as a source follower. This configuration

permits a user to obtain an extremely low dropout, UltraFast

transient response regulator with excellent high frequency

PSRR performance. The LT3070-1 achieves superior

regulator bandwidth and transient load performance by

eliminating expensive bulk tantalum or electrolytic capaci-

tors in the most modern and demanding microprocessor

applications. Users realize significant cost savings as all

additional bulk capacitance is removed. The additional

savings of insertion cost, purchasing/inventory cost and

board space are readily apparent. Precision incremental

output voltage control accommodates legacy and future

microprocessor power supply voltages.

Output capacitor networks simplify to direct parallel com-

binations of ceramic capacitors. Often, the high frequency

ceramic decoupling capacitors required by these various

FPGA and ASIC processors are sufficient to stabilize the

system (see Stability and Output Capacitance section). This

regulator design provides ample bandwidth and responds

to transient load changes in a few hundred nanoseconds

versus regulators that respond in many microseconds.

The LT3070-1 also incorporates precision current limiting,

enable/disable control of output voltage and integrated

overvoltage and thermal shutdown protection. The LT3070-

1’s unique design combines the benefits of low dropout

voltage, high functional integration, precision performance

and UltraFast transient response, as well as providing

significant cost savings on the output capacitance needed

in fast load transient applications.

As lower voltage applications become increasingly preva-

lent with higher frequency switching power supplies, the

LT3070-1 offers superior regulation and an appreciable

LT3070-1

Rev 0

For more information www.analog.com

APPLICATIONS INFORMATION

component cost savings. The LT3070-1 steps to the next

level of performance for the latest generation FPGAs, DSPs

and microprocessors. The simple versatility and benefits

derived from these circuits exceed the power supply needs

of today’s high performance microprocessors.

Programming Output Voltage

Three tri-level input pins, VO2, VO1 and VO0, select the

value of output voltage. Table 1 illustrates the 3-bit digital

word to output voltage resulting from setting these pins

high, low or allowing them to float.

These pins may be tied high or low by either pin-strapping

them to VBIAS or driving them with digital ports. Pins that

float may either actually float or require logic that has

Hi-Z output capability. This allows output voltage to be

dynamically changed if necessary.

Output voltage is selectable from a minimum of 0.8V to

a maximum of 1.8V in increments of 50mV. The MSB,

VO2, sets the pedestal voltage, and the LSB’s, VO1 and

VO0 increment VOUT

Output voltage is limited to 1.8V maximum by an internal

override of VO1 (default to low) when VO2 = high.

Table 1. VO2 to VO0 Settings vs Output Voltage

VO2 VO1 VO0 VOUT(NOM) VO2 VO1 VO0 VOUT(NOM)

0 0 0 0.80V Z 0 1 1.35V

0 0 Z 0.85V Z Z 0 1.40V

0 0 1 0.90V Z Z Z 1.45V

0 Z 0 0.95V Z Z 1 1.50V

0 Z Z 1.00V Z 1 0 1.55V

0 Z 1 1.05V Z 1 Z 1.60V

0 1 0 1.10V Z 1 1 1.65V

0 1 Z 1.15V 1 X 0 1.70V

0 1 1 1.20V 1 X Z 1.75V

Z 0 0 1.25V 1 X 1 1.80V

Z 0 Z 1.30V

X = Don’t Care, 0 = Low, Z = Float, 1 = High

The input logic low threshold is less than 250mV refer-

enced to GND and the logic high threshold is greater than

VBIAS – 250mV. The range between these two thresholds

as set by a window comparator defines the logic Hi-Z state.

REF/BYP—Voltage Reference

This pin is the buffered output of the internal bandgap

reference and has an output impedance of ≅19kΩ. The

design includes an internal compensation pole at fC =

4kHz. A 10nF REF/BYP capacitor to GND creates a low-

pass pole at fLP = 840Hz. The 10nF capacitor decreases

reference voltage noise to about 10µVRMS and soft-starts

the reference. The LT3070-1 soft-starts the reference

voltage when the EN pin is toggled from low to high. In

comparison, the LT3070 soft-starts only when turning

the BIAS supply voltage on. Output voltage noise is the

RMS sum of the reference voltage noise in addition to the

amplifier noise. Curves for start-up time and output noise

vs REF/BYP capacitance appear in the Typical Performance

Characteristics section.

The REF/BYP pin must not be DC loaded by anything except

for applications that parallel other LT3070-1 regulators for

higher output currents. Consult the Applications Section

on Paralleling for further details.

Output Voltage Margining

Two tri-level input pins, MARGSEL (polarity) and MARGTOL

(scale), select the polarity and amount of output voltage

margining. Margining is programmable in increments of

±1%, ±3% and ±5%. Margining is internally implemented

as a scaling of the reference voltage.

Table 2 illustrates the 2-bit digital word to output voltage

margining resulting from setting these pins high, low or

allowing them to float.

These pins may be set high or low by either pin-strapping

them to VBIAS or driving them with digital ports. Pins that

float may either actually float or require logic that has

“Hi-Z” output capability. This allows output voltage to be

dynamically margined if necessary.

The MARGSEL pin determines both the polarity and the ac-

tive state of the margining function. The logic low threshold

is less than 250mV referenced to GND and enables negative

voltage margining. The logic high threshold is greater than

VBIAS – 250mV and enables positive voltage margining.

The voltage range between these two logic thresholds as

set by a window comparator defines the logic Hi-Z state

and disables the margining function.

LT3070-1

Rev 0

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The MARGTOL pin selects the absolute value of margin-

ing (1%, 3% or 5%) if enabled by the MARGSEL input.

The logic low threshold is less than 250mV referenced to

GND and enables either ±1% change in VOUT depending

on the state of the MARGSEL pin. The logic high threshold

is greater than VBIAS – 250mV and enables either ±5%

change in VOUT depending on the state of the MARGSEL

pin. The voltage range between these two logic thresholds

as set by a window comparator defines the logic Hi-Z state

and enables either ±3% change in VOUT depending on the

state of the MARGSEL pin.

Table 2. Programming Margining

MARGSEL MARGTOL % OF VOUT(NOM)

0 0 –1

0 Z –3

0 1 –5

Z00

ZZ0

Z10

101

1Z3

115

Enable Function—Turning On and Off

The EN pin enables/disables the reference output and output

power device. The LT3070-1's support functions remain

active if VBIAS is above its UVLO threshold. Pulling the EN

pin low puts the LT3070-1 into nap mode. In nap mode,

the output is disabled and quiescent current decreases.

Drive the EN pin with either a digital logic port or an open-

collector NPN or an open-drain NMOS terminated with

a pull-up resistor to VBIAS. The pull-up resistor must be

less than 35k to meet the VIH condition of the EN pin. If

unused, connect EN to BIAS.

Input Undervoltage Lockout on BIAS Pin

An internal undervoltage lockout (UVLO) comparator

monitors the BIAS supply voltage. If VBIAS drops below

the UVLO threshold, all functions shut down, the pass

transistor is gated off and output current falls to zero. The

typical BIAS pin UVLO threshold is 1.55V on the rising

edge of VBIAS. The UVLO circuit incorporates about 150mV

of hysteresis on the falling edge of VBIAS.

High Efficiency Linear Regulator—Input-to-Output

Voltage Control

The VIOC (voltage input-to-output control) pin is a func-

tion to control a switching regulator and facilitate a design

solution that maximizes system efficiency at high load cur-

rents and still provides low dropout voltage performance.

The VIOC pin is the output of an integrated transcon-

ductance amplifier that sources and sinks about 250µA

of current. It typically regulates the output of most LTC

switching regulators or LTM

power modules, by sinking

current from the ITH compensation node. The VIOC func-

tion controls a buck regulator powering the LT3070-1’s

input by maintaining the LT3070-1’s input voltage to VOUT

+ 300mV. This 300mV VIN-VOUT differential voltage is

chosen to provide fast transient response and good high

frequency PSRR while minimizing power dissipation and

maximizing efficiency. For example, 1.5V to 1.2V conver-

sion and 1.3V to 1V conversion yield 1.5W maximum

power dissipation at 5A full output current.

Figure 2 depicts that the switcher’s feedback resistor net-

work sets the maximum switching regulator output volt-

age if the linear regulator is disabled. However, once the

LT3070-1 is enabled, the VIOC feedback loop decreases the

switching regulator output voltage back to VOUT + 300mV.

Using the VIOC function creates a feedback loop between

the LT3070-1 and the switching regulator. As such, the

feedback loop must be frequency compensated for sta-

bility. Fortunately, the connection of VIOC to many ADI

switching regulator ITH pins represents a high impedance

characteristic which is the optimum circuit node to fre-

quency compensate the feedback loop. Figure 2 illustrates

the typical frequency compensation network used at the

VIOC node to GND.

The VIOC amplifier characteristics are:

gm = 3.2mS, IOUT = ±250µA, BW = 10MHz.

If the VIOC function is not used, terminate the VIOC pin to

GND with a small capacitor (1000pF) to prevent oscillations.

LT3070-1

Rev 0

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REFERENCE

LT3070-1

VREF

VOUT +

300mV

OUT

VIOC

30701 F02

LOAD

–

PWM

SWITCHING REGULATOR

REF

ITH

Figure 2. VIOC Control Block Diagram

PWRGD—Power Good

PWRGD pin is an open-drain NMOS digital output that

actively pulls low if any one of these fault modes is detected:

• VOUT is less than 90% of VOUT(NOMINAL) on the rising

edge of VOUT

• VOUT drops below 85% of VOUT(NOMINAL) for more than

25µs.

• VBIAS is less than its undervoltage lockout threshold.

• The OUT-to-IN reverse-current detector activates.

• Junction temperature exceeds 145°C typically.*

*The junction temperature detector is an early warning

indicator that trips approximately 20°C before thermal

shutdown engages.

Stability and Output Capacitance

The LT3070-1’s feedback loop requires an output capaci-

tor for stability. Choose COUT carefully and mount it in

close proximity to the LT3070-1’s OUT and GND pins.

Include wide routing planes for OUT and GND to minimize

inductance. If possible, mount the regulator immediately

adjacent to the application load to minimize distributed

inductance for optimal load transient performance. Point-

of-Load applications present the best case layout scenario

for extracting full LT3070-1 performance.

Low ESR, X5R or X7R ceramic chip capacitors are the

ADI recommended choice for stabilizing the LT3070-1.

Additional bulk capacitors distributed beyond the immedi-

ate decoupling capacitors are acceptable as their parasitic

ESL and ESR, combined with the distributed PCB induc-

tance isolates them from the primary compensation pole

provided by the local surface mount ceramic capacitors.

The LT3070-1 requires a minimum output capacitance

of 15µF for stability. ADI strongly recommends that the

output capacitor network consist of several low value

ceramic capacitors in parallel.

Why Do Multiple, Small-Value Output Capacitors

Connected in Parallel Work Better?

The LT3070-1’s unity-gain bandwidth with COUT of 15µF is

about 1MHz at its full-load current of 5A. Surface mounted

MLCC capacitors have a self-resonance frequency of

fR = 1/(2π√LC), which must be pushed to a frequency higher

than the regulator bandwidth. Standard MLCC capacitors

are acceptable. To keep the resonant frequency greater

than 1MHz, the product 1/(2π√LC) must be greater than

1MHz. At this bandwidth, PCB vias can add significant

inductance, thus the fundamental decoupling capacitors

must be mounted on the same plane as the LT3070-1.

Typical 0603 or 0805 case-size capacitors have an ESL of

~800pH and PCB mounting can contribute up to ~200pH.

Thus, it becomes necessary to reduce the parasitic in-

ductance by using a parallel capacitor combination. A

LT3070-1

Rev 0

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suitable methodology must control this paralleling as

capacitors with the same self-resonant frequency, fR, will

form a tank circuit that can induce ringing of their own

accord. Small amounts of ESR (5mΩ to 20mΩ) have some

benefit in dampening the resonant loop, but higher ESRs

degrade the capacitor response to transient load steps

with rise/fall times less than 1µs. The most area efficient

parallel capacitor combination is a graduated 4/2/1 scale

of fR of the same case size. Under these conditions, the

individual ESLs are relatively uniform, and the resonance

peaks are deconstructively spread beyond the regulator

bandwidth. The recommended parallel combination that

approximates 15µF is 10µF + 4.7µF + 2.2µF. Capacitors

with case sizes larger than 0805 have higher ESL and

lower ESR (<5mΩ). Therefore, more capacitors with

smaller values (<10µF) must be chosen. Users should

consider new generation, low inductance capacitors to

push out fR and maximize stability. Refer to the surface

mount ceramic capacitor manufacturer’s data sheets for

capacitor specifications. Figure 3 illustrates an optimum

PCB layout for the parallel output capacitor combination,

but also illustrates the GND connection between the IN

capacitor and the OUT capacitors to minimize the AC

GND loop for fast load transients. This tight bypassing

connection minimizes EMI and optimizes bypassing.

Many of the applications in which the LT3070-1 excels,

such as FPGA, ASIC processor or DSP supplies, typically

require a high frequency decoupling capacitor network for

the device being powered. This network generally consists

of many low value ceramic capacitors in parallel. In some

applications, this total value of capacitance may be close to

the LT3070-1’s minimum 15µF capacitance requirement.

This may reduce the required value of capacitance directly

at the LT3070-1’s output. Multiple low value capacitors

in parallel present a favorable frequency characteristic

that pushes many of the parasitic poles/zeroes beyond

the LT3070-1’s unity-gain crossover frequency. This

technique illustrates the method that extracts the full

bandwidth performance of the LT3070-1.

Give additional consideration to the use of ceramic ca-

pacitors. Ceramic capacitors are manufactured with a

variety of dielectrics, each with different behavior across

temperature and applied voltage. The most common

dielectrics used are specified with EIA temperature char-

acteristic codes of Z5U, Y5V, X5R and X7R. The Z5U and

Y5V dielectrics are good for providing high capacitances

in a small package, but they tend to have strong voltage

and temperature coefficients as shown in Figure 4 and

Figure 5. When used with a 5V regulator, a 16V 10µF Y5V

capacitor can exhibit an effective value as low as 1µF to

2µF for the DC bias voltage applied and over the operating

temperature range. The X5R and X7R dielectrics result in

more stable characteristics and are more suitable for use

as the output capacitor. The X7R type has better stability

across temperature, while the X5R is less expensive and

is available in higher values. Care still must be exercised

when using X5R and X7R capacitors; the X5R and X7R

codes only specify operating temperature range and maxi-

mum capacitance change over temperature. Capacitance

change due to DC bias with X5R and X7R capacitors

is better than Y5V and Z5U capacitors, but can still be

significant enough to drop capacitor values below ap-

propriate levels. Capacitor DC bias characteristics tend to

improve as component case size increases, but expected

capacitance at operating voltage should be verified. Voltage

and temperature coefficients are not the only sources of

problems. Some ceramic capacitors have a piezoelectric

response. A piezoelectric device generates voltage across

its terminals due to mechanical stress, similar to the way

a piezoelectric microphone works. For a ceramic capacitor

the stress can be induced by vibrations in the system or

thermal transients.

2.2µF

4.7µF

10µF

47µF

30701 F03

Lo-Z

INPUT

LOAD PLANE

LT3070-1

SENSE

IN OUT

GND

Figure 3. Example PCB Layout

LT3070-1

Rev 0

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Stability and Input Capacitance

The LT3070-1 is stable with a minimum capacitance of

47µF connected to its IN pins. Use low ESR capacitors to

minimize instantaneous voltage drops under large load

transient conditions. Large VIN droops during large load

transients may cause the regulator to enter dropout with

corresponding degradation in load transient response.

Increased values of input and output capacitance may be

necessary depending on an application’s requirements.

Sufficient input capacitance is critical as the circuit is in-

tentionally operated close to dropout to minimize power.

Ideally, the output impedance of the supply that powers

IN should be less than 10mΩ to support a 5A load with

large transients.

In cases where wire is used to connect a power supply to

the input of the LT3070-1 (and also from the ground of the

LT3070-1 back to the power supply ground), large input

capacitors are required to avoid an unstable application.

This is due to the inductance of the wire forming an LC

tank circuit with the input capacitor and not a result of the

LT3070-1 being unstable. The self inductance, or isolated

inductance, of a wire is directly proportional to its length.

However, the diameter of a wire does not have a major

influence on its self inductance. For example, one inch of

18-AWG, 0.04 inch diameter wire has 28nH of self induc-

tance. The self inductance of a 2-AWG isolated wire with

a diameter of 0.26 inch is about half the inductance of a

18-AWG wire. The overall self inductance of a wire can be

reduced in two ways. One is to divide the current flowing

towards the LT3070-1 between two parallel conductors

which flows in the same direction in each. In this case,

the farther the wires are placed apart from each other, the

more inductance will be reduced, up to a 50% reduction

when placed a few inches apart. Splitting the wires basi-

cally connects two equal inductors in parallel. However,

when placed in close proximity from each other, mutual

inductance is added to the overall self inductance of the

wires. The most effective way to reduce overall inductance

is to place the forward and return-current conductors (the

wire for the input and the wire for the return ground) in

very close proximity. Two 18-AWG wires separated by 0.05

inch reduce the overall self inductance to about one-fourth

of a single isolated wire. If the LT3070-1 is powered by a

battery mounted in close proximity with ground and power

planes on the same circuit board, a 47µF input capacitor

is sufficient for stability. However, if the LT3070-1 is

input capacitor on the order of 330µF. As power supply

output impedance varies, the minimum input capacitance

needed for application stability also varies.

Bias Pin Capacitance Requirements

The BIAS pin supplies current to most of the internal

control circuitry and the output stage driving the pass

transistor. The LT3070-1 requires a minimum 2.2µF

bypass capacitor for stability and proper operation. To

ensure proper operation, the BIAS voltage must sat-

isfy the following conditions: 2.2V ≤ VBIAS ≤ 3.6V and

VBIAS ≥ (1.25 • VOUT + 1V). For VOUT ≤ 0.95V, the

minimum BIAS voltage is limited to 2.2V.

DC BIAS VOLTAGE (V)

–100

CHANGE IN VALUE (%)

–80

–60

–40

–20

4 8 12 16

30701 F04

2 6 10

X5R

Y5V

BOTH CAPACITORS ARE 16V,

1210 CASE SIZE, 10µF

TEMPERATURE (°C)

–50

–20

25 75

X5R

Y5V

30701 F05

–40

–60

–25 0 50 100 125

–80

–100

CHANGE IN VALUE (%)

BOTH CAPACITORS ARE 16V,

1210 CASE SIZE, 10µF

Figure 4. Ceramic Capacitor DC Bias Characteristics

Figure 5. Ceramic Capacitor Temperature Characteristics

LT3070-1

Rev 0

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Load Regulation

The LT3070-1 provides a Kelvin sense pin for VOUT , allowing

the application to correct for parasitic package and PCB

I-R drops. However, ADI recommends that the SENSE pin

terminate in close proximity to the LT3070-1’s OUT pins.

This minimizes parasitic inductance and optimizes regula-

tion. The LT3070-1 handles moderate levels of output line

impedance, but excessive impedance between VOUT and

COUT causes excessive phase shift in the feedback loop

and adversely affects stability.

Figure 1 in the Pin Functions section illustrates the Kelvin-

Sense connection method that eliminates voltage drops

due to PCB trace resistance. However, note that the voltage

drop across the external PCB traces adds to the dropout

voltage of the regulator. The SENSE pin input bias current

depends on the selected output voltage. SENSE pin input

current varies from 50µA typically at VOUT = 0.8V to 300µA

typically at VOUT = 1.8V.

Short-Circuit and Overload Recovery

Like many IC power regulators, the LT3070-1 has safe

operating area (SOA) protection. The safe area protection

decreases current limit as input-to-output voltage increases

and keeps the power transistor inside a safe operating

region for all values of input-to-output voltage up to the

absolute maximum voltage rating. VBIAS must be above

the UVLO threshold for any function. The LT3070-1 has

a precision current limit specified at ±20% that is active

if VBIAS is above UVLO.

Under conditions of maximum ILOAD and maximum

VIN-VOUT the device’s power dissipation peaks at about

3W. If ambient temperature is high enough, die junction

temperature will exceed the 125°C maximum operating

temperature. If this occurs, the LT3070-1 relies on two

additional thermal safety features. At about 145°C, the

PWRGD output pulls low providing an early warning of

an impending thermal shutdown condition. At 165°C typi-

cally, the LT3070-1’s thermal shutdown engages and the

output is shut down until the IC temperature falls below

the thermal hysteresis limit. The SOA protection decreases

current limit as the IN-to-OUT voltage increases and keeps

the power dissipation at safe levels for all values of input-

to-output voltage. The LT3070-1 provides some output

current at all values of input-to-output voltage up to the

absolute maximum voltage rating. See the Current Limit

vs VIN curve in the Typical Performance Characteristics.

During start-up, after the BIAS voltage has cleared its UVLO

threshold and VIN is increasing, output voltage increases

at the rate of current limit charging COUT

With a high input voltage, a problem can occur where the

removal of an output short will not allow the output voltage

to recover. Other regulators with current limit foldback

also exhibit this phenomenon, so it is not unique to the

LT3070-1. The load line for such a load may intersect the

output current curve at two points: normal operation and

the SOA restricted load current settings. A common situ-

ation is immediately after the removal of a short circuit,

but with a static load ≥ 1A. In this situation, removal of the

load or reduction of IOUT to <1A will clear this condition

and allow VOUT to return to normal regulation.

Reverse Voltage

The LT3070-1 incorporates a circuit that detects if VIN

decreases below VOUT

. This reverse-voltage detector has

a typical threshold of about (VIN – VOUT) = –6mV. If the

threshold is exceeded, this detector circuit turns off the

drive to the internal NMOS pass transistor, thereby turning

off the output. The output pulls low with the load current

discharging the output capacitance. This circuit’s intent

is to limit and prevent back-feed current from OUT to IN

if the input voltage collapses due to a fault or overload

condition. It should be noted that a negative (−) reverse

detection threshold implies that a small back-feed cur-

rent can flow from VOUT to VIN, as long as the DUT is

enabled. To guarantee shutdown the enable (EN) pin must

be pulled low.

Thermal Considerations

The LT3070-1’s maximum rated junction temperature of

125°C limits its power handling capability and is domi-

nated by the output current multiplied by the input/output

voltage differential:

IOUT • (VIN – VOUT)

LT3070-1

Rev 0

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The LT3070-1’s internal power and thermal limiting cir-

cuitry protect it under overload conditions. For continuous

normal load conditions, do not exceed the maximum junc-

tion temperature of 125°C. Give careful consideration to

all sources of thermal resistance from junction to ambient.

This includes junction to case, case-to-heat sink interface,

heat sink resistance or circuit board to ambient as the

application dictates. Also, consider additional heat sources

mounted in proximity to the LT3070-1. The LT3070-1 is

a surface mount device and as such, heat sinking is ac-

complished by using the heat spreading capabilities of the

PC board and its copper traces. Surface mount heat sinks

and plated through-holes can also be used to spread the

heat generated by power devices. Junction-to-case thermal

resistance is specified from the IC junction to the bottom

of the case directly below the die. This is the lowest resis-

tance path for heat flow. Proper mounting is required to

ensure the best possible thermal flow from this area of the

package to the heat sinking material. Note that the exposed

pad is electrically connected to GND.

Table 3 lists thermal resistance as a function of copper

area in a fixed board size. All measurements were taken

in still air on a 4-layer FR-4 board with 1 oz solid internal

planes and 2 oz top/bottom external trace planes with a

total board thickness of 1.6mm. PCB layers, copper weight,

board layout and thermal vias affect the resultant thermal

resistance. For further information on thermal resistance

and high thermal conductivity test boards, refer to JEDEC

standard JESD51, notably JESD51-12 and JESD51-7.

Achieving low thermal resistance necessitates attention

to detail and careful PCB layout.

Table 3. UFD Plastic Package, 28-Lead QFN

COPPER AREA

BOARD AREA

THERMAL RESISTANCE

(JUNCTION-TO-AMBIENT)TOPSIDE* BACK SIDE

2500mm22500mm22500mm230°C/W

1000mm22500mm22500mm232°C/W

225mm22500mm22500mm233°C/W

100mm22500mm22500mm235°C/W

*Device is mounted on topside

Calculating Junction Temperature

Example: Given an output voltage of 0.9V, an input voltage

range of 1.2V ± 5%, a BIAS voltage of 2.5V, a maximum

output current of 4A and a maximum ambient temperature

of 50°C, what will the maximum junction temperature be?

The power dissipated by the device equals:

IOUT(MAX) • (VIN(MAX) – VOUT) + (IBIAS – IGND) • VOUT

+ IGND • VBIAS

where:

IOUT(MAX) = 4A

VIN(MAX) = 1.26V

IBIAS at (IOUT = 4A, VBIAS = 2.5V) = 6.91mA

IGND at (IOUT = 4A, VBIAS = 2.5V) = 0.87mA

thus:

P = 4A(1.26V – 0.9V) + (6.91mA – 0.87mA)0.9V +

0.87mA(2.5V) = 1.448W

With the QFN package soldered to maximum copper

area, the thermal resistance is 30°C/W. So the junction

temperature rise above ambient equals:

1.448W at 30°C/W = 43.44°C

The maximum junction temperature equals the maximum

ambient temperature plus the maximum junction tempera-

ture rise above ambient or:

TJMAX = 50°C + 43.44°C = 93.44°C

Applications that cannot support extensive PCB space for

heat sinking the LT3070-1 require a derating of output

current or increased airflow.

Paralleling Devices for Higher IOUT

Multiple LT3070-1s may be paralleled to obtain higher

output current. This paralleling concept borrows from the

scheme employed by the LT3080.

To accomplish this paralleling, tie the REF/BYP pins of

the paralleled regulators together. This effectively gives

an averaged value of multiple 600mV reference voltage

sources. Tie the OUT pins of the paralleled regulators to

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Rev 0

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the common load plane through a small piece of PC trace

ballast or an actual surface mount sense resistor beyond

the primary output capacitors of each regulator. The re-

quired ballast is dependent upon the application output

voltage and peak load current. The recommended ballast

is that value which contributes 1% to load regulation. For

example, two LT3070-1 regulators configured to output 1V,

sharing a 10A load require 2mΩ of ballast at each output.

The Kelvin SENSE pins connect to the regulator side of the

ballast resistors to keep the individual control loops from

conflicting with each other (see Figure 8 and Figure 9).

Keep this ballast trace area free of solder to maintain a

controlled resistance.

Table 4 shows a simple guideline for PCB trace resistance

as a function of weight and trace width.

Table 4. PC Board Trace Resistance

WEIGHT (Oz) 100 MIL WIDTH* 200 MIL WIDTH*

1 5.43 2.71

2 2.71 1.36

*Trace resistance is measured in milliohms/in

Quieting the Noise

The LT3070-1 offers numerous noise performance advan-

tages. Each LDO has several sources of noise. An LDO’s

most critical noise source is the reference, followed by

the LDO error amplifier. Traditional low noise regulators

buffer the voltage reference out to an external pin (usu-

ally through a large value resistor) to allow for bypassing

and noise reduction of reference noise. The LT3070-1

deviates from the traditional voltage reference by generat-

ing a low voltage VREF from a reference current into an

internal resistor ≅19k. This intermediate impedance node

(REF/BYP) facilitates external filtering directly. A 10nF filter

capacitor minimizes reference noise to 10µVRMS at the

600mV REF/BYP pin, equivalently a 17µV contribution to

output noise at VOUT = 1V. See the Typical Performance

Characteristics for Noise vs Output Voltage performance

as a function of CREF/BYP

This approach also accommodates reference sharing

between LT3070-1 regulators that are hooked up in cur-

rent sharing applications. The REF/BYP filter capacitor

delays the initial power-up time by a factor of the RC time

constant. VREF is disabled in nap mode, thus start-up time

is well controlled coming out of nap mode (EN:LO↑HI),

soft-starting the output.

BIAS

50k

LT3070-1

VO0

VO1

330µF

2.2µF

2.2µF*

0.01µF

1nF

4.7µF*

30701 F06

10µF*

*X5R OR X7R CAPACITORS

PWRGD

VOUT

1.2V

VO2

MARGSEL

MARGTOL

VIOC

SENSE

OUT

VBIAS

2.5V TO 3.6V

VIN

1.5V PWRGD

REF/BYP

GND

Figure 6. 1.5V to 1.2V Linear Regulator

LT3070-1

Rev 0

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Figure 7. Regulator with VIOC Buck Control

0.1µF

1Ω

47µF

6.3V

×3

BIAS

50k

LT3070-1

VO2

VO0

2.2µF

47µF

1.3V/5A

1nF

4.7nF

100µF

6.3V

×2

2.2µF*

0.01µF

NOTE: LTC3415 SWITCHER, 2MHz INTERNAL OSCILLATOR

LTC3415 AND LT3070-1 ON SAME PCB POWER PLANE

4.7µF*

30701 F07

10µF*

PWRGD

*X5R OR X7R CAPACITORS

OUT

VO1

MARGTOL

MARGSEL

NC VIOC

SENSE

OUT

BIAS

3.3V

PWRGD

REF/BYP

GND

SGND

PVIN

PLLLPF

CLKOUT

PHMODE

CLKIN

MODE

MGN

BSEL

VFB

ITHM

SGND

PGNDPGNDPGNDPGND PGNDPGND

PGND

PVIN

RUNPGOOD TRACK 0.2µH

SVIN

LTC3415EUHF

10k

20k

ITH

Figure 8. 1V, 7A Point-of-Load Current Sharing Regulators

0.1µF

1Ω

47µF

6.3V

×3

BIAS

50k

LT3070-1

VO2

VO0

2.2µF

47µF

1nF

1.3V/7A

100µF

6.3V

×2

2.2µF*

0.01µF

4.7µF* 10µF*

PWRGD

*X5R OR X7R CAPACITORS

VOUT

3.5A

VO1

MARGTOL

MARGSEL

VIOC

SENSE

OUT

BIAS

3.3V

PWRGD

REF/BYP

GND

BIAS

LT3070-1

VO2

VO0 2.2µF*

0.01µF

1nF

4.7µF*

30701 F08

10µF*

*X5R OR X7R CAPACITORS

VOUT

3.5A

VO1

MARGTOL

MARGSEL

VIOC

SENSE

OUT

PWRGD

REF/BYP

GND

0.2µH

17.5k

15k

RTRACE

3mΩ

CONTROLLED

P.O.L. 1

P.O.L. 2

RTRACE

3mΩ

CONTROLLED

POWER

PLANE

1V/8A

NOTE: LTC3415 SWITCHER, 2MHz INTERNAL OSCILLATOR

LTC3415 AND LT3070-1 ×2 ON SAME PCB POWER PLANE

SGND

PVIN

PLLLPF

CLKOUT

MGN

BSEL

VFB

ITHM

SGND

PHMODE

CLKIN

MODE

PGNDPGNDPGNDPGND PGNDPGND

PGND

PVIN

RUNPGOOD TRACKSVIN

SVIN

LTC3415EUHF

ITH

LT3070-1

Rev 0

For more information www.analog.com

APPLICATIONS INFORMATION

Figure 9. Triple Output Supply Providing 1V, 8A and 1.8V, 5A and 1.5V, 3A

BIAS

50k

LT3070-1

VO2

VO0

2.2µF

47µF

VBUCK1 1.3V/8A

VBUCK2 2.1V/8A

1nF

2.2µF*

0.01µF

4.7µF* 10µF*

PWRGD

VIN

3.3V

VIN

3.3V

VIN

3.3V

VIN

3.3V

VOUT

VO1

MARGTOL

MARGSEL

VIOC

SENSE

OUT

PWRGD

REF/BYP

GND

BIAS

LT3070-1

VO2

VO0

2.2µF*

0.01µF1nF

4.7µF* 10µF*

VOUT

VO1

MARGTOL

MARGSEL

VIOC

SENSE

OUT

PWRGD

REF/BYP

GND

VIN1

SVIN1

RUN1

PLLLPF1

MODE1

PHMODE1

TRACK1

VIN2

SVIN2

RUN2

PLLLPF2

MODE2

PHMODE2

TRACK2

VOUT1

MGN1

FB1

ITH1

ITHM1

BSEL1

PGOOD1

VOUT2

MGN2

FB2

ITH2

ITHM2

BSEL2

PGOOD2

CLKIN2CLKOUT1CLKIN1SW1 CLKOUT2

NCNCNCNC

SGND2GND1SGND1SW2 GND2

LTM4616

100µF

6.3V

X5R

100µF

6.3V

X5R

10µF

VIN

3.3V

10µF

NOTE: THE TWO LTM4616 MODULE CHANNELS ARE

INDEPENDENTLY CONTROLLED BY THE VIOC

CONTROLS FROM THE LINEAR REGULATORS

4.7nF

47µF

RTRACE

2.5mΩ

CONTROLLED

P.O.L. 1

P.O.L. 2

RTRACE

2.5mΩ

CONTROLLED

10k

20k

10k

4.7nF

2k 1nF

POWER

PLANE

1V/7A

2.2µF

BIAS

LT3070-1

VO2

VO0

2.2µF*

0.01µF

4.7µF* 10µF*

VOUT

1.8V

VOUT

1.5V

VO1

MARGTOL

MARGSEL

VIOC

SENSE

OUT

PWRGD

REF/BYP

GND

2.2µF

47µF

BIAS

LT3070-1

VO2

VO0

2.2µF*

30701 F09

1nF

4.7µF* 10µF*

*X5R OR X7R CAPACITORS

VO1

MARGTOL

MARGSEL

VIOC

SENSE

OUT

PWRGD

REF/BYP

GND

LT3070-1

Rev 0

For more information www.analog.com

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog

Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications

subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

PACKAGE DESCRIPTION

4.00 ±0.10

(2 SIDES)

2.50 REF

5.00 ±0.10

(2 SIDES)

NOTE:

1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGHD-3).

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

PIN 1

TOP MARK

(NOTE 6)

0.40 ±0.10

27 28

BOTTOM VIEW—EXPOSED PAD

3.50 REF

0.75 ±0.05 R = 0.115

TYP

R = 0.05

TYP

PIN 1 NOTCH

R = 0.20 OR 0.35

× 45° CHAMFER

0.25 ±0.05

0.50 BSC

0.200 REF

0.00 – 0.05

(UFD28) QFN 0816 REV C

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

0.70 ±0.05

0.25 ±0.05

0.50 BSC

2.50 REF

3.50 REF

4.10 ±0.05

5.50 ±0.05

2.65 ±0.05

3.10 ±0.05

4.50 ±0.05

PACKAGE OUTLINE

2.65 ±0.10

3.65 ±0.10

3.65 ±0.05

UFD Package

28-Lead Plastic QFN (4mm × 5mm)

(Reference LTC DWG # 05-08-1712 Rev C)

LT3070-1

Rev 0

For more information www.analog.com

 ANALOG DEVICES, INC. 2018

D17101-0-9/18(0)

www.analog.com

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275mV Dropout Voltage (2-Supply Operation), Low Noise: 40µVRMS,

VIN: 1.2V to 36V, VOUT

: 0V to 35.7V, Current-Based Reference with 1

Resistor VOUT Set; Directly Parallelable (No Op Amp Required), Stable

with Ceramic Caps, MSOP-8 and 2mm × 3mm DFN-6 Packages

LTC3025-1/

LTC3025-2

500mA Micropower VLDO Linear Regulator

in 2mm × 2mm DFN

VIN = 0.9V to 5.5V, Dropout Voltage: 75mV, Low Noise 80µVRMS,

Low IQ: 54µA, Fixed Output: 1.2V (LTC3025-2); Adjustable Output

Range: 0.4V to 3.6V (LTC3025-1) 2mm × 2mm 6-Lead DFN Package

LTC3026 1.5A, Low Input Voltage VLDO Regulator VIN: 1.14V to 3.5V (Boost Enabled), 1.14V to 5.5V (with External

5V), VDO = 0.1V, IQ = 950µA, Stable with 10µF Ceramic Capacitors,

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LT3071 5A, Low Noise, Programmable Output, 85mV Dropout Linear

Regulator with Analog Margining

VIN: 0.95V to 3V, VOUT: 0.8V to 1.8V in 50mV Increments, Low

Noise: 25µVRMS, Stable with Ceramic Capacitors, 4mm × 5mm

28-Lead QFN Package

BIAS

50k

LT3070-1

VO0

VO1

330µF

2.2µF

2.2µF*

0.01µF

1nF

4.7µF*

30701 TA02

10µF*

*X5R OR X7R CAPACITORS

PWRGD

VOUT

1.2V

VO2

MARGSEL

MARGTOL

VIOC

SENSE

OUT

VBIAS

2.5V TO 3.6V

VIN

1.5V PWRGD

REF/BYP

GND

1.5V to 1.2V Linear Regulator

TYPICAL APPLICATION