© 2005 Fairchild Semiconductor Corporation DS500249 www.fairchildsemi.com
September 2000
Revised May 2005
74LCXH162244 Low Voltage 16-Bit Buffer /Line Driver with Bushol d and 26: Seri es Resistors in Outputs
74LCXH162244
Low Voltage 16-Bit Buffer/Line Driver with Bushold
and 26: Series Resistors in Outputs
General Descript ion
The LCXH162244 contains sixteen non-inverting buffers
with 3-STATE outputs designed to be employed as a mem-
ory and addre ss driver, clock driver, or bu s o riented trans-
mitter/receiver . The device is nibble controlled. Each nibble
has separate 3- S TAT E con tro l inpu ts which can be sh ort ed
together for full 16-bit operation.
The LCXH162244 data inputs include active bushold cir-
cuitry, eliminating the need for external pull-up resistors to
hold unused or floating data inputs at a valid logic level.
In addition, the outputs include equivalent 26
:
(nominal)
series resistors to reduce overshoot and undershoot and
are designed to sink/source up to 12 mA at VCC
3.0V.
The LCXH162244 is designed for low voltage (2.5V or
3.3V) VCC applications with capability of interfacing to a 5V
signal environment.
The LCXH162244 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing CMOS low power dissipation.
Features
■5V tolerant control inputs and outputs
■2.3V–3.6V VCC specifications provided
■Outputs include equivalent series resistance of 26
:
to
make external termination resistors unnecessary and
reduce overshoot and undershoot
■Bushold on data inputs eliminat es the need for external
pull-up/pull-down resistors
■5.3 ns tPD max (VCC
3.0V), 20
P
A ICC max
■Power down high impedance inputs and outputs
■
r
12 mA output drive (VCC
3.0V)
■Latch-up per for man c e exce eds 500 mA
■ESD performa nce :
Human body model
!
2000V
Machine model
!
200V
Ordering Code:
Order Number Package Number Package Description
74LCXH162244MEA MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
[RAIL]
74LCXH162244MEX MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
[TAPE and REEL]
74LCXH162244MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[RAIL]
74LCXH162244MTX MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TAPE and REEL]
■Implements proprietary noise/EMI reduction circuitry
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74LCXH162244
Connection Diagram Logic Symbol
Pin Descriptions
Pin Names Description
OEnOutput Enable Input (Active LOW)
I0–I15 Bushold Inputs
O0–O15 Outputs
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74LCXH162244
Truth Tables
H
HIGH Voltage Level
L
LOW Voltage Level X
Immaterial
Z
High Impedance
Functional Description
The LCXH162244 contains sixteen non-inverting buffers
with 3-STATE standard outputs. The LCXH162244 data
inputs include active bushold ci rcuitry elim inating th e need
for pu l l- up re s is t ors t o h o ld u n us ed or f l oat i ng d at a i np ut s a t
a valid logic level. The devise is also designed with 26
:
series resistors in the outputs. This design reduces line
noise in applications such as memory address drivers,
clock drivers and bus transceiver/transmitters. The device
is nibble (4 bits) controlled with each nibble functioning
identically, but independent of the other. The control pins
can be sh orted togeth er to obtain full 1 6-bit o peratio n. The
3-STATE outputs are controlled by an Output Enable (OEn)
input for each nibble. When OEn is LOW , the outputs are in
2-state mode. When OEn is HIGH, the outputs are in the
high impedance mode, but this does not interfere with
enteri ng new data into t he inpu ts.
Logic Diagram
Inputs Outputs Inputs Outputs
OE1I0–I3O0–O3OE3I8–I11 O8–O11
LL L LL L
LH H LH H
HX Z HX Z
Inputs Outputs Inputs Outputs
OE2I4–I7O4–O7OE4I12–I15 O12–O15
LL L LL L
LH H LH H
HX Z HX Z
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74LCXH162244
Absolute Maximum Ratings(Note 1)
Recommended Operating Conditions (Note 3)
Note 1: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be opera t ed
at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recom-
mend ed Operating Co nditions ” tab le w ill define th e c onditions fo r ac t ual devi c e operation.
Note 2: IO Absolute Maximum Rating must be observed.
Note 3: Unused c ontrol in puts m ust be he ld H I GH or LOW. They may not f loat.
DC Electrical Characteristics
Symbol Parameter Value Conditions Units
VCC Supply Voltage
0.5 to
7.0 V
VIDC Input Voltage OE
0.5 to
7.0 V
I0 - I15
0.5 to VCC
0.5
VODC Output Voltage
0.5 to
7.0 Output in 3-STATE V
0.5 to VCC
0.5 Output in HIGH or LOW State (Note 2)
IIK DC In put Diode Current
50 VI
GND mA
IOK DC Output Diode Current
50 VO
GND mA
50 VO
!
VCC
IODC Output Source/Sink Current
r
50 mA
ICC DC Supply Current per Supply Pin
r
100 mA
IGND DC Ground Current per Ground Pin
r
100 mA
TSTG Storage Temperature
65 to
150
q
C
Symbol Parameter Min Max Units
VCC Supply Voltage Operating 2.0 3.6 V
Data Retention 1.5 3.6
VIInput Voltage 0V
CC V
VOOutput Voltage HIGH or LOW State 0 VCC V
3-STATE 0 5.5
IOH/IOL Output Current VCC
3.0V
3.6V
r
12 mAVCC
2.7V
3.0V
r
8
VCC
2.3V
2.7V
r
4
TAFree-Air Operating Temp erature
40 85
q
C
'
t/
'
V Input Edge Rate, VIN
0.8V–2.0V, VCC
3.0V 0 10 ns/V
Symbol Parameter Conditions VCC TA
40
q
C to
85
q
CUnits
(V) Min Max
VIH HIGH Level Input Voltage 2.3
2.7 1.7 V
2.7
3.6 2.0
VIL LOW Level Input Voltage 2.3
2.7 0.7 V
2.7
3.6 0.8
VOH HIGH Level Output Voltage IOH
100
P
A2.3
3.6 VCC
0.2
V
IOH
4 mA 2.3 1.8
IOH
4 mA 2.7 2.2
IOH
6 mA 3.0 2.4
IOH
8 mA 2.7 2.0
IOH
12 mA 3.0 2.0
VOL LOW Level Output Voltage IOL
100
P
A2.3
3.6 0.2
V
IOL
4 mA 2.3 0.6
IOL
4 mA 2.7 0.4
IOL
6 mA 3.0 0.55
IOL
8 mA 2.7 0.6
IOL
12 mA 3.0 0.8
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74LCXH162244
DC Electrical Characteristics (Continued)
Note 4: An exte rnal driver must source at least the specified curren t to switch from LOW-to-HIGH.
Note 5: An external driver mus t s ink at least the s pec if ied current to switc h f rom HIG H -t o-LOW.
AC Electrical Characteristics
Note 6: S k ew is def i ned as t he absolute valu e of the differen c e betwee n t he actu al propagation delay fo r any two separ at e outputs of the same d evice. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (t OSLH). Parameter gu arantee d by design.
Dynamic Switching Characteristics
Capacitance
Symbol Parameter Conditions VCC TA
40
q
C to
85
q
CUnits
(V) Min Max
IIInput Leakage Current Data VI
VCC or GND 2.3
3.6
r
5.0
P
A
Control 0
d
VI
d
5.5 2.3
3.6
r
5.0
II(HOLD) Bushold Input Minimum VIN
0.7V 2.3 45
P
A
Drive Hold Current VIN
1.7V
45
VIN
0.8V 3.0 75
VIN
2.0V
75
II(OD) Bushold Input Over-Drive (Note 4) 2.7 300
P
A
Current to Change State (Note 5)
300
(Note 4) 3.6 450
(Note 5)
450
IOZ 3-STATE Output Leakage 0
d
VO
d
5.5V 2.3
3.6
r
5.0
P
A
VI
VIH or VIL
IOFF Power-Off Leakage Current VO
5.5V 0 10
P
A
ICC Quiescent Supply Current VI
VCC or GND 2.3
3.6 20
P
A
'
ICC Increase in ICC per Input VIH
VCC
0.6V 2.3
3.6 500
P
A
Symbol Parameter
TA
40
q
C to
85
q
C, RL
500
:
Units
VCC
3.3V
r
0.3V VCC
2.7V VCC
2.5V
r
0.2V
CL
50 pF CL
50 pF CL
30 pF
Min Max Min Max Min Max
tPHL Propagation Delay 1.0 5.3 1.0 6.0 1.0 6.4 ns
tPLH Data to Output 1.0 5.3 1.0 6.0 1.0 6.4
tPZL Output Enable Time 1.0 6.3 1.0 7.1 1.0 8.2 ns
tPZH 1.0 6.3 1.0 7.1 1.0 8.2
tPLZ Output Disable Time 1.0 5.4 1.0 5.7 1.0 6.5 ns
tPHZ 1.0 5.4 1.0 5.7 1.0 6.5
tOSHL Output to Output Skew (Note 6) 1.0 ns
tOSLH 1.0
Symbol Parameter Conditions VCC TA
25
q
CUnits
(V) Typical
VOLP Quiet Output Dynamic Peak VOL CL
50 pF, VIH
3.3V, VIL
0V 3.3 0.35 V
CL
30 pF, VIH
2.5V, VIL
0V 2.5 0.25
VOLV Quiet Output Dynamic Valley VOL CL
50 pF, VIH
3.3V, VIL
0V 3 .3
0.35 V
CL
30 pF, VIH
2.5V, VIL
0V 2 .5
0.25
Symbol Parameter Conditions Typical Units
CIN Input Capacitance VCC
Open, VI
0V or VCC 7pF
COUT Output Capacitance VCC
3.3V, VI
0V or VCC 8pF
CPD Power Dissipation Capacitance VCC
3.3V, VI
0V or VCC, f
10 M Hz 20 pF
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74LCXH162244
AC LOADING and WAVEFORMS Generic for LCX Family
FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance)
Waveform for Inverting and Non-Inverting Functions
Propagation Delay. Pulse Width and trec Waveforms
3-STA TE Output Low Enable and
Disable Times for Logic
3-STATE Output High Enable and
Disable Times for Logic
Setup Time, Hold Time and Recovery Time for Logic
trise and tfall
FIGURE 2. Waveforms
(Input Cha ra cteristics; f =1MHz , tR = tF = 3ns)
VICL
6V for VCC
3.3V, 2.7V 50 pF
VCC * 2 for VCC
2.5V 30 pF
Symbol VCC
3.3V
r
0.3V 2.7V 2.5V
r
0.2V
Vmi 1.5V 1.5V VCC/2
Vmo 1.5V 1.5V VCC/2
VxVOL
0.3V VOL
0.3V VOL
0.15V
VyVOH
0.3V VOH
0.3V VOH
0.15V
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74LCXH162244
Schematic Diagram Generic for LCXH Family
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74LCXH162244
Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
Packag e Num b er MS48A
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74LCXH162244 Low Voltage 16-Bit Buffer/Line Driver with Bushold and 26: Series Resistors in Outputs
Physical Dim ensions inches (millimeters) unless otherwise noted (Continued)
48-Lea d Th in S hri nk Sm all Ou tlin e Pack age (TSSOP ), JED EC MO-1 53, 6.1mm Wide
Package Number MTD48
Fairchild does not assum e any responsibility for use of any circuitry described, no cir cuit patent licenses are im plied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life suppor t de vices o r syst ems are dev ic es or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instruct ions fo r use provided in the l abe li ng, can be re a-
sonably expected to result in a significant injury to the
user.
2. A crit ical com ponen t in any com ponen t of a life s uppor t
device or system whose failure to perform can be rea-
sonabl y e xpec ted to cause th e fa i lure of the l ife suppor t
device or system, or to affect its safety or effectiveness.
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