HMXNV0100
www.honeywell.com/aerospace
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HXNV0100
64K x 16 Non-Volatile
Magnetic RAM
Advanced Information
The 64K x 16 radiation hardened low power nonvolatile
Magnetic RAM (MRAM) is a high performance 65,536
word x 16-bit magnetic random access memory with
industry-standard functionality.
The MRAM is designed for very high reliability.
Redundant write control lines, error correction coding
and low-voltage write protection ensure the correct
operation of the memory and that it is protected from
inadvertent writes.
Integrated Power Up and Power Down circuitry controls
the condition of the device during power transitions.
It is fabricated with Honeywell’s radiation hardened
Silicon On Insulator (SOI) technology, and is designed
for use in low-voltage systems operating in radiation
environments. The MRAM operates over the full military
temperature range and is operated with 3.3 ± 0.3V and
1.8 ± 0.15 V power supplies.
FEATURES
Read Cycle Time ≤60 ns
Write Cycle Time ≤100ns
Typical Operating Power ≤500 mW
Unlimited Read/Write (>1E15
Cycles)
>10 years Power-Off Data
Retention
Synchronous Operation
Single-Bit Error Detection &
Correction (ECC)
Fabricated on S150 Silicon On
Insulator (SOI) CMOS
Underlayer Technology
150 nm Process (Leff = 130 nm)
Total Dose Hardness ≥ 3x105
rad (SiO2)
Dose Rate Upset Hardness ≥
1x1010 rad(Si)/s
Dose Rate Survivability ≥1x1012
rad(Si)/s
Soft Error Rate ≤1x10-10
upsets/bit-day
Neutron Hardness ≥1x1013 cm-2
No Latchup
Dual Power Supplies
• 1.8 V ± 0.15V, 3.3 V ±0.3V
• 3.3V CMOS Compatible I/O
Operating Range is -55°C to
+125°C
Package: 64 Lead Shielded
ceramic Quad Flat Pack
HMXNV0100
FUNCTIONAL BLOCK DIAGRAM
Memory Array
65,536 x 16
Column Decoder
Data Input/Output
Read Circuits
Bit Line Current Drivers
Digit Line Current
Drivers
A(7:15)
WE
NWI
DQ(0:15)
ECC Array
65,536 x 5
ECC Logic
DQ
C
CS
DQ
C
OE
WE_AS
A(0:6)
DQ
C
ECC_DISABLE
ERROR
SIGNAL DESCRIPTION
Signal Definition
A(0:6) Column Select Address Input. Signals which select a column within the
memory array.
A–(7:15) Row Select Address Input. Signals which select a row within the
memory array.
DQ(0:15) Data Input/Output Signals. Bi-directional data pins which serve as data
outputs during a read operation and as data inputs during a write
operation.
CS Chip select. The rising edge of CS will clock in the address and WE
signals
WE Write Enable. This signal is latched to enable a write.
WE_AS Write Enable Asynchronous – This signal can be used to delay the
beginning of the write cycle
OE Output Enable.
NWI_0
NWI_1
Not Write Inhibit – When set low, these signals inhibit writes to the
memory. A high level allows the memory to be written.
NWI(0) controls address locations A(15:0) = 0x0000 to 0x7FFF.
NWI(1) controls address locations A(15:0) = 0x1000 to 0xFFFF.
ECC_Disable Error Correction Disable – Disables the error correction function.
ERROR ECC Error flag
Test_1
Test_2
These signals are for Honeywell test purposes only. These should be
grounded in normal operation.
VDD1 DC Power Source Input: 1.8V
VDD2 DC Power Source Input: 3.3V
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HMXNV0100
TRUTH TABLE
NWI WE & WE_ASY OE MODE DQ
L X L Deselected High Z
H L L Disabled High Z
H L H Read Data Out
H H X Write Data In
X: VI = VIH or VIL
PACKAGE PINOUT
64 GND
63 DQ(2)
62 DQ(3)
61 DQ(4)
60 DQ(5)
59 DQ(6)
58 DQ(7)
57 VDD2
56 GND
55 ADDR(0)
54 ADDR(1)
53 ADDR(2)
52 ADDR(3)
51 ADDR(4)
50 ADDR(5)
49 VDD1
48 GND
47 VDD2
46 ADR(6)
45 ADR(15)
44 WE
43 WE_ASY
42 OE
41 VDD2
40 VDD1
39 GND
38 ADDR(14)
37 ADDR(13)
36 ADDR(12)
35 ADDR(11)
34 GND
33 VDD1
VDD1 1
GND 2
DQ(1) 3
DQ(0) 4
CS 5
N
WI(0) 6
VDD2 7
VDD1 8
GND 9
N
WI(1) 10
ECCDISABLE 11
ERROR 12
DQ(8) 13
DQ(9) 14
VDD2 15
GND 16
HMXNV1000
VDD1 17
DQ(10) 18
DQ(11) 19
DQ(12) 20
DQ(13) 21
DQ(14) 22
DQ(15) 23
GND 24
VDD2 25
ADDR(7) 26
ADDR(8) 27
ADDR(9) 28
ADDR(10) 29
TEST 30
TEST 31
GND 32
RAM and ROM Functional Capability
This MRAM incorporates two write control
signals allowing the two sections of the
memory to be controlled independently.
The two NOT WRITE INHIBIT signals,
NWI(0) and NWI(1), allow one section of the
devices to operate as a RAM and the other
to operate as a ROM at the full control of the
user.
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HMXNV0100
SOI AND MAGNETIC MEMORY TECHNOLOGY
Honeywell’s S150 Silicon On Insulator
(SOI) is radiation hardened through the use
of advanced and proprietary design, layout
and process hardening techniques. The 150
nm process is a technology with a 32Å gate
oxide for 1.8 V transistors and 70Å gate
oxide for 3.3 V transistors. The memory
element is a magnetic tunnel junction (MTJ)
that is composed of a magnetic storage
layer structure and a magnetic pinned layer
structure separated by an insulating tunnel
barrier interlayer. During a write cycle, the
storage layer is written by the application of
two orthogonal currents of the desired
polarity using row-and-column addressing.
The resistance of the MTJ depends on the
magnetic state of the storage layer, which
uses the pinned layer structure as a
reference, and which enables sensing,
signal amplification, and readback. The
resistance change is a consequence of the
change in tunneling magnetoresistance
(TMR) between the storage and pinned
layers that depends on the magnetic state of
the storage layer. With read and write cycles
in excess of 1015, there is no wear-out.
ERROR CORRECTION CODE (ECC)
Hamming 5-Bit ECC
A 5-bit Hamming ECC is generated for all
data written into memory. This code allows
for the correction of all single-bit errors per
address. On a read cycle, the data is read
from memory and corrected, if necessary,
before being placed on the output data bus.
There is no change made to the actual data
in the memory cells based on the ECC
results. Actual data in memory is changed
only upon writing new values.
RADIATION CHARACTERISTIC
Total Ionizing Radiation Dose
The MRAM will meet all stated functional
and electrical specifications over the entire
operating temperature range after the
specified total ionizing radiation dose. All
electrical and timing performance
parameters will remain within specifications
after rebound at typical VDD and T =125°C
extrapolated to ten years of operation. Total
dose hardness is assured by wafer level
testing of process monitor transistors and
RAM product using 10 KeV X-ray and Co60
radiation sources. Transistor gate threshold
shift correlations have been made between
10 KeV X-rays applied at a dose rate of
1x105 rad(SiO2)/min at T = 25°C and gamma
rays (Cobalt 60 source) to ensure that wafer
level X-ray testing is consistent with
standard military radiation test
environments.
Transient Pulse Ionizing Radiation
The MRAM is capable of writing, reading,
and retaining stored data during and after
exposure to a transient ionizing radiation
pulse, up to the specified transient dose rate
upset specification, when applied under
recommended operating conditions. To
ensure validity of all specified performance
parameters before, during, and after
radiation (timing degradation during
transient pulse radiation is ±10%), it is
suggested that stiffening capacitance be
placed near the package VDD2 and ground
(GND).
It is recommended that the inductance
between the MRAM package leads and the
stiffening capacitance be less that 1.0 nH. If
there are no operate through or valid stored-
data requirements, typical circuit board
mounted de-coupling capacitors are
recommended. The MRAM will meet any
functional or electrical specification after
exposure to a radiation pulse up to the
transient dose rate survivability
specification, when applied under
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HMXNV0100
recommended operating conditions. Note
that the current conducted during the pulse
by the RAM inputs, outputs, and power
supply may significantly exceed the normal
operating levels. The application design
must accommodate these effects.
Neutron Radiation
The MRAM will meet any functional or timing
specification after exposure to the specified
neutron fluence under recommended
operating or storage conditions. This
assumes equivalent neutron energy of 1
MeV.
Soft Error Rate
The MRAM is capable of meeting the
specified Soft Error Rate (SER) under
recommended operating conditions. This
hardness level is defined by the Adams 90%
worst case cosmic ray environment for
geosynchronous orbits.
Latchup
The MRAM will not latch up under any of the
above radiation exposure conditions when
applied under recommended operating
conditions. Fabrication with the SIMOX
substrate material provides oxide isolation
between adjacent PMOS and NMOS
transistors and eliminates any potential
SCR-type latchup structures. Sufficient
transistor body tie connections to the p-
channel and n-channel substrates are made
to ensure no source/drain snapback occurs.
Radiation-Hardness Ratings
Parameter Limits Units Test Conditions
Total Dose:
R-Level
F-Level
H-Level
≥ 1 x 105
≥ 3 x 105
≥ 1 x 106
Rads(SiO2)
VDD1= 1.95 Volts, VDD2= 3.6 Volts
TA = 25C, X-Ray or Co60
Soft Error Rate: ≤ 1 x 10-10 Upsets/bit-day VDD1= 1.8 Volts, VDD2= 3.3 Volts
TC = -55 to 125°C
Transient Dose
Rate Upset ≥ 1 x 1010 Rads(Si)/s VDD1= 1.65 Volts, VDD2= 3.0 Volts
TC = 125°C Pulse Width = 1µsec, X-
Ray
Transient Dose
Rate Survivability ≥ 1 x 1012 Rads(Si)/s VDD1= 1.95 Volts, VDD2= 3.6 Volts
TA = 25°C
Pulse Width = 50 nsec, X-Ray
Neutron Fluence 1x1013 N/cm-2 1MeV equivalent energy
MAGNETIC FIELD CHARACTERISTICS
The MRAM will meet all stated functional
and electrical specifications over the entire
operating temperature range when exposed
to the specified magnetic fields. The
magnetic field hardening is achieved
through a combination of SOI technology
characteristics, circuit design and
specialized packaging.
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HMXNV0100
MAGNETIC FIELD RATING
Parameter Limits Units Test Conditions
Magnetic Field 50 Oe VDD1= 1.8 Volts, VDD2= 3.3 Volts
TC = -55 to 125°C
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (1)
Ratings
Symbol Parameter Min Max Units
VDD1 Positive Supply Voltage (2) -0.5 2.5 Volts
VDD2 Positive Supply Voltage (2) -0.5 4.5 Volts
VPIN Voltage on Any Pin (2) -0.5 VDD2 + 0.5 Volts
TSTORE Storage Temperature -65 150 °C
TSOLDER Soldering Temperature 225°C °C*sec (5)
PD Package Power Dissipation (3) 2.5 W
PJC Package Thermal Resistance (Junction
to Case)
2.0
°C/W
VPROT Electrostatic Discharge Protection
Voltage (4)
2000 V
TJ Junction Temperature 175 °C
1. Stresses in excess of those listed above may result in immediate permanent damage
to the device. These are stress ratings only, and operation at these levels is not
implied. Frequent or extended exposure to absolute maximum conditions may affect
device reliability.
2. Voltage referenced to GND
3. RAM power dissipation due to IDDS, IDDOP, and IDDSEI, plus RAM output driver power
dissipation due to external loading must not exceed this specification
4. Class 2 electrostatic discharge (ESD) input protection voltage per MIL-STD-883,
Method 3015
5. Maximum soldering temp of 225°C can be maintained for no more than 5 seconds.
RECOMMENDED OPERATING CONDITIONS (1)
Limits
Symbol Parameter Min Typical Max Units
VDD1 Positive Supply Voltage 1.65 1.8 1.95 Volts
VDD2 Positive Supply Voltage 3.0 3.3 3.6 Volts
TC External Package Temperature -55 25 125 °C
VPIN Voltage On Any Pin -0.3 VDD2+0.3 Volts
(1) Voltages referenced to GND
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HMXNV0100
DC ELECTRICAL CHARACTERISTICS
Limits
Symbol Parameter Min Typical Max Units Test Conditions
VIL Low Level Input
Voltage
0.3VDD V
VIH High-level Input Voltage 0.7VDD V
VOL Low-level Output
Voltage
0.35 0.5 V VDD = 3.0 volts
VOH High-level Output
Voltage
VDD-0.5 2.66
(2.95)
V VDD = 3.0 volts
(VDD = 3.3 volts)
IOZ Output Leakage
Current
TBD
µA
IL Input Leakage Current TBD µA
IO Output Drive Current 6 mA
IDDSB Standby Current
VDD1 (1.8V)
VDD2 (3.3V)
3
3
mA
AC ELECTRICAL CHARACTERISTICS
Limits
Symbol Parameter Min Typical Max Units Test Conditions
IDDWR Average Write Current
VDD1 (1.8V)
VDD2 (3.3V)
15
260
mA Continuous write
cycle at 10 MHz (1)
IDDRD Average Read Current
VDD1 (1.8V)
VDD2 (3.3V)
15
3
mA Continuous read
cycle at 10 MHz (1)
1. Current consumption is reduced with lower duty cycle. The scale is linear with respect to
duty cycle with 3 mA minimum values of on each VDD signal.
CAPACITANCE (1)
Limits Test Conditions
Symbol Parameter Min Max Units
Ca and CC Address and Control line
Capacitance
6 pF TBD
CD Data Line Capacitance 9 pF Value is I/O buffer only.
CNWI Not Write Inhibit
Capacitance
100 pF
Note: 1. These values are tested at characterization only.
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HMXNV0100
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RISE/FALL TIMES
Value Test Conditions
Symbol Parameter Min Max Units
Rt Rise Time 1.4 ns Cload = 5 pF
Rt Rise Time 2.9 ns Cload = 25 pF
Ft Fall Time 1.4 ns Cload = 5 pF
Ft Fall Time 2.9 ns Cload = 25 pF
DATA ENDURANCE
Ratings Test Conditions
Parameter Min Max Units
Data Endurance 1x1015 Cycles
DATA RETENTION
Ratings Test Conditions
Parameter Min Max Units
Data Retention >10 years
Tester Equivalent Load Circuit
Valid High
Output
3.3V
V1
249 Valid Low
Output
V2
DUT
Output
CL > 50 pf
HMXNV0100
READ CYCLE
The RAM is synchronous in operation
relative to the rising edge of the Chip Select
(CS) signal. With the initiation of a CS
signal, the address and the Write Enable
(WE) signal are latched into the device and
the read operation begins. The memory
locations are read and compared with the
ECC values. Any single bit errors are
detected and corrected.
If WE was low when latched in, the data is
sent to the output drivers. In addition to WE
low being latched, Output Enable (OE) must
be set to a high value to enable the DQ
output buffers. OE is not latched, and may
be set high before or after the rising edge of
CS.
READ CYCLE AC TIMING CHARACTERISTICS
READ CYCLE
Trdc
CS
Tcspw
ADDR[0:15] ADDR VALID
Tadsu Tadhd Tcsdv
WE
Twesu Twehd
OE
Toedv
DQ[0:15] HIGH Z OUTPUT DATA VALID
Min Typ Max
Tcspw CS pulse width (for valid read) 10ns ------ ------
Tcspi CS ignored pulse width (glitch tolerance) ------ ------ 1ns
Twesu WE setup time with respect to rising edge of CS 3ns ------ ------
Twehd WE hold time with respect to rising edge of CS 2ns ------ ------
Tadsu Address setup time with respect to rising edge of CS 8ns ------ ------
Tadhd Address hold time with respect to rising edge of CS 2ns ------ ------
Tcsdv Output data valid with respect to rising edge of CS ------ ------ 60ns
Toedv Output data valid with respect to rising edge of OE ------ ------ 10ns
Trdc CS rising edge to next CS rising edge (read cycle time) 60ns ------ ------
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HMXNV0100
WRITE CYCLE
The RAM is synchronous in operation
relative to the rising edge of the Chip Select
(CS) signal. With the initiation of a CS
signal, the address and the Write Enable
(WE) signal are latched into the device.
If WE was high when latched in, the Write
Asynchronous (WE_AS) signal is checked.
If WE_AS is high, the WRITE CYCLE will
begin. If WE_AS is low, the WRITE CYCLE
will be delayed until WE_AS is set high. This
allows control by the host processor of the
actual time the data is written to memory.
The WRITE CYCLE begins by reading the
current value in memory. The current
memory data is compared to the data to be
written. If the location needs to change
value, the data is then written.
The bit cell construction of this device does
not provide a method of simply writing a “1”
or a “0” to match the data. The “write” to a
bit can only change its state, thus the need
to read the bit locations first. Only the bits
which need to “change state” are actually
written.
WRITE CYCLE AC TIMING CHARACTERISTICS
NON-DELAYED
WRITE CYCLE - non delayed (WE_ASYN < 40ns after CS)
Twrc
CS
Tcspw
ADDR[0:15] ADDR VALID
Tadsu Tadhd
WE
Twesu Twehd
Tcswa
WE_ASYN
DQ[0:15] DATA VALID DAT A W RITTEN
Tdqsu
Tdqhd
NWI
Tcsdw, Tcshd
Min Typ Max
Tcspw CS pulse width (for valid write) 10ns ------ ------
Tcspi CS ignored pulse width (glitch tolerance) ------ ------ 1ns
Twesu W E setup time with respect to rising edge of CS 3ns ------ ------
Twehd W E hold time with respect to rising edge of CS 2ns ------ ------
Tadsu Address setup time with respect to rising edge of CS 8ns ------ ------
Tadhd Address hold time with respect to rising edge of CS 2ns ------ ------
Tcswa W E_ASYN delay from rising edge of CS 40ns
Tdqsu DQ setup time after rising edge of CS ------ ------ 20ns
Tdqhd DQ hold time with respect to rising edge of CS 60ns ------ ------
Tcsdw Valid data write time WRT rising edge of CS ------ ------ 100ns
Tcshd NW I,W E_ASYNC hold time WRT rising edge of CS 100ns ------ ------
Twrc CS rising edge to next CS rising edge (write cycle time) 100ns ------ ------
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HMXNV0100
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DELAYED
W RITE CYCLE - de la ye d (W E_ASYN > 40ns after CS)
Twrdc
CS
Tcspw
ADDR[0:15] ADDR VALID
Tadsu Tadhd
WE
Twesu Twehd
Tcswa
WE_ASYN
DQ[0:15] DATA VALID DATA WRITTEN
Tdqsu Tdqhd
NWI
Twahd
Typ Max
Tcspw CS pulse width (for valid write) ------ ------
Tcspi CS ignored pulse width (glitch tolerance) ------ 1ns
Twesu W E setup time with respect to rising edge of CS ------ ------
Twehd W E hold time with respect to rising edge of CS ------ ------
Tadsu Address setup time with respect to rising edge of CS ------ ------
Tadhd Address hold time with respect to rising edge of CS ------ ------
Tcswa W E_ASYN delay from rising edge of CS ------ ------
Tdqsu DQ setup time to rising edge of WE_ASYN ------ ------
Tdqhd DQ hold time WRT rising edge of WE_ASYN ------ ------
Twadw Valid data write time WRT rising edge of WE_ASYNC ------ 60ns
Twahd NWI,WE_ASYN, hold tim e WRT rising edge of WE_ASYN ------ ------
Twrdc CS rising edge to next CS rising edge (write cycle time) ------ ------
Min
3ns
2ns
60ns
40ns
4ns
20ns
10ns
------
Tcswa + 60ns
8ns
2ns
------
POWER UP TIMING
During power-up there are no restrictions on
which supply comes up first provided NWI is
asserted (low). NWI is de-asserted within
1us of both supplies reaching their 90%
values.
HMXNV0100
POWER-UP SEQUENCE
VDD1
VDD2 1us
NWI
POWER DOWN TIMING
POWER-DOWN SEQUENCE
VDD1
VDD2
NWI
100ns
QUALITY AND RADIATION HARDNESS ASSURANCE
Honeywell maintains a high level of product
integrity through process control, utilizing
statistical process and six sigma controls. It
is part of a “Total Quality Assurance
Program”, the computer-based process
performance tracking system and a radiation
hardness assurance stategy.
SCREENING LEVELS
Honeywell offers several levels of device
screeing to meet your needs. “Engineering
Devices” are available with limited
perfomrance and screening for prototype
development and evaluation testing. Hi-Rel
Level B and S devices undergo additional
screening per the requirements of MIL-STD-
883.
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HMXNV0100
RELIABILITY
Honeywell understands the stringent
reliability requirements that space and
defense systems require. Honeywell has
extensive experience in reliability testing on
programs of this nature. Reliability attributes
of the SOI process were characterized by
testing specially designed structures to
evaluate failure mechanisms including hot
carriers, electro migration, and time-
dependent dielectric breakdown. The
results are feedback to improve the process
to ensure the highest reliability products.
In addition, our products are subjected to
dynamic, accelerated life tests. The
packages used are qualified through MIL-
STD-883, TM 5005 Class S. The product
screening flow can be modified to meet the
specific requirements. Quality conformance
testing is performed as an option on all
production lots to ensure on-going reliability.
PACKAGE OUTLINE
The 64 Lead Shielded Ceramic QFP Package shown is preliminary and is subject to change,
including external capacitors. The outline is for reference only.
VS S
VDD2
VS S
VDD2
110
11
38
39
47
VS S
VDD2
VS S
VDD2
48
75
215
220
225
230
235
240
245
250
255
260
265
270
275
280
145150155160165170175180185190195200205210
75
80
85
90
95
100
105
110
115
120
125
130
135
140
510152025303540455055606570
Hon e ywell
DSE S
2202xx xx
VS S
VDD1
VDD2
.900
.900
.018
.050
.150
.075
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HMXNV0100
ORDERING INFORMATION (1)
H X
(1) To order parts or obtain technical assistance, call 1-800-323-8295
(2) Engineering Model Description: Parameters are tested from-55 to 1250C, 24-hour burn-in, no radiation
guarantee.
0100 S HA
Source
H = Honeywell
Process
X = SOI
Package Designation
A = 64 Lead QFP
Part Numbe
r
0100 = 1 Meg
Screen Level
V = QML Class V
Q = QML Class Q
S = Level S
B = Level B
E = Eng. Model (2)
Total Dose Hardness
R = 1x105 rad (SiO2)
F = 3x105 rad (SiO2)
H = 1x106 rad (SiO2)
N = No Level Guaranteed
NV
Part Type
NV = Non Volatile
For more information about Honeywell’s MRAM product and our family of memory and ASIC
products and services, visit www.myspaceparts.com.
Honeywell reserves the right to make changes to any products or technology herein to improve reliability, function or design. Honeywell does not
assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its
patent rights nor the rights of others.
Honeywell International Inc.
A
erospace Electronics Systems
Defense & Space Electronics Systems
12001 Highway 55
Plymouth, MN 55441
1-800-323-8295
www.honeywell.com
Form #900232
May 2005
©2005 Honeywell International Inc.
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