Freescale Semiconductor
Data Sheet: Advanced Information Document Number: MCF51JE256
Rev. 4, 08/2012
© Freescale Semiconductor, Inc., 2009-2012. All rights reserved.
This document contains information on a product under development. Freescale reserves the
right to change or discontinue this product without notice.
32-Bit ColdFire V1 Central Processor Unit (CPU)
• Up to 50.33 MHz ColdFire CPU above 2.4V and 40 MHz CPU above 2.1V
and 20 MHz CPU above 1.8 V across temperature range of -40°C to
105°C.
• ColdFire Instruction Se t Revision C (ISA_C).
• 32-bit multiply an d accumulate (MAC) sup ports signed or unsigned integer
or signed fractional inputs.
On-Chip Memory
• 256 K Flash comprised of two independent 128K flash arrays;
read/program/erase over full operating voltage and temperature; allows
interrupt processing while programming.
• 32 KB System Random-access memory (RAM).
• Security circuitry to prevent unauthorized access to RAM and Flash
contents.
Power-Saving Modes
• Two ultra-low power stop modes. Peripheral clock enable register can
disable clocks to unused modules to reduce currents.
• Time of Day (TOD) — Ultra low-power
1/4 sec counter with up to 64 sec
timeout.
• Ultra-low power external oscillator that can be used in stop modes to
provide accurate cloc k source to the T OD. 6 µs typical wake up time from
stop3 mode.
Clock Source Options
• Oscillator (XOSC1) — Loop-control Pierce oscillator; 32.768 kHz crystal or
ceramic resonator dedicated for TOD operation.
• Oscillator (XOSC2) for high frequency crystal input for MCG reference to
be used for system clock and USB operations.
• Multipurpose Clock Gen erator (MCG) —
PLL and FLL; precision trimming
of internal reference allows 0.2% resolution and typical +0.5% to -1%
deviation over temperature and voltage; supports CPU frequencies up to
50 MHz.
System Protection
• Watchdog computer operating properly (COP) reset with option to run from
dedicated 1kHz internal clock source or bus clock.
• Low-voltage detection with reset or interrupt; selectable trip points;
separate low voltage warnin g with optional interrupt; selecta ble trip points.
• Illegal opcode and illegal address detection with reset.
• Flash block protection for each array to prevent accidental write/erasure.
• Hardware CRC to support fast cyclic redundancy checks.
Development Support
• Integrated ColdFire DEBUG_Rev_B+ interface with single wire BDM
connection supports same electrical interfa ce used by the S08 family
debug modules.
• Real-time debug with 6 hardware breakpoints (4 PC, 1 address and 1
data).
• On-chip trace buffer provides programmable start/stop recording
conditions.
Peripherals
•
USB
— Dual-role USB On-The -Go (OTG) device , supp orts USB in eit her
device, host or OTG configuration. On-chip transceiver and 3 .3V regulator
help save system cost , fully comp liant with USB Specif ication 2. 0. Allows
control, bulk, interrupt and isochronous transfers.
•
SCIx
— Two serial communications interf ace s with opt iona l 13-bit break ;
option to connect Rx input to PRACMP output on SCI1 and SCI2; High
current drive on Tx on SCI1 and SCI2; wake-up from stop3 on Rx edge.
•
SPI1
— Serial peripheral interface with 32-bit FIFO buffer; 16-bit or 8-bit
data transfers; full-duplex or single-wire bidirectional; double-buffered
transmit and receive; mast er or slave mode; MSB-first or LSB-first shifting.
•
SPI2
— Serial peripheral interfa ce w ith full-dup lex or single-wire
bidirectional; Double-buffered transmit and receive; Master or Slave
mode; MSB-first or LSB-first sh ifting.
•
IIC
— Up to 100 kbps with maximu m bus loading; Multi-m aster operation;
Programmable sla ve address; In terrupt driv en byte-b y-byte dat a transfer;
supports broadcast mode and 10-bit addressing.
•
CMT
— Carrier Modulator timer for remote control communications.
Carrier generator, modulator and driver for dedicated infrared out (IRO).
Can be used as an output compare timer.
•
TPM
x — Two 4-channel Timer/PWM Module; Selectable input capture,
output compare, or buffered edge- or center-aligned PWM on each
channel; external clock input/pulse accumulator.
•
Mini-FlexBus
— Multi-function extern al bus inte rfa ce with use r
programmable chip selects and the option to multiplex address and data
lines.
•
PRACMP
— Analog comparato r with selectable interrupt; comp are option
to programmable internal reference voltage; operation in stop3.
•
ADC12
— 12-bit Successive approximation ADC with up to12
single-ended cha nn els; int ernal ba nd gap refere nce chan ne l; ope ra tion in
stop3; fully functional from 3.6V to 1.8V.
•
PDB
— Programmable delay block with 16-bit counter and modulus and
prescale to set re ference clock to bus divided by 1 t o bus divided by 2048;
8 trigger outputs for ADC module provides periodic coordination of ADC
sampling sequence with sequence completion interrupt; Back-to-Back
mode and Timed mode.
•
DAC
— 12-bit resolution DAC; configurable settling time.
Input/Output
• Up to 68 GPIOs and 1 output-only pin.
• Voltage Reference output (VREFO).
• Dedicated infrared output pin (IRO)
withhigh current sink capability.
• Up to 16 KBI pins with selectable
polarity.
• Up to 16 pins of rapid general purpose
I/O (RGPIO).
An Energy-Efficient Solution from Freescale
MCF51JE256/128
The MCF51JE256 series devices are members of the low-cost,
low-power, high-performance ColdFire V1 f amily of 32-bit
microcontrollers (MCUs).
Not all features are available in all devices or packages; see
Table 1 for a comparison of features by device. 80-LQFP
12mm x 12mm 81-BGA
10mm x 10mm 100-LQFP
14mm x 14mm 104-BGA
10mm x 10mm
Document Number: MCF51JE256
Rev. 4, 08/2012
MCF51JE256/128
MCF51JE256 Datasheet, Rev. 4
Freescale Semiconductor2
Contents
Table of Contents
1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2 Pinouts and Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . .7
2.1 104-Pin MAPBGA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.2 100-Pin LQFP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.3 81-Pin MAPBGA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
2.4 80-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
2.5 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3 Preliminary Electrical Characteristics . . . . . . . . . . . . . . . . . .15
3.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . .15
3.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . .15
3.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .16
3.4 ESD Protection Characteristics. . . . . . . . . . . . . . . . . . .18
3.5 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
3.6 Supply Current Characteristics. . . . . . . . . . . . . . . . . . .21
3.7 PRACMP Electricals . . . . . . . . . . . . . . . . . . . . . . . . . . .24
3.8 12-bit DAC Electricals . . . . . . . . . . . . . . . . . . . . . . . . . .24
3.9 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .26
3.10 MCG and External Oscillator (XOSC) Characteristics .29
3.11 Mini-FlexBus Timing Specifications . . . . . . . . . . . . . . .32
3.12 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
3.12.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . .34
3.12.2 TPM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
3.13 SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
3.14 Flash Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .40
3.15 USB Electricals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
3.16 VREF Electrical Specifications . . . . . . . . . . . . . . . . . . .41
4 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
4.1 Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
4.2 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . .44
4.3 Mechanical Drawings . . . . . . . . . . . . . . . . . . . . . . . . . .44
5 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
List of Figures
Figure 1.MCF51JE256/128 Block Diagram. . . . . . . . . . . . . . . . . 3
Figure 2.104-Pin MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3.100-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4.81-Pin MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 5.80-Pin LQFP Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 6.Stop IDD versus Temperature. . . . . . . . . . . . . . . . . . . 23
Figure 7.Offset at Half Scale vs Temperature . . . . . . . . . . . . . . 26
Figure 8.ADC Input Impedance Equivalency Diagram . . . . . . . 28
Figure 9.Mini-FlexBus Read Timing . . . . . . . . . . . . . . . . . . . . . 33
Figure 10.Mini-FlexBus Write Timing . . . . . . . . . . . . . . . . . . . . 33
Figure 11.Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 12.IRQ/KBIPx Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 13.Timer External Clock . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 14.Timer Input Capture Pulse. . . . . . . . . . . . . . . . . . . . . 36
Figure 15.SPI Master Timing (CPHA = 0) . . . . . . . . . . . . . . . . . 38
Figure 16.SPI Master Timing (CPHA = 1) . . . . . . . . . . . . . . . . . 38
Figure 17.SPI Slave Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . 39
Figure 18.SPI Slave Timing (CPHA = 1) . . . . . . . . . . . . . . . . . . 39
Figure 19.Typical VREF Output vs Temperature . . . . . . . . . . . . 42
Figure 20.Typical VREF Output vs VDD . . . . . . . . . . . . . . . . . . . 43
List of Tables
Table 1. MCF51JE Features by MCU and Package. . . . . . . . . . 4
Table 2. MCF51JE256/128 Functional Units. . . . . . . . . . . . . . . . 5
Table 2-3.Package Pin Assignments . . . . . . . . . . . . . . . . . . . . . 11
Table 4. Parameter Classifications . . . . . . . . . . . . . . . . . . . . . . 15
Table 5. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . 16
Table 6. Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . 17
Table 7. ESD and Latch-up Test Conditions . . . . . . . . . . . . . . . 18
Table 8. ESD and Latch-Up Protection Characteristics. . . . . . . 18
Table 9. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 10.Supply Current Characteristics . . . . . . . . . . . . . . . . . . 21
Table 11.Stop Mode Adders. . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 12.PRACMP Electrical Specifications . . . . . . . . . . . . . . . 24
Table 13.DAC 12LV Operating Requirements . . . . . . . . . . . . . . 24
Table 14.DAC 12-Bit Operating Behaviors. . . . . . . . . . . . . . . . . 25
Table 15.12-bit ADC Operating Conditions . . . . . . . . . . . . . . . . 26
Table 16.12-bit SAR ADC Characteristics full operating range
(VREFH = VDDAD, VREFL = VSSAD) . . . . . . . . . . . . 28
Table 17.MCG (Temperature Range = –40 to 105×C Ambient). 29
Table 18.XOSC (Temperature Range = –40 to 105×C Ambient) 31
Table 19.Mini-FlexBus AC Timing Specifications. . . . . . . . . . . . 32
Table 20.Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 21.TPM Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 22.SPI Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 23.Flash Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 24.Internal USB 3.3 V Voltage Regulator Characteristics 40
Table 25.VREF Electrical Specifications . . . . . . . . . . . . . . . . . . 41
Table 26.VREF Limited Range Operating Behaviors. . . . . . . . . 42
Table 27.Orderable Part Number Summary. . . . . . . . . . . . . . . . 44
Table 28.Package Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 29.Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
MCF51JE256 Datasheet, Rev. 4
Freescale Semiconductor 3
Figure 1. MCF51JE256/128 Block Diagram
Port B
Port D Port C
Port E Port A
SPI1
VREG
SIM
V1 ColdFire Core
USB_DM
USB_DP
SS1
SPSCK1
MOSI1
MISO1
SCI2 RX2
TX2
RAM
MCG
VREFH/VREFL
VDDA/VSSA
VDD1,2,3VSS1,2,3
COP
32KB
XOSC2
LVD
4 Ch TPM2
BKGD/MS
DBG
BDM
INTC
4 Ch TPM1
VREF
CMT IRO:
RGPIO RGPIO[15:8]
RGPIO[7:0]
CLKO
SCI1 RX1
TX1
PDB
KBI1 & KBI2
PTD0/BKGD/MS
IIC SDA
SCL
PRACMP
VREFO
ACMPO
ACMPO
FLASH1
128/64 KB Robust
Update
Manager
Hardware CRC
KBI1P[7:0]
with MAC
VDDA/VSSA
VREFH/VREFL
ADC12 ADP[11:4]
HWTRS[H:A] HWTRS[H:A]
EXTAL1
XTAL1
XOSC1
CLKO
TOD
control
REF CLK IRCLK
Clock Check
& Select
SPI2
SS2
SPSCK2
MOSI2
MISO2
Port F
IRQ
PTE4/CMPP3/
TPMCLK/VPP/IRQ
TPMCLK
TPM1CH[3:0]
TPMCLK
TPM2CH[3:0]
control
KBI2P[7:0]
VDDA/VSSA
VREFH/VREFL
DACO
USBOTG
FLASH2
128/64 KB
USB_DM USB_DP VBUS
Port G
Port H
Port J
Dtrig
Dtrig
COCOx
USB_ALTCLK
USB_PULLUP(D+)
USB_DM_DOWN
USB_DP_DOWN
USB_VBUSVLD
USB_ID
USB_SESSVLD
USB_SESSEND
MINIFLEX
FB_AD[19:0]
BUS
FB_D[7:0]
DACO
DADP[3:0]
IRO
FB_AD[19:0]
Green pins not available on the 100, 81 or 80 pin package
Blue pins not available on the 81 or 80 pin package
Red pin not available on the 80 pin package
VUSB33
PTB3/XTAL1
PTB4/EXTAL2
PTB5/XTAL2
PTB2/EXTAL1
PTB1/BLMS
PTB0
PTB6/KBI1P3/RGPIOP0/FB_AD17
PTB7/KBI1P4/RGPIOP1/FB_AD0
PTD3/USB_PULLUP(D+)/RGPIOP9/TPM1CH1
PTD4/SDA/RGPIOP10/TPM1CH2
PTD5/SCL/RGPIOP11/TPM1CH3
PTD2/USB_ALTCLK/RGPIOP8/TPM1CH0
PTD1/CMPP2/RESET
PTD6/USB_ALTCLK/TX1
PTD7/USB_PULLUP(D+)/RX1
PTC3/KBI1P6/SS2/ADP7
PTC4/KBI1P7/CMPP0/ADP8
PTC5/KBI2P0/CMPP1/ADP9
PTC2/KBI1P5/SPSCK2/ADP6
PTC1/MISO2/FB_D0/FB_AD1
PTC0/MOSI2/FB_OE_b/FB_CS0
PTC6/KBI2P1/PRACMPO/ADP10
PTA3/KBI1P2/FB_D6/ADP5
PTA4
PTA5
PTA2/KBI1P1/RX1/ADP4
PTA1/KBI1P0/TX1/FB_D1
PTA0/FB_D2/SS1
PTA6
PTA7
PTF3/SCL/FB_D5/FB_AD11
PTF4/SDA/FB_D4/FB_AD10
PTF5/KBI2P7/FB_D3/FB_AD9
PTF2/TX2/USB_DM_DOWN/TPM2CH0
PTF1/RX2/USB_DP_DOWN/TPM2CH1
PTF0/USB_ID/TPM2CH2
PTF6/MOSI1
PTF7/MISO1
PTE2/KBI2P5/RGPIOP14/FB_AD7
PTE3/KBI2P6/FB_AD8
PTE5/FB_D7/USB_SESSVLD/TX2
PTE1/KBI2P4/RGPIOP13/FB_AD6
PTE0/KBI2P3/FB_ALE/FB_CS1
PTE6/FB_RW_b/USB_SESSEND/RX2
PTE7/USB_VBUSVLD/TPM2CH3
PTG3/USB_DP_DOWN
PTG4/USB_SESSVLD
PTG5/FB_RW_b
PTG2/USB_DM_DOWN
PTG1/USB_SESSEND
PTG0/SPSCK1
PTG6/FB_AD19
PTG7/FB_AD18
PTH3/RGPIOP3/FB_D6
PTH4/RGPIOP4/FB_D5
PTH5/RGPIOP5/FB_D4
PTH2/RGPIOP2/FB_D7
PTH1/FB_D0
PTH0/FB_OE_b
PTH6/RGPIOP6/FB_D3
PTH7/RGPIOP7/FB_D2
PTJ3/RGPIOP12/FB_AD5
PTJ4/RGPIOP15/FB_AD16
PTJ5/FB_AD15
PTJ2/FB_AD4
PTJ1/FB_AD3
PTJ0/FB_AD2
PTJ6/FB_AD14
PTJ7/FB_AD13
PTC7/KBI2P2CLKOUT/ADP11
DADM[3:0] DADP/M[3:0]
MCF51JE256 Datasheet, Rev. 4
Features
Freescale Semiconductor4
1Features
The following table provides a cross-comparison of the features of the MCF51JE256/128 according to
package.
The following table describes the functional units of the MCF51JE256/128.
Table 1. MCF51JE Featu res by MCU and Package
Feature MCF51JE256 MCF51JE128
FLASH size (bytes) 262144 131072
RAM size (bytes) 32K 32K
Pin quantity 104 100 81 80 81 80
Programmable Analog Comparator (PRACMP) yes
Debug Module (DBG) yes
Multipurpose Clock Generator (MCG) yes
Inter-Integrated Communication (IIC) yes
Interrupt Request Pin (IRQ) yes
Keyboard Interrupt (KBI) 16
Digital General purpose I/O1
1Port I/O count does not include BLMS, BKGD and IRQ. BLMS BKGD are Output only, IRQ is input only.
69 65 48 47 48 47
Power and Ground Pins 8
Time Of Day (TOD) yes
Serial Communications (SCI1) yes
Serial Communications (SCI2) yes
Serial Peripheral Interface (SPI1(FIFO)) yes
Serial Peripheral Interface(SPI2) yes
Carr ier Modulator Timer pin (IRO) yes
Programmable Delay Block (PDB) yes
TPM input clock pin (TPMCLK) yes
TPM1 channels 4
TPM2 channels 4
XOSC1 yes
XOSC2 yes
USBOTG yes
MiniFlex Bus yes DATA
Rapid GPIO 16 9
ADC single-ended channels 12
DAC ouput pin (DACO) yes
Voltage reference output pin (VREFO) yes
Features
MCF51JE256 Datasheet, Rev. 4
Freescale Semiconductor 5
Table 2. MCF51JE256/128 Functional Units
Unit Function
DAC (digital to analog converter) Used to output voltage levels.
12-BIT SAR ADC (analog-to-digital
converter) Measures analog voltages at up to 12 bits of resolution. The ADC has
up to 12 single-ended inputs.
PDB (Programmable Delay Block) Precisely trigger the DAC FIFO buffer.
Mini-FlexBus Provides expansion capability for off-chip memory and peripherals.
USB On-the-Go Supports the USB On-the-Go dual-ro le controller.
CMT (Carrier Modulator Timer) Infrared output used for the Remote Controller operation.
MCG (Multipurpose Clock Generator) Provides clocking options for the device, including a phase-locked loop
(PLL) and frequency-locked loop (FLL) for multiplying slower reference
clock sources.
BDM (Background Debug Module) Provides single pin debugging interface (part of the V1 ColdFire core).
CF1 CORE (V1 ColdFire Core) Executes programs and interrupt handlers.
PRACMP Analog comparators for comparing external analog signals against
each other, or a variety of refere nce levels.
COP (Computer Operating Properly) Software Watchdog.
IRQ (Interrupt Request) Single-pin high-priority interrupt (part of the V1 ColdFire core).
CRC (Cyclic Redundancy Check) High-speed CRC calculation.
DBG (Debug) Provides debugging and emulation capabilities (part of the V1 ColdFire
core).
FLASH (Flash Memory) Provides storage for program code, constants, and variables.
IIC (Inter-integrated Circuits) Supports standard IIC communica tions protocol and SMBus.
INTC (Interrupt Controller) Controls and prioritizes all device interrupts.
KBI1 & KBI2 Keyboard Interfaces 1 and 2.
LVD (Low-voltage Detect) Provides an interrupt to the ColdFire V1 CORE in the event that the
supply voltage drops below a critical value. The LVD can also be
programmed to reset the device upon a low voltage event.
VREF (V olta ge Reference) The V olt age Reference output is available for both on- and off-chip use.
RAM (Random-Access Memory) Provides stack and variable storage.
RGPIO (Rapid General-purpose
Input/output) Allows for I/O port access at CPU clock speeds. RGPIO is used to
implement GPIO functionality.
SCI1, SCI2 (Serial Communications
Interfaces) Serial communications UARTs capable of supporting RS-232 and LIN
protocols.
SIM (system integration unit)
MCF51JE256 Datasheet, Rev. 4
Features
Freescale Semiconductor6
SPI1 (FIFO), SPI2 (Serial Peripheral
Interfaces) SPI1 and SPI2 provide standard master/slave capability . SPI contains a
FIFO buffer in order to increase the throughput for this periphe ral.
TPM1, TPM2 (Timer/PWM Module) Timer/PWM module can be used fo r a variety of generic timer
operations as well as pulse-width modulation.
VREG (Voltage Regulator) Controls power management across the device.
XOSC1 and XOSC2 (Crystal Oscillators) These devices incorporate redundant crystal oscillators. One is
intended primarily for use by the TOD, and the other by the CPU and
other peripherals.
Table 2 . MCF51JE256/128 Functional Units (continued)
Unit Function
Pinouts and Pin Assignments
MCF51JE256 Datasheet, Rev. 4
Freescale Semiconductor 7
2 Pinouts and Pin Assignments
2.1 104-Pin MAPBGA
The following figure shows the 104-pin MAPBGA pinout configuration.
Figure 2. 104-Pin MAPBGA
1234567891011
APTF6 PTF7 USB_DP USB_DM VUSB33 PTF4 PTF3 FB_AD12 PTJ7 PTJ5 PTJ4 A
BPTG0 PTA0 PTG3 VBUS PTF5 PTJ6 PTH0 PTE5 PTF0 PTF1 PTF2 B
CIRO PTG4 PTA6 PTG2 PTG6 PTG5 PTG7 PTH1 PTE4 PTE6 PTE7 C
DPTA5 PTA4 PTB1 VDD1 VDD2 VDD3 PTA1 PTE3 PTE2 D
EVSSA PTA7 PTB0 PTA2 PTJ3 PTE1 E
FVREFL PTG1 PTC7 PTJ2 PTJ0 PTJ1 F
GADP2 PTD5 PTD7 PTE0 G
HPTA3 VSS1 VSS2 VSS3 PTD4 PTD3 PTD2 H
JADP0 PTH7 PTH6 PTH4 PTH3 PTH2 PTD6 PTC2 PTC0 PTC1 J
KADP1 PTH5 PTB6 PTB7 PTC3 PTD1 PTC4 PTC5 PTC6 K
LADP3 DACO VREFO VREFH VDDA PTB3 PTB2 PTD0 PTB5 PTB4 L
1234567891011
MCF51JE256 Datasheet, Rev. 4
Pinouts and Pin Assignments
Freescale Semiconductor8
2.2 100-Pin LQFP
The following figure shows the 100-pin LQFP pinout configuration.
Figure 3. 100-Pin LQFP
PTC2/KBI1P5/SPSCK2/ADP6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
PTA0/FB_D2/SS1
IRO
PTG5/FB_RW
PTG6/FB_AD19
PTG7/FB_AD18
PTH0/FB_OE
PTA1/KBI1P0/TX1/FB_D1
PTA2/KBI1P1/RX1/ADP4
PTA3/KBI1P2/FB_D6/ADP5
PTA4
PTA5
PTA6
PTA7
PTB0
PTB1/BLMS
VSSA
VREFL
NC
NC
ADP2
NC
NC
NC
100 LQFP
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PTE4/CMPP3/TPMCLK/IRQ
PTE3/KBI2P6/FB_AD8
PTE2/KBI2P5/RGPIOP14/FB_AD7
PTE1/KBI2P4/RGPIOP13/FB_AD6
PTJ3/RGPIOP12/FB_AD5
PTJ2/FB_AD4
PTJ1/FB_AD3
PTJ0/FB_AD2
PTE0/KBI2P3/FB_ALE/FB_CS1
PTD7/USB_PULLUP(D+)/RX1
PTD6/USB_ALTCLK/TX1
PTD5/SCL/RGPIOP11/TPM1CH3
PTD4/SDA/RGPIOP10/TPM1CH2
PTD3/USB_PULLUP(D+)/RGPIOP9/TPM1CH1
PTD2/USB_ALTCLK/RGPIOP8/TPM1CH0
PTD1/CMPP2/RESET
PTD0/BKGD/MS
PTC7/KBI2P2/CLKOUT/ADP11
PTC6/KBI2P1/PRACMPO/ADP10
PTC5/KBI2P0/CMPP1/ADP9
PTC4/KBI1P7/CMPP0/ADP8
PTC1/MISO2/FB_D0/FB_AD1
PTC0/MOSI2/FB_OE/FB_CS0
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
PTG0/SPSCK1
PTF7/MISO1
PTF6/MOSI1
VDD1
VSS1
VBUS
USB_DP
USB_DM
VUSB33
PTF5/KBI2P7/FB_D3/FB_AD9
PTF4/SDA/FB_D4/FB_AD10
PTF3/SCL/FB_D5/FB_AD11
FB_AD12
PTJ7/FB_AD13
PTJ6/FB_AD14
PTJ4/RGPIOP15/FB_AD16
PTF2/TX2/USB_DM_DOWN/TPM2CH0
PTF1/RX2/USB_DP_DOWN/TPM2CH1
PTF0/USB_ID/TPM2CH2
PTE7/USB_VBUSVLD/TPM2CH3
PTE6/FB_RW/USB_SESSEND/RX2
PTE5/FB_D7/USB_SESSVLD/TX2
VDD3
VSS3
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
DACO
ADP3
NC
NC
ADP0
NC
VREFO
ADP1
NC
VREFH
VDDA
VSS2
PTB2/EXTAL1
PTB3/XTAL1
VDD2
PTB4/EXTAL2
PTB5/XTAL2
PTB6/KBI1P3/RGPIOP0/FB_AD17
PTB7/KBI1P4/RGPIOP1/FB_AD0
PTH2/RGPIOP2/FB_D7
PTH3/RGPIOP3/FB_D6
PTH4/RGPIOP4/FB_D5
PTH5/RGPIOP5/FB_D4
PTH6/RGPIOP6/FB_D3
PTH7/RGPIOP7/FB_D2
NC
PTH1/FB_D0
PTC3/KBI1P6/SS2/ADP7
PTJ5/FB_AD15
Pinouts and Pin Assignments
MCF51JE256 Datasheet, Rev. 4
Freescale Semiconductor 9
2.3 81-Pin MAPBGA
The following figure shows the 81-pin MAPBGA pinout configuration.
Figure 4. 81-Pin MAPBGA
123456789
AIRO PTG0 PTF6 USB_DP VBUS VUSB33 PTF4 PTF3 PTE4 A
BPTF7 PTA0 PTG1 USB_DM PTF5 PTE7 PTF1 PTF0 PTE3 B
CPTA4 PTA5 PTA6 PTA1 PTF2 PTE6 PTE5 PTE2 PTE1 C
DPTA7 PTB0 PTB1 PTA2 PTA3 PTD5 PTD7 PTE0 D
EVDD2 VDD3 VDD1 PTD2 PTD3 PTD6 E
FADP2 VSS2 VSS3 VSS1 PTB7 PTC7 PTD4 F
GADP0 DACO ADP3 VREFO PTB6 PTC0 PTC1 PTC2 G
HADP1 PTC3 PTC4 PTD0 PTC5 PTC6 H
JVSSA VREFL VREFH VDDA PTB2 PTB3 PTD1 PTB4 PTB5 J
123456789
MCF51JE256 Datasheet, Rev. 4
Pinouts and Pin Assignments
Freescale Semiconductor10
2.4 80-Pin LQFP
The following figure shows the 80-pin LQFP pinout configuration.
Figure 5. 80-Pin LQFP Pinout
PTA0/FB_D2/SS1
IRO
PTA1/KBI1P0/TX1/FB_D1
PTA2/KBI1P1/RX1/ADP4
PTA3/KBI1P2/FB_D6/ADP5
PTA4
PTA5
PTA6
PTA7
PTB0
PTB1/BLMS
VSSA
VREFL
NC
NC
ADP2
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
DACO
NC
NC
ADP0
NC
VREFO
ADP1
NC
VREFH
VDDA
VSS2
PTB2/EXTAL1
PTB3/XTAL1
VDD2
PTB4/EXTAL2
PTB5/XTAL2
PTB6/KBI1P3/RGPIOP0/FB_AD17
PTB7/KBI1P4/RGPIOP1/FB_AD0
PTC0/MOSI2/FB_OE/FB_CS0
PTE4/CMPP3/TPMCLK/IRQ
PTE3/KBI2P6/FB_AD8
PTE2/KBI2P5/RGPIOP14/FB_AD7
PTE1/KBI2P4/RGPIOP13/FB_AD6
PTE0/KBI2P3/FB_ALE/FB_CS1
PTD7/USB_PULLUP(D+)/RX1
PTD6/USB_ALTCLK/TX1
PTD5/SCL/RGPIOP11/TPM1CH3
PTD4/SDA/RGPIOP10/TPM1CH2
PTD3/USB_PULLUP(D+)/RGPIOP9/TPM1CH1
PTD2/USB_ALTCLK/RGPIOP8/TPM1CH0
PTD1/CMPP2/RESET
PTD0/BKGD/MS
PTC7/KBI2P2/CLKOUT/ADP11
PTC6/KBI2P1/PRACMPO/ADP10
PTC5/KBI2P0/CMPP1/ADP9
PTC4/KBI1P7/CMPP0/ADP8
PTC3/KBI1P6/SS2/ADP7
PTC2/KBI1P5/SPSCK2/ADP6
PTC1/MISO2/FB_D0/FB_AD1
PTG0/SPSCK1
PTF7/MISO1
PTF6/MOSI1
VDD1
VSS1
VBUS
USB_DP
USB_DM
VUSB33
PTF5/KBI2P7/FB_D3/FB_AD9
PTF4/SDA/FB_D4/FB_AD10
PTF3/SCL/FB_D5/FB_AD11
PTF2/TX2/USB_DM_DOWN/TPM2CH0
PTF1/RX2/USB_DP_DOWN/TPM2CH1
PTF0/USB_ID/TPM2CH2
PTE7/USB_VBUSVLD/TPM2CH3
PTE6/FB_RW/USB_SESSEND/RX2
PTE5/FB_D7/USB_SESSVLD/TX2
VDD3
VSS3
ADP3
80-Pin LQFP
Pinouts and Pin Assignments
MCF51JE256 Datasheet, Rev. 4
Freescale Semiconductor 11
2.5 Pin Assignments
Table 3. Package Pin Assignments
Package
Default
Function Alternate 1 Alternate 2 Alternate 3 Composite Pin Name
104
MAPB
GA
100
LQFP
81
MAPB
GA
80
LQFP
B2 1 B2 1 PTA0 FB_D2 SS1 — PTA0/FB_D2/SS1
C12A12 IRO — — — IRO
C6 3 — — PTG5 FB_RW — — PTG5/FB_RW
C5 4 — — PTG6 FB_AD19 — — PTG6/FB_AD19
C7 5 — — PTG7 FB_AD18 — — PTG7/FB_AD18
B7 6 — — PTH0 FB_OE — — PTH0/FB_OE
C8 7 — — PTH1 FB_D0 — — PTH1/FB_D0
D9 8 C4 3 PTA1 KBI1P0 TX1 FB_D1 PTA1/KBI1P0/TX1/FB_D1
E9 9 D5 4 PTA2 KBI1P1 RX1 ADP4 PTA2/KBI1P1/RX1/ADP4
H3 10 D6 5 PTA3 KBI1P2 FB_D6 ADP5 PTA3/KBI1P2/FB_D6/ADP5
D2 11 C1 6 PTA4 — — — PTA4
D1 12 C2 7 PTA5 — — — PTA5
C3 13 C3 8 PTA6 — — — PTA6
E2 14 D2 9 PTA7 — — — PTA7
E3 15 D3 10 PTB0 — — — PTB0
D3 16 D4 11 PTB1 BLMS — — PTB1/BLMS
E1 17 J1 12 VSSA — — — VSSA
F1 18 J2 13 VREFL — — — VREFL
F2 19 D1 19 — — — — NC
G2 20 E2 15 — — — — NC
G1 21 F2 16 ADP2 — — — ADP2
H1 22 F1 17 — — — — NC
H2 23 E2 18 NC — — — NC
F3 24 F3 19 — — — — NC
G3 25 E3 20 — — — — NC
L2 26 G2 21 DACO — — — DACO
L1 27 G3 22 ADP3 — — — ADP3
K1 28 H4 23 — — — — NC
K2 29 G4 24 NC — — — NC
J1 30 G1 25 ADP0 — — — ADP0
J2 31 H1 26 — — — — NC
L4 32 G5 27 VREFO — — — VREFO
K3 33 H3 28 ADP1 — — — ADP1
L3 34 H2 29 NC — — — NC
MCF51JE256 Datasheet, Rev. 4
Pinouts and Pin Assignments
Freescale Semiconductor12
L5 35 J3 30 VREFH — — — VREFH
L6 36 J4 31 VDDA — — — VDDA
H6 37 F4 32 VSS2 — — — VSS2
L8 38 J5 33 PTB2 EXTAL1 — — PTB2/EXTAL1
L7 39 J6 34 PTB3 XTAL1 — — PTB3/XTAL1
D6 40 E4 35 VDD2 — — — VDD2
L11 41 J8 36 PTB4 EXTAL2 — — PTB4/EXTAL2
L1042J937 PTB5 XTAL2 — — PTB5/XTAL2
K5 43 G6 38 PTB6 KBI1P3 RGPIOP0 FB_AD17 PTB6/KBI1P3/RGPIOP0/
FB_AD17
K6 44 F7 39 PTB7 KBI1P4 RGPIOP1 FB_AD0 PTB7/KBI1P4/RGPIOP1/
FB_AD0
J7 45 — — PTH2 RGPIOP2 FB_D7 — PTH2/RGPIOP2/FB_D7
J6 46 — — PTH3 RGPIOP3 FB_D6 — PTH3/RGPIOP3/FB_D6
J5 47 — — PTH4 RGPIOP4 FB_D5 — PTH4/RGPIOP4/FB_D5
K4 48 — — PTH5 RGPIOP5 FB_D4 — PTH5/RGPIOP5/FB_D4
J4 49 — — PTH6 RGPIOP6 FB_D3 — PTH6/RGPIOP6/FB_D3
J3 50 — — PTH7 RGPIOP7 FB_D2 — PTH7/RGPIOP7/FB_D2
J1051G740 PTC0 MOSI2 FB_OE FB_CS0 PTC0/MOSI2/FB_OE/ FB_CS0
J11 52 G8 41 PTC1 MISO2 FB_D0 FB_AD1 PTC1/MISO2/FB_D0/FB_AD1
J9 53 G9 42 PTC2 KBI1P5 SPSCK2 ADP6 PTC2/KBI1P5/SPSCK2/ADP6
K7 54 H5 43 PTC3 KBI1P6 SS2 ADP7 PTC3/KBI1P6/SS2/ADP7
K9 55 H6 44 PTC4 KBI1P7 CMPP0 ADP8 PTC4/KBI1P7/CMPP0/ADP8
K10 56 H8 45 PTC5 KBI2P0 CMPP1 ADP9 PTC5/KBI2P0/CMPP1/ADP9
K11 57 H9 46 PTC6 KBI2P1 PRACMPO ADP10 PTC6/KBI2P1/PRACMPO/
ADP10
F8 58 F8 47 PTC7 KBI2P2 CLKOUT ADP11 PTC7/KBI2P2/CLKOUT/ADP11
L9 59 H7 48 PTD0 BKGD MS — PTD0/BKGD/MS
K8 60 J7 49 PTD1 CMPP2 RESET — PTD1/CMPP2/RESET
H11 61 E7 50 PTD2 USB_ALTCL
KRGPIOP8 TPM1CH0 PTD2/USB_ALTCLK/RGPIOP8/
TPM1CH0
H10 62 E8 51 PTD3 USB_PULL
UP(D+) RGPIOP9 TPM1CH1 PTD3/USB_PULLUP(D+)/
RGPIOP9/TPM1CH1
H9 63 F9 52 PTD4 SDA RGPIOP10 TPM1CH2 PTD4/SDA/RGPIOP10/
TPM1CH2
G9 64 D7 53 PTD5 SCL RGPIOP11 TPM1CH3 PTD5/SCL/RGPIOP11/
TPM1CH3
J8 65 E9 54 PTD6 USB_ALTCL
KTX1 — PTD6/USB_ALTCLK/TX1
Table 3. Package Pin Assignments (continued)
Package
Default
Function Alternate 1 Alternate 2 Alternate 3 Composite Pin Name
104
MAPB
GA
100
LQFP
81
MAPB
GA
80
LQFP
Pinouts and Pin Assignments
MCF51JE256 Datasheet, Rev. 4
Freescale Semiconductor 13
G10 66 D8 55 PTD7 USB_PULL
UP(D+) RX1 — PTD7/USB_PULLUP(D+) /RX1
G11 67 D9 56 PTE0 KBI2P3 FB_ALE FB_CS1 PTE0/KBI2P3/FB_ALE/
FB_CS1
F10 68 — — PTJ0 FB_AD2 — — PTJ0/FB_AD2
F11 69 — — PTJ1 FB_AD3 — — PTJ1/FB_AD3
F9 70 — — PTJ2 FB_AD4 — — PTJ2/FB_AD4
E10 71 — — PTJ3 RGPIOP12 FB_AD5 — PTJ3/RGPIOP12/FB_AD5
E11 72 C9 57 PTE1 KBI2P4 RGPIOP13 FB_AD6 PTE1/KBI2P4/RGPIOP13/
FB_AD6
D11 73 C8 58 PTE2 KBI2P5 RGPIOP14 FB_AD7 PTE2/KBI2P5/RGPIOP14/
FB_AD7
D10 74 B9 59 PTE3 KBI2P6 FB_AD8 — PTE3/KBI2P6/FB_AD8
C9 75 A9 60 PTE4 CMPP3 TPMCLK IRQ PTE4/CMPP3/TPMCLK/VPP/
IRQ
H8 76 F5 61 VSS3 — — — VSS3
D8 77 E5 62 VDD3 — — — VDD3
B8 78 C7 63 PTE5 FB_D7 USB_
SESSVLD TX2 PTE5/FB_D7/USB_SESSVLD/
TX2
C10 79 C6 64 PTE6 FB_RW USB_
SESSEND RX2 PTE6/FB_RW_b/
USB_SESSEND/RX2
C11 80 B6 65 PTE7 USB_VBUS
VLD TPM2CH3 — PTE7/USB_VBUSVLD/
TPM2CH3
B9 81 B8 66 PTF0 USB_ID TPM2CH2 — PTF0/USB_ID/TPM2CH2
B10 82 B7 67 PTF1 RX2 USB_DP_
DOWN TPM2CH1 PTF1/RX2/USB_DP_DOWN/
TPM2CH1
B11 83 C5 68 PTF2 TX2 USB_DM_
DOWN TPM2CH0 PTF2/TX2/USB_DM_DOWN/
TPM2CH0
A11 84 — — PTJ4 RGPIOP15 FB_AD16 — PTJ4/RGPIOP15/FB_AD16
A10 85 — — PTJ5 FB_AD15 — — PTJ5/FB_AD15
B6 86 — — PTJ6 FB_AD14 — — PTJ6/FB_AD14
A9 87 — — PTJ7 FB_AD13 — — PTJ7/FB_AD13
A8 88 — — FB_AD12 — — — FB_AD12
A7 89 A8 69 PTF3 SCL FB_D5 FB_AD11 PTF3/SCL/FB_D5/FB_AD11
A6 90 A7 70 PTF4 SDA FB_D4 FB_AD10 PTF4/SDA/FB_D4/FB_AD10
B5 91 B5 71 PTF5 KBI2P7 FB_D3 FB_AD9 PTF5/KBI2P7/FB_D3/FB_AD9
A5 92 A6 72 VUSB33 — — — VUSB33
A4 93 B4 73 USB_DM — — — USB_DM
A3 94 A4 74 USB_DP — — — USB_DP
B4 95 A5 75 VBUS — — — VBUS
Table 3. Package Pin Assignments (continued)
Package
Default
Function Alternate 1 Alternate 2 Alternate 3 Composite Pin Name
104
MAPB
GA
100
LQFP
81
MAPB
GA
80
LQFP
MCF51JE256 Datasheet, Rev. 4
Pinouts and Pin Assignments
Freescale Semiconductor14
H4 96 F6 76 VSS1 — — — VSS1
D4 97 E6 77 VDD1 — — — VDD1
A1 98 A3 78 PTF6 MOSI1 — — PTF6/MOSI1
A2 99 B1 79 PTF7 MISO1 — — PTF7/MISO1
B1 100 A2 80 PTG0 SPSCK1 — — PTG0/SPSCK1
F4 — B3 — PTG1 USB_SESS
END — — PTG1/USB_SESSEND
C4 — — — PTG2 USB_DM_D
OWN — — PTG2/USB_DM_DOWN
B3 — — — PTG3 USB_DP_D
OWN — — PTG3/USB_DP_DOWN
C2 — — — PTG4 USB_SESS
VLD — — PTG4/USB_SESSVLD
Table 3. Package Pin Assignments (continued)
Package
Default
Function Alternate 1 Alternate 2 Alternate 3 Composite Pin Name
104
MAPB
GA
100
LQFP
81
MAPB
GA
80
LQFP
Preliminary Electrical Characteristics
MCF51JE256 Datasheet, Rev. 4
Freescale Semiconductor 15
3 Preliminary Electrical Characteristics
This section contains electrical specification tables and reference timing diagrams for the
MCF51JE256/128 microcontroller, including detailed information on power considerations, DC/AC
electrical characteristics, and AC timing specifications.
The electrical specifications are preliminary and are from previous designs or design simulations. These
specifications may not be fully tested or guaranteed at this early stage of the product life cycle. These
specifications will, however , be met for production silicon. Finalized specifications will be published after
complete characterization and device qualifications have been completed.
NOTE
The parameters specified in this data sheet supersede any values found in the module
specifications.
3.1 Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the
customer a better understanding, the following classification is used and the parameters are tagged
accordingly in the tables where appropriate:
NOTE
The classification is shown in the column labeled “C” in the parameter tables where
appropriate.
3.2 Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not
guaranteed. S tress beyond the limits specified in the following table may affect device reliability or cause
permanent damage to the device. For functional operating conditions, refer to the re maining tables in this
section.
Table 4. Parameter Classifications
PThose parameters are guaranteed during production testing on each individual device.
CThose parameters are achieved by the design characterization by measuring a statistically relevant
sample size across process variations.
TThose parameters are achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted. All values shown in the typical column are within this
category.
DThose parameters are derived mainly from simulations.
MCF51JE256 Datasheet, Rev. 4
Preliminary Electrical Characteristics
Freescale Semiconductor16
This device contains circuitry protecting against damage due to high static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD).
3.3 Thermal Characteristics
This section provides information about operating temperature range, power dissipation, and package
thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in
on-chip logic and it is user-determined rather than being controlled by the MCU design. In order to take
PI/O into account in power calculations, determine the difference between actual pin voltage and VSS or
VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current (heavy
loads), the difference between pin voltage and VSS or VDD will be very small.
Table 5. Absolute Maximum Ratings
# Rating Symbol Value Unit
1 Supply voltage VDD –0.3 to 3.8 V
2 Maximum current into VDD IDD 120 mA
3 Digital Input v oltage VIn –0.3 to VDD + 0.3 V
4Instantaneous maximum current
Single pin limit (applies to all port pins)1, 2, 3
1Input must be current limited to the value specified. To determine the value of the required current-limiting resistor,
calculate resistance values for positive (VDD) and negative (VSS) clamp voltages, then use the larger of the two
resistance values.
2All functional non-supply pins are internally clamped to VSS and VDD.
3Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum
current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD
and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater
than maximum injection current. This will be the greatest risk when the MCU is not consuming power . Examples are: if
no system clock is present, or if the clock rate is very low (which would reduce overall power consumption).
ID25 mA
5 Storage temperature range Tstg –55 to 150 C
Preliminary Electrical Characteristics
MCF51JE256 Datasheet, Rev. 4
Freescale Semiconductor 17
The average chip-junction temperature (TJ) in C can be obtained from:
TJ = TA + (PD JA)Eqn. 1
where:
TA = Ambient temperature, C
JA = Package thermal resistance, junction-to-ambient, C/W
PD = Pint PI/O
Pint = IDD VDD, Watts — chip int ernal power
PI/O = Power dissipation on input and output pins — user determined
For most applications, PI/O  Pint and can be neglected. An approximate relationship between PD and TJ
(if PI/O is neglected) is:
PD = K (TJ + 273C) Eqn. 2
Solving Equation 1 and Equation 2 for K gives:
K = PD (TA + 273C) + JA (PD)2Eqn. 3
Table 6. Thermal Characteristics
# Symbol Rating Value Unit
1TA
Operating temperature range (packaged):
C
MCF51JE256 –40 to 105
MCF51JE128 –40 to 105
2TJMAX Maximum junction temperature 135 C
3JA
Thermal resistance1,2,3,4 Single-layer board — 1s
1Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temper ature , air flow, power dissipation of other components on the board, and board
thermal resistance.
2Junction to Ambient Natural Convection
31s — Single layer board, one signal layer
42s2p — Four layer board, 2 signal and 2 power layers
C/W
104-pin MBGA 67
100-pin LQFP 53
81-pin MBGA 67
80-pin LQFP 53
4JA
Thermal resistance1, 2, 3, 4 Four-layer board — 2s2p
C/W
104-pin MBGA 39
100-pin LQFP 41
81-pin MBGA 39
80-pin LQFP 39
MCF51JE256 Datasheet, Rev. 4
Preliminary Electrical Characteristics
Freescale Semiconductor18
where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring
PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by
solving Equation 1 and Equation 2 iteratively for any value of TA.
3.4 ESD Protection Characteristics
Although damage from static discharge is much less common on these devices than on early CMOS
circuits, normal handling precautions should be used to avoid exposure to static discharge. Qualification
tests are performed to ensure that these devices can withstand exposure to reasonable levels of static
without suffering any permanent damage.
All ESD testing is in conformity with CDF-AEC-Q00 Stress Test Qualification for Automotive Grade
Integrated Circuits. (http://www.aecouncil.com/) This device was qualified to AEC-Q100 Rev E.
A device is considered to have failed if, after exposure to ESD pulses, the device no longer meets the
device specification requirements. Complete dc parametric and functional testing is performed per the
applicable device specification at room temperature followed by hot temperature, unless specified
otherwise in the device specification.
3.5 DC Characteristics
This section includes information about power supply requirements, I/O pin characteristics, and power
supply current in various operating modes.
Table 7. ESD and Latch-up Test Conditions
Model Description Symbol Value Unit
Human Body
Series Resistance R1 150 0
Storage Capacitance C 100 pF
Number of Pulse per pin — 3 —
Machine
Series Resistance R1 0
Storage Capacitance C 200 pF
Number of Pulse per pin — 3 —
Latch-up Minimum input voltage limit —–2.5 V
Maximum input voltage limit —7.5 V
Table 8. ESD and Latch-Up Protection Characteristics
# Rating Symbol Minimum Maximum Unit C
1 Human Body Model (HBM) VHBM 2000 — V T
2 Machine Model (MM) VMM 200 — V T
3 Charge Device Model (CDM) VCDM 500 — V T
4 Latch-up Current at TA = 125CI
LAT 00 — mA T
Preliminary Electrical Characteristics
MCF51JE256 Datasheet, Rev. 4
Freescale Semiconductor 19
Table 9. DC Characteristics
#Symbol Characteristic Condition Minimum Typical1Maximum Unit C
1— Operating Voltage — 1.82—3.6V—
2VOH Output high
voltage All I/O pins, low-drive strength
VDD 1.8 V,
ILoad = –600 AVDD – 0.5 — — V C
All I/O pins, high-drive strength
VDD 2.7 V,
ILoad = –10 mA VDD – 0.5 — — V P
VDD 2.3 V,
ILoad = –6 mA VDD – 0.5 — — V T
VDD 1.8V,
ILoad = –3 mA VDD – 0.5 — — V C
3IOHT Output high
current Max total IOH for all ports
— — — 100 mA D
4VOL Output low
voltage All I/O pins, low-drive strength
VDD 1.8 V,
ILoad = 600 A——0.5VC
All I/O pins, high-drive strength
VDD 2.7 V,
ILoad = 10 mA ——0.5VP
VDD 2.3 V,
ILoad = 6 mA ——0.5VT
VDD 1.8 V,
ILoad = 3 mA ——0.5VC
5IOLT
Output low
current Max total IOL for all ports
— — — 100 mA D
6VIH Input high voltage all digital inputs
VDD 2.7 V 0.70 x VDD ——VP
VDD 1.8 V 0.85 x VDD ——VC
7VIL Input low voltage all digital inputs
VDD 2.7 V — — 0.35 x VDD VP
VDD 1.8 V — — 0.30 x VDD VC
8Vhys Input hysteresis all digital inputs — 0.06 x VDD ——mVC
9|IIn|Input leakage
current all input only pins
(Per pin) VIn = VDD or VSS ——0.5AP
10 |IOZ|Hi-Z (off-state)
leakage current3 all input/output
(per pin) VIn = VDD or VSS —0.0030.5AP
MCF51JE256 Datasheet, Rev. 4
Preliminary Electrical Characteristics
Freescale Semiconductor20
11 RPU Pull-up resistors all digital inputs, when
enabled — 17.5 — 52.5 kP
12 RPD
Internal
pull-down
resistors4— 17.5 — 52.5 kP
13 IIC DC injection
current 5, 6, 7
Single pin limit VSS > VIN > VDD –0.2 — 0.2 mA D
Total MCU limit, includes
sum of all stressed pins VSS > VIN > VDD –5 — 5 mA
14 CIn Input Capacitance, all pins — — — 8 pF C
15 VRAM RAM retention voltage — — 0.6 1.0 V C
16 VPOR POR re-arm voltage8—0.91.41.79VC
17 tPOR POR re-arm time — 10 — — sD
18 VLVDH Low-voltage detection thresho ld — high range9
VDD falling 2.11 2.16 2.22 V P
VDD rising 2.16 2.21 2.27 V P
19 VLVDL Low-voltage detection threshold — low range9
VDD falling 1.80 1.82 1.91 V P
VDD rising 1.86 1.90 1.99 V P
20 VLVWH Low-voltage warning threshold — high range9
VDD falling 2.36 2.46 2.56 VP
VDD rising 2.36 2.46 2.56 V P
21 VLVWL Low-voltage warning threshold — low range9
VDD falling 2.11 2.16 2.22 V P
VDD rising 2.16 2.21 2.27 V P
22 Vhys Low-voltage inhibit reset/recover
hysteresis10 ——50—mVC
23 VBG Bandgap Voltage Reference11 — 1.145 1.17 1.195 V P
1Typical values are measured at 25C. Characterized, not tested
2As the supply voltage rises, the LVD circuit will hold the MCU in reset until the supply has risen above VLVDL.
3Does not include analog module pins. Dedicated analog pins should not be pulled to VDD or VSS and should be left floating when not used
to reduce current leakage.
4Measured with VIn = VDD.
5All functional non-supply pins are internally clamped to VSS and VDD,except PTD1.
6Input must be current limited to the value specified. To determine the value of the required current-limiting resistor , calculate resistance values
for positive and negative clamp voltages, then use the larger of the two values.
7Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If positive
injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out
of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU
is not consuming power. Examples are: if no system clock is present, or if clock rate is very low (which would reduce overall power
consumption).
Table 9. DC Characteristics (c on tinued)
#Symbol Characteristic Condition Minimum Typical1Maximum Unit C
Preliminary Electrical Characteristics
MCF51JE256 Datasheet, Rev. 4
Freescale Semiconductor 21
3.6 Supply Current Characteristics
8Maximum is highest voltage that POR is guaranteed.
9Run at 1 MHz bus frequency.
10 Low voltage detection and warning limits measured at 1 MHz bus frequency.
11 Factory trimmed at VDD = 3.0 V, Temp = 25C.
Table 10. Supply Current Characteristics
# Symbol Parameter Bus
Freq VDD
(V) Typical1Maximum Unit Temperature
(C) C
1RIDD Run supply current
FEI mode, all modules ON2
25.165 MHz 3 44 48 mA –40 to 25 P
25.165 MHz 3 44 48 mA 105 P
20 MHz 3 32.3 — mA –40 to 105 T
8 MHz 3 16.4 — mA –40 to 105 T
1 MHz 3 2.9 — mA –40 to 105 T
2RIDD Run supply current
FEI mode, all modules OFF3
25.165 MHz 3 29 29.6 mA –40 to 105 C
20 MHz 3 25.4 — mA –40 to 105 T
8 MHz 3 12.7 — mA –40 to 105 T
1 MHz 3 2.4 — mA –40 to 105 T
3RIDD Run supply current
LPR=0, all modules OFF3
16 kHz FBI 3 232 280 A –40 to 105 T
16 kHz FBE 3 231 296 A –40 to 105 T
4RIDD Run supply current
LPR=1, all modules OFF3
16 kHz
BLPE 374 75A 0 to 70 T
16 kHz
BLPE 3 74 120 A –40 to 105 T
5WIDD W ait mode supply current
FEI mode, all modules OFF3
25.165 MHz 3 16.5 — mA –-40 to 105 C
20 MHz 3 10.3 — mA –-40 to 105 T
8 MHz 3 6.6 — mA –-40 to 105 T
1 MHz 3 1.7 — mA –-40 to 105 T
MCF51JE256 Datasheet, Rev. 4
Preliminary Electrical Characteristics
Freescale Semiconductor22
6S2IDD Stop 2 mode
supply current4
N/A 3 0.410 1 A -40 to 25 P
N/A 3 3.7 10 A70C
N/A 3 10 20 A85C
N/A 3 21 31.5 A105P
N/A 2 0.410 0.640 A -40 to 25 C
N/A 2 3.4 9 A70C
N/A 2 9.5 18 A85C
N/A 2 20 30 A105C
7S3IDD
St op3 mode
supply current
No clocks active N/A 3 0.750 1.3 A -40 to 25 P
N/A 3 8.5 18 A70C
N/A 3 20 28 A85C
N/A 3 53 63 A105P
N/A 2 0.400 0.900 A -40 to 25 C
N/A 2 8.2 16 A70C
N/A 2 18 26 A85C
N/A 2 47 59 A105C
1Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value.
2ON = System Clock Gating Control registers turn on system clock to the corresponding modules.
3OFF = System Clock Gating Control registers turn off system clock to the corresponding modules.
4All digital pins must be configured to a known state to prevent floating pins from adding current. Smaller packages may have some pins that
are not bonded out; however, software must still be configured to the largest pin package available so that all pins are in a known state.
Otherwise, floating pins that are not bonded in the smaller packages may result in a higher current draw. NOTE: I/O pins are configured to
output low; input-only pins are configured to pullup-enab led. IRO pin connects to ground. FB_AD12 pin is pullup-enabled. D ACO , and VREFO pins
are at reset state and unconnected.
Table 11. Stop Mode Adders
# Parameter Condition Temperatur e (°C ) Units C
-40257085105
1LPO —50 75 100 150 250 nA D
2EREFSTEN RANGE = HGO = 0 600 650 750 850 1000 nA D
3IREFSTEN1——73 80 93 125 AT
4TOD Does not inclu de clock source current 50 75 100 150 250 nA D
Table 10. Supply Current Characteristics (continued)
# Symbol Parameter Bus
Freq VDD
(V) Typical1Maximum Unit Temperature
(C) C
Preliminary Electrical Characteristics
MCF51JE256 Datasheet, Rev. 4
Freescale Semiconductor 23
Figure 6. Stop IDD versus Temperature
5LVD1LVDSE = 1 116 117 126 132 172 AT
6PRACMP1 Not using the bandgap (BGBE = 0) 17 18 24 35 74 AT
7ADC1ADLPC = ADLSMP = 1
Not using the bandgap (BGBE = 0) 75 85 100 115 165 AT
8DAC1High power mode; no load on DACO 500 500 500 500 500 AT
1Not available in stop2 mode.
Table 1 1. Stop Mode Adders (continued)
# Parameter Condition Temperatur e (°C ) Units C
-40257085105
MCF51JE256 Datasheet, Rev. 4
Preliminary Electrical Characteristics
Freescale Semiconductor24
3.7 PRACMP Electricals
3.8 12-bit DAC Electricals
Table 12. PRACMP Electrical Specif ic at ions
# Characteristic Symbol Minimum Typical Maximum Unit C
1 Supply voltage VPWR 1.8 — 3.6 V P
2 Supply current (active) (PRG enabled) IDDACT1 ——80AD
3 Supply current (active) (PRG disabled) IDDACT2 ——40AD
4Supply current (ACMP and PRG all
disabled) IDDDIS —— 2 nAD
5 Analog input voltage VAIN VSS – 0.3 — VDD VD
6 Analog input offset voltage VAIO — 5 40 mV D
7 Analog comparator hysteresis VH3.0 — 20.0 mV D
8 Analog input leakage current IALKG —— 1 nAD
9 Analog comparator initialization de lay tAINIT ——1.0sD
10 Programmable reference generator inputs VIn2 (VDD25)1.8 — 2.75 V D
11 Programmab le reference generator setup
delay tPRGST —1—sD
12 Programmab le reference generator step
size Vstep 0.75 1 1.25 LSB D
13 Programmab le reference generator voltage
range Vprgout VIn/32 — Vin VP
Table 13. DAC 12LV Operating Requirements
# Characteristic Symbol Minimum Maximum Unit C
1 Supply voltage VDDA 1.8 3.6 V P
2 Reference voltage VDACR 1.15 3.6 VC
3 Temperature TA-40 105 °C C
4Output load capacitance1
1A small load capacitance (47 pF) can improve the bandwidth performance of the DAC.
CL— 100 pF C
5 Ou tput load current IL—1mAC
Preliminary Electrical Characteristics
MCF51JE256 Datasheet, Rev. 4
Freescale Semiconductor 25
Table 14. DAC 12-Bit Operating Behaviors
# Characteristic Symbol Minimum Typical Maximum Unit C Notes
1 Resolution N 12 — 12 bit T
2 Supply current low-power mode IDDA_DAC
LP —50100AT
3 Supply current high-power mode IDDA_DAC
HP — 345 500 AT
4Full-scale Settling time (1 LSB)
(0x080 to 0xF7F or 0xF7F to 0x080)
low-power mode TsFSLP ——200sT
• VDDA = 3 V or 2.2 V
• VREFSEL = 1
• Temperature
= 25°C
5Full-scale Settling time (1 LSB)
(0x080 to 0xF7F or 0xF7F to 0x080)
high-power mode TsFSHP ——30sT
• VDDA = 3 V or 2.2 V
• VREFSEL = 1
• Temperature
= 25°C
6Code-to-c ode Settling time (1 LSB)
(0xBF8 to 0xC08 or 0xC08 to
0xBF8) low-power mode TsC-CLP ——5s T • VDDA = 3 V or 2.2 V
• VREFSEL = 1
• Temperature = 25°C
7Code-to-c ode Settling time (1 LSB)
(0xBF8 to 0xC08 or 0xC08 to
0xBF8) high-power mode TsC-CHP —1—s T • VDDA = 3 V or 2.2 V
• VREFSEL = 1
• Temperature = 25°C
8DAC output voltage range low
(high-power mode, no load, DAC set
to 0, 3 V at room temperature) Vdacoutl ——
100 mV T
9DAC output voltage range high
(high-power mode, no load, DAC set
to 0x0FFF) Vdacouth VDACR–100 ——mV T
10 Integral non-linearity error INL — — 8LSB T
11 Differential non-linearity error
VDACR is > 2.4 V DNL — — ±1 LSB T
12 Offset error EO—±0.4±3
%FSR T
Calculat ed by a best fit
curve from VSS +
100mV to VREFH
–100mV
13 Gain error (VREF = Vext = VDD)EG— ±0.1 ±0.5 %FSR T
Calculat ed by a best fit
curve from VSS +
100mV to VREFH
–100mV
14 Power supply rejection ratio
VDD 2.4 V PSRR 60 — — dB T
MCF51JE256 Datasheet, Rev. 4
Preliminary Electrical Characteristics
Freescale Semiconductor26
Figure 7. Offset at Half Scale vs Temperature
3.9 ADC Characteristics
15 Temperature drift of offset voltage
(DAC set to 0x0800)1Tco ——2mV T See Typical Drift figure
that follows.
16 Offset aging coefficient AC——8V/yr T
1See Typical Drift figure that follows.
Table 15. 12-bit ADC Operating Conditions
#Symb Characteristic Conditions Minimum Typical1Maximum Unit C
1VDDAD Supply voltage Absolute 1.8 — 3.6 V D
2VDDAD Supply voltage Delta to VDD (VDD-VDDAD)2-100 0 +100 mV D
3VSSAD Ground vo ltage Delta to VSS (VSS-VSSAD)2-100 0 +100 mV D
4VREFH Ref Voltage High — 1.13 VDDAD VDDAD VD
Table 14. DAC 12-Bit Operating Behaviors
# Characteristic Symbol Minimum Typical Maximum Unit C Notes
Preliminary Electrical Characteristics
MCF51JE256 Datasheet, Rev. 4
Freescale Semiconductor 27
5VREFL Ref Voltage Low — VSSAD VSSAD VSSAD VD
6VADIN Input Voltage — VREFL —V
REFH VD
7CADIN Input
Capacitance ——45pFC
8RADIN Input Resistance — — 2 5 kC
9RAS Analog Source Resistance3
12 bit mode
fADCK > 8 MHz — — 1kC
4 MHz < fADCK > 8 MHz —— 2kC
fADCK < 4 MHz — — 5 kC
10-bit mode
fADCK > 8MHz — — 2 kC
4 MHz < fADCK < 8 MHz —— 5kC
fADCK < 4 MHz ——10kC
8-bit mode
fADCK > 8 MHz —— 5kC
fADCK < 8 MHz ——10kC
10 fADCK ADC Conversion Clock Freq.
High Speed (ADLPC=0,
ADHSC=1) 1.0 — 8.0 MHz D
High Speed (ADLPC=0,
ADHSC=0) 1.0 — 5.0 MHz D
Low Power (ADLPC=1,
ADHSC=1) 1.0 — 2.5 MHz D
1Typical values assume VDDAD = 3.0V, Temp = 25C, fADCK=1.0 MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
2DC potential difference.
3External to MCU. Assumes ADLSMP=0.
Table 15. 12-bit ADC Operating Conditions (continued)
#Symb Characteristic Conditions Minimum Typical1Maximum Unit C
MCF51JE256 Datasheet, Rev. 4
Preliminary Electrical Characteristics
Freescale Semiconductor28
Figure 8. ADC Input Impedance Equivalency Diagram
Table 16. 12-bit SAR ADC Characteristics full operating range
(VREFH = VDDAD, VREFL = VSSAD)
# Symbol Characteristic Conditions1Minimum Typical2Maximum Unit C
1IDDAD
Supply Current
(ADLSMP=0,
ADCO=1)
ADLPC=1, ADHSC=0 — 215 — AT
ADLPC=0, ADHSC=0 — 470 — AT
ADLPC=0, ADHSC=1 — 610 — AT
Sto p, Reset, Module Off — 0.01 — AC
2fADACK
ADC
Asynchronous
Clock Source
(tADACK
=1/fADACK)
ADLPC=1, ADHSC=0 — 2.4 — MHz P
ADLPC=0, ADHSC=0 — 5.2 — MHz P
ADLPC=0, ADHSC=1 — 6.2 — MHz P
3—Sample Time — See Ref e re nce Manual for sample times.
4—Conversion Time — See Rreference Manual for conversion times.
5TUE
Total Unadjusted
Error
32x Hardware
Averaging (AVGE
= %1 AVGS =
%11)
12-bit single-ended mode — 1.75 3.5 LSB3T
10-bit single-ended mode — 0.8 ±1.5 LSB3T
8-bit single-ended mode — 0.5 ±1.0 LSB3T
6Differential
Non-Linearity
12-bit single-ended mode — 0.7 1LSB
3T
10-bit single-ended mode — 0.5 ±0.75 LSB3T
8-bit single-ended mode — 0.2 ±0.5 LSB3T
+
–
+
–
VAS
RAS
CAS
VADIN
ZAS Pad
leakage
due to
input
protection
ZADIN
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
RADIN ADC SAR
ENGINE
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
INPUT PIN
RADIN
CADIN
INPUT PIN
RADIN
INPUT PIN
RADIN
Preliminary Electrical Characteristics
MCF51JE256 Datasheet, Rev. 4
Freescale Semiconductor 29
3.10 MCG and External Oscillator (XOSC) Characteristics
7INL Integral
Non-Linearity
12-bit single-ended mode — 1.0 2.5 LSB3T
10-bit single-ended mode — 0.5 ±1.0 LSB3T
8-bit single-ended mode — 0.3 ±0.5 LSB3T
8EZS Zero-Scale Error
(VADIN = VSSAD)
12-bit single-ended mode — 0.7 2.0 LSB3T
10-bit single-ended mode — 0.4 ±1.0 LSB3T
8-bit single-ended mode — 0.2 ±0.5 LSB3T
9EFS Full-Scale Error
(VADIN = VDDAD)
12-bit single-ended mode — 1.0 3.5 LSB3T
10-bit single-ended mode — 0.4 ±1.5 LSB3T
8-bit single-ended mode — 0.2 ±0.5 LSB3T
10 EQQuantization
Error All modes — — ±0.5 LSB3D
11 EIL
Input Leakage
Error (IIn =
leakage current
(refer to DC
Characteristics)
All modes IIn * RAS mV D
12 mTemp Sensor
Slope -40C to 25C — 1.646 — mV/xC C
25C to 125C — 1.769 — mV/xC C
13 VTEMP25 Temp Sensor
Voltage 25C — 701.2 — mV C
1All accuracy numbers assume the ADC is calibrated with VREFH=VDDAD.
2Typical values assume VDDAD = 3.0V, Temp = 25C, fADCK=2.0MHz unless otherwise stated. Typical values are for reference only
and are not tested in production.
31 LSB = (VREFH - VREFL)/2N
Table 17. MCG (Temperature Range = –40 to 105C Ambient)
# Rating Symbol Min Typical Max Unit C
1 Internal reference startup time tirefst — 55 100 sD
2Average internal reference
frequency
factory trimmed at
VDD=3.0V and
temp=25Cfint_ft — 31.25 — kHz C
user trimmed 31.25 — 39.0625 KHz C
3DCO output frequency range -
trimmed
Low range (DRS=00) fdco_t 16 — 20 MHz C
Mid range (DRS=01) 32 — 40 MHz C
High range1
(DRS=10) 40 — 60 MHz C
4Resolution of tri mme d DCO output
frequency at fixed voltage and
temperature
with FTRIM fdco_res_t —0.1 0.2 %fdco C
without FTRIM — 0.2 0.4 %fdco C
Table 16. 12-bit SAR ADC Characteristics full operating range
(VREFH = VDDAD, VREFL = VSSAD) (continued)
# Symbol Characteristic Conditions1Minimum Typical2Maximum Unit C
MCF51JE256 Datasheet, Rev. 4
Preliminary Electrical Characteristics
Freescale Semiconductor30
5Total deviation of trimmed DCO
output frequency over v oltage and
temperature
ov er voltage and
temperature
fdco_t
—1.0 2%fdco P
ov er fixed voltage
and temp range
of 0 - 70 C—0.5 1%fdco C
6Acquisition time
FLL2tfll_acquire —— 1 msC
PLL3 tpll_acquire —— 1 msD
7Long term Jitter of DCO output clock (averaged over 2mS
interval) 4CJitter — 0.02 0.2 %fdco C
8 V CO operating frequency fvco 7.0 — 55.0 MHz D
9 P LL reference frequency range fpll_ref 1.0 — 2.0 MHz D
10 Jitter of PLL output clock measured
over 625 ns Long term fpll_jitter_625
ns —0.5664—%fpllD
11 Lock frequency tolerance Entry5Dlock 1.49 — 2.98 % D
Exit6Dunl 4.47 — 5.97 % D
12 Lock time FLL tfll_lock ——
tfll_acquire+
1075(1/fint_t) sD
PLL tpll_lock ——
tpll_acquire+
1075(1/fpll_ref) sD
13 Loss of external clock minimum frequency - RANGE = 0 floc_low (3/5) x
fint_t — — kHz D
14 Loss of external clock minimum frequency - RANGE = 1 floc_high (16/5) x
fint_t ——kHzD
1This should not exceed the maximum CPU frequency of 50.33 MHz.
2This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed, DMX32 bit is
changed, DRS bit is changed, or changing from FLL disabled (BLPE, BLPI) to FLL enab led (FEI, FEE, FBE, FBI). If a crystal/resonator is
being used as the reference, this specification assumes it is already running.
3This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE, BLPI)
to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
4Jitter is the av erage de viation from the programmed frequency measured over the specified interval at maxim um fBUS. Measurements are
made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the FLL circuitry via
VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage for a given interval.
5Below Dlock minimum, the MCG is guaranteed to enter lock. Abov e Dlock maximum, the MCG will not enter lock. But if the MCG is already
in lock, then the MCG may stay in lock.
6Below Dunl minimum, the MCG will not exit lock if already in lock. Above Dunl maximum, the MCG is guaranteed to exit lock.
Table 17. MCG (Temperature Range = –40 to 105C Ambient) (continued)
# Rating Symbol Min Typical Max Unit C
Preliminary Electrical Characteristics
MCF51JE256 Datasheet, Rev. 4
Freescale Semiconductor 31
o
Table 18. XOSC (Temperature Range = –40 to 105C Ambient)
# Characteristic Symbol Minimum Typical1
1Data in Typical column was characterized at 3.0 V, 25C or is typical recommended value.
Maximum Unit
1Oscillator crystal or resonator
(EREFS = 1, ERCLKEN = 1)
• Low range (RANGE = 0) flo 32 — 38.4 kHz
• High range (RANGE = 1),
• FEE or FBE mode 2
2When MCG is configured for FEE or FBE mode, input clock source must be divisible using RDIV to within the range of 31.25 kHz to 39.0625
kHz.
fhi-fll 1— 5MHz
• High range (RANGE = 1),
• PEE or PBE mode 3
3When MCG is configured for PEE or PBE mode, input clock source must be divisible using RDIV to within the range of 1 MHz to 2 MHz.
fhi-pll 1—16MHz
• High range (RANGE = 1),
• High gain (HGO = 1),
• FBELP mode fhi-hgo 1—16MHz
• High range (RANGE = 1),
• Low power (HGO = 0),
• FBELP mode fhi-lp 1— 8MHz
2 Load capacitors C1
C2See Note 4
4See crystal or resonator manufacturer’s recommendation.
3Feedback resistor Low range
(32 kHz to 38.4 kHz) RF—10 —
M
High range
(1 MHz to 16 MHz) —— 1 —
4Series resistor — Low range Low Gain (HGO = 0) RS—0 —
k
High Gain (HGO = 1) — 100 —
5 Series resisto r — High range
• Low Gain (HGO = 0)
RS
—0 —
k
• High Gain (HGO = 1)
8 MHz — 0 0
4 MHz — 0 10
1 MHz — 0 20
6 Crystal start-up time 5, 6
5This parameter is characterized and not tested on each device.
6Proper PC board layout procedures must be followed to achieve specifications.
Low range, low gain
(RANGE=0,HGO=0) tCSTL
— 200 —
ms
Low range, high gain
(RANGE=0,HGO=1) — 400 —
High range, low gain
(RANGE=1,HGO=0) tCSTH
—5 —
High range, high gain (RANGE=1,
HGO=1) —15 —
MCF51JE256 Datasheet, Rev. 4
Preliminary Electrical Characteristics
Freescale Semiconductor32
3.11 Mini-FlexBus Timing Specifications
A multi-function external bus interface called Mini-FlexBus is provided with basic functionality to
interface to slave-only devices up to a maximum bus frequency of 25.1666 MHz. It can be directly connected
to asynchronous or synchronous devices such as external boot ROMs, flash memories, gate-array logic, or
other simple target (slave) devices with little or no additional circuitry . For asynchronous devices, a simple
chip-select based interface can be used.
All processor bus timings are synchronous; that is, input setup/hold and output delay are given in respect
to the rising edge of a reference clock, MB_CLK. The MB_CLK frequency is half the internal system bus
frequency.
The following timing numbers indicate when data is latched or driven onto the exter nal bus, relative to the
Mini-FlexBus output clock (MB_CLK). All other timing relationships can be derived from these values.
Table 19. Mini-FlexBus AC Timing Specifications
# Characteristic Symbol Min Max Unit C
1 Frequency of Operation — — 25.1666 MHz —
2 Clock Period MB1 39.73 — ns D
3Output Valid1
1Specification is valid for all MB_A[19:0], MB_D[7:0], MB_CS[1:0], MB_OE, MB_R/W, and MB_ALE.
MB2 — 20 ns T
4Output Hold1MB3 1.0 — ns D
5Input Setup2
2Specification is valid for all MB_D[7:0].
MB4 22 — ns T
6Input Hold2MB5 10 — ns D
Preliminary Electrical Characteristics
MCF51JE256 Datasheet, Rev. 4
Freescale Semiconductor 33
Figure 9. Mini-FlexBus Read Timing
Figure 10. Mini-FlexBus Write Timing
MCF51JE256 Datasheet, Rev. 4
Preliminary Electrical Characteristics
Freescale Semiconductor34
3.12 AC Characteristics
This section describes ac timing characteristics for each peripheral system.
3.12.1 Control Timing
Table 20. Co nt rol Timin g
# Parameter Symbol Minimum Typica
l1
1Typical values are based on characterization data at VDD = 5.0 V, 25 C unless otherwise stated.
Maximum Unit C
1 Bus frequency (tcyc = 1/fBus)
VDD 1.8 V fBus dc — 10 MHz D
VDD > 2.1 V fBus dc — 20 MHz D
VDD > 2.4 V fBus dc — 25.165 MHz D
2 Internal low-power oscillator period tLPO 700 1000 1300 sP
3 External reset pulse width2
2This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to override reset
requests from internal sources.
(tcyc =
1/fSelf_reset)textrst 100 — — ns D
4 Reset low drive trstdrv 66 x tcyc ——nsD
5Active back grou nd debug mode latch setup time tMSSU 500 — — ns D
6 Active background debug mode latch hold time tMSH 100 — — ns D
7IRQ pulse width
• Asynchronous path2
• Synchronous path3
3This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be
recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
tILIH, tIHIL 100
1.5 x tcyc ——ns
D
8KBIPx pulse width
• Asynchronous path2
• Synchronous path3tILIH, tIHIL 100
1.5 x tcyc ——ns
D
9 Port rise and fall time (load = 50 pF)4, Low Drive
4Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40 C to 105 C.
Slew rate
control disabled
(PTxSE = 0)
tRise, tFall —11—nsD
Slew rate
control enabled
(PTxSE = 1)
tRise, tFall —35—nsD
Slew rate
control disabled
(PTxSE = 0)
tRise, tFall —40—nsD
Slew rate
control enabled
(PTxSE = 1)
tRise, tFall —75—nsD
Preliminary Electrical Characteristics
MCF51JE256 Datasheet, Rev. 4
Freescale Semiconductor 35
Figure 11. Reset Timing
Figure 12. IRQ/KBIPx Timing
textrst
RESET PIN
tIHIL
IRQ/KBIPx
tILIH
IRQ/KBIPx
MCF51JE256 Datasheet, Rev. 4
Preliminary Electrical Characteristics
Freescale Semiconductor36
3.12.2 TPM Timing
Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that
can be used as the optional external source to the timer counter. These synchronizers operate from the
current bus rate clock.
Figure 13. Timer External Clock
Figure 14. Timer Input Capture Pulse
Table 21. TPM Input Timing
# C Function Symbol Minimum Maximum Unit
1 — External clock frequency fTPMext dc fBus/4 MHz
2 — External clock period tTPMext 4—t
cyc
3 D External clock high time tclkh 1.5 — tcyc
4 D External clock low time tclkl 1.5 — tcyc
5 D Input capture pulse width tICPW 1.5 — tcyc
tTPMext
tclkh
tclkl
TPMxCLK
tICPW
TPMxCHn
tICPW
TPMxCHn
Preliminary Electrical Characteristics
MCF51JE256 Datasheet, Rev. 4
Freescale Semiconductor 37
3.13 SPI Characteristics
The following table and Figure 15 through Figure 18 describe the timing requirements for the SPI system.
Table 22. SPI Timing
No.1
1Numbers in this column identify elements in Figure 15 through Figure 18.
Characteristic2
2All timing is shown with respect to 20% VDD and 70% VDD, unless noted; 100 pF load on all SPI pins. All timing assumes slew
rate control disabled and high drive strength enabled for SPI output pins.
Symbol Minimum Maximum Unit C
1Operating frequency Master
Slave fop
fop
fBus/2048
0fBus/2
fBus/4 Hz
Hz D
2SPSCK period Master
Slave tSPSCK
tSPSCK
2
42048
—tcyc
tcyc
D
3Enable lead time Master
Slave tLead
tLead
12
1—
—tSPSCK
tcyc
D
4Enable lag time Master
Slave tLag
tLag
12
1—
—tSPSCK
tcyc
D
5Clock (SPSCK) high or low time Master
Slave tWSPSCK
tWSPSCK
tcyc –30
tcyc – 30 1024 tcyc
—ns
ns D
6Data setup time (inputs) Master
Slave tSU
tSU
15
15 —
—ns
ns D
7Data hold time (inputs) Master
Slave tHI
tHI
0
25 —
—ns
ns D
8Slave access time3
3Time to data active from high-impedance state.
ta—1t
cyc D
9Slave MISO disable time4
4Hold time to high-impedance state.
tdis —1t
cyc D
10 Data valid (after SPSCK edge) Master
Slave tv
tv
—
—25
25 ns
ns D
11 Data hold time (outputs) Master
Slave tHO
tHO
0
0—
—ns
ns D
12 Rise time Input
Output tRI
tRO
—
—tcyc – 25
25 ns
ns D
13 Fall time Input
Output tFI
tFO
—
—tcyc – 25
25 ns
ns D
MCF51JE256 Datasheet, Rev. 4
Preliminary Electrical Characteristics
Freescale Semiconductor38
Figure 15. SPI Master Timing (CPHA = 0)
Figure 16. SPI Master Timing (CPHA = 1)
SCK
(OUTPUT)
SCK
(OUTPUT)
MISO
(INPUT)
MOSI
(OUTPUT)
MSB IN(2)
BIT 6 . . . 1
LSB IN
MSB OUT(2) LSB OUT
BIT 6 . . . 1
(CPOL = 0)
(CPOL = 1)
SS(1)
(OUTPUT)
1. SS output mode (MODFEN = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
NOTES:
2
2
3
45
67
11 12
54
Preliminary Electrical Characteristics
MCF51JE256 Datasheet, Rev. 4
Freescale Semiconductor 39
Figure 17. SPI Slave Timing (CPHA = 0)
Figure 18. SPI Slave Timing (CPHA = 1)
SCK
(INPUT)
SCK
(INPUT)
MOSI
(INPUT)
MISO
(OUTPUT)
SS
(INPUT)
MSB IN
BIT 6 . . . 1
LSB IN
MSB OUT SLAVE LS B OUT
BIT 6 . . . 1
(CPOL = 0)
(CPOL = 1)
NOTE:
SLAVE SEE
NOTE
1. Not defined, but normally MSB of character just received
2
2
3
4
67
8
9
11 12
5
54
SCK
(INPUT)
SCK
(INPUT)
MOSI
(INPUT)
MISO
(OUTPUT)
MSB IN
BIT 6 . . . 1
LSB IN
MSB OUT SLAVE LSB OUT
BIT 6 . . . 1
SEE
(CPOL = 0)
(CPOL = 1)
SS
(INPUT)
NOTE:
SLAVE
NOTE
1. Not defined, but normally LSB of character just receiv ed
2
2
3
4
67
8
9
11 12
4
5
5
MCF51JE256 Datasheet, Rev. 4
Preliminary Electrical Characteristics
Freescale Semiconductor40
3.14 Flash Specifications
This section provides details about program/erase times and program-erase endurance for the Flash
memory.
Program and erase operations do not require any special power sources other than the normal VDD supply.
For more detailed information abou t program/erase operations, s ee the Memory chapter in the Reference
Manual for this device (MCF51JE256RM).
3.15 USB Electricals
The USB electricals for the USB On-the-Go module conform to the standards documented by the
Universal Serial Bus Implementers Forum. For the most up-to-date standards, visit http://www.usb.org.
If the Freescale USB On-the-Go implementation has electrical characteristics that deviate from the
standard or require additional information, this space would be used to communicate that information.
Table 23. Flash Characteristics
# Characteristic Symbol Minimum Typical Maximum Unit C
1Supply voltage for program/erase
-40C to 105CV
prog/erase 1.8 —3.6 V D
2Supply voltage for read operation VRead 1.8 — 3.6 V D
3Internal FCLK frequency1
1The frequency of this clock is controlled by a software setting.
fFCLK 150 — 200 kHz D
4Internal FCLK period (1/FCLK) tFcyc 5—6.67sD
5Byte program time (random location)2tprog 9t
Fcyc P
6Byte program time (burst mode)2tBurst 4t
Fcyc P
7Page erase time2
2These values are hardware state machine controlled. User code does not need to count cycles. This information supplied for calcu lating
approximate time to program and erase.
tPage 4000 tFcyc P
8Mass erase time2tMass 20,000 tFcyc P
9Program/erase endurance3
TL to TH = –40C to + 105C
T = 25C
3Typical endurance for flash was evaluated for this product family on the HC9S12Dx64. For additional information on how Freescale defines
typical endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile Memory.
10,000
——
100,000 —
—cycles C
10 Data retention4
4Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25C using
the Arrhenius equation. For additional information on how Freescale defines typical data retention, please refer to Engineering Bulletin EB618,
Typical Data Retention for Nonvolatile Memory.
tD_ret 15 100 — years C
Table 24. Internal USB 3.3 V Voltage Regulator Characteri stics
# Characteristic Symbol Minimum Typical Maximu
mUnit C
1 Regulator operating voltage Vregin 3.9 — 5.5 V C
2VREG output V
regout 3 3.3 3.75 V P
Preliminary Electrical Characteristics
MCF51JE256 Datasheet, Rev. 4
Freescale Semiconductor 41
3.16 VREF Electrical Specifications
3VUSB33 input with internal VREG
disabled Vusb33in 33.33.6V C
4 VREG Quiescent Current IVRQ —0.5—mAC
Table 25. VREF Electrical Specifications
# Characteristic Symbol Minimum Maximum Unit C
1 Supply voltage VDDA 1.80 3.6 V C
2 Temperature TA–40 105 CC
3 Output Load Capacitance CL— 100 nf D
4 Maximum Load — — 10 mA —
5 Voltage Reference Output with Factory
Trim. VDD = 3 V. Vout 1.148 1.152 V P
6 Temperature Drift (Vmin - Vmax across
the full temperature range) Tdrift — 25 mV1
1See typical chart below.
T
7 Aging Coefficient2
2Linear reliability model (1008 hours stress at 125oC = 10 years operating life) used to calculate Aging V/year. Vrefo data recorded per
month.
Ac — 60 V/year C
8 Powered do wn Current (Off Mode,
VREFEN = 0, VRSTEN = 0) I — 0.10 AC
9 Bandgap only (MODE_LV[1:0] = 00) I — 75 AT
10 Low-Power b uffer (MODE_LV[1:0] = 01) I — 125 AT
11 Tight-Regulation buff er (MODE_LV[1:0]
= 10) I—1.1mAT
12 Load Regulation (MODE_LV = 10) — — 100 V/mA C
13 Line Regulation MODE = 1:0, Tight
Regulation VDD < 2.3 V, Delta VDDA =
100 mV, VREFH = 1.2 V driv en
externally with VREFO disabled.
(Power Supply Rejection
DC 70
—
dB C
Table 24. Internal USB 3.3 V Voltage Regulator Characteristics (continued)
# Characteristic Symbol Minimum Typical Maximu
mUnit C
MCF51JE256 Datasheet, Rev. 4
Preliminary Electrical Characteristics
Freescale Semiconductor42
Figure 19. Typical VREF Output vs Temperature
Table 26. VREF Limited Range Operating Behaviors
# Characteristic Symbol Minimum Maximum Unit C
1Voltage Reference Output with
Factory Trim Vout 1.149 1.152 mV T
2Temperature Drift (Vmin – Vmax
Temperature range from 0° C to
50° C Tdrift — 3 mV1
1See typical chart that follows (Figure 19).
T
Preliminary Electrical Characteristics
MCF51JE256 Datasheet, Rev. 4
Freescale Semiconductor 43
Figure 20. Typical VREF Output vs VDD
MCF51JE256 Datasheet, Rev. 4
Ordering Information
Freescale Semiconductor44
4 Ordering Information
This section contains ordering information for the device numbering system. See Table 1 for feature
summary by package information.
4.1 Part Numbers
4.2 Package Information
4.3 Mechanical Drawings
Table 28 provides the available package types and their document numbers. The latest package
outline/mechanical drawings are available on the MCF51JE256/128 Product Summary pages at
http://www.freescale.com.
To view the latest drawing, either:
• Click on the appropriate link in Table 28, or
Table 27. Orderable Part Number Summary
Freescale Part
Number Description Flash / SRAM
(Kbytes) Package Temperature
MCF51JE256VML MCF51JE256 ColdFire Microcontroller 256K/32K 104 MAPBGA –40 to 105 °C
MCF51JE256VLL MCF51JE256 ColdFire Microcontroller 256K/32K 100 LQFP –40 to 105 °C
MCF51JE256VMB MCF51JE256 ColdFire Mi crocontroller 256K/32K 81 MAPBGA –40 to 105 °C
MCF51JE256VLK MCF51JE256 ColdFire Microcontroller 256K/32K 80 LQFP –40 to 105 °C
MCF51JE128VMB MCF51JE128 ColdFire Mi crocontroller 128K/32K 81 MAPBGA –40 to 105 °C
MCF51JE256CML MCF51JE256 ColdFire Microcontroller 256K/32K 104 MAPBGA –40 to 85 °C
MCF51JE256CLL MCF51JE256 ColdFire Microcontroller 256K/32K 10 O LQFP –40 to 85 °C
MCF51JE256CMB MCF51JE256 ColdFire Microcontroller 256K/32K 8 1 MAPBGA –40 to 85 °C
MCF51JE256CLK MCF51JE256 Co ldFire Microcontroller 256K/32K 80 LQFP –40 to 85 °C
MCF51JE128CMB MCF51JE128 ColdFire Microcontroller 128K/32K 8 1 MAPBGA –40 to 85 °C
MCF51JE128CLK MCF51JE128 Co ldFire Microcontroller 128K/32K 80 LQFP –40 to 85 °C
Table 28. Package Descriptions
Pin Count Package Type Abbreviation Designator Case No. Document No.
100 Low Quad Flat Package LQFP LL 983-03 98ASS23308W
80 Low Quad Flat Package LQFP LK 1418 98ASS23174W
104 MAP BGA Package MAPBGA ML 1285-02 98ARH98267A
81 MAP BGA Package MAPBGA MB 1662-01 98ASA10670D
Revision History
MCF51JE256 Datasheet, Rev. 4
Freescale Semiconductor 45
• Open a browser to the Freescale® website (http://www.freescale.com), and enter the appropriate
document number (from Table 28) in the “Enter Keyword” search box at the top of the page.
5 Re vision History
This section lists major changes between versions of the MCF51JE256 Data Sheet.
Table 29. Revision History
Revision Date Description
0 March/April 09 Initial Draft
1 July 20 0 9
• Revised to follow standard template.
• Removed extraneous headings from the TOC.
• Corrected units for Monotoncity to be blank in for the DAC specification.
• Updated ADC characteristic tables to include 16-Bit SAR in headings.
2 July 20 0 9 • Changed MCG (XOSC) Electrical s Table - Row 2, Average Internal Reference
Frequency typical value from 32.768 to 31.25
3 April 2010
• Updated Thermal Characteristics table. Reinserted the 81 and 104 MapBGA devices.
• Revised the ESD and Latch-Up Protection Characeristic description to read: Latch-up
Current at TA = 125°C.
• Changed Table 9. DC Characteristics rows 2 and 4, to 1.8 V, ILoad = -600 mA
conditions to 1.8 V, ILoad = 600A respectively.
• Corrected the 16-bit SAR ADC Operating Condition table Ref Voltage High Min value
to be 1.13 instead of 1.15.
• Updated the ADC electricals.
• Inserted the Mini-FlexBus Timing Specifications.
• Added a Temp Drift parameter to the VREF Electr ical Specifications.
• Removed the S08 Naming Convention diagram.
• Updated the Orderable P art Number Summary to include the F reescale Part Number
suffixes.
• Completed the Package Description table values.
• Changed the 80LQFP package drawing from 98ARL10530D to 98ASS231 74W.
• Updated electrical characteristic data.
MCF51JE256 Datasheet, Rev. 4
Revision History
Freescale Semiconductor46
4 August 2012
•In Table 1.”MCF51JE256/128 Features by MCU and Package, removed the row of
“12-bit SAR ADCDifferential Channels”.
• In Table 3, “Package Pin Assignments”, changed from: ‘A1’ — PTG1 USB_
SESSEND to:’B3’ — PTG1 USB_ SESSEND.
• In Table 10,”Supply Current Characteristics”, for S3IDD changed the max v alue from
‘1.2’ to ‘1.3’ and typical value from ‘0.650’ to ‘0.750’ for the first row.
• In Table 10,”Supply Current Characteristics”:
— For par ameter 3 and parameter 4 changed LPS to LPR.
— For par ameter 3,changed “FBILP” to “FBI”.
— For parameter 4, changed “FBELP ” to “BLPE”.
• Fixed the TBD parameters and added figure"Typical Output vs VDD", following the
same setup of MM256DS
— Added Figure 7,”Offset at Half Scale vs Temperature”.
— Updated Table 9,”DC Characteristics”.
— Updated Table 10,”Supply Current Characteristics”.
— Updated Table 11,”Stop Mode Adders”.
— Added Figure 20,”Typical Outp ut vs. VDD.
— Updated Table 14,”D AC 12-Bit Operating Behaviors”.
— Updated Table 20,”Control Timing”.
— Removed “SPI Electrical Characteristics” table.
— Updated Table 25”VREF Electrical Specifications”.
— Updated Table 26,”VREF Limi ted Range Operating Behaviors“.
• Updated Figure 3, Figure 4, and Figure 5.
Table 29. Revision History
Revision Date Description
Document Number : MCF51JE256
Rev. 4
08/2012
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