LIBERATOR CL10K100E Key Features u Fully Compatible to the Altera(R) FLEX(R) 10KE Family u Prototype Your System With Altera FPGAs Y R A u Seamlessly Migrate Production To Clear Logic u No ASIC Engineering, No NRE, And No Test Vector Development N I M u Very Fast, Dense Signal Routing Using Vertical Link Interconnect u "Gate Array" Option Eliminates Configuration EPROMs I L u Fabricated Using 0.25 Micron CMOS Process E R u Very Low Power Consumption (Active And Standby) P u High Density - 100,000 Usable Gates - 4,992 Logic Elements - 49,152 RAM Bits - 338 Maximum User I/O Pins CL10KE Product Family Overview CL10K30E CL10K50E CL10K50S CL10K100E CL10K200E CL10K200S Typical Gates (Logic and RAM) 30,000 50,000 100,000 200,000 Maximum System Gates 119,000 199,000 257,000 513,000 1,728 2,880 4,992 9,984 6 10 12 24 24,576 40,960 49,152 98,304 220 254 338 470 -1, -2, -3 -1, -2, -3 -1, -2, -3 -1, -2, -3 144-pin TQFP 208-pin PQFP 256-pin FBGA 484-pin FBGA 144-pin TQFP 208-pin PQFP 240-pin PQFP 256-pin FBGA 356-pin SBGA 484-pin FBGA 208-pin PQFP 240-pin PQFP 256-pin FBGA 356-pin SBGA 484-pin FBGA 240-pin PQFP 356-pin SBGA 484-pin FBGA 600-pin SBGA 672-pin FBGA Parameter Logic Elements Embedded Array Blocks Total RAM Bits Max User I/O pins Speed Grades Packages 10KE tbl 01 January 2001 Page 1 LIBERATOR CL10K100E (PRELIMINARY) Description The LIBERATOR CL10KE family offers you all of the time-tomarket benefits of designing with programmable logic. Simply use Altera FLEX 10KE FPGAs to prototype and verify the design. Then, take five minutes to submit the bitstream using Clear Logic's web site! Within eight weeks, your system can be in volume production using compatible Clear Logic devices. LIBERATOR technology frees you to completely design, prototype, and verify your custom logic using Altera FLEX 10KE products. Clear Logic's innovative technology eliminates NRE costs, test vector development, ordering minimums, and long lead times. No re-simulation or re-layout is required, because Clear Logic offers an architecture that is exactly compatible to the functionality of the FPGA prototype. Clear Logic's NoFault(R) test technology ensures complete test coverage through the use of special scan test registers. The LIBERATOR family is based upon an array of logic elements. Each logic element contains a configurable look-up table for combinatorial functions and a register for sequential operations. Eight logic elements in a group form a block. Logic functions and signal routing are defined by Clear Logic's proprietary vertical metal links. Laser-based configuration allows quick-turn prototyping and eliminates NRE costs for photomasks. Inherent CL10KE family performance benefits include extremely consistent propagation delays, reduced power consumption, and improved immunity to noise and upset events. Configuration Page 2 The "Gate Array" configuration mode eliminates the need for external EPROMs or software configuration. The LIBERATOR device is already factory-configured when it is shipped. When using the device in the "Gate Array" mode, it powers up fully configured. In this mode, if the customer selects INIT_DONE option, this pin will always be high. LIBERATOR CL10K100E (PRELIMINARY) Additional Information For further information on designing with the LIBERATOR family, please refer to these documents: u AN-01: Requesting a First Article. This document provides instructions on how to request first articles by submitting a bitstream file to Clear Logic's web site. u AN-02: Clear Logic Packaging Guide. This document provides specifications and drawings for packages used by the CL10K family and other Clear Logic devices. u AN-13: LIBERATOR -- A New Way To Design. This document describes the most efficient path for custom logic designs up to 200K gates using FPGA design techniques and going to production with Clear Logic. u AN-14: CL10K Technology White Paper. This document outlines the technologies employed by the LIBERATOR family. u AN-15: LIBERATOR System Configuration. This document contains a detailed discussion of all aspects of configuring CL10K-based systems. u AN-16: Introduction to the Clear Logic Verilog Model Generator. Clear Logic now has Verilog models of your FPGA converted design. Learn what it is and how it can help you. u AN-17: Clear Logic LIBERATOR Design Models. This document outlines the capabilities and freedom available in the Clear Logic Verilog and VHDL design models. u AN-18: Debugging Designs Using Clear Logic Models. This document shows the enhanced troubleshooting capabilities that the Clear Logic LIBERATOR Verilog/VHDL design models bring to the system debugging process. Page 3 LIBERATOR CL10K100E (PRELIMINARY) Block Diagram Embedded Array Block (EAB) I/O Element (IOE) IOE IOE IOE IOE IOE IOE IOE IOE IOE IOE IOE IOE IOE IOE Column Interconnect Logic Array EAB Logic Building Block (LBB) IOE IOE IOE IOE Logic Element (LE) Row Interconnect EAB Local Interconnect Logic Array 10KE drw 01 IOE IOE IOE IOE Logical Memory Array (LMA) Page 4 IOE IOE IOE IOE IOE IOE LIBERATOR CL10K100E (PRELIMINARY) Pin Configuration Pin Name 208-Pin PQFP 240-Pin PQFP MSEL0 108 124 MSEL1 107 123 nSTATUS 52 60 nCONFIG 105 121 DCLK 155 179 CONF_DONE 2 2 INIT_DONE 19 26 154 178 3 3 nWS 206 238 nRS 204 236 nCS 208 240 CS 207 239 RDYnBSY 16 23 CLKUSR 10 11 DATA7 166 190 DATA6 164 188 DATA5 162 186 DATA4 161 185 DATA3 159 183 nCE nCEO 10K100E tbl 01A Page 5 LIBERATOR CL10K100E (PRELIMINARY) Pin Configuration Pin Name 208-Pin PQFP 240-Pin PQFP DATA2 158 182 DATA1 157 181 DATA0 156 180 TDI 153 177 TDO 4 4 TCK 1 1 TMS 50 58 TRST 51 59 78, 80, 182, 184 90, 92, 210, 212 79, 183 91, 211 DEV_CLRn 180 209 DEV_OE 186 213 VCCINT 6, 23, 35, 43, 76, 106, 109, 117, 137, 145, 181 5, 27, 47, 96, 122, 130, 150, 170 VCCIO 5, 22, 34, 42, 66, 84, 98, 110, 118, 138, 146, 165, 178, 194 16, 37, 57, 77, 112, 140, 160, 189, 205, 224 77 89 20, 21, 32, 33, 48, 49, 59, 72, 82, 91, 123, 124, 129, 130, 151, 152, 171, 185, 188, 201 10, 22, 32, 42, 52, 69, 85, 93, 104, 125, 135, 145, 155, 165, 176, 197, 216, 232 GND_CKLK 81 93 No Connect - - 147 189 Dedicated Inputs Dedicated Clock Pins VCC_CKLK GNDINT Total user I/O Pins 10K100E tbl 01B Page 6 LIBERATOR CL10K100E (PRELIMINARY) Pin Configuration Pin Name 256-Pin FBGA 356-Pin SBGA 484-Pin FBGA MSEL0 P1 D4 U4 MSEL1 R1 D3 V4 nSTATUS T16 D24 W19 nCONFIG N4 D2 T7 DCLK B2 AC5 E5 CONF_DONE C15 AC24 F18 INIT_DONE G16 T24 K19 nCE B1 AC2 E4 nCEO B16 AC22 E19 nWS B14 AE24 E17 nRS C14 AE23 F17 nCS A16 AD24 D19 CS A15 AD23 D18 RDYnBSY G14 U22 K17 CLKUSR D15 AA24 G18 DATA7 B5 AF4 E8 DATA6 D4 AD8 G7 DATA5 A4 AE5 D7 DATA4 B4 AD6 E7 DATA3 C3 AF2 F6 DATA2 A2 AD5 D5 DATA1 B3 AD4 E6 DATA0 A1 AD3 D4 TDI C2 AC3 F5 TDO C16 AC23 F19 TCK B15 AD25 E18 10K100E tbl 01C Page 7 LIBERATOR CL10K100E (PRELIMINARY) Pin Configuration Pin Name 256-Pin FBGA 356-Pin SBGA 484-Pin FBGA TMS P15 D22 U18 TRST R16 D23 V19 B9, E8, M9, R9 A13, B14, AF14, AE13 E12, H11, R12, V11 A9, L8 A14, AF13 D12, P11 DEV_CLRn D8 AD13 G11 DEV_OE C9 AE14 F12 VCCINT E11, F5, F7, F9, F12, H6, G7, G10, J7, J10, J11, K9, L5,L7, L12, M11, R2 A1, A26, C14, C26, D5, F1, H22, J1, M26, N1, T26, U5, AA1, AD26, AF1, AF26 C11, C15, H14, J8, J10, J12, J15, L9, L10, L13, M10, M13, M14, N12, P8, P10, P15, R14, V5, W21, Y8, AA12 Dedicated Inputs Dedicated Clock Pins VCCIO VCC_CKLK GND GND_CKLK No Connect Total user I/O Pins A7, A23, B3, C15, D25, F4, D12, E6, F8, F10, G6, G8, G11, H24, K5, M23, P2, T25, V2, H11, J6, K6, K8, K11, L10, M6, W22, AB1, AC25, AD18M AF3, N12 AF7, AF16 L9 C14 A2, A10, A20, B1, B13, B22, B25, B26, C2, C9, C13, C25, E5, E12, F6, F11, G7, G9, G10, H23, J26, K1, M1, N26, R1, H8, H9, J8, J9, K7, K10, L6, R26, T1, U26, W1, AD2, AD14, L11, M5, M12 AD20, AE1, AE2, AE7, AE25, AE26, AF11, AF19, AF25 T8 A6, A13, B5, E1, G1, G15, H9, H20, J11, J13, K9, K11, K14, K20, L14, M9, N3, N9, N11, N14, N20, P13, R1, R9, T3, T15, T22, V22, AB13 P12 A1, A8, A22, B1, B2, B17, B21, B22, C2, C21, E21, G3, G21, H2, H8, H15, J9, J14, J20, K3, K10, K12, K13, L11, L12, M11, M12, M20, N10, N13, P9, P14, R8, R15, R22, T1, V3, W20, Y1, Y2, Y3, Y21, Y22, AA1, AA6, AA22, AB11, AB16 B13 W11 - - A2, A3. A4. A5, B3, B4, B10, C17, F2, J2, K2, L2, N1, P20, P22, R3, T20, T21, U1, W22, Y16, AA15, AB3, AB4, AB5, AB7, AB15, AB17, AB18, AB19, AB20 191 274 338 10K100E tbl 01D Page 8 LIBERATOR CL10K100E (PRELIMINARY) DC Electrical Specifications Absolute Maximum Ratings Symbol Min Max Unit Supply Voltage -0.5 3.6 V DC Input Voltage [1] -2.0 5.75 V IOUT DC Output Current, per Pin -25 25 mA TSTG Storage Temperature No Bias -65 150 C TAMB Ambient Temperature Under Bias -65 135 C TJ Junction Temperature Under Bias 135 C VCC VI Parameter Conditions 10KE tbl 02 Recommended Operating Conditions Symbol Parameter VCCINT VCCIO VCCIO [2] Min Max Unit Supply Voltage, Internal Logic and Input Buffers Commercial Grade Devices Industrial Grade Devices 2.375 2.375 2.625 2.625 V V DC Input Voltage for 3.3V Operation Commercial Grade Devices Industrial Grade Devices 3.00 3.00 3.60 3.60 V V DC Input Voltage for 2.5V Operation Commercial Grade Devices Industrial Grade Devices 2.375 2.375 2.625 2.625 V V -0.5 5.75 V 0 VCCIO V 0 -40 70 85 C C VI Input Voltage VO Output Voltage TA Operating Temperature Commercial Temperature Range Industrial Temperature Range Conditions tR Input Signal Rise Time 40 ns tF Input Signal Fall Time 40 ns 10KE tbl 03B Page 9 LIBERATOR CL10K100E (PRELIMINARY) DC Electrical Specifications cont. DC Electrical Characteristics (over the operating range) Symbol Parameter Conditions Min Typ[3] Max Unit VIH Input HIGH Voltage Lower of 1.7 or 0.5 x VCCINT 5.75 V VIL Input LOW Voltage -0.5 0.3 x VCCIO V VOH 3.3-V High-Level TTL Output Voltage IOH = -8 mA DC, VCCIO = 3.00 V 3.3-V High-Level CMOS Output Voltage 3.3-V High-Level PCI Output Voltage 2.5-V High-Level Output Voltage VOL 2.4 V IOH = -0.1 mA DC, VCCIO = 3.00 V VCCIO-0.2 V IOH = -0.5 mA DC, VCCIO = 3 to 3.60 V 0.9 x VCCIO V IOH = -0.1 mA DC, VCCIO = 2.30 V 2.1 V IOH = -1 mA DC, VCCIO = 2.30 V 2.0 V IOH = -2 mA DC, VCCIO = 2.30 V 1.7 V 3.3-V Low-Level TTL Output Voltage IOL = 9 mA DC, VCCIO = 3.00 V 3.3-V Low-Level CMOS Output Voltage IOL = 0.1 mA DC, VCCIO = 3.00 V 3.3-V Low-Level PCI Output Voltage IOL = 1.5 mA DC, VCCIO = 3 to 3.60 V 2.5-V Low-Level Output Voltage 0.45 V 0.2 V 0.1 x VCCIO V IOL = 0.1 mA DC, VCCIO = 2.30 V 0.2 V IOL = 1 mA DC, VCCIO = 2.30 V 0.4 V IOL = 2 mA DC, VCCIO = 2.30 V 0.7 V IIN Input Leakage Current VI = 5.3V to -0.3V -10 10 A IOZ Output Leakage Current VO = 5.3V to -0.3V -10 10 A ICC0 Standby Current VI = GND, No Load 5 mA 10KE tbl 04 Capacitance[4] Symbol Parameter Conditions C IN Input Capacitance COUT Output Capacitance Min Max Unit VIN = 0 V, f = 1.0 MHz 10 pF VOUT = 0 V, f = 1.0 MHz 10 pF 10KE tbl 05 Page 10 LIBERATOR CL10K100E (PRELIMINARY) AC Electrical Specifications I/O Element Timing Parameters [5] Speed: -1 Symbol Parameter Min Max Speed: -2 Min Max Speed: -3 Min Max Unit tIOD IOE Register Data Delay 2.4 2.8 3.8 ns tIOC IOE Register Control Signal Delay 0.3 0.3 0.5 ns tIOCO IOE Register Clock to Output Delay 0.2 0.2 0.3 ns IOE Combinatorial Delay 0.5 0.6 0.8 ns tIOCOMB tIOSU IOE Register Setup Time Before Clock 2.2 2.6 3.5 ns tIOH IOE Register Hold Time After Clock 0.5 0.6 0.8 ns tIOCLR IOE Register Clear Delay 0.2 0.2 0.3 ns tOD1 Output Buffer and Pad Delay Slow Slew Rate = off, VCCIO = VCCINT 1.1 1.3 1.8 ns tOD2 Output Buffer and Pad Delay Slow Slew Rate = off, VCCIO = Low Voltage 0.6 0.9 1.6 ns tOD3 Output Duffer and Pad Delay Slow Slew Rate = on 3.0 3.5 4.8 ns tZX Output Buffer Disable Delay[6] 1.1 1.3 1.8 ns tZX1 Output Buffer Disable Delay Slow Slew Rate = off, VCCIO = VCCINT[6] 1.1 1.3 1.6 ns 0.6 0.9 1.6 ns Output Buffer Disable Delay Slow Slew Rate = on [6] 3.0 3.5 4.8 ns tINREG IOE Input Pad and Buffer to IOE Register Delay 5.0 5.9 8.0 ns tIOFD IOE Register Feedback Delay 3.0 3.6 4.8 ns IOE Input Pad and Buffer to Interconnect Delay 3.0 3.6 4.8 ns tZX2 Output Buffer Disable Delay Slow Slew Rate = off, VCCIO = Low Voltage tZX3 tINCOMB [6] 10KE tbl 06A Page 11 LIBERATOR CL10K100E (PRELIMINARY) AC Electrical Specifications cont. External Timing Parameters[4] Symbol Parameter Speed: -1 Min Max Speed: -2 Min Max Speed: -3 Min Max Unit 16.0 ns tDRR Register to Register Delay via Four LEs, Three Row Interconnects, and Four Local Interconnects tINSU Setup Time with Global Clock at IOE Register 3.1 3.7 4.7 ns tINH Hold time with Global Clock at IOE Register 0.0 0.0 0.0 ns Output Data Hold Time After Clock 2.0 tOUTCO 10.0 3.7 12.0 2.0 4.4 2.0 6.3 ns 10KE tbl 07A Logic Element Timing Parameters[5] Speed: -1 Symbol Parameter Min Max Speed: -2 Min Max Speed: -3 Min Max Unit tLUT Look-up Table Delay for Data-in 0.6 0.8 1.1 ns tCLUT Look-up Table Delay for Carry-in 0.5 0.6 0.8 ns tRLUT Look-up Table Delay for LE Register Feedback 0.7 0.8 1.1 ns Data-in to Packed Register Delay 0.5 0.6 0.8 ns tEN LE Register Enable Delay 0.6 0.7 0.9 ns tCICO Carry-in to Carry-out Delay 0.2 0.2 0.3 ns tCGEN Data-in to Carry-out Delay 0.5 0.5 0.8 ns tCGENR LE Register Feedback to Carry-out Delay 0.2 0.2 0.3 ns tCASC Cascade Chain Routing Ddelay 0.8 0.9 1.2 ns tC LE Register Control Signal Delay 0.5 0.6 0.8 ns tCO LE Register Clock-to-output Delay 0.5 0.6 0.7 ns Combinatorial Delay 0.5 0.6 0.7 ns tPACKED tCOMB tSU LE Register Setup Time Before Clock 0.5 0.6 0.8 ns tH LE Register Hold Time After Clock 0.9 1.1 1.5 ns tPRE LE Register Preset Delay 0.5 0.6 0.8 ns tCLR LE Register Clear Delay 0.5 0.6 0.8 ns tCH Clock High Time 2.0 2.5 3.0 ns tCL Clock Low Time 2.0 2.5 3.0 ns 10KE tbl 08A Page 12 LIBERATOR CL10K100E (PRELIMINARY) AC Electrical Specifications cont. Interconnect Timing Parameters[5] Speed: -1 Symbol Parameter Min Max Speed: -2 Min Max Speed: -3 Min Max Unit tDIN2IOE Delay from Dedicated Input Pin to IOE Control Input 3.5 3.9 4.9 ns tDIN2LE Delay from Dedicated Input Pin to LE or EAB Control Input 0.6 0.6 0.9 ns Delay from Dedicated Input or Clock Pin to LE or EAB Data 2.0 2.1 2.9 ns tDCLK2IOE Delay from Dedicated Clock Pin to IOE Clock 1.7 2.0 2.8 ns tDCLK2LE Delay from Dedicated Clock Pin to LE or EAB Clock 0.6 0.6 0.9 ns tSAMELAB Delay from an LE to LE in Same LAB 0.1 0.1 0.2 ns tSAMEROW Delay for Driving a Row IOE, LE or EAB to a Row IOE, LE or EAB in the Same Row 1.7 1.8 1.7 ns Delay from an LE to IOE in the Same Column 1.2 1.1 0.8 ns tDIFFROW Delay for Driving a Column IOE, LE or EAB to an LE or EAB in a Different Row 2.9 2.9 2.5 ns tTWOROWS Delay for Driving a Row IOE or EAB to an LE or EAB in a Different Row 4.6 4.7 4.2 ns tLEPERIPH Delay from an LE to IOE Control Signal via the Peripheral Dontol Bus 4.3 4.9 5.9 ns tLABCARRY Delay from an LE Carry-out Signal to an LE Carry-in Signal in a Different LAB 0.1 0.1 0.2 ns tLABCASC Delay from an LE Cascade-out Signal to an LE Cascade-in Signal in a Different LAB 0.3 0.3 0.5 ns tDIN2DATA tSAMECOLUMN 10KE tbl 09A Page 13 LIBERATOR CL10K100E (PRELIMINARY) AC Electrical Specifications cont. EAB Timing Parameters[5] Speed: -1 Symbol Parameter Min Max Speed: -2 Min Max Speed: -3 Min Max Unit tEABDATA1 Delay from Data or Address to EAB for Combinatorial Input 1.7 2.0 2.7 ns tEABDATA2 Delay from Data or Address to EAB for Registered Input 0.6 0.7 0.9 ns tEABWE1 WE Delay to EAB for Combinatorial Input 1.1 1.3 1.8 ns tEABWE2 WE Delay to EAB for Registered Input 0.4 0.4 0.6 ns tEABCLK EAB Register Clock Delay 0.0 0.0 0.0 ns tEABCO EAB Register Clock-to-output Delay 0.3 0.3 0.5 ns 0.5 0.6 0.8 ns tEABBYPASS Bypass Register Delay tEABSU EAB Register Setup Time 0.9 1.0 1.4 ns tEABH EAB Register Hold Time 0.4 0.4 0.6 ns tAA Address Access Delay 3.2 3.8 5.1 ns tWP Write Pulse Width 2.5 2.9 3.9 ns tWDSU Data Setup Time Before Falling Edge of Write Pulse 0.9 1.0 1.4 ns tWDH Data Hold Time After Falling Edge of Write Pulse 0.1 0.1 0.2 ns tWASU Address Setup Time Before Rising Edge of Write Pulse 1.7 2.0 2.7 ns tWAH Address Hold After Falling Edge of Write Pulse 1.8 2.1 2.9 ns tWO Write Enable to Date Output Delay 2.5 2.9 3.9 ns tDD Data-in to Date-out Delay 2.5 2.9 3.9 ns tEABOUT Data-out Delay 0.5 0.6 0.8 ns tEABCH Clock High Time 1.5 2.0 2.5 ns tEABCL Clock Low Time 1.5 2.0 2.5 ns 10KE tbl 10A Page 14 LIBERATOR CL10K100E (PRELIMINARY) AC Electrical Specifications cont. EAB Timing Parameters[5] Speed: -1 Symbol tEABAA Parameter Min EAB Address Access Delay Max Speed: -2 Min 6.4 Max Speed: -3 Min 7.6 Max Unit 10.2 ns tEABRCCOMB EAB Asynchronous Read Cycle Time 6.4 7.6 10.2 ns tEABRCREG EAB Synchronous Read Cycle Time 4.4 5.1 7.0 ns 2.5 2.9 3.9 ns tEABWCCOMB EAB Asynchronous Write Cycle Time 6.0 7.0 9.5 ns tEABWCREG EAB Synchronous Write Cycle Time 6.8 7.8 10.6 ns tEABWP tEABDD EAB Write Pulse Width EAB Data-in to Data-out Delay 5.7 6.7 9.0 ns tEABDATACO EAB Clock-to-output Delay Using Output Registers 0.8 0.9 1.3 ns tEABDATASU EAB Data/Address Setup Time Using Input Register 1.5 1.7 2.3 ns tEABDATAH EAB Data/Address Hold Time Using Input Register 0.0 0.0 0.0 ns tEABWESU EAB WE Setup When Using Input Register 1.3 1.4 2.0 ns tEABWESH EAB WE Hold Time When Using Input Register 0.0 0.0 0.0 ns tEABWDSU EAB Data Setup Time to Falling Edge of Write Pulse When Not Using Input Registers 1.5 1.7 2.3 ns tEABWDH EAB Data Hold Time After Falling Edge of Write Pulse When Not Using Input Registers 0.0 0.0 0.0 ns tEABWASU EAB Address Setup Time to Rising Edge of Write Pulse When Not Using Input Registers 3.0 3.6 4.8 ns tEABWAH EAB Address Hold Time After Falling Edge of Write Pulse When Not Using Input Registers 0.5 0.5 0.8 ns tEABWO EAB WE to Data Output Delay 5.1 6.0 8.1 ns 10KE tbl 11A Page 15 LIBERATOR CL10K100E (PRELIMINARY) AC Electrical Specifications cont. External Bidirectional Timing Parameters[5] Speed: -1 Symbol Parameter Min Max Speed: -2 Min Max Speed: -3 Min Max Unit tINSUBIDIR Setup for Bi-directional Pins with Global Clock at Adjacent LE Registers 2.5 3.3 4.4 ns tINHBIDIR Hold Time for Bi-directional Pins with Global Glock at Adjacent LE Registers 0.0 0.0 0.0 ns tOUTCOBIDIR Clock-to-output Delay for Bi-directional Pins with Global Clock at IOE Register 2.0 3.7 2.0 4.4 2.0 6.3 ns tXZBIDIR Synchronous IOE Output Buffer Disable Delay 2.0 5.2 2.0 6.1 2.0 8.3 ns tZXBIDIR Synchronous IOE Output Buffer Disable Delay, Slow Slew Rate = off 2.0 4.7 2.0 5.6 2.0 8.1 ns 10KE tbl 12A AC Test Conditions (A) VCCIO (B) 481 VCCIO OUTPUT Includes jig capacitance All Input Pulses 481 3.0V 90% 90% OUTPUT 35 pF 481 Includes jig capacitance 5 pF 481 GND 10% 3ns 10% 3ns 10KE drw 02 A: Test fixture set-up A is for general testing. B: Test fixture set-up B is for high Z testing (tZX#). Notes to Tables 1. During transitions, inputs may undershoot to -2.0V or overshoot to 5.75V for periods shorter than 20ns. Otherwise, minimum DC input voltage is -0.5V. 2. Device inputs may be driven before VCCINT and VCCIO are powered. 3. Typical values are at VCC of 3.3 volts and ambient temperature of 25 C. 4. Guaranteed but not tested. Characterized initially, and after any design changes which may affect these parameters. 5. Internal timing delays are based on characterization, and cannot be explicitly tested. Internal timing parameters should be used for performance estimation only. 6. Use AC Test Conditions set-up B for these parameters. Revision History Page 16 02 Dec. 2000: Created new document LIBERATOR CL10K100E (PRELIMINARY) Ordering Information Part Number CL10K100EQC208-3 Temperature Range Commercial Package Type Altera Equivalent -3 EPF10K100EQC208-3 CL10K100EQC208-2 -2 EPF10K100EQC208-2 CL10K100EQC208-2X* -2 EPF10K100EQC208-2X CL10K100EQC208-1 -1 EPF10K100EQC208-1 CL10K100EQC208-1X* -1 EPF10K100EQC208-1X -2 EPF10K100EQI208-2 -3 EPF10K100EQC240-3 CL10K100EQC240-2 -2 EPF10K100EQC240-2 CL10K100EQC240-2X* -2 EPF10K100EQC240-2X CL10K100EQC240-1 -1 EPF10K100EQC240-1 CL10K100EQC240-1X* -1 EPF10K100EQC240-1X -3 EPF10K100EFC256-3 CL10K100EFC256-2 -2 EPF10K100EFC256-2 CL10K100EFC256-2X* -2 EPF10K100EFC256-2X CL10K100EFC256-1 -1 EPF10K100EFC256-1 CL10K100EFC256-1X* -1 EPF10K100EFC256-1X -2 EPF10K100EFI256-2 -3 EPF10K100EBC356-3 CL10K100EBC356-2 -2 EPF10K100EBC356-2 CL10K100EBC356-2X* -2 EPF10K100EBC356-2X CL10K100EBC356-1 -1 EPF10K100EBC356-1 CL10K100EBC356-1X* -1 EPF10K100EBC356-1X -3 EPF10K100EFC484-3 CL10K100EFC484-2 -2 EPF10K100EFC484-2 CL10K100EFC484-2X* -2 EPF10K100EFC484-2X CL10K100EFC484-1 -1 EPF10K100EFC484-1 CL10K100EFC484-1X* -1 EPF10K100EFC484-1X CL10K100EQI208-2 Industrial CL10K100EQC240-3 Commercial CL10K100EFC256-3 Commercial CL10K100EFI256-2 Industrial CL10K100EBC356-3 Commercial CL10K100EFC484-3 Commercial 208-pin Plastic QFP Speed 240-pin Plastic QFP 256-pin FBGA 356-pin SBGA 484-pin FBGA 10K100E tbl 02 * Contact your local Clear Logic Representative for availability. Page 17 LIBERATOR CL10K100E (PRELIMINARY) Page 18