8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet The SST49LF080A flash memory device is designed to interface with the LPC bus for PC and Internet Appliance application in compliance with Intel Low Pin Count (LPC) Interface Specification 1.0. Two interface modes are supported: LPC mode for in-system operations and Parallel Programming (PP) mode to interface with programming equipment. The SST49LF080A flash memory device is manufactured with SST's proprietary, high-performance SuperFlash(R) Technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches Features * LPC Interface Flash * Two Operational Modes - SST49LF080A: 1024K x8 (8 Mbit) * Conforms to Intel LPC Interface Specification 1.0 * Flexible Erase Capability - Uniform 4 KByte Sectors - Uniform 64 KByte overlay blocks - 64 KByte Top Boot Block protection - Chip-Erase for PP Mode Only * Single 3.0-3.6V Read and Write Operations * Superior Reliability - Endurance: 100,000 Cycles (typical) - Greater than 100 years Data Retention * Low Power Consumption - Active Read Current: 6 mA (typical) - Standby Current: 10 A (typical) * Fast Sector-Erase/Byte-Program Operation - Sector-Erase Time: 18 ms (typical) - Block-Erase Time: 18 ms (typical) - Chip-Erase Time: 70 ms (typical) - Byte-Program Time: 14 s (typical) - Chip Rewrite Time: 16 seconds (typical) - Single-pulse Program or Erase - Internal timing generation (c)2011 Silicon Storage Technology, Inc. - Low Pin Count (LPC) Interface mode for in-system operation - Parallel Programming (PP) Mode for fast production programming * LPC Interface Mode - 5-signal communication interface supporting byte Read and Write - 33 MHz clock frequency operation - WP# and TBL# pins provide hardware write protect for entire chip and/or top boot block - Standard SDP Command Set - Data# Polling and Toggle Bit for End-of-Write detection - 5 GPI pins for system design flexibility - 4 ID pins for multi-chip selection * Parallel Programming (PP) Mode - 11-pin multiplexed address and 8-pin data I/O interface - Supports fast programming In-System on programmer equipment * CMOS and PCI I/O Compatibility * Packages Available - 32-lead PLCC - 32-lead TSOP (8mm x 14mm) * All non-Pb (lead-free) devices are RoHS compliant www.microchip.com DS25086A 11/11 8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet Product Description The SST49LF080A flash memory device is designed to interface with the LPC bus for PC and Internet Appliance application in compliance with Intel Low Pin Count (LPC) Interface Specification 1.0. Two interface modes are supported: LPC mode for in-system operations and Parallel Programming (PP) mode to interface with programming equipment. The SST49LF080A flash memory device is manufactured with SST's proprietary, high-performance SuperFlash Technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST49LF080A device significantly improves performance and reliability, while lowering power consumption. The SST49LF080A device writes (Program or Erase) with a single 3.0-3.6V power supply. It uses less energy during Erase and Program than alternative flash memory technologies. The total energy consumed is a function of the applied voltage, current and time of application. For any give voltage range, the SuperFlash technology uses less current to program and has a shorter erase time; the total energy consumed during any Erase or Program operation is less than alternative flash memory technologies. The SST49LF080A product provides a maximum Byte-Program time of 20 sec. The entire memory can be erased and programmed byte-by-byte typically in 16 seconds when using status detection features such as Toggle Bit or Data# Polling to indicate the completion of Program operation. The SuperFlash technology provides fixed Erase and Program time, independent of the number of Erase/Program cycles that have performed. Therefore the system software or hardware does not have to be calibrated or correlated to the cumulative number of Erase cycles as is necessary with alternative flash memory technologies, whose Erase and Program time increase with accumulated Erase/Program cycles. To meet high density, surface mount requirements, the SST49LF080A device is offered in 32-lead TSOP and 32-lead PLCC packages. See Figures 2 and 3 for pin assignments and Table 1 for pin descriptions. (c)2011 Silicon Storage Technology, Inc. DS25086A 2 11/11 8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet Functional Block Diagram TBL# WP# INIT# X-Decoder SuperFlash Memory LAD[3:0] LCLK LFRAME# LPC Interface Address Buffers Latches Y-Decoder ID[3:0] GPI[4:0] R/C# A[10:0] DQ[7:0] Control Logic I/O Buffers and Data Latches Programmer Interface OE# WE# MODE RST# CE# 1235 B1.0 Figure 1: Functional Block Diagram (c)2011 Silicon Storage Technology, Inc. DS25086A 3 11/11 8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet NC 2 1 A10 (GPI4) RST# (RST#) 3 R/C# (LCLK) A9 (GPI3) 4 VDD (VDD) A8 (GPI2) Pin Assignments 32 31 30 29 A7(GPI1) 5 A6 (GPI0) 6 28 NC (CE#) A5 (WP#) 7 27 NC A4 (TBL#) 8 26 NC A3 (ID3) 9 25 VDD (VDD) A2 (ID2) 10 24 OE# (INIT#) A1 (ID1) 11 23 WE# (LFRAME#) A0 (ID0) 12 22 NC DQ0 (LAD0) 13 21 14 15 16 17 18 19 20 DQ7 (RES) DQ6 (RES) DQ5 (RES) DQ4 (RES) DQ3 (LAD3) VSS (VSS) DQ2 (LAD2) DQ1 (LAD1) 32-lead PLCC Top View MODE (MODE) ( ) Designates LPC Mode 1235 32-plcc P1.0 Figure 2: Pin Assignments for 32-lead PLCC NC NC NC NC (CE#) MODE (MODE) A10 (GPI4) R/C# (LCLK) VDD (VDD) NC RST# (RST#) A9 (GPI3) A8 (GPI2) A7 (GPI1) A6 (GPI0) A5 (WP#) A4 (TBL#) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Standard Pinout Top View Die Up OE# (INIT#) WE# (LFRAME#) VDD (VDD) DQ7 (RES) DQ6 (RES) DQ5 (RES) DQ4 (RES) DQ3 (LAD3) VSS (VSS) DQ2 (LAD2) DQ1 (LAD1) DQ0 (LAD0) A0 (ID0) A1 (ID1) A2 (ID2) A3 (ID3) 1235 32-tsop P2.0 ( ) Designates LPC Mode Figure 3: Pin Assignments for 32-lead TSOP (8mm x 14mm) (c)2011 Silicon Storage Technology, Inc. DS25086A 4 11/11 8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet Table 1: Pin Description Symbol A10-A0 Pin Name Address DQ7-DQ0 Data Type1 I I/O OE# WE# MODE Output Enable Write Enable Interface Mode Select I I I INIT# Initialize I ID[3:0] Identification Inputs I GPI[4:0] General Purpose Inputs I TBL# Top Block Lock I LAD[3:0] Address and Data LCLK Clock LFRAME# Frame I/O I I RST# WP# Reset Write Protect I I R/C# I RES VDD VSS CE# Row/Column Select Reserved Power Supply Ground Chip Enable PWR PWR I NC No Connection I Interface PP LPC Functions X Inputs for low-order addresses during Read and Write operations. Addresses are internally latched during a Write cycle. For the programming interface, these addresses are latched by R/C# and share the same pins as the high-order address inputs. X To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a Write cycle. The outputs are in tri-state when OE# is high. X To gate the data output buffers. X To control the Write operations. X X This pin determines which interface is operational. When held high, programmer mode is enabled and when held low, LPC mode is enabled. This pin must be setup at power-up or before return from reset and not change during device operation. This pin must be held high (VIH) for PP mode and low (VIL) for LPC mode. X This is the second reset pin for in-system use. This pin is internally combined with the RST# pin; If this pin or RST# pin is driven low, identical operation is exhibited. X These four pins are part of the mechanism that allows multiple parts to be attached to the same bus. The strapping of these pins is used to identify the component.The boot device must have ID[3:0]=0000 for all subsequent devices should use sequential up-count strapping. These pins are internally pulled-down with a resistor between 20-100 K X These individual inputs can be used for additional board flexibility. The state of these pins can be read through LPC registers. These inputs should be at their desired state before the start of the PCI clock cycle during which the read is attempted, and should remain in place until the end of the Read cycle. Unused GPI pins must not be floated. X When low, prevents programming to the boot block sectors at top of memory. When TBL# is high it disables hardware write protection for the top block sectors. This pin cannot be left unconnected. X To provide LPC control signals, as well as addresses and Command Inputs/Outputs data. X To provide a clock input to the control unit X To indicate start of a data transfer operation; also used to abort an LPC cycle in progress. X X To reset the operation of the device X When low, prevents programming to all but the highest addressable blocks. When WP# is high it disables hardware write protection for these blocks. This pin cannot be left unconnected. X Select for the Programming interface, this pin determines whether the address pins are pointing to the row addresses, or to the column addresses. X These pins must be left unconnected. X X To provide power supply (3.0-3.6V) X X Circuit ground (0V reference) X This signal must be asserted to select the device. When CE# is low, the device is enabled. When CE# is high, the device is placed in low power standby mode. X X Unconnected pins. T1.0 25026 1. I=Input, O=Output (c)2011 Silicon Storage Technology, Inc. DS25086A 5 11/11 8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet Device Memory Maps Block 15 TBL# Block 14 Block 13 Block 12 Block 11 Block 10 Block 9 Block 8 WP# for Block 0 14 0FFFFFH Boot Block 0F0000H 0EFFFFH 0E0000H 0DFFFFH 0D0000H 0CFFFFH 0C0000H 0BFFFFH 0B0000H 0AFFFFH 0A0000H 09FFFFH 090000H 08FFFFH 080000H 07FFFFH Block 7 Block 6 070000H 06FFFFH 060000H 05FFFFH Block 5 Block 4 050000H 04FFFFH 040000H 03FFFFH Block 3 Block 2 Block 1 Block 0 (64 KByte) 030000H 02FFFFH 020000H 01FFFFH 010000H 00FFFFH 4 KByte Sector 15 002000H 4 KByte Sector 2 001000H 4 KByte Sector 1 000000H 4 KByte Sector 0 1235 F03.0 Figure 4: Device Memory Map (c)2011 Silicon Storage Technology, Inc. DS25086A 6 11/11 8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet Design Considerations SST recommends a high frequency 0.1 F ceramic capacitor to be placed as close as possible between VDD and VSS less than 1 cm away from the VDD pin of the device. Additionally, a low frequency 4.7 F electrolytic capacitor from VDD to VSS should be placed within 5 cm of the VDD pin. If you use a socket for programming purposes add an additional 1-10 F next to each socket. Product Identification The Product Identification mode identifies the device as the SST49LF080A and manufacturer as SST. Table 2: Product Identification Manufacturer's ID Address Data 0000H BFH 0001H 5BH Device ID SST49LF080A T2.0 25026 Mode Selection The SST49LF080A flash memory devices can operate in two distinct interface modes: the LPC mode and the Parallel Programming (PP) mode. The mode pin is used to set the interface mode selection. If the mode pin is set to logic High, the device is in PP mode. If the mode pin is set Low, the device is in the LPC mode. The mode selection pin must be configured prior to device operation. The mode pin is internally pulled down if the pin is left unconnected. In LPC mode, the device is configured to its host using standard LPC interface protocol. Communication between Host and the SST49LF080A occurs via the 4-bit I/O communication signals, LAD [3:0] and LFRAME#. In PP mode, the device is programmed via an 11-bit address and an 8-bit data I/O parallel signals. The address inputs are multiplexed in row and column selected by control signal R/C# pin. The row addresses are mapped to the lower internal addresses (A10-0), and the column addresses are mapped to the higher internal addresses (AMS-11). See Figure 4, the Device Memory Map, for address assignments. (c)2011 Silicon Storage Technology, Inc. DS25086A 7 11/11 8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet LPC Mode Device Operation The LPC mode uses a 5-signal communication interface, a 4-bit address/data bus, LAD[3:0], and a control line, LFRAME#, to control operations of the SST49LF080A. Cycle type operations such as Memory Read and Memory Write are defined in Intel Low Pin Count Interface Specification, Revision 1.0. JEDEC Standard SDP (Software Data Protection) Program and Erase commands sequences are incorporated into the standard LPC memory cycles. See Figures 7 through 12 for command sequences. LPC signals are transmitted via the 4-bit Address/Data bus (LAD[3:0]), and follow a particular sequence, depending on whether they are Read or Write operations. LPC memory Read and Write cycle is defined in Tables 5 and 6. Both LPC Read and Write operations start in a similar way as shown in Figures 5 and 6. The host (which is the term used here to describe the device driving the memory) asserts LFRAME# for two or more clocks and drives a start value on the LAD[3:0] bus. At the beginning of an operation, the host may hold the LFRAME# active for several clock cycles, and even change the Start value. The LAD[3:0] bus is latched every rising edge of the clock. On the cycle in which LFRAME# goes inactive, the last latched value is taken as the Start value. CE# must be asserted one cycle before the start cycle to select the SST49LF080A for Read and Write operations. Once the SST49LF080A identifies the operation as valid (a start value of all zeros), it next expects a nibble that indicates whether this is a memory Read or Write cycle. Once this is received, the device is now ready for the Address cycles. The LPC protocol supports a 32-bit address phase. The SST49LF080A encodes ID and register space access in the address field. See Table 3 for address bits definition. For Write operation the Data cycle will follow the Address cycle, and for Read operation TAR and SYNC cycles occur between the Address and Data cycles. At the end of every operation, the control of the bus must be returned to the host by a 2-clock TAR cycle. Table 3: Address bits definition A31: A251 A24:A23 1111 111b or 0000 000b ID[3:2]2 A22 1 = Memory Access 0 = Register access A21: A20 A19:A0 ID[1:0]2 Device Memory address T3.1 25026 1. The top 32MByte address range FFFF FFFFH to FE00 0000H and the bottom 128 KByte memory access address 000F FFFFH to 000E 0000H are decoded. 2. See Table 7 for multiple device selection configuration (c)2011 Silicon Storage Technology, Inc. DS25086A 8 11/11 8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet CE# The CE# pin, enables and disables the SST49LF080A, controlling read and write access of the device. To enable the SST49LF080A, the CE# pin must be driven low one clock cycle prior to LFRAME# being driven low. The device will enter standby mode when internal Write operations are completed and CE# is high. LFRAME# The LFRAME# signifies the start of a (frame) bus cycle or the termination of an undesired cycle. Asserting LFRAME# for two or more clock cycle and driving a valid START value on LAD[3:0] will initiate device operation. The device will enter standby mode when internal operations are completed and LFRAME# is high. TBL#, WP# The Top Boot Lock (TBL#) and Write Protect (WP#) pins are provided for hardware write protection of device memory. The TBL# pin is used to Write-Protect 16 boot sectors (64 KByte) at the highest memory address range for the SST49LF080A. The WP# pin write protects the remaining sectors in the flash memory. An active low signal at the TBL# pin prevents Program and Erase operations of the top boot sectors. When TBL# pin is held high, the write protection of the top boot sectors is disabled. The WP# pin serves the same function for the remaining sectors of the device memory. The TBL# and WP# pins write protection functions operate independently of one another. Both TBL# and WP# pins must be set to their required protection states prior to starting a Program or Erase operation. A logic level change occurring at the TBL# or WP# pin during a Program or Erase operation could cause unpredictable results. (c)2011 Silicon Storage Technology, Inc. DS25086A 9 11/11 8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet INIT#, RST# A VIL on INIT# or RST# pin initiates a device reset. INIT# and RST# pins have the same function internally. It is required to drive INIT# or RST# pins low during a system reset to ensure proper CPU initialization. During a Read operation, driving INIT# or RST# pins low deselects the device and places the output drivers, LAD[3:0], in a high-impedance state. The reset signal must be held low for a minimal duration of time TRSTP. A reset latency will occur if a reset procedure is performed during a Program or Erase operation. See Table 19, Reset Timing Parameters for more information. A device reset during an active Program or Erase will abort the operation and memory contents may become invalid due to data being altered or corrupted from an incomplete Erase or Program operation. System Memory Mapping The LPC interface protocol has address length of 32-bit or 4 GByte. The SST49LF080A will respond to addresses in the range as specified in Table 4. Refer to "Multiple Device Selection" section for more detail on strapping multiple SST49LF080A devices to increase memory densities in a system and "Registers" section on valid register addresses. Table 4: Address Decoding Range ID Strapping Device #0 - 3 Device #4 - 7 Device #8 - 11 Device #12 - 15 Device #01 Device Access Address Range Memory Size Memory Access FFFF FFFFH : FFC0 0000H 4 MByte Register Access FFBF FFFFH : FF80 0000H 4 MByte Memory Access FF7F FFFFH : FF40 0000H 4 MByte Register Access FF3F FFFFH : FF00 0000H 4 MByte Memory Access FEFF FFFFH : FEC0 0000H 4 MByte Register Access FEBF FFFFH : FE80 0000H 4 MByte Memory Access FE7F FFFFH : FE40 0000H 4 MByte Register Access FE3F FFFFH : FE00 0000H 4 MByte Memory Access 000F FFFFH : 000E 0000H 128 KByte T4.0 25026 1. For device #0 (Boot Device), SST49LF080A decodes the physical addresses of the top 2 blocks (including Boot Block) both at system memory ranges FFFF FFFFH to FFFE 0000H and 000F FFFFH to 000E 0000H. (c)2011 Silicon Storage Technology, Inc. DS25086A 10 11/11 8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet Table 5: LPC Read Cycle Clock Cycle Field Name Field Contents LAD[3:0]1 LAD[3:0] Direction 1 START 0000 IN LFRAME# must be active (low) for the part to respond. Only the last start field (before LFRAME# transitions high) should be recognized. 2 CYCTYPE + DIR 010X IN Indicates the type of cycle. Bits 3:2 must be "01b" for memory cycle. Bit 1 indicates the type of transfer "0" for Read. Bit 0 is reserved. 3-10 ADDRESS YYYY IN Address Phase for Memory Cycle. LPC protocol supports a 32-bit address phase. YYYY is one nibble of the entire address. Addresses are transferred most-significant nibble fist. See Table 3 for address bits definition and Table 4 for valid memory address range. 11 TAR0 1111 IN then Float In this clock cycle, the host has driven the bus to all 1s and then floats the bus. This is the first part of the bus "turnaround cycle." 12 TAR1 1111 (float) Float then OUT The SST49LF080A takes control of the bus during this cycle 13 SYNC 0000 OUT The SST49LF080A outputs the value 0000b indicating that data will be available during the next clock cycle. 14 DATA ZZZZ OUT This field is the least-significant nibble of the data byte. 15 DATA ZZZZ OUT This field is the most-significant nibble of the data byte. 16 TAR0 1111 OUT then Float 17 TAR1 1111 (float) Float then IN Comments In this clock cycle, the SST49LF080A has driven the bus to all 1s and then floats the bus. This is the first part of the bus "turnaround cycle." The host takes control of the bus during this cycle T5.0 25026 1. Field contents are valid on the rising edge of the present clock cycle. CE# LCLK LFRAME# LAD[3:0] Start CYCTYPE + DIR 0000b 010Xb 1 Clock 1 Clock Address A[31:28] A[27:24] A[23:20] A[19:16] A[15:12] Load Address in 8 Clocks A[11:8] A[7:4] A[3:0] TAR0 TAR1 1111b Tri-State 2 Clocks Sync 0000b Data D[3:0] D[7:4] TAR 1 Clock Data Out 2 Clocks 1235 F04.0 Figure 5: LPC Read Cycle Waveform (c)2011 Silicon Storage Technology, Inc. DS25086A 11 11/11 8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet Table 6: LPC Write Cycle Clock Cycle Field Name Field Contents LAD[3:0]1 LAD[3:0] Direction 1 START 0000 IN LFRAME# must be active (low) for the part to respond. Only the last start field (before LFRAME# transitions high) should be recognized. 2 CYCTYPE + DIR 011X IN Indicates the type of cycle. Bits 3:2 must be "01b" for memory cycle. Bit 1 indicates the type of transfer "1" for Write. Bit 0 is reserved. 3-10 ADDRESS YYYY IN Address Phase for Memory Cycle. LPC protocol supports a 32-bit address phase. YYYY is one nibble of the entire address. Addresses are transferred most-significant nibble first. See Table 3 for address bits definition and Table 4 for valid memory address range. 11 DATA ZZZZ IN This field is the least-significant nibble of the data byte. 12 DATA ZZZZ IN This field is the most-significant nibble of the data byte. 13 TAR0 1111 IN then Float In this clock cycle, the host has driven the bus to all `1's and then floats the bus. This is the first part of the bus "turnaround cycle." 14 TAR1 1111 (float) Float then OUT The SST49LF080A takes control of the bus during this cycle. 15 SYNC 0000 OUT The SST49LF080A outputs the values 0000, indicating that it has received data or a flash command. 16 TAR0 1111 OUT then Float In this clock cycle, the SST49LF080A has driven the bus to all `1's and then floats the bus. This is the first part of the bus "turnaround cycle." 17 TAR1 1111 (float) Float then IN Comments Host resumes control of the bus during this cycle. T6.0 25026 1. Field contents are valid on the rising edge of the present clock cycle. CE# LCLK LFRAME# LAD[3:0] Start CYCTYPE + DIR 0000b 011Xb 1 Clock 1 Clock Address A[31:28] A[27:24] A[23:20] A[19:16] A[15:12] A[11:8] Load Address in 8 Clocks A[7:4] A[3:0] Data Data TAR0 TAR1 D[3:0] D[7:4] 1111b Tri-State Load Data in 2 Clocks 2 Clocks Sync 0000b TAR 1 Clock 1235 F05.0 Figure 6: LPC Write Cycle Waveform (c)2011 Silicon Storage Technology, Inc. DS25086A 12 11/11 8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet Response To Invalid Fields During LPC Read/Write operations, the SST49LF080A will not explicitly indicate that it has received invalid field sequences. The response to specific invalid fields or sequences is as follows: Address out of range: The SST49LF080A will only respond to address ranges as specified in Table 4. ID mismatch: ID information is included in every address cycle. The SST49LF080A will compare ID bits in the address field with the hardware ID strapping. If there is a mis-match, the device will ignore the cycle. See Multiple Device Selection section for details. Once valid START, CYCTYPE + DIR, valid address range and ID bits are received, the SST49LF080A will always complete the bus cycle. However, if the device is busy performing a flash Erase or Program operation, no new internal Write command (memory write or register write) will be executed. As long as the states of LAD[3:0] and LAD[4] are known, the response of the SST49LF080A to signals received during the LPC cycle should be predictable. Abort Mechanism If LFRAME# is driven low for one or more clock cycles after the start of an LPC cycle, the cycle will be terminated. The host may drive the LAD[3:0] with `1111b' (ABORT nibble) to return the interface to ready mode. The ABORT only affects the current bus cycle. For a multi-cycle command sequence, such as the Erase or Program SDP commands, ABORT doesn't interrupt the entire command sequence, but only the current bus cycle of the command sequence. The host can re-send the bus cycle and continue the SDP command sequence after the device is ready again. Write Operation Status Detection The SST49LF080A device provides two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system Write cycle time. The software detection includes two status bits: Data# Polling, D[7], and Toggle Bit, D[6]. The End-of-Write detection mode is incorporated into the LPC Read Cycle. The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either D[7] or D[6]. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid. Data# Polling When the SST49LF080A device is in the internal Program operation, any attempt to read D[7] will produce the complement of the true data. Once the Program operation is completed, D[7] will produce true data. Note that even though D[7] may have valid data immediately following the completion of an internal Write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive Read cycles after an interval of 1 s. During internal Erase operation, any attempt to read D[7] will produce a `0'. Once the internal Erase operation is completed, D[7] will produce a `1'. Proper status will not be given using Data# Polling if the address is in the invalid range. (c)2011 Silicon Storage Technology, Inc. DS25086A 13 11/11 8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet Toggle Bit During the internal Program or Erase operation, any consecutive attempts to read D[6] will produce alternating 0s and 1s, i.e., toggling between 0 and 1. When the internal Program or Erase operation is completed, the toggling will stop. Multiple Device Selection Multiple LPC flash devices may be strapped to increase memory densities in a system. The four ID pins, ID[3:0], allow up to 16 devices to be attached to the same bus by using different ID strapping in a system. BIOS support, bus loading, or the attaching bridge may limit this number. The boot device must have an ID of 0 (determined by ID[3:0]); subsequent devices use incremental numbering. Equal density must be used with multiple devices. When used as a boot device, ID[3:0] must be strapped as 0000; all subsequent devices should use a sequential up-count strapping (i.e. 0001, 0010, 0011, etc.). With the hardware strapping, ID information is included in every LPC address memory cycle. The ID bits in the address field are inverse of the hardware strapping. The address bits [A24:A23, A21:A20] are used to select the device with proper IDs. See Table 7 for IDs. The SST49LF080A will compare these bits with ID[3:0]'s strapping values. If there is a mismatch, the device will ignore the remainder of the cycle. Table 7: Multiple Device Selection Configuration Hardware Strapping Device # Address Bits Decoding ID[3:0] A24 A23 A21 A20 0 (Boot device) 0000 1 1 1 1 1 0001 1 1 1 0 2 0010 1 1 0 1 3 0011 1 1 0 0 4 0100 1 0 1 1 5 0101 1 0 1 0 6 0110 1 0 0 1 7 0111 1 0 0 0 8 1000 0 1 1 1 9 1001 0 1 1 0 10 1010 0 1 0 1 11 1011 0 1 0 0 12 1100 0 0 1 1 13 1101 0 0 1 0 14 1110 0 0 0 1 15 1111 0 0 0 0 T7.0 25026 (c)2011 Silicon Storage Technology, Inc. DS25086A 14 11/11 8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet Registers There are two registers available on the SST49LF080A, the General Purpose Inputs Registers (GPI_REG) and the JEDEC ID Registers. Since multiple LPC memory devices may be used to increase memory densities, these registers appear at its respective address location in the 4 GByte system memory map. Unused register locations will read as 00H. Any attempt to read registers during internal Write operation will respond as "Write operation status detection" (Data# Polling or Toggle Bit). Any attempt to write any registers during internal Write operation will be ignored. Table 9 lists GPI_REG and JEDEC ID address locations for SST49LF080A with its respective device strapping. Table 8: General Purpose Inputs Register Pin # Bit Function 32-PLCC 32-TSOP 7:5 Reserved - - 4 GPI[4] Reads status of general purpose input pin 30 6 3 GPI[3] Reads status of general purpose input pin 3 11 2 GPI[2] Reads status of general purpose input pin 4 12 1 GPI[1] Reads status of general purpose input pin 5 13 0 GPI[0] Reads status of general purpose input pin 6 14 T8.0 25026 (c)2011 Silicon Storage Technology, Inc. DS25086A 15 11/11 8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet General Purpose Inputs Register The GPI_REG (General Purpose Inputs Register) passes the state of GPI[4:0] pins at power-up on the SST49LF080A. It is recommended that the GPI[4:0] pins be in the desired state before LFRAME# is brought low for the beginning of the next bus cycle, and remain in that state until the end of the cycle. There is no default value since this is a pass-through register. See the General Purpose Inputs Register table for the GPI_REG bits and function, and Table 9 for memory address locations for its respective device strapping. JEDEC ID Registers The JEDEC ID registers identify the device as SST49LF080A and manufacturer as SST in LPC mode. See Table 9 for memory address locations for its respective JEDEC ID location. Table 9: Memory Map Register Addresses for SST49LF080A JEDEC ID Device # Hardware Strapping ID[3:0] GPI_REG Manufacturer Device 0 (Boot device) 0000 FFBC 0100H FFBC 0000H FFBC 0001H 1 0001 FFAC 0100H FFAC 0000H FFAC 0001H 2 0010 FF9C 0100H FF9C 0000H FF9C 0001H 3 0011 FF8C 0100H FF8C 0000H FF8C 0001H 4 0100 FF3C 0100H FF3C 0000H FF3C 0001H 5 0101 FF2C 0100H FF2C 0000H FF2C 0001H 6 0110 FF1C 0100H FF1C 0000H FF1C 0001H 7 0111 FF0C 0100H FF0C 0000H FF0C 0001H 8 1000 FEBC 0100H FEBC 0000H FEBC 0001H 9 1001 FEAC 0100H FEAC 0000H FEAC 0001H 10 1010 FE9C 0100H FE9C 0000H FE9C 0001H 11 1011 FE8C 0100H FE8C 0000H FE8C 0001H 12 1100 FE3C 0100H FE3C 0000H FE3C 0001H 13 1101 FE2C 0100H FE2C 0000H FE2C 0001H 14 1110 FE1C 0100H FE1C 0000H FE1C 0001H 15 1111 FE0C 0100H FE0C 0000H FE0C 0001H T9.0 25026 (c)2011 Silicon Storage Technology, Inc. DS25086A 16 11/11 8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet Parallel Programming Mode Device Operation Commands are used to initiate the memory operation functions of the device. The data portion of the software command sequence is latched on the rising edge of WE#. During the software command sequence the row address is latched on the falling edge of R/C# and the column address is latched on the rising edge of R/C#. Reset Driving the RST# low will initiate a hardware reset of the SST49LF080A. See Table 25 for Reset timing parameters and Figure 17 for Reset timing diagram. Read The Read operation of the SST49LF080A device is controlled by OE#. OE# is the output control and is used to gate data from the output pins. Refer to the Read cycle timing diagram, Figure 18, for further details. Byte-Program Operation The SST49LF080A device is programmed on a byte-by-byte basis. Before programming, one must ensure that the sector in which the byte is programmed is fully erased. The Byte-Program operation is initiated by executing a four-byte command load sequence for Software Data Protection with address (BA) and data in the last byte sequence. During the Byte-Program operation, the row address (A10-A0) is latched on the falling edge of R/C# and the column address (A21-A11) is latched on the rising edge of R/C#. The data bus is latched on the rising edge of WE#. The Program operation, once initiated, will be completed, within 20 s. See Figure 22 for Program operation timing diagram and Figure 34 for its flowchart. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands written during the internal Program operation will be ignored. Sector-Erase Operation The Sector-Erase operation allows the system to erase the device on a sector-by-sector basis. The sector architecture is based on uniform sector size of 4 KByte. The Sector-Erase operation is initiated by executing a six-byte command load sequence for Software Data Protection with Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The internal Erase operation begins after the sixth WE# pulse. The End-of-Erase can be determined using either Data# Polling or Toggle Bit methods. See Figure 23 for Sector-Erase timing waveforms. Any commands written during the SectorErase operation will be ignored. Block-Erase Operation The Block-Erase Operation allows the system to erase the device in 64 KByte uniform block size for the SST49LF080A. The Block-Erase operation is initiated by executing a six-byte command load sequence for Software Data Protection with Block-Erase command (50H) and block address. The internal Block-Erase operation begins after the sixth WE# pulse. The End-of-Erase can be determined using either Data# Polling or Toggle Bit methods. See Figure 24 for Block-Erase timing waveforms. Any commands written during the Block-Erase operation will be ignored. (c)2011 Silicon Storage Technology, Inc. DS25086A 17 11/11 8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet Chip-Erase Operation The SST49LF080A devices provide a Chip-Erase operation, which allows the user to erase the entire memory array to the "1s" state. This is useful when the entire device must be quickly erased. The Chip-Erase operation is initiated by executing a six- byte Software Data Protection command sequence with Chip-Erase command (10H) with address 5555H in the last byte sequence. The internal Erase operation begins with the rising edge of the sixth WE#. During the internal Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 11 for the command sequence, Figure 25 for Chip-Erase timing diagram, and Figure 37 for the flowchart. Any commands written during the ChipErase operation will be ignored. Write Operation Status Detection The SST49LF080A devices provide two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system Write cycle time. The software detection includes two status bits: Data# Polling D[7] and Toggle Bit D[6]. The End-of-Write detection mode is enabled after the rising edge of WE# which initiates the internal Program or Erase operation. The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either D[7] or D[6]. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid. Data# Polling (DQ7) When the SST49LF080A device is in the internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce true data. Note that even though DQ7 may have valid data immediately following the completion of an internal Write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive Read cycles after an interval of 1 s. During internal Erase operation, any attempt to read DQ7 will produce a `0'. Once the internal Erase operation is completed, DQ7 will produce a `1'. The Data# Polling is valid after the rising edge of fourth WE# pulse for Program operation. For Sector-, Block-, or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# pulse. See Figure 20 for Data# Polling timing diagram and Figure 35 for a flowchart. Proper status will not be given using Data# Polling if the address is in the invalid range. (c)2011 Silicon Storage Technology, Inc. DS25086A 18 11/11 8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet Toggle Bit (DQ6) During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating `0's and `1's, i.e., toggling between 0 and 1. When the internal Program or Erase operation is completed, the toggling will stop. The device is then ready for the next operation. The Toggle Bit is valid after the rising edge of fourth WE# pulse for Program operation. For Sector-, Block-, or ChipErase, the Toggle Bit is valid after the rising edge of sixth WE# pulse. See Figure 21 for Toggle Bit timing diagram and Figure 35 for a flowchart. Table 10:Operation Modes Selection (PP Mode) Mode RST# OE# WE# Read Erase VIH VIH VIH VIL VIH VIH Reset VIL X Write Inhibit VIH X VIH VIL Program Product Identification DQ Address VIH DOUT AIN VIL DIN AIN VIL X1 Sector or Block address, XXH for Chip-Erase X High Z X VIL X X VIH VIH High Z/DOUT High Z/DOUT X X Manufacturer's ID (BFH) Device ID2 See Table 11 T10.0 25026 1. X can be VIL or VIH, but no other value. 2. Device ID = 5BH for SST49LF080A Data Protection (PP Mode) The SST49LF080A devices provide both hardware and software features to protect nonvolatile data from inadvertent writes. Hardware Data Protection Noise/Glitch Protection: A WE# pulse of less than 5 ns will not initiate a Write cycle. VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V. Write Inhibit Mode: Forcing OE# low, WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down. Software Data Protection (SDP) The SST49LF080A provides the JEDEC approved Software Data Protection scheme for all data alteration operation, i.e., Program and Erase. Any Program operation requires the inclusion of a series of three-byte sequence. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or powerdown. Any Erase operation requires the inclusion of a six-byte load sequence. (c)2011 Silicon Storage Technology, Inc. DS25086A 19 11/11 8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet Software Command Sequence Table 11:Software Command Sequence 1st1 Cycle 2nd1 Cycle 3rd1 Cycle 4th1 Cycle 5th1 Cycle Command Sequence Addr2 Data Addr2 Data Addr2 Data Addr2 Data Byte-Program YYYY 5555H AAH YYYY 2AAA H 55H YYYY 5555 H A0H PA3 Data Sector-Erase YYYY 5555H AAH YYYY 2AAA H 55H YYYY 5555 H 80H YYYY 5555 H Block-Erase YYYY 5555H AAH YYYY 2AAA H 55H YYYY 5555 H 80H Chip-Erase6 YYYY 5555H AAH YYYY 2AAA H 55H YYYY 5555 H 80H Software ID Entry YYYY 5555H AAH YYYY 2AAA H 55H YYYY 5555 H 90H Software ID Exit8 XXXX XXXXH F0H Software ID Exit8 YYYY 5555H AAH YYYY 2AAA H 55H YYYY 5555 H F0H 6th1 Cycle Addr2 Data Addr2 Data AAH YYYY 2AAA H 55H SAX4 30H YYYY 5555 H AAH YYYY 2AAA H 55H BAX5 50H YYYY 5555 H AAH YYYY 2AAA H 55H YYYY 5555 H 10H Read ID7 T11.0 25026 1. LPC mode use consecutive Write cycles to complete a command sequence; PP mode use consecutive bus cycles to complete a command sequence. 2. YYYY = A[31:16]. In LPC mode, during SDP command sequence, YYYY must be within memory address range specified in Table 4. In PP mode, YYYY can be VIL or VIH, but no other value. 3. PA = Program Byte address 4. SAX for Sector-Erase Address 5. BAX for Block-Erase Address 6. Chip-Erase is supported in PP mode only 7. SST Manufacturer's ID = BFH, is read with A0 = 0. With A19-A1 = 0; SST49LF080A Device ID = 5BH, is read with A0 = 1. 8. Both Software ID Exit operations are equivalent (c)2011 Silicon Storage Technology, Inc. DS25086A 20 11/11 8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet CE# LCLK LFRAME# LAD[3:0] 1st Start Memory Write Cycle 0000b 011Xb Address1 A[31:28] A[27:24] A[23:20] A[19:16] 1 Clock 1 Clock 0101b Data 0101b 0101b 0101b Load Address YYYY 5555H in 8 Clocks 1010b TAR 1010b 1111b Start next Command Sync TAR Tri-State 0000b Load Data AAH in 2 Clocks 2 Clocks 1 Clock 1 Clock Write the 1st command to the device in LPC mode. CE# LCLK LFRAME# LAD[3:0] 2nd Start Memory Write Cycle 0000b 011Xb 1 Clock 1 Clock Address1 A[31:28] A[27:24] A[23:20] A[19:16] 0010b Data 1010b 1010b 1010b 0101b TAR 0101b 1111b Load Data 55H in 2 Clocks 2 Clocks Load Address YYYY 2AAAH in 8 Clocks Start next Command Sync Tri-State 0000b TAR 1 Clock 1 Clock Write the 2nd command to the device in LPC mode. CE# LCLK LFRAME# Address1 3rd Start LAD[3:0] 0000b 011Xb 1 Clock 1 Clock A[31:28] A[27:24] A[23:20] A[19:16] 0101b Data 0101b 0101b Load Address YYYY 5555H in 8 Clocks 0101b 0000b TAR 1010b 1111b Tri-State 0000b Load Data A0H in 2 Clocks 2 Clocks Start next Command Sync TAR 1 Clock 1 Clock Write the 3rd command to the device in LPC mode. CE# LCLK LFRAME# LAD[3:0] 4th Start Memory Write Cycle 0000b 011Xb Internal program start Address1 A[31:28] A[27:24] A[23:20] A[19:16] A[15:12] A[11:8] Data A[7:4] Load Ain in 8 Clocks 1 Clock 1 Clock A[3:0] D[3:0] TAR D[7:4] Load Data in 2 Clocks 1111b Sync Tri-State 0000b 2 Clocks TAR 1 Clock Write the 4th command (target locations to be programmed) to the device in LPC mode. Internal program start 1235 F06.0 Note: 1. Address must be within memory address range specified in Table 4. Figure 7: Program Command Sequence (LPC Mode) (c)2011 Silicon Storage Technology, Inc. DS25086A 21 11/11 8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet CE# LCLK LFRAME# 1st Start LAD[3:0] Memory Write Cycle 0000b 011Xb 1 Clock 1 Clock Address1 A[31:28] A[27:24] A[23:20] A[19:16] Data A[15:12] A[11:8] A[7:4] A[3:0] D[3:0] Dn[7:4] TAR Sync 1111b Tri-State 0000b 2 Clocks 1 Clock Load Data in 2 Clocks Load Address in 8 Clocks Start next Command 0000b TAR 1 Clock Write the last command (Program or Erase) to the device in LPC mode. CE# LCLK LFRAME# Start LAD[3:0] 0000b Next start Memory Read Cycle 010Xb 1 Clock 1 Clock Address1 A[31:28] A[27:24] A[23:20] A[19:16] Sync TAR A[15:12] A[11:8] A[7:4] A[3:0] 1111b Tri-State 0000b 2 Clocks Load Address in 8 Clocks Read the DQ7 to see if internal write complete or not. 1 Clock Data XXXXb D7#,xxx TAR 0000b 1 Clock Data out 2 Clocks CE# LCLK LFRAME# Start LAD[3:0] 0000b Next start Memory Read Cycle 010Xb 1 Clock 1 Clock Address1 A[31:28] A[27:24] A[23:20] A[19:16] TAR A[15:12] A[11:8] A[7:4] A[3:0] Load Address in 8 Clocks 1111b Tri-State 2 Clocks Sync 0000b Data XXXXb D7,xxx 1 Clock Data out 2 Clocks TAR 0000b 1 Clock When internal write complete, the DQ7 will equal to D7. 1235 F07.0 Note: 1. Address must be within memory address range specified in Table 4. Figure 8: Data# Polling Command Sequence (LPC Mode) (c)2011 Silicon Storage Technology, Inc. DS25086A 22 11/11 8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet CE# LCLK LFRAME# LAD[3:0] 1st Start Memory Write Cycle 0000b 011Xb 1 Clock 1 Clock Address1 Data A[19:16] A[15:12] A[11:8] A[31:28] A[27:24] A[23:20] A[7:4] Load Address in 8 Clocks A[3:0] D[3:0] TAR D[7:4] Load Data in 2 Clocks 1111b Start next Command 0000b Sync Tri-State 0000b 2 Clocks TAR 1 Clock 1 Clock Write the last command (Program or Erase) to the device in LPC mode. CE# LCLK LFRAME# Start LAD[3:0] 0000b Next start Memory Read Cycle 010Xb 1 Clock 1 Clock Address1 A[31:28] A[27:24] A[23:20] A[19:16] TAR A[15:12] A[11:8] A[7:4] A[3:0] 1111b Load Address in 8 Clocks Sync Tri-State 0000b Data XXXXb X,D6#,XXb 2 Clocks 1 Clock Data out 2 Clocks TAR Sync Data 0000b TAR 1 Clock Read the DQ6 to see if internal write complete or not. CE# LCLK LFRAME# Next start Start LAD[3:0] 0000b Memory Read Cycle 010Xb 1 Clock 1 Clock Address1 A[31:28] A[27:24] A[23:20] A[19:16] A[15:12] A[11:8] A[7:4] A[3:0] 1111b Load Address in 8 Clocks When internal write complete, the DQ6 will stop toggle. Tri-State 0000b 2 Clocks XXXXb X,D6,XXb 0000b TAR 1 Clock 1 Clock Data out 2 Clocks 1235 F08.0 Note: 1. Address must be within memory address range specified in Table 4. Figure 9: Toggle Bit Command Sequence (LPC Mode) (c)2011 Silicon Storage Technology, Inc. DS25086A 23 11/11 8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet CE# LCLK LFRAME# Memory Write Cycle 1st Start LAD[3:0] 0000b 011Xb 1 Clock 1 Clock Address1 Data A[31:28] A[27:24] A[23:20] A[19:16] 0101b 0101b 0101b Load Address YYYY 5555H in 8 Clocks 0101b 1010b TAR 1010b 1111b Start next Command Sync Tri-State 0000b Load Data AAH in 2 Clocks 2 Clocks TAR 1 Clock 1 Clock Write the 1st command to the device in LPC mode. CE# LCLK LFRAME# Memory Write Cycle 2nd Start LAD[3:0] 0000b 011Xb 1 Clock 1 Clock Address1 Data 0010b A[31:28] A[27:24] A[23:20] A[19:16] 1010b 1010b Load Address YYYY 2AAAH in 8 Clocks 1010b 0101b TAR 0101b 1111b Load Data 55H in 2 Clocks Start next Command Sync Tri-State 0000b 2 Clocks TAR 1 Clock 1 Clock Write the 2nd command to the device in LPC mode. CE# LCLK LFRAME# 3rd Start LAD[3:0] Memory Write Cycle 0000b 011Xb 1 Clock 1 Clock Address1 A[31:28] A[27:24] A[23:20] A[19:16] Data 0101b 0101b 0101b Load Address YYYY 5555H in 8 Clocks 0101b 0000b TAR 1000b Load Data 80H in 2 Clocks Start next Command Sync Tri-State 0000b 1111b 2 Clocks TAR 1 Clock 1 Clock Write the 3rd command to the device in LPC mode. CE# LCLK LFRAME# Memory Write Cycle 4th Start LAD[3:0] 0000b 011Xb 1 Clock 1 Clock Address1 A[31:28] A[27:24] A[23:20] A[19:16] TAR Data 0101b 0101b 0101b Load Address YYYY 5555H in 8 Clocks 0101b 1010b 1010b Start next Command Sync Tri-State 1111b Load Data AAH in 2 Clocks 2 Clocks 0000b TAR 1 Clock 1 Clock Write the 4th command to the device in LPC mode. CE# LCLK LFRAME# LAD[3:0] 5th Memory Write Cycle 0000b 011Xb 1 Clock 1 Clock Address1 A[31:28] A[27:24] A[23:20] A[19:16] TAR Data 0010b 1010b Load Address YYYY 2AAA in 8 ClocksH 1010b 1010b 0101b 0101b Load Data 55H in 2 Clocks 2 Clocks Start next Command Sync Tri-State 1111b 0000b TAR 1 Clock 1 Clock Write the 5th command to the device in LPC mode. CE# LCLK Internal erase start LFRAME# 6th Start LAD[3:0] 0000b Memory Write Cycle 011Xb 1 Clock 1 Clock Address1 A[31:28] A[27:24] A[23:20] A[19:16] Data SAX XXXXb XXXXb XXXXb 0000b 0011b Load Sector Address in 8 Clocks Load Data "30" in 2 Clocks Write the 6th command (target sector to be erased) to the device in LPC mode. SAX = Sector Address TAR 1111b Tri-State 2 Clocks Internal erase start Sync 0000b TAR 1 Clock 1235 F12.0 Figure 10:Sector-Erase Command Sequence (LPC Mode) (c)2011 Silicon Storage Technology, Inc. DS25086A 24 11/11 8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet CE# LCLK LFRAME# 1st Start LAD[3:0] Memory Write Cycle Address1 011Xb A[31:28] A[27:24] A[23:20] A[19:16] 0000b Start next Command Data 0101b 0101b 0101b 0101b 1010b Sync TAR 1111b 1010b Tri-State 0000b Load Data AAH in 2 Clocks 2 Clocks Load Address YYYY 5555H in 8 Clocks Write the 1st command to the device in LPC mode. 1 Clock 1 Clock TAR 1 Clock 1 Clock CE# LCLK LFRAME# 2nd Start Memory Write Cycle 0000b 011Xb LAD[3:0] 1 Clock 1 Clock Start next Command Address1 A[31:28] A[27:24] A[23:20] A[19:16] Data 0010b 1010b 1010b Load Address YYYY 2AAAH in 8 Clocks 1010b 0101b TAR 0101b 1111b Load Data 55H in 2 Clocks Sync Tri-State 2 Clocks 0000b TAR 1 Clock 1 Clock Write the 2nd command to the device in LPC mode. CE# LCLK LFRAME# 3rd Start LAD[3:0] 0000b Memory Write Cycle 011Xb 1 Clock 1 Clock Start next Command Address1 A[31:28] A[27:24] A[23:20] A[19:16] Data 0101b 0101b 0101b Load Address YYYY 5555H in 8 Clocks 0101b 0000b TAR 1000b Sync 1111b Tri-State Load Data 80H in 2 Clocks 2 Clocks 0000b TAR 1 Clock 1 Clock Write the 3rd command to the device in LPC mode. CE# LCLK LFRAME# 4th Start LAD[3:0] 0000b Start next Command Memory Write Cycle 011Xb 1 Clock 1 Clock Address1 A[31:28] A[27:24] A[23:20] A[19:16] Data 0101b 0101b 0101b 0101b 1010b Sync TAR 1111b 1010b Tri-State Load Data AAH in 2 Clocks 2 Clocks Load Address YYYY 5555H in 8 Clocks Write the 4th command to the device in LPC mode. 0000b TAR 1 Clock 1 Clock CE# LCLK LFRAME# 5th LAD[3:0] 0000b Memory Write Cycle 011Xb 1 Clock 1 Clock Start next Command Address1 A[31:28] A[27:24] A[23:20] A[19:16] Data 0010b 1010b 1010b 1010b 0101b 1111b 0101b Load Data 55H in 2 Clocks Load Address YYYY 2AAAH in 8 Clocks Sync TAR Tri-State 2 Clocks 0000b TAR 1 Clock 1 Clock Write the 5th command to the device in LPC mode. CE# LCLK Internal erase start LFRAME# 6th Start LAD[3:0] 0000b Memory Write Cycle Address1 011Xb A[31:28] A[27:24] A[23:20] A[19:16] 1 Clock 1 Clock Data BAX XXXXb XXXXb Load Block Address in 8 Clocks XXXXb 0000b 0101b Load Data "50" in 2 Clocks Write the 6th command (target sector to be erased) to the device in LPC mode. BAX = Block Address TAR 1111b 2 Clocks Internal erase start Sync Tri-State 0000b TAR 1 Clock 1235 F10.0 Note: 1. Address must be within memory address range specified in Table 4. Figure 11:Block-Erase Command Sequence (LPC Mode) (c)2011 Silicon Storage Technology, Inc. DS25086A 25 11/11 8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet CE# LCLK LFRAME# Start LAD[3:0] 0000b Memory Read Cycle 010Xb Address1 A[31:28] A[27:24] A[23:20] A[19:16] A[15:12] A[11:8] 1 Clock 1 Clock Load Address in 8 Clocks TAR A[7:4] A[3:0] 1111b Tri-State 2 Clocks Sync 0000b 1 Clock Start next Data D[3:0] D[7:4] 0000b TAR 1 Clock Data out 2 Clocks 1235 F11.0 Note: 1. See Table 9 for register addresses. Figure 12:Register Readout Command Sequence (LPC Mode)DS25086 (c)2011 Silicon Storage Technology, Inc. DS25086A 26 11/11 8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet Electrical Specifications The AC and DC specifications for the LPC interface signals (LA0[3:0], LFRAME, LCLCK and RST#) as defined in Section 4.2.2.4 of the PCI local Bus specification, Rev. 2.1. Refer to Table 14 for the DC voltage and current specifications. Refer to Tables 18 through 21 and Tables 23 through 25 for the AC timing specifications for Clock, Read, Write, and Reset operations. Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this datasheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to +125C Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C D.C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V Package Power Dissipation Capability (Ta=25C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Surface Mount Solder Reflow Temperature1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C for 10 seconds Output Short Circuit Current2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA 1. Excluding certain with-Pb 32-PLCC units, all packages are 260C capable in both non-Pb and with-Pb solder versions. Certain with-Pb 32-PLCC package types are capable of 240C for 10 seconds; please consult the factory for the latest information. 2. Outputs shorted for no more than one second. No more than one output shorted at a time. Table 12:Operating Range Range Commercial Ambient Temp VDD 0C to +85C 3.0-3.6V T12.1 25026 Table 13:AC Conditions of Test1 Input Rise/Fall Time Output Load 3 ns CL = 30 pF T13.1 25026 1. See Figures 28 and 29 (c)2011 Silicon Storage Technology, Inc. DS25086A 27 11/11 8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet DC Characteristics Table 14:DC Operating Characteristics (All Interfaces) Limits Symbol Parameter IDD1 Min Max Units Test Conditions Active VDD Current ISB LCLK (LPC mode) and Address Input (PP mode)=VILT/VIHT at f=33 MHz (LPC mode) or 1/TRC min (PP Mode) All other inputs=VIL or VIH Read 12 mA All outputs = open, VDD=VDD Max Write 24 mA See Note2 100 A LCLK (LPC mode) and Address Input (PP mode)=VILT/VIHT Standby VDD Current (LPC Interface) at f=33 MHz (LPC mode) or 1/TRC min (PP Mode) LFRAME#=0.9 VDD, f=33 MHz, CE#=0.9 VDD, VDD=VDD Max, All other inputs 0.9 VDD or 0.1 VDD IRY3 Ready Mode VDD Current (LPC Interface) 10 mA LCLK (LPC mode) and Address Input (PP mode)=VILT/VIHT II Input Current for Mode and ID[3:0] pins 200 ILI Input Leakage Current 1 A VIN=GND to VDD, VDD=VDD Max ILO Output Leakage Current 1 A VOUT=GND to VDD, VDD=VDD Max VIHI INIT# Input High Voltage 1.1 VDD+0. 5 V VDD=VDD Max VILI INIT# Input Low Voltage -0.5 0.4 V VDD=VDD Min VIL Input Low Voltage -0.5 0.3 VDD V VDD=VDD Min VIH Input High Voltage 0.5 VDD VDD+0. 5 V VDD=VDD Max VOL Output Low Voltage 0.1 VDD V IOL=1500 A, VDD=VDD Min VOH Output High Voltage V IOH=-500 A, VDD=VDD Min at f=33 MHz (LPC mode) or 1/TRC min (PP Mode) LFRAME#=VIL, f=33 MHz, VDD=VDD Max All other inputs 0.9 VDD or 0.1 VDD 0.9 VDD A VIN=GND to VDD, VDD=VDD Max T14.0 25026 1. IDD active while a Read or Write (Program or Erase) operation is in progress. 2. For PP Mode: OE# = WE# = VIH; For LPC Mode: f = 1/TRC min, LFRAME# = VIH, CE# = VIL. 3. The device is in Ready mode when no activity is on the LPC bus. Table 15:Recommended System Power-up Timings Symbol Parameter Minimum Units TPU-READ1 Power-up to Read Operation 100 s Power-up to Write Operation 100 s TPU-WRITE 1 T15.0 25026 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter (c)2011 Silicon Storage Technology, Inc. DS25086A 28 11/11 8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet Table 16:Pin Capacitance (VDD=3.3V, Ta=25 C, f=1 Mhz, other pins open) Parameter Description Test Condition Maximum CI/O1 I/O Pin Capacitance VI/O=0V 12 pF Input Capacitance VIN=0V 12 pF 1 CIN T16.0 25026 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. Table 17:Reliability Characteristics Symbol NEND 1 Parameter Minimum Specification Units Test Method Endurance 10,000 Cycles JEDEC Standard A117 100 Years JEDEC Standard A103 100 + IDD mA TDR1 Data Retention ILTH1 Latch Up JEDEC Standard 78 T17.0 25026 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. Table 18:Clock Timing Parameters (LPC Mode) Symbol Parameter Min Max Units TCYC LCLK Cycle Time 30 ns THIGH LCLK High Time 11 ns TLOW LCLK Low Time 11 - LCLK Slew Rate (peak-to-peak) 1 - RST# or INIT# Slew Rate 50 ns 4 V/ns mV/ns T18.0 25026 Tcyc Thigh Tlow 0.6 VDD 0.5 VDD 0.4 VDD p-to-p (minimum) 0.4 VDD 0.3 VDD 0.2 VDD 1235 F12.0 Figure 13:LCLK Waveform (LPC Mode) (c)2011 Silicon Storage Technology, Inc. DS25086A 29 11/11 8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet Table 19:Reset Timing Parameters, VDD=3.0-3.6V (LPC Mode) Symbol Parameter TPRST VDD stable to Reset Low Min TKRST TRSTP TRSTF RST# Low to Output Float TRST1 RST# High to LFRAME# Low TRSTE RST# Low to reset during Sector-/Block-Erase or Program Max Units 1 ms Clock Stable to Reset Low 100 s RST# Pulse Width 100 ns 48 ns 1 s 10 s T19.0 25026 1. There may be additional latency due toTRSTE if a reset procedure is performed during a Program or Erase operation. VDD TPRST CLK TKRST TRSTP RST#/INIT# TRSTE TRSTF TRST Sector-/Block-Erase or Program operation aborted LAD[3:0] LFRAME# 1235 F13.0 Figure 14:Reset Timing Diagram (LPC Mode) (c)2011 Silicon Storage Technology, Inc. DS25086A 30 11/11 8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet AC Characteristics Table 20:Read/Write Cycle Timing Parameters, VDD=3.0-3.6V (LPC Mode) Symbol Parameter TCYC Clock Cycle Time 30 ns TSU Data Set Up Time to Clock Rising 7 ns TDH Clock Rising to Data Hold Time 0 ns Clock Rising to Data Valid 2 TVAL 1 Min TBP Byte Programming Time Max Units 11 ns 20 s TSE Sector-Erase Time 25 ms TBE Block-Erase Time 25 ms TON Clock Rising to Active (Float to Active Delay) TOFF Clock Rising to Inactive (Active to Float Delay) 2 ns 28 ns T20.0 25026 1. Minimum and maximum times have different loads. See PCI spec. Table 21:AC Input/Output Specifications (LPC Mode) Symbol Parameter IOH(AC) Switching Current High Min Max Units mA mA 0 < VOUT 0.3 VDD 0.3 VDD < VOUT < 0.9 VDD 0.7 VDD < VOUT < VDD -32 VDD mA VOUT = 0.7 VDD Equation D1 mA mA VDD >VOUT 0.6 VDD 0.6 VDD > VOUT > 0.1 VDD 0.18 VDD > VOUT > 0 38 VDD mA VOUT = 0.18 VDD -12 VDD -17.1(VDD-VOUT) Equation C1 (Test Point) IOL(AC) Switching Current Low 16 VDD 26.7 VOUT (Test Point) Conditions ICL Low Clamp Current -25+(VIN+1)/0.015 mA -3 < VIN -1 ICH High Clamp Current 25+(VIN-VDD-1)/0.015 mA VDD+4 > VIN VDD+1 slewr2 Output Rise Slew Rate 1 4 V/ns 0.2 VDD-0.6 VDD load slewf2 Output Fall Slew Rate 1 4 V/ns 0.6 VDD-0.2 VDD load T21.0 25026 1. See PCI spec. 2. PCI specification output load is used. (c)2011 Silicon Storage Technology, Inc. DS25086A 31 11/11 8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet VTH LCLK VTEST VTL TVAL LAD [3:0] (Valid Output Data) LAD [3:0] (Float Output Data) TON TOFF 1235 F14.0 Figure 15:Output Timing Parameters (LPC Mode) VTH VTEST LCLK VTL TSU TDH LAD [3:0] (Valid Input Data) Inputs Valid VMAX 1235 F15.0 Figure 16:Input Timing Parameters (LPC Mode) Table 22:Interface Measurement Condition Parameters (LPC Mode) Symbol Value Units VTH1 0.6 VDD V 1 0.2 VDD V VTEST 0.4 VDD V 1 0.4 VDD V 1 V/ns VTL VMAX Input Signal Edge Rate T22.0 25026 1. The input test environment is done with 0.1 VDD of overdrive over VIH and VIL. Timing parameters must be met with no more overdrive than this. VMAX specified the maximum peak-to-peak waveform allowed for measuring input timing. Production testing may use different voltage values, but must correlate results back to these parameters (c)2011 Silicon Storage Technology, Inc. DS25086A 32 11/11 8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet Table 23:Read Cycle Timing Parameters, VDD=3.0-3.6V (PP Mode) Symbol Parameter Min TRC Read Cycle Time 270 Max Units ns TRST RST# High to Row Address Setup 1 s TAS R/C# Address Set-up Time 45 ns TAH R/C# Address Hold Time 45 TAA Address Access Time ns 120 TOE Output Enable Access Time TOLZ OE# Low to Active Output TOHZ OE# High to High-Z Output TOH Output Hold from Address Change ns 60 ns 0 ns 35 ns 0 ns T23.0 25026 Table 24:Program/Erase Cycle Timing Parameters, VDD=3.0-3.6V (PP Mode) Symbol Parameter Min Max Units TRST RST# High to Row Address Setup 1 s TAS R/C# Address Setup Time 50 ns TAH R/C# Address Hold Time 50 ns TCWH R/C# to Write Enable High Time 50 ns TOES OE# High Setup Time 20 ns TOEH OE# High Hold Time 20 ns TOEP OE# to Data# Polling Delay 40 ns TOET OE# to Toggle Bit Delay 40 ns TWP WE# Pulse Width 100 ns TWPH WE# Pulse Width High 100 ns TDS Data Setup Time 50 ns TDH Data Hold Time 5 ns TIDA Software ID Access and Exit Time 150 ns TBP Byte Programming Time 20 s TSE Sector-Erase Time 25 ms TBE Block-Erase Time 25 ms TSCE Chip-Erase Time 100 ms T24.0 25026 (c)2011 Silicon Storage Technology, Inc. DS25086A 33 11/11 8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet Table 25:Reset Timing Parameters, VDD=3.0-3.6V (PP Mode) Symbol Parameter TPRST VDD stable to Reset Low TRSTP RST# Pulse Width TRSTF RST# Low to Output Float TRST 1 Min Max Units 1 ms 100 ns 48 RST# High to Row Address Setup ns 1 s TRSTE RST# Low to reset during Sector-/Block-Erase or Program 10 TRSTC RST# Low to reset during Chip-Erase 50 s s T25.0 25026 1. There may be additional reset latency due to TRSTE or TRSTC if a reset procedure is performed during a Program or Erase operation. VDD TPRST Addresses Row Address R/C# TRSTP RST# Sector-/Block-Erase or Program operation aborted TRSTE TRSTC TRSTF TRST Chip-Erase aborted DQ7-0 1235 F16.0 Figure 17:Reset Timing Diagram (PP Mode) (c)2011 Silicon Storage Technology, Inc. DS25086A 34 11/11 8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet RST# TRST TRC Addresses Row Address Column Address TAS TAS TAH Row Address Column Address TAH R/C# WE# VIH TAA OE# TOH TOE TOHZ TOLZ DQ7-0 High-Z Data Valid High-Z 1235 F17.0 Figure 18:Read Cycle Timing Diagram (PP Mode) TRST RST# Addresses Row Address TAS Column Address TAH TAS TAH R/C# TOEH TCWH OE# TOES TWPH TWP WE# TDS DQ7-0 TDH Data Valid 1235 F18.0 Figure 19:Write Cycle Timing Diagram (PP Mode) (c)2011 Silicon Storage Technology, Inc. DS25086A 35 11/11 8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet Row Addresses Column R/C# WE# OE# TOEP D DQ7 D# D# D 1235 F19.0 Figure 20:Data# Polling Timing Diagram (PP Mode) Addresses Row Column R/C# WE# OE# TOET DQ6 D D 1235 F20.0 Figure 21:Toggle Bit Timing Diagram (PP Mode) A14-0 (Internal AMS-0) 5555 2AAA 5555 BA R/C# OE# WE# DQ7-0 Internal Program Starts 55 AA BA = Byte-Program Address AMS = Most Significant Address A0 DATA 1235 F21.0 Figure 22:Byte-Program Timing Diagram (PP Mode) (c)2011 Silicon Storage Technology, Inc. DS25086A 36 11/11 8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet A14-0 (Internal AMS-0) 5555 2AAA 5555 5555 2AAA SAX R/C# OE# WE# Internal Erase Starts DQ7-0 55 AA 80 AA 55 30 1235 F22.0 SAX = Sector Address Figure 23:Sector-Erase Timing Diagram (PP Mode) A14-0 (Internal AMS-0) 5555 2AAA 5555 5555 2AAA BAX R/C# OE# WE# Internal Erase Starts DQ7-0 55 AA 80 AA 55 50 1235 F23.0 BAX = Block Address Figure 24:Block-Erase Timing Diagram (PP Mode) A14-0 (Internal AMS-0) 5555 2AAA 5555 5555 2AAA 5555 R/C# OE# WE# Internal Erase Starts DQ7-0 AA 55 80 AA 55 10 1235 F24.0 Figure 25:Chip-Erase Timing Diagram (PP Mode) (c)2011 Silicon Storage Technology, Inc. DS25086A 37 11/11 8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet A14-0 (Internal AMS-0) 2AAA 5555 5555 0000 0001 R/C# OE# TWP WE# TIDA TWPH DQ7-0 55 AA TAA BF 90 Device ID 1235 F25.0 Note: Device ID = 5BH for SST49LF080A Figure 26:Software ID Entry and Read (PP Mode) A14-0 (Internal AMS-0) 2AAA 5555 5555 R/C# OE# TIDA WE# DQ7-0 AA 55 F0 1235 F26.0 Figure 27:Software ID Exit (PP Mode) (c)2011 Silicon Storage Technology, Inc. DS25086A 38 11/11 8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet VIHT INPUT VIT REFERENCE POINTS VOT OUTPUT VILT 1235 F27.0 AC test inputs are driven at VIHT (0.9 VDD) for a logic "1" and VILT (0.1 VDD) for a logic "0". Measurement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% 90%) are <3 ns. Note: VIT - VINPUT Test VOT - VOUTPUT Test VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test Figure 28:AC Input/Output Reference Waveforms TO TESTER TO DUT CL 1235 F28.0 Figure 29:A Test Load Example Read Command Sequence Address: AIN Read Data: DOUT Cycle: 1 Available for Next Command 1235 F29.0 Figure 30:Read Flowchart (LPC Mode) (c)2011 Silicon Storage Technology, Inc. DS25086A 39 11/11 8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet Address: 5555H Write Data: AAH Cycle: 1 Address: 2AAAH Write Data: 55H Cycle: 2 Address: 5555H Write Data: A0H Cycle: 3 Address: AIN Write Data: DIN Cycle: 4 Wait TBP Available for Next Byte 1235 F30.0 Figure 31:Byte-Program Flowchart (LPC Mode) (c)2011 Silicon Storage Technology, Inc. DS25086A 40 11/11 8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet Block-Erase Command Sequence Sector-Erase Command Sequence Address: 5555H Write Data: AAH Cycle: 1 Address: 5555H Write Data: AAH Cycle: 1 Address: 2AAAH Write Data: 55H Cycle: 2 Address: 2AAAH Write Data: 55H Cycle: 2 Address: 5555H Write Data: 80H Cycle: 3 Address: 5555H Write Data: 80H Cycle: 3 Address: 5555H Write Data: AAH Cycle: 4 Address: 5555H Write Data: AAH Cycle: 4 Address: 2AAAH Write Data: 55H Cycle: 5 Address: 2AAAH Write Data: 55H Cycle: 5 Address: BAX Write Data: 50H Cycle: 6 Address: SAX Write Data: 30H Cycle: 6 Wait TBE Wait TSE Block erased to FFH Sector erased to FFH Available for Next Command Available for Next Command 1235 F31.0 Figure 32:Erase Command Sequences Flowchart (LPC Mode) (c)2011 Silicon Storage Technology, Inc. DS25086A 41 11/11 8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet Software Product ID Entry Command Sequence Software Product ID Exit Command Sequence Address: 5555H Write Data: AAH Cycle: 1 Address: 5555H Write Data: AAH Cycle: 1 Address: XXXXH Write Data: F0H Cycle: 1 Address: 2AAAH Write Data: 55H Cycle: 2 Address: 2AAAH Write Data: 55H Cycle: 2 Wait TIDA Address: 5555H Write Data: 90H Cycle: 3 Address: 5555H Write Data: F0H Cycle: 3 Available for Next Command Wait TIDA Wait TIDA Address: 0001H Read Data: BFH Cycle: 4 Available for Next Command Address: 0002H Read Data: Cycle: 5 Available for Next Command Note: X can be VIL or VIH, but no other value. 1235 F32.0 Figure 33:Software Product ID Command Sequences Flowchart (LPC Mode) (c)2011 Silicon Storage Technology, Inc. DS25086A 42 11/11 8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet Start Write data: AAH Address: 5555H Write data: 55H Address: 2AAAH Write data: A0H Address: 5555H Load Byte Address/Byte Data Wait for end of Program (TBP, Data# Polling bit, or Toggle bit operation) Program Completed 1235 F33.0 Figure 34:Byte-Program Command Sequences Flowchart (PP Mode) (c)2011 Silicon Storage Technology, Inc. DS25086A 43 11/11 8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet Internal Timer Toggle Bit Data# Polling ByteProgram/Erase Initiated ByteProgram/Erase Initiated ByteProgram/Erase Initiated Wait TBP, TSCE, TBE, or TSE Read byte Read DQ7 Read same byte Program/Erase Completed No Is DQ7 = true data Yes No Does DQ6 match Program/Erase Completed Yes Program/Erase Completed 1235 F34.0 Figure 35:Wait Options Flowchart (PP Mode) (c)2011 Silicon Storage Technology, Inc. DS25086A 44 11/11 8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet Software Product ID Entry Command Sequence Software Product ID Exit Command Sequence Write data: AAH Address: 5555H Write data: AAH Address: 5555H Write data: F0H Address: XXH Write data: 55H Address: 2AAAH Write data: 55H Address: 2AAAH Wait TIDA Write data: 90H Address: 5555H Write data: F0H Address: 5555H Return to normal operation Wait TIDA Wait TIDA Read Software ID Return to normal operation 1235 F35.0 Figure 36:Software Product ID Command Sequences Flowchart (PP Mode) (c)2011 Silicon Storage Technology, Inc. DS25086A 45 11/11 8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet Chip-Erase Command Sequence Block-Erase Command Sequence Sector-Erase Command Sequence Write data: AAH Address: 5555H Write data: AAH Address: 5555H Write data: AAH Address: 5555H Write data: 55H Address: 2AAAH Write data: 55H Address: 2AAAH Write data: 55H Address: 2AAAH Write data: 80H Address: 5555H Write data: 80H Address: 5555H Write data: 80H Address: 5555H Write data: AAH Address: 5555H Write data: AAH Address: 5555H Write data: AAH Address: 5555H Write data: 55H Address: 2AAAH Write data: 55H Address: 2AAAH Write data: 55H Address: 2AAAH Write data: 10H Address: 5555H Write data: 50H Address: BAX Write data: 30H Address: SAX Wait TSCE Wait TBE Wait TSE Chip erased to FFH Block erased to FFH Sector erased to FFH 1235 F36.0 Figure 37:Erase Command Sequence Flowchart (PP Mode) (c)2011 Silicon Storage Technology, Inc. DS25086A 46 11/11 8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet Product Ordering Information SST 49 LF XX XX 080A XXXX - 33 XX - 4C XX - NHE XXX Environmental Attribute E1 = non-Pb Package Modifier H = 32 leads Package Type N = PLCC W = TSOP (type 1, die up, 8mm x 14mm) Operating Temperature C = Commercial = 0C to +85C Minimum Endurance 4 = 10,000 cycles Serial Access Clock Frequency 33 = 33 MHz Version Device Density 080 = 8 Mbit Voltage Range L = 3.0-3.6V 1. Environmental suffix "E" denotes non-Pb solder. SST non-Pb solder devices are "RoHS Compliant". Valid combinations for SST49LF080A SST49LF080A-33-4C-WHE SST49LF080A-33-4C-NHE Note:Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. (c)2011 Silicon Storage Technology, Inc. DS25086A 47 11/11 8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet Packaging Diagrams TOP VIEW Optional Pin #1 Identifier .048 .042 .495 .485 .453 .447 2 1 32 SIDE VIEW .112 .106 .020 R. .029 x 30 MAX. .023 .040 R. .030 .042 .048 .595 .553 .585 .547 BOTTOM VIEW .021 .013 .400 .530 BSC .490 .032 .026 .050 BSC .015 Min. .095 .075 .050 BSC .140 .125 .032 .026 Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (max/min). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches. 32-plcc-NH-3 4. Coplanarity: 4 mils. Figure 38:32-lead Plastic Lead Chip Carrier (PLCC) SST Package Code: NH (c)2011 Silicon Storage Technology, Inc. DS25086A 48 11/11 8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet 1.05 0.95 Pin # 1 Identifier 0.50 BSC 8.10 7.90 0.27 0.17 0.15 0.05 12.50 12.30 DETAIL 1.20 max. 0.70 0.50 14.20 13.80 0- 5 0.70 0.50 Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent. 32-tsop-WH-7 1mm 2. All linear dimensions are in millimeters (max/min). 3. Coplanarity: 0.1 mm 4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads. Figure 39:32-lead Thin Small Outline Package (TSOP) 8mm x 14mm SST Package Code: WH (c)2011 Silicon Storage Technology, Inc. DS25086A 49 11/11 8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet Table 26:Revision History Revision Description 00 * 01 * 02 * * * * * * * A Date Initial release (SST49LF080A previously released in data sheet S71206) Added statement that non-Pb devices are RoHS compliant to Features section Updated Surface Mount Solder Reflow Temperature information Added footnote to Product Ordering Information section Removed leaded part numbers Updated Table 5 on page 11 Applied new document format Released document under letter revision system Updated Spec number from S71235 to DS25086 Apr 2003 Jan 2006 May 2006 Nov 2011 ISBN:978-1-61341-753-9 (c) 2011 Silicon Storage Technology, Inc-a Microchip Technology Company. All rights reserved. SST, Silicon Storage Technology, the SST logo, SuperFlash, MTP, and FlashFlex are registered trademarks of Silicon Storage Technology, Inc. MPF, SQI, Serial Quad I/O, and Z-Scale are trademarks of Silicon Storage Technology, Inc. All other trademarks and registered trademarks mentioned herein are the property of their respective owners. Specifications are subject to change without notice. Refer to www.microchip.com for the most recent documentation. For the most current package drawings, please see the Packaging Specification located at http://www.microchip.com/packaging. Memory sizes denote raw storage capacity; actual usable capacity may be less. SST makes no warranty for the use of its products other than those expressly contained in the Standard Terms and Conditions of Sale. For sales office locations and information, please see www.microchip.com. Silicon Storage Technology, Inc. A Microchip Technology Company www.microchip.com (c)2011 Silicon Storage Technology, Inc. DS25086A 50 11/11