STM8S207xx STM8S208xx Performance line, 24 MHz STM8S 8-bit MCU, up to 128 KB Flash, integrated EEPROM, 10-bit ADC, timers, 2 UARTs, SPI, IC, CAN Features Core - Max fCPU: up to 24 MHz, 0 wait states @ fCPU 16 MHz - Advanced STM8 core with Harvard architecture and 3-stage pipeline - Extended instruction set - Max 20 MIPS @ 24 MHz Memories - Program: up to 128 Kbytes Flash; data retention 20 years at 55 C after 10 kcycles - Data: up to 2 Kbytes true data EEPROM; endurance 300 kcycles - RAM: up to 6 Kbytes Clock, reset and supply management - 2.95 to 5.5 V operating voltage - Low power crystal resonator oscillator - External clock input - Internal, user-trimmable 16 MHz RC - Internal low power 128 kHz RC - Clock security system with clock monitor - Wait, active-halt, & halt low power modes - Peripheral clocks switched off individually - Permanently active, low consumption power-on and power-down reset Interrupt management - Nested interrupt controller with 32 interrupts - Up to 37 external interrupts on 6 vectors Timers - 2x 16-bit general purpose timers, with 2+3 CAPCOM channels (IC, OC or PWM) - Advanced control timer: 16-bit, 4 CAPCOM channels, 3 complementary outputs, deadtime insertion and flexible synchronization - 8-bit basic timer with 8-bit prescaler - Auto wakeup timer - Window watchdog, independent watchdog February 2012 LQFP80 14x14 LQFP64 14x14 LQFP64 10x10 LQFP48 7x7 LQFP44 10x10 LQFP32 7x7 Communications interfaces - High speed 1 Mbit/s active beCAN 2.0B - UART with clock output for synchronous operation - LIN master mode - UART with LIN 2.1 compliant, master/slave modes and automatic resynchronization - SPI interface up to 10 Mbit/s - I2C interface up to 400 Kbit/s 10-bit ADC with up to 16 channels I/Os - Up to 68 I/Os on an 80-pin package including 18 high sink outputs - Highly robust I/O design, immune against current injection - Development support - Single wire interface module (SWIM) and debug module (DM) 96-bit unique ID key for each device Table 1. Device summary Part numbers: STM8S207xx STM8S207MB, STM8S207M8, STM8S207RB, STM8S207R8, STM8S207R6, STM8S207CB, STM8S207C8, STM8S207C6, STM8S207SB, STM8S207S8, STM8S207S6, STM8S207K8 STM8S207K6 Part numbers: STM8S208xx STM8S208MB, STM8S208M8, STM8S208RB, STM8S208R8, STM8S208R6, STM8S208CB, STM8S208C8, STM8S208C6, STM8S208SB, STM8S208S8, STM8S208S6 Doc ID 14733 Rev 12 1/103 www.st.com 1 Contents STM8S207xx, STM8S208xx Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 Product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5 6 4.1 Central processing unit STM8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.2 Single wire interface module (SWIM) and debug module (DM) . . . . . . . . 14 4.3 Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.4 Flash program and data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . 14 4.5 Clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.6 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.7 Watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.8 Auto wakeup counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.9 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.10 TIM1 - 16-bit advanced control timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.11 TIM2, TIM3 - 16-bit general purpose timers . . . . . . . . . . . . . . . . . . . . . . . 18 4.12 TIM4 - 8-bit basic timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.13 Analog-to-digital converter (ADC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.14 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 UART1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.14.2 UART3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.14.3 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.14.4 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.14.5 beCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.2 Alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.1 2/103 4.14.1 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Doc ID 14733 Rev 12 STM8S207xx, STM8S208xx 6.2 Contents Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7 Interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 8 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9 Unique ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 10 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 10.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 10.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 10.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 10.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 10.1.4 Typical current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 10.1.5 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 10.1.6 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 10.1.7 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 10.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 10.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 10.3.1 VCAP external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 10.3.2 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 10.3.3 External clock sources and timing characteristics . . . . . . . . . . . . . . . . . 64 10.3.4 Internal clock sources and timing characteristics . . . . . . . . . . . . . . . . . 66 10.3.5 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 10.3.6 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 10.3.7 Reset pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 10.3.8 SPI serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 10.3.9 I2C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 10.3.10 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 10.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 11 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 11.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 11.1.1 11.2 LQFP package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 11.2.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 11.2.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . . 96 Doc ID 14733 Rev 12 3/103 Contents 12 STM8S207xx, STM8S208xx STM8 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 12.1 Emulation and in-circuit debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . 97 12.2 Software tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 12.3 12.2.1 STM8 toolset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 12.2.2 C and assembly toolchains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 13 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 4/103 Doc ID 14733 Rev 12 STM8S207xx, STM8S208xx List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 STM8S20xxx performance line features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers . . . . . . . . . . . . . . . 16 TIM timer features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Legend/abbreviations for pinout table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Flash, Data EEPROM and RAM boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 I/O port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 CPU/SWIM/debug module/interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Unique ID registers (96 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Total current consumption with code execution in run mode at VDD = 5 V. . . . . . . . . . . . . 57 Total current consumption with code execution in run mode at VDD = 3.3 V . . . . . . . . . . . 58 Total current consumption in wait mode at VDD = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Total current consumption in wait mode at VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Total current consumption in active halt mode at VDD = 5 V, TA -40 to 85 C . . . . . . . . . . 60 Total current consumption in active halt mode at VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . 60 Total current consumption in halt mode at VDD = 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Total current consumption in halt mode at VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Wakeup times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Total current consumption and timing in forced reset state . . . . . . . . . . . . . . . . . . . . . . . . 62 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 HSE user external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Flash program memory/data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Output driving current (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Output driving current (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Output driving current (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 ADC accuracy with RAIN < 10 k , VDDA = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 ADC accuracy with RAIN < 10 k RAIN, VDDA = 3.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Doc ID 14733 Rev 12 5/103 List of tables Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. 6/103 STM8S207xx, STM8S208xx ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 80-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 64-pin low profile quad flat package mechanical data (14 x 14) . . . . . . . . . . . . . . . . . . . . . 90 64-pin low profile quad flat package mechanical data (10 x 10) . . . . . . . . . . . . . . . . . . . . . 91 48-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 44-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 32-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Doc ID 14733 Rev 12 STM8S207xx, STM8S208xx List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. STM8S20xxx performance line block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Flash memory organisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 LQFP 80-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 LQFP 64-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 LQFP 48-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 LQFP 44-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 LQFP 32-pin pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Supply current measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 fCPUmax versus VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Typ. IDD(RUN) vs VDD, HSI RC osc, fCPU = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Typ. IDD(WFI) vs VDD, HSI RC osc, fCPU = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 HSE external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 HSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Typical HSI frequency variation vs VDD at 4 temperatures. . . . . . . . . . . . . . . . . . . . . . . . . 66 Typical LSI frequency variation vs VDD @ 25 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Typical VIL and VIH vs VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Typical pull-up resistance vs VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Typical pull-up current vs VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Typ. VOL @ VDD = 5 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Typ. VOL @ VDD = 3.3 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Typ. VOL @ VDD = 5 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Typ. VOL @ VDD = 3.3 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Typ. VOL @ VDD = 5 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Typ. VOL @ VDD = 3.3 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Typ. VDD - VOH @ VDD = 5 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Typ. VDD - VOH @ VDD = 3.3 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Typ. VDD - VOH @ VDD = 5 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Typ. VDD - VOH @ VDD = 3.3 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Typical NRST VIL and VIH vs VDD @ 4 temperatures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Typical NRST pull-up resistance vs VDD @ 4 temperatures. . . . . . . . . . . . . . . . . . . . . . . . 76 Typical NRST pull-up current vs VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Recommended reset pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Typical application with I2C bus and timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Typical application with ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 80-pin low profile quad flat package (14 x 14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 64-pin low profile quad flat package (14 x 14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 64-pin low profile quad flat package (10 x 10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 48-pin low profile quad flat package (7 x 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 44-pin low profile quad flat package (10 x 10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 32-pin low profile quad flat package (7 x 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Doc ID 14733 Rev 12 7/103 List of figures Figure 49. 8/103 STM8S207xx, STM8S208xx STM8S207xx/208xx performance line ordering information scheme(1) . . . . . . . . . . . . . . . 99 Doc ID 14733 Rev 12 STM8S207xx, STM8S208xx 1 Introduction Introduction This datasheet contains the description of the STM8S20xxx performance line features, pinout, electrical characteristics, mechanical data and ordering information. For complete information on the STM8S microcontroller memory, registers and peripherals, please refer to the STM8S microcontroller family reference manual (RM0016). For information on programming, erasing and protection of the internal Flash memory please refer to the STM8S Flash programming manual (PM0051). For information on the debug and SWIM (single wire interface module) refer to the STM8 SWIM communication protocol and debug module user manual (UM0470). For information on the STM8 core, please refer to the STM8 CPU programming manual (PM0044). Doc ID 14733 Rev 12 9/103 Description 2 STM8S207xx, STM8S208xx Description The STM8S20xxx performance line 8-bit microcontrollers offer from 32 to 128 Kbytes Flash program memory. They are referred to as high-density devices in the STM8S microcontroller family reference manual. All devices of the STM8S20xxx performance line provide the following benefits: reduced system cost, performance robustness, short development cycles, and product longevity. The system cost is reduced thanks to an integrated true data EEPROM for up to 300 k write/erase cycles and a high system integration level with internal clock oscillators, watchdog, and brown-out reset. Device performance is ensured by 20 MIPS at 24 MHz CPU clock frequency and enhanced characteristics which include robust I/O, independent watchdogs (with a separate clock source), and a clock security system. Short development cycles are guaranteed due to application scalability across a common family product architecture with compatible pinout, memory map and and modular peripherals. Full documentation is offered with a wide choice of development tools. Product longevity is ensured in the STM8S family thanks to their advanced core which is made in a state-of-the art technology for applications with 2.95 V to 5.5 V operating supply. 10/103 Doc ID 14733 Rev 12 STM8S207xx, STM8S208xx Device Max. number of GPIOs (I/O) Ext. interrupt pins Timer CAPCOM channels Timer complementary outputs A/D converter channels HIgh sink I/Os High density Flash program memory (bytes) Data EEPROM (bytes RAM (bytes) beCAN interface STM8S20xxx performance line features Pin count Table 2. Description STM8S207MB STM8S207M8 STM8S207RB STM8S207R8 STM8S207R6 STM8S207CB STM8S207C8 STM8S207C6 STM8S207SB STM8S207S8 STM8S207S6 STM8S207K8 STM8S207K6 80 80 64 64 64 48 48 48 44 44 44 32 32 68 68 52 52 52 38 38 38 34 34 34 25 25 37 37 36 36 36 35 35 35 31 31 31 23 23 9 9 9 9 9 9 9 9 8 8 8 8 8 3 3 3 3 3 3 3 3 3 3 3 3 3 16 16 16 16 16 10 10 10 9 9 9 7 7 18 18 16 16 16 16 16 16 15 15 15 12 12 128 K 64 K 128 K 64 K 32 K 128 K 64 K 32 K 128 K 64 K 32 K 64 K 32 K 2048 2048 2048 1536 1024 2048 1536 1024 1536 1536 1024 1024 1024 6K 6K 6K 6K 6K 6K 6K 6K 6K 6K 6K 6K 6K No STM8S208MB STM8S208RB STM8S208R8 STM8S208R6 STM8S208CB STM8S208C8 STM8S208C6 STM8S208SB STM8S208S8 STM8S208S6 80 64 64 64 48 48 48 44 44 44 68 52 52 52 38 38 38 34 34 34 37 37 37 37 35 35 35 31 31 31 9 9 9 9 9 9 9 8 8 8 3 3 3 3 3 3 3 3 3 3 16 16 16 16 10 10 10 9 9 9 18 16 16 16 16 16 16 15 15 15 128 K 128 K 64 K 32 K 128 K 64 K 32 K 128 K 64 K 32 K 2048 2048 2048 2048 2048 2048 2048 1536 1536 1536 6K 6K 6K 6K 6K 6K 6K 6K 6K 6K Yes Doc ID 14733 Rev 12 11/103 Block diagram 3 STM8S207xx, STM8S208xx Block diagram Figure 1. STM8S20xxx performance line block diagram Reset block XTAL 1-24 MHz Clock controller Reset Reset RC int. 16 MHz Detector POR/PDR RC int. 128 kHz BOR Clock to peripherals and core Window WDG STM8 core Independent WDG high density program Flash 400 Kbit/s I2C 10 Mbit/s SPI LIN master SPI emul. UART1 Master/slave autosynchro UART3 1 Mbit/s beCAN 16 channels ADC2 1/2/4 kHz beep Up to 128 Kbytes Debug/SWIM Up to 2 Kbytes data EEPROM Address and data bus Single wire debug interf. Boot ROM 16-bit advanced control timer (TIM1) 16-bit general purpose timers (TIM2, TIM3) 8-bit basic timer (TIM4) Beeper AWU timer 1. Legend: ADC: Analog-to-digital converter beCAN: Controller area network BOR: Brownout reset IC: Inter-integrated circuit multimaster interface Independent WDG: Independent watchdog POR/PDR: Power on reset / power down reset SPI: Serial peripheral interface SWIM: Single wire interface module UART: Universal asynchronous receiver transmitter Window WDG: Window watchdog 12/103 Up to 6 Kbytes RAM Doc ID 14733 Rev 12 Up to 4 CAPCOM channels + 3 complementary outputs Up to 5 CAPCOM channels STM8S207xx, STM8S208xx 4 Product overview Product overview The following section intends to give an overview of the basic features of the STM8S20xxx performance line functional modules and peripherals. For more detailed information please refer to the corresponding family reference manual (RM0016). 4.1 Central processing unit STM8 The 8-bit STM8 core is designed for code efficiency and performance. It contains 6 internal registers which are directly addressable in each execution context, 20 addressing modes including indexed indirect and relative addressing and 80 instructions. Architecture and registers Harvard architecture 3-stage pipeline 32-bit wide program memory bus - single cycle fetching for most instructions X and Y 16-bit index registers - enabling indexed addressing modes with or without offset and read-modify-write type data manipulations 8-bit accumulator 24-bit program counter - 16-Mbyte linear memory space 16-bit stack pointer - access to a 64 K-level stack 8-bit condition code register - 7 condition flags for the result of the last instruction Addressing 20 addressing modes Indexed indirect addressing mode for look-up tables located anywhere in the address space Stack pointer relative addressing mode for local variables and parameter passing Instruction set 80 instructions with 2-byte average instruction size Standard data movement and logic/arithmetic functions 8-bit by 8-bit multiplication 16-bit by 8-bit and 16-bit by 16-bit division Bit manipulation Data transfer between stack and accumulator (push/pop) with direct stack access Data transfer using the X and Y registers or direct memory-to-memory transfers Doc ID 14733 Rev 12 13/103 Product overview 4.2 STM8S207xx, STM8S208xx Single wire interface module (SWIM) and debug module (DM) The single wire interface module and debug module permits non-intrusive, real-time incircuit debugging and fast memory programming. SWIM Single wire interface module for direct access to the debug module and memory programming. The interface can be activated in all device operation modes. The maximum data transmission speed is 145 bytes/ms. Debug module The non-intrusive debugging module features a performance close to a full-featured emulator. Beside memory and peripherals, also CPU operation can be monitored in realtime by means of shadow registers. 4.3 4.4 R/W to RAM and peripheral registers in real-time R/W access to all resources by stalling the CPU Breakpoints on all program-memory instructions (software breakpoints) Two advanced breakpoints, 23 predefined configurations Interrupt controller Nested interrupts with three software priority levels 32 interrupt vectors with hardware priority Up to 37 external interrupts on six vectors including TLI Trap and reset interrupts Flash program and data EEPROM memory Up to 128 Kbytes of high density Flash program single voltage Flash memory Up to 2K bytes true data EEPROM Read while write: Writing in data memory possible while executing code in program memory. User option byte area Write protection (WP) Write protection of Flash program memory and data EEPROM is provided to avoid unintentional overwriting of memory that could result from a user software malfunction. There are two levels of write protection. The first level is known as MASS (memory access security system). MASS is always enabled and protects the main Flash program memory, data EEPROM and option bytes. To perform in-application programming (IAP), this write protection can be removed by writing a MASS key sequence in a control register. This allows the application to write to data EEPROM, modify the contents of main program memory or the device option bytes. A second level of write protection, can be enabled to further protect a specific area of memory known as UBC (user boot code). Refer to Figure 2. 14/103 Doc ID 14733 Rev 12 STM8S207xx, STM8S208xx Product overview The size of the UBC is programmable through the UBC option byte (Table 13.), in increments of 1 page (512 bytes) by programming the UBC option byte in ICP mode. This divides the program memory into two areas: Main program memory: Up to 128 Kbytes minus UBC User-specific boot code (UBC): Configurable up to 128 Kbytes The UBC area remains write-protected during in-application programming. This means that the MASS keys do not unlock the UBC area. It protects the memory used to store the boot program, specific code libraries, reset and interrupt vectors, the reset routine and usually the IAP and communication routines. Figure 2. Flash memory organisation Data EEPROM memory Data memory area (2 Kbytes) Option bytes UBC area Remains write protected during IAP Programmable area from 1 Kbyte (2 first pages) up to 128 Kbytes (1 page steps) Up to 128 Kbytes Flash program memory Program memory area Write access possible for IAP Read-out protection (ROP) The read-out protection blocks reading and writing the Flash program memory and data EEPROM memory in ICP mode (and debug mode). Once the read-out protection is activated, any attempt to toggle its status triggers a global erase of the program and data memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller. Doc ID 14733 Rev 12 15/103 Product overview 4.5 STM8S207xx, STM8S208xx Clock controller The clock controller distributes the system clock (fMASTER) coming from different oscillators to the core and the peripherals. It also manages clock gating for low power modes and ensures clock robustness. Features Clock prescaler: To get the best compromise between speed and current consumption the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler. Safe clock switching: Clock sources can be changed safely on the fly in run mode through a configuration register. The clock signal is not switched until the new clock source is ready. The design guarantees glitch-free switching. Clock management: To reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory. Master clock sources: Four different clock sources can be used to drive the master clock: - 1-24 MHz high-speed external crystal (HSE) - Up to 24 MHz high-speed user-external clock (HSE user-ext) - 16 MHz high-speed internal RC oscillator (HSI) - 128 kHz low-speed internal RC (LSI) Startup clock: After reset, the microcontroller restarts by default with an internal 2 MHz clock (HSI/8). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts. Clock security system (CSS): This feature can be enabled by software. If an HSE clock failure occurs, the internal RC (16 MHz/8) is automatically selected by the CSS and an interrupt can optionally be generated. Configurable main clock output (CCO): This outputs an external clock for use by the application. Table 3. 16/103 Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers Bit Peripheral clock Bit Peripheral clock Bit Peripheral clock Bit Peripheral clock PCKEN17 TIM1 PCKEN13 UART3 PCKEN27 beCAN PCKEN23 ADC PCKEN16 TIM3 PCKEN12 UART1 PCKEN26 Reserved PCKEN22 AWU PCKEN15 TIM2 PCKEN11 SPI PCKEN25 Reserved PCKEN21 Reserved PCKEN14 TIM4 PCKEN10 I2C PCKEN24 Reserved PCKEN20 Reserved Doc ID 14733 Rev 12 STM8S207xx, STM8S208xx 4.6 Product overview Power management For efficent power management, the application can be put in one of four different low-power modes. You can configure each mode to obtain the best compromise between lowest power consumption, fastest start-up time and available wakeup sources. 4.7 Wait mode: In this mode, the CPU is stopped, but peripherals are kept running. The wakeup is performed by an internal or external interrupt or reset. Active halt mode with regulator on: In this mode, the CPU and peripheral clocks are stopped. An internal wakeup is generated at programmable intervals by the auto wake up unit (AWU). The main voltage regulator is kept powered on, so current consumption is higher than in active halt mode with regulator off, but the wakeup time is faster. Wakeup is triggered by the internal AWU interrupt, external interrupt or reset. Active halt mode with regulator off: This mode is the same as active halt with regulator on, except that the main voltage regulator is powered off, so the wake up time is slower. Halt mode: In this mode the microcontroller uses the least power. The CPU and peripheral clocks are stopped, the main voltage regulator is powered off. Wakeup is triggered by external event or reset. Watchdog timers The watchdog system is based on two independent timers providing maximum security to the applications. Activation of the watchdog timers is controlled by option bytes or by software. Once activated, the watchdogs cannot be disabled by the user program without performing a reset. Window watchdog timer The window watchdog is used to detect the occurrence of a software fault, usually generated by external interferences or by unexpected logical conditions, which cause the application program to abandon its normal sequence. The window function can be used to trim the watchdog behavior to match the application perfectly. The application software must refresh the counter before time-out and during a limited time window. A reset is generated in two situations: 1. Timeout: At 16 MHz CPU clock the time-out period can be adjusted between 75 s up to 64 ms. 2. Refresh out of window: The downcounter is refreshed before its value is lower than the one stored in the window register. Doc ID 14733 Rev 12 17/103 Product overview STM8S207xx, STM8S208xx Independent watchdog timer The independent watchdog peripheral can be used to resolve processor malfunctions due to hardware or software failures. It is clocked by the 128 kHZ LSI internal RC clock source, and thus stays active even in case of a CPU clock failure The IWDG time base spans from 60 s to 1 s. 4.8 4.9 Auto wakeup counter Used for auto wakeup from active halt mode Clock source: Internal 128 kHz internal low frequency RC oscillator or external clock LSI clock can be internally connected to TIM3 input capture channel 1 for calibration Beeper The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in the range of 1, 2 or 4 kHz. 4.10 TIM1 - 16-bit advanced control timer This is a high-end timer designed for a wide range of control applications. With its complementary outputs, dead-time control and center-aligned PWM capability, the field of applications is extended to motor control, lighting and half-bridge driver 4.11 18/103 16-bit up, down and up/down autoreload counter with 16-bit prescaler Four independent capture/compare channels (CAPCOM) configurable as input capture, output compare, PWM generation (edge and center aligned mode) and single pulse mode output Synchronization module to control the timer with external signals Break input to force the timer outputs into a defined state Three complementary outputs with adjustable dead time Encoder mode Interrupt sources: 3 x input capture/output compare, 1 x overflow/update, 1 x break TIM2, TIM3 - 16-bit general purpose timers 16-bit autoreload (AR) up-counter 15-bit prescaler adjustable to fixed power of 2 ratios 1...32768 Timers with 3 or 2 individually configurable capture/compare channels PWM mode Interrupt sources: 2 or 3 x input capture/output compare, 1 x overflow/update Doc ID 14733 Rev 12 STM8S207xx, STM8S208xx 4.12 Table 4. Product overview TIM4 - 8-bit basic timer 8-bit autoreload, adjustable prescaler ratio to any power of 2 from 1 to 128 Clock source: CPU clock Interrupt source: 1 x overflow/update TIM timer features Timer Counter size (bits) Prescaler TIM1 16 Any integer from 1 to 65536 Up/down 4 3 Yes TIM2 16 Any power of 2 from 1 to 32768 Up 3 0 No TIM3 16 Any power of 2 from 1 to 32768 Up 2 0 No TIM4 8 Any power of 2 from 1 to 128 Up 0 0 No Counting CAPCOM Complem. Ext. mode trigger channels outputs Timer synchronization/ chaining No 4.13 Analog-to-digital converter (ADC2) STM8S20xxx performance line products contain a 10-bit successive approximation A/D converter (ADC2) with up to 16 multiplexed input channels and the following main features: 4.14 Input voltage range: 0 to VDDA Dedicated voltage reference (VREF) pins available on 80 and 64-pin devices Conversion time: 14 clock cycles Single and continuous modes External trigger input Trigger from TIM1 TRGO End of conversion (EOC) interrupt Communication interfaces The following communication interfaces are implemented: UART1: Full feature UART, SPI emulation, LIN2.1 master capability, Smartcard mode, IrDA mode, single wire mode. UART3: Full feature UART, LIN2.1 master/slave capability SPI : Full and half-duplex, 10 Mbit/s IC: Up to 400 Kbit/s beCAN (rev. 2.0A,B) - 3 Tx mailboxes - up to 1 Mbit/s Doc ID 14733 Rev 12 19/103 Product overview 4.14.1 STM8S207xx, STM8S208xx UART1 Main features One Mbit/s full duplex SCI SPI emulation High precision baud rate generator Smartcard emulation IrDA SIR encoder decoder LIN master mode Single wire half duplex mode Asynchronous communication (UART mode) Full duplex communication - NRZ standard format (mark/space) Programmable transmit and receive baud rates up to 1 Mbit/s (fCPU/16) and capable of following any standard baud rate regardless of the input frequency Separate enable bits for transmitter and receiver Two receiver wakeup modes: - Address bit (MSB) - Idle line (interrupt) Transmission error detection with interrupt generation Parity control Synchronous communication Full duplex synchronous transfers SPI master operation 8-bit data communication Maximum speed: 1 Mbit/s at 16 MHz (fCPU/16) LIN master mode 4.14.2 Emission: Generates 13-bit synch break frame Reception: Detects 11-bit break frame UART3 Main features 20/103 1 Mbit/s full duplex SCI LIN master capable High precision baud rate generator Doc ID 14733 Rev 12 STM8S207xx, STM8S208xx Product overview Asynchronous communication (UART mode) Full duplex communication - NRZ standard format (mark/space) Programmable transmit and receive baud rates up to 1 Mbit/s (fCPU/16) and capable of following any standard baud rate regardless of the input frequency Separate enable bits for transmitter and receiver Two receiver wakeup modes: - Address bit (MSB) - Idle line (interrupt) Transmission error detection with interrupt generation Parity control LIN master capability Emission: Generates 13-bit synch break frame Reception: Detects 11-bit break frame LIN slave mode 4.14.3 Autonomous header handling - one single interrupt per valid message header Automatic baud rate synchronization - maximum tolerated initial clock deviation 15 % Synch delimiter checking 11-bit LIN synch break detection - break detection always active Parity check on the LIN identifier field LIN error management Hot plugging support SPI Maximum speed: 10 Mbit/s (fMASTER/2) both for master and slave Full duplex synchronous transfers Simplex synchronous transfers on two lines with a possible bidirectional data line Master or slave operation - selectable by hardware or software CRC calculation 1 byte Tx and Rx buffer Slave/master selection input pin Doc ID 14733 Rev 12 21/103 Product overview 4.14.4 I2C 4.14.5 STM8S207xx, STM8S208xx I2C master features: - Clock generation - Start and stop generation I2C slave features: - Programmable I2C address detection - Stop bit detection Generation and detection of 7-bit/10-bit addressing and general call Supports different communication speeds: - Standard speed (up to 100 kHz) - Fast speed (up to 400 kHz) beCAN The beCAN controller (basic enhanced CAN), interfaces the CAN network and supports the CAN protocol version 2.0A and B. It has been designed to manage a high number of incoming messages efficiently with a minimum CPU load. For safety-critical applications the beCAN controller provides all hardware functions to support the CAN time triggered communication option (TTCAN). The maximum transmission speed is 1 Mbit. Transmission Three transmit mailboxes Configurable transmit priority by identifier or order request Time stamp on SOF transmission Reception 8-, 11- and 29-bit ID One receive FIFO (3 messages deep) Software-efficient mailbox mapping at a unique address space FMI (filter match index) stored with message Configurable FIFO overrun Time stamp on SOF reception Six filter banks, 2 x 32 bytes (scalable to 4 x 16-bit) each, enabling various masking configurations, such as 12 filters for 29-bit ID or 48 filters for 11-bit ID Filtering modes: 22/103 - Mask mode permitting ID range filtering - ID list mode Time triggered communication option - Disable automatic retransmission mode - 16-bit free running timer - Configurable timer resolution - Time stamp sent in last two data bytes Doc ID 14733 Rev 12 STM8S207xx, STM8S208xx Pinouts and pin description 5 Pinouts and pin description 5.1 Package pinouts LQFP 80-pin pinout 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 PD7/TLI PD6/UART3_RX PD5/UART3_TX PD4 (HS)/TIM2_CH1 [BEEP] PD3 (HS)/TIM2_CH2 [ADC_ETR] PD2 (HS)/TIM3_CH1 [TIM2_CH3] PD1 (HS)/SWIM PD0 (HS)/TIM3_CH2 [TIM1_BKIN] [CLK_CCO] PI7 PI6 PE0 (HS)/CLK_CCO PE1(T)/I2C_SCL PE2 (T]/I 2C_SDA PE3/TIM1_BKIN PE4 PG7 PG6 PG5 PI5 PI4 Figure 3. 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 PI3 PI2 PI1 PI0 PG4 PG3 PG2 PG1/CAN_RX PG0/CAN_TX PC7 (HS)/SPI_MISO PC6 (HS)/SPI_MOSI VDDIO_2 VSSIO_2 PC5 (HS)/SPI_SCK PC4 (HS)/TIM1_CH4 PC3 (HS)/TIM1_CH3 PC2 (HS)/TIM1_CH2 PC1 (HS)/TIM1_CH1 PC0/ADC_ETR PE5/SPI_NSS AIN11/PF3 VREF+ VDDA VSSA VREFAIN10/PF0 AIN7/PB7 AIN6/PB6 [I2C_SDA] AIN5/PB5 [I2C_SCL] AIN4/PB4 [TIM1_ETR] AIN3/PB3 [TIM1_CH3N] AIN2/PB2 [TIM1_CH2N] AIN1/PB1 [TIM1_CH1N] AIN0/PB0 TIM1_ETR/PH4 TIM1_CH3N/PH5 TIM1_CH2N/PH6 TIM1_CH1N/PH7 AIN8/PE7 AIN9/PE6 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 NRST OSCIN/PA1 OSCOUT/PA2 VSSIO_1 VSS VCAP VDD VDDIO_1 [TIM3_CH1] TIM2_CH3/PA3 UART1_RX/ (HS) PA4 UART1_TX/ (HS) PA5 UART1_CK/ (HS) PA6 (HS) PH0 (HS) PH1 PH2 PH3 AIN15/PF7 AIN14/PF6 AIN13/PF5 AIN12/PF4 1. (HS) high sink capability. 2. (T) True open drain (P-buffer and protection diode to VDD not implemented). 3. [ ] alternate function remapping option (If the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function). 4. CAN_RX and CAN_TX is available on STM8S208xx devices only. Doc ID 14733 Rev 12 23/103 Pinouts and pin description LQFP 64-pin pinout PD7/TLI PD6/UART3_RX PD5/UART3_TX PD4 (HS)/TIM2_CH1 [BEEP] PD3 (HS)/TIM2_CH2[ADC_ETR] PD2 (HS)/TIM3_CH1[TIM2_CH3] PD1 (HS)/SWIM PD0 (HS)/TIM3_CH2 [TIM1_BKIN] [CLK_CCO] PE0 (HS)/CLK_CCO PE1 (T)/I2C_SCL PE2 (T)/I2C_SDA PE3/TIM1_BKIN PE4 PG7 PG6 PG5 Figure 4. STM8S207xx, STM8S208xx 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 8 40 9 39 10 38 11 37 12 36 13 35 14 34 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PI0 PG4 PG3 PG2 PG1/CAN_RX PG0/CAN_TX PC7 (HS)/SPI_MISO PC6 (HS)/SPI_MOSI VDDIO_2 VSSIO_2 PC5 (HS)/SPI_SCK PC4 (HS)/TIM1_CH4 PC3 (HS)/TIM1_CH3 PC2 (HS)/TIM1_CH2 PC1 (HS)/TIM1_CH1 PE5/SPI_NSS AIN11/PF3 VREF+ VDDA VSSA VREFAIN10/PF0 AIN7/PB7 AIN6/PB6 [I2C_SDA] AIN5/PB5 [I2C_SCL] AIN4/PB4 [TIM1_ETR] AIN3/PB3 [TIM1_CH3N] AIN2/PB2 [TIM1_CH2N] AIN1/PB1 [TIM1_CH1N] AIN0/PB0 AIN8/PE7 AIN9/PE6 NRST OSCIN/PA1 OSCOUT/PA2 VSSIO_1 VSS VCAP VDD VDDIO_1 [TIM3_CH1] TIM2_CH3/PA3 UART1_RX/ (HS) PA4 UART1_TX/ (HS) PA5 UART1_CK/ (HS) PA6 AIN15/PF7 AIN14/PF6 AIN13/PF5 AIN12/PF4 24/103 1. (HS) high sink capability. 2. (T) True open drain (P-buffer and protection diode to VDD not implemented). 3. [ ] alternate function remapping option (If the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function). 4. CAN_RX and CAN_TX is available on STM8S208xx devices only. Doc ID 14733 Rev 12 STM8S207xx, STM8S208xx LQFP 48-pin pinout PD7/TLI PD6/UART3_RX PD5/UART3_TX PD4 (HS)/TIM2_CH1 [BEEP] PD3 (HS)/TIM2_CH2 [ADC_ETR] PD2 (HS)/TIM3_CH1 [TIM2_CH3] PD1 (HS)/SWIM PD0 (HS)/TIM3_CH2 [TIM1_BKIN] [CLK_CCO] PE0 (HS)/CLK_CCO PE1 (T)/I2C_SCL PE2 (T)/I2C_SDA PE3/TIM1_BKIN Figure 5. Pinouts and pin description 48 47 46 45 44 43 42 41 40 39 38 37 36 1 2 35 34 3 33 4 32 5 31 6 30 7 29 8 28 9 27 10 26 11 25 12 13 14 15 16 17 18 19 20 21 2223 24 PG1/CAN_RX PG0/CAN_TX PC7 (HS)/SPI_MISO PC6 (HS)/SPI_MOSI VDDIO_2 VSSIO_2 PC5 (HS)/SPI_SCK PC4 (HS)/TIM1_CH4 PC3 (HS)/TIM1_CH3 PC2 (HS)/TIM1_CH2 PC1 (HS)/TIM1_CH1 PE5/SPI_NSS VDDA VSSA AIN7/PB7 AIN6/PB6 [I2C_SDA] AIN5/PB5 [I2C_SCL] AIN4/PB4 [TIM1_ETR/AIN3/PB3 [TIM1_CH3N] AIN2/PB2 [TIM1_CH2N] AIN1/PB1 [TIM1_CH1N] AIN0/PB0 AIN8/PE7 AIN9/PE6 NRST OSCIN/PA1 OSCOUT/PA2 VSSIO_1 VSS VCAP VDD VDDIO_1 [TIM3_CH1] TIM2_CH3/PA3 UART1_RX/(HS) PA4 UART1_TX/(HS) PA5 UART1_CK/(HS) PA6 1. (HS) high sink capability. 2. (T) True open drain (P-buffer and protection diode to VDD not implemented). 3. [ ] alternate function remapping option (If the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function). 4. CAN_RX and CAN_TX is available on STM8S208xx devices only. Doc ID 14733 Rev 12 25/103 Pinouts and pin description LQFP 44-pin pinout PD7/TLI [TIM1_CH4] PD6/UART3_RX PD5/UART3_TX PD4 (HS)/TIM2_CH1[BEEP] PD3 (HS)/TIM2_CH2 [ADC_ETR] PD2 (HS)/TIM3_CH1 [TIM2_CH3] PD1 (HS)/SWIM PD0 (HS)/TIM3_CH2 [TIM1_BKIN] [CLK_CCO] PE0 (HS)/CLK_CCO PE1 (T)/I2C_SCL PE2 (T)/I2C_SDA Figure 6. STM8S207xx, STM8S208xx 44 43 42 41 40 39 38 37 36 35 34 1 33 2 32 3 31 4 30 5 29 6 28 7 27 8 26 9 25 10 24 11 23 12 13 14 15 16 17 18 19 20 21 22 PG1/CAN_RX PG0/CAN_TX PC7 (HS)/SPI_MISO PC6 (HS)/SPI_MOSI VDDIO_2 VSSIO_2 PC5 (HS)/SPI_SCK PC3 (HS)/TIM1_CH3 PC2 (HS)/TIM1_CH2 PC1 (HS)/TIM1_CH1 PE5/SPI_NSS VDDA VSSA AIN7/PB7 AIN6/PB6 [I2C_SDA] AIN5/PB5 [I2C_SCL] AIN4/PB4 [TIM1_ETR] AIN3/PB3 [TIM1_CH3N] AIN2/PB2 [TIM1_CH2N] AIN1/PB1 (TIM1_CH1N] AIN0/PB0 AIN9/PE6 NRST OSCIN/PA1 OSCOUT/PA2 VSSIO_1 VSS VCAP VDD VDDIO_1 UART1_RX/ UART1_TX/ UART1_CK/ 26/103 1. (HS) high sink capability. 2. (T) True open drain (P-buffer and protection diode to VDD not implemented). 3. [ ] alternate function remapping option (If the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function). 4. CAN_RX and CAN_TX is available on STM8S208xx devices only. Doc ID 14733 Rev 12 STM8S207xx, STM8S208xx LQFP 32-pin pinout PD7/TLI PD6/UART3_RX PD5/UART3_TX PD4 (HS)/TIM2_CH1 [BEEP] PD3 (HS)/TIM2_CH2 [ADC_ETR] PD2 (HS)/TIM3_CH1[TIM2_CH3] PD1 (HS)/SWIM PD0 (HS)/TIM3_CH2 [TIM1_BKIN] [CLK_CCO] Figure 7. Pinouts and pin description 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 9 10 11 12 13 14 1516 PC7 (HS)/SPI_MISO PC6 (HS)/SPI_MOSI PC5 (HS)/SPI_SCK PC4 (HS)/TIM1_CH4 PC3 (HS)/TIM1_CH3 PC2 (HS)/TIM1_CH2 PC1 (HS)/TIM1_CH1 PE5/SPI_NSS VDDA VSSA [I2C_SDA] AIN5/PB5 [I2C_SCL] AIN4/PB4 [TIM1_ETR] AIN3/PB3 [TIM1_CH3N] AIN2/PB2 [TIM1_CH2N] AIN1/PB1 [TIM1_CH1N] AIN0/PB0 NRST OSCIN/PA1 OSCOUT/PA2 VSS VCAP VDD VDDIO AIN12/PF4 1. (HS) high sink capability. 2. [ ] alternate function remapping option (If the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function). Doc ID 14733 Rev 12 27/103 Pinouts and pin description Table 5. STM8S207xx, STM8S208xx Legend/abbreviations for pinout table Type I= Input, O = Output, S = Power supply Level Input CM = CMOS Output HS = High sink Output speed O1 = Slow (up to 2 MHz) O2 = Fast (up to 10 MHz) O3 = Fast/slow programmability with slow as default state after reset O4 = Fast/slow programmability with fast as default state after reset Port and control Input configuration Output Reset state T = True open drain, OD = Open drain, PP = Push pull Bold X (pin state after internal reset release) Unless otherwise specified, the pin state is the same during the reset phase and after the internal reset release. Output 1 NRST I/O X 2 2 2 2 2 PA1/OSCIN I/O X X 3 3 3 3 3 PA2/OSCOUT I/O X X 4 4 4 4 - VSSIO_1 S I/O ground 5 5 5 5 4 VSS S Digital ground 6 6 6 6 5 VCAP S 1.8 V regulator capacitor 7 7 7 7 6 VDD S Digital power supply 8 8 8 8 7 VDDIO_1 S I/O power supply 9 9 9 - - PA3/TIM2_CH3 I/O X X X 10 10 10 9 - PA4/UART1_RX(1) I/O X X X HS O3 X X Port A4 UART1 receive 11 11 11 10 - PA5/UART1_TX I/O X X X HS O3 X X Port A5 12 12 12 11 - PA6/UART1_CK I/O X X X HS O3 X UART1 X Port A6 synchronous clock 13 - - - - PH0 I/O X X HS O3 X X Port H0 14 - - - - PH1 I/O X X HS O3 X X Port H1 15 - - - - PH2 I/O X X O1 X X Port H2 28/103 PP 1 OD LQFP32 1 Speed LQFP44 1 wpu LQFP48 1 Pin name floating LQFP64 Default alternate function LQFP80 High sink Input Type Pin number Main function (after reset) Pin description Ext. interrupt Table 6. float = floating, wpu = weak pull-up Alternate function after remap [option bit] Reset X O1 X X Port A1 Resonator/ crystal in O1 X X Port A2 Resonator/ crystal out O1 X Doc ID 14733 Rev 12 X Port A3 Timer 2 channel3 UART1 transmit TIM3_CH1 [AFR1] STM8S207xx, STM8S208xx PP OD - PH3 Speed - High sink LQFP32 - Output Ext. interrupt LQFP44 - floating LQFP48 16 Pin name Type LQFP64 Input LQFP80 Pin number Main function (after reset) Pin description (continued) wpu Table 6. Pinouts and pin description Default alternate function I/O X X O1 X X Port H3 17 13 - - - PF7/AIN15 I/O X X O1 X X Port F7 Analog input 15 18 14 - - - PF6/AIN14 I/O X X O1 X X Port F6 Analog input 14 19 15 - - - PF5/AIN13 I/O X X O1 X X Port F5 Analog input 13 20 16 - - 8 PF4/AIN12 I/O X X O1 X X Port F4 Analog input 12 21 17 - - - PF3/AIN11 I/O X X O1 X X Port F3 Analog input 11 22 18 - - - VREF+ S ADC positive reference voltage 9 VDDA S Analog power supply 24 20 14 13 10 VSSA S Analog ground 25 21 - - - VREF- S ADC negative reference voltage 26 22 - - - PF0/AIN10 I/O X X 27 23 15 14 - PB7/AIN7 I/O X X 28 24 16 15 - PB6/AIN6 I/O X 29 25 17 16 11 PB5/AIN5 23 19 13 12 Analog input 10 O1 X X X O1 X X Port B7 Analog input 7 X X O1 X X Port B6 Analog input 6 I/O X X X O1 X X Port B5 Analog input 5 I2C_SDA [AFR6] 30 26 18 17 12 PB4/AIN4 I/O X X X O1 X X Port B4 Analog input 4 I2C_SCL [AFR6] 31 27 19 18 13 PB3/AIN3 I/O X X X O1 X X Port B3 Analog input 3 TIM1_ETR [AFR5] 32 28 20 19 14 PB2/AIN2 I/O X X X O1 X X Port B2 Analog input 2 TIM1_ CH3N [AFR5] 33 29 21 20 15 PB1/AIN1 I/O X X X O1 X X Port B1 Analog input 1 TIM1_ CH2N [AFR5] 34 30 22 21 16 PB0/AIN0 I/O X X X O1 X X Port B0 Analog input 0 TIM1_ CH1N [AFR5] Doc ID 14733 Rev 12 Port F0 Alternate function after remap [option bit] 29/103 Pinouts and pin description Output - PH4/TIM1_ETR I/O X X O1 X X Port H4 36 - - - - PH5/ TIM1_CH3N I/O X X O1 X Timer 1 X Port H5 inverted channel 3 37 - - - - PH6/ TIM1_CH2N I/O X X O1 X Timer 1 X Port H6 inverted channel 2 38 - - - - PH7/ TIM1_CH1N I/O X X O1 X Timer 1 X Port H7 inverted channel 2 - - PE7/AIN8 I/O X X X O1 X X Port E7 Analog input 8 - PE6/AIN9 I/O X X X O1 X X Port E6 Analog input 9 41 33 25 23 17 PE5/SPI_NSS I/O X X X O1 X X SPI Port E5 master/slave select 42 - PC0/ADC_ETR I/O X X X O1 X X Port C0 ADC trigger input 43 34 26 24 18 PC1/TIM1_CH1 I/O X X X HS O3 X X Port C1 Timer 1 channel 1 44 35 27 25 19 PC2/TIM1_CH2 I/O X X X HS O3 X X Port C2 Timer 1channel 2 45 36 28 26 20 PC3/TIM1_CH3 I/O X X X HS O3 X X Port C3 Timer 1 channel 3 46 37 29 I/O X X X HS O3 X X Port C4 Timer 1 channel 4 I/O X X X HS O3 X X Port C5 SPI clock 39 31 23 40 32 24 22 - - - - 21 PC4/TIM1_CH4 47 38 30 27 22 PC5/SPI_SCK PP - OD LQFP32 - Speed LQFP44 - wpu LQFP48 35 Pin name floating LQFP64 Default alternate function LQFP80 High sink Input Type Pin number Main function (after reset) Pin description (continued) Ext. interrupt Table 6. STM8S207xx, STM8S208xx Timer 1 trigger input 48 39 31 28 - VSSIO_2 S I/O ground 49 40 32 29 - VDDIO_2 S I/O power supply 50 41 33 30 23 PC6/SPI_MOSI I/O X X X HS O3 X SPI master X Port C6 out/ slave in 51 42 34 31 24 PC7/SPI_MISO I/O X X X HS O3 X X Port C7 SPI master in/ slave out 52 43 35 32 - PG0/CAN_TX(2) I/O X X O1 X X Port G0 beCAN transmit 53 44 36 33 - PG1/CAN_RX(2) I/O X X O1 X X Port G1 beCAN receive 30/103 Doc ID 14733 Rev 12 Alternate function after remap [option bit] STM8S207xx, STM8S208xx Default alternate function I/O X X O1 X X Port G2 55 46 - - - PG3 I/O X X O1 X X Port G3 56 47 - - - PG4 I/O X X O1 X X Port G4 57 48 - - - PI0 I/O X X O1 X X Port I0 58 - - - - PI1 I/O X X O1 X X Port I1 59 - - - - PI2 I/O X X O1 X X Port I2 60 - - - - PI3 I/O X X O1 X X Port I3 61 - - - - PI4 I/O X X O1 X X Port I4 62 - - - - PI5 I/O X X O1 X X Port I5 63 49 - - - PG5 I/O X X O1 X X Port G5 64 50 - - - PG6 I/O X X O1 X X Port G6 65 51 - - - PG7 I/O X X O1 X X Port G7 66 52 - - - PE4 I/O X X X O1 X X Port E4 - - PE3/TIM1_BKIN I/O X X X O1 X X Port E3 68 54 38 34 - PE2/I2C_SDA I/O X X O1 T(3) Port E2 I2C data 69 55 39 35 - PE1/I2C_SCL I/O X X O1 T(3) Port E1 I2C clock 70 56 40 36 - PE0/CLK_CCO I/O X X X HS O3 X X Port E0 71 - - - - PI6 I/O X X O1 X X Port I6 72 - - - - PI7 I/O X X O1 X X Port I7 67 53 37 PP - PG2 OD - Speed - wpu 54 45 Pin name floating LQFP32 High sink Output LQFP44 Type Input LQFP48 LQFP64 LQFP80 Pin number Main function (after reset) Pin description (continued) Ext. interrupt Table 6. Pinouts and pin description Alternate function after remap [option bit] Timer 1 break input Configurable clock output TIM1_BKIN [AFR3]/ CLK_CCO [AFR2] 73 57 41 37 25 PD0/TIM3_CH2 I/O X X X HS O3 X Timer 3 X Port D0 channel 2 74 58 42 38 26 PD1/SWIM(4) I/O X X X HS O4 X X Port D1 SWIM data interface 75 59 43 39 27 PD2/TIM3_CH1 I/O X X X HS O3 X X Port D2 Timer 3 channel 1 TIM2_CH3 [AFR1] 76 60 44 40 28 PD3/TIM2_CH2 I/O X X X HS O3 X X Port D3 Timer 2 channel 2 ADC_ETR [AFR0] PD4/TIM2_CH1/B I/O X EEP X X HS O3 X X Port D4 Timer 2 channel 1 BEEP output [AFR7] X X X Port D5 UART3 data transmit 77 61 45 41 29 78 62 46 42 30 PD5/ UART3_TX I/O X O1 X Doc ID 14733 Rev 12 31/103 Pinouts and pin description PD6/ UART3_RX(1) 80 64 48 44 32 PD7/TLI X Port D6 UART3 data receive I/O X X X O1 X X Port D7 Top level interrupt PP O1 X OD X Speed X floating I/O X Type Ext. interrupt 79 63 47 43 31 Pin name Output wpu Input LQFP32 LQFP44 LQFP48 LQFP64 LQFP80 Pin number Main function (after reset) Pin description (continued) High sink Table 6. STM8S207xx, STM8S208xx Default alternate function Alternate function after remap [option bit] TIM1_CH4 [AFR4](5) 1. The default state of UART1_RX and UART3_RX pins is controlled by the ROM bootloader. These pins are pulled up as part of the bootloader activation process and returned to the floating state before a return from the bootloader. 2. The beCAN interface is available on STM8S208xx devices only 3. In the open-drain output column, `T' defines a true open-drain I/O (P-buffer, weak pull-up, and protection diode to VDD are not implemented). 4. The PD1 pin is in input pull-up during the reset phase and after the internal reset release. 5. Available in 44-pin package only. On other packages, the AFR4 bit is reserved and must be kept at 0. 5.2 Alternate function remapping As shown in the rightmost column of the pin description table, some alternate functions can be remapped at different I/O ports by programming one of eight AFR (alternate function remap) option bits. Refer to Section 8: Option bytes on page 46. When the remapping option is active, the default alternate function is no longer available. To use an alternate function, the corresponding peripheral must be enabled in the peripheral registers. Alternate function remapping does not effect GPIO capabilities of the I/O ports (see the GPIO section of the family reference manual, RM0016). 32/103 Doc ID 14733 Rev 12 STM8S207xx, STM8S208xx Memory and register map 6 Memory and register map 6.1 Memory map Figure 8. Memory map 0x00 0000 0x00 17FF 0x00 1800 RAM (up to 6 Kbytes) 1024 bytes stack Reserved 0x00 3FFF 0x00 4000 Up to 2 Kbytes data EEPROM 0x00 47FF 0x00 4800 0x00 487F 0x00 4900 Option bytes Reserved 0x00 4FFF 0x00 5000 0x00 57FF 0x00 5800 GPIO and peripheral registers (see Table 8 and Table 9) Reserved 0x00 5FFF 0x00 6000 2 Kbytes boot ROM 0x00 67FF 0x00 6800 Reserved 0x00 7EFF 0x00 7F00 0x00 7FFF 0x00 8000 0x00 807F 0x00 8080 CPU/SWIM/debug/ITC registers (see Table 10 ) 32 interrupt vectors Flash program memory (64 to 128 Kbytes) 0x02 7FFF Doc ID 14733 Rev 12 33/103 Memory and register map STM8S207xx, STM8S208xx Table 7 lists the boundary addresses for each memory size. The top of the stack is at the RAM end address in each case. Table 7. Flash, Data EEPROM and RAM boundary addresses Memory area Flash program memory RAM Data EEPROM 6.2 Start address End address 128 K 0x00 8000 0x02 7FFF 64 K 0x00 8000 0x01 7FFF 32 K 0x00 8000 0x00 FFFF 6K 0x00 0000 0x00 17FF 4K 0x00 0000 0x00 1000 2K 0x00 0000 0x00 07FF 2048 0x00 4000 0x00 47FF 1536 0x00 4000 0x00 45FF 1024 0x00 4000 0x00 43FF Register map Table 8. I/O port hardware register map Register label Register name Reset status 0x00 5000 PA_ODR Port A data output latch register 0x00 0x00 5001 PA_IDR Port A input pin value register 0x00 PA_DDR Port A data direction register 0x00 0x00 5003 PA_CR1 Port A control register 1 0x00 0x00 5004 PA_CR2 Port A control register 2 0x00 0x00 5005 PB_ODR Port B data output latch register 0x00 0x00 5006 PB_IDR Port B input pin value register 0x00 PB_DDR Port B data direction register 0x00 0x00 5008 PB_CR1 Port B control register 1 0x00 0x00 5009 PB_CR2 Port B control register 2 0x00 0x00 500A PC_ODR Port C data output latch register 0x00 0x00 500B PB_IDR Port C input pin value register 0x00 PC_DDR Port C data direction register 0x00 0x00 500D PC_CR1 Port C control register 1 0x00 0x00 500E PC_CR2 Port C control register 2 0x00 Address 0x00 5002 0x00 5007 0x00 500C 34/103 Size (bytes) Block Port A Port B Port C Doc ID 14733 Rev 12 STM8S207xx, STM8S208xx Table 8. Memory and register map I/O port hardware register map (continued) Register label Register name Reset status 0x00 500F PD_ODR Port D data output latch register 0x00 0x00 5010 PD_IDR Port D input pin value register 0x00 PD_DDR Port D data direction register 0x00 0x00 5012 PD_CR1 Port D control register 1 0x02 0x00 5013 PD_CR2 Port D control register 2 0x00 0x00 5014 PE_ODR Port E data output latch register 0x00 0x00 5015 PE_IDR Port E input pin value register 0x00 PE_DDR Port E data direction register 0x00 0x00 5017 PE_CR1 Port E control register 1 0x00 0x00 5018 PE_CR2 Port E control register 2 0x00 0x00 5019 PF_ODR Port F data output latch register 0x00 0x00 501A PF_IDR Port F input pin value register 0x00 PF_DDR Port F data direction register 0x00 0x00 501C PF_CR1 Port F control register 1 0x00 0x00 501D PF_CR2 Port F control register 2 0x00 0x00 501E PG_ODR Port G data output latch register 0x00 0x00 501F PG_IDR Port G input pin value register 0x00 PG_DDR Port G data direction register 0x00 0x00 5021 PG_CR1 Port G control register 1 0x00 0x00 5022 PG_CR2 Port G control register 2 0x00 0x00 5023 PH_ODR Port H data output latch register 0x00 0x00 5024 PH_IDR Port H input pin value register 0x00 PH_DDR Port H data direction register 0x00 0x00 5026 PH_CR1 Port H control register 1 0x00 0x00 5027 PH_CR2 Port H control register 2 0x00 0x00 5028 PI_ODR Port I data output latch register 0x00 0x00 5029 PI_IDR Port I input pin value register 0x00 PI_DDR Port I data direction register 0x00 0x00 502B PI_CR1 Port I control register 1 0x00 0x00 502C PI_CR2 Port I control register 2 0x00 Address 0x00 5011 0x00 5016 0x00 501B 0x00 5020 0x00 5025 0x00 502A Block Port D Port E Port F Port G Port H Port I Doc ID 14733 Rev 12 35/103 Memory and register map Table 9. STM8S207xx, STM8S208xx General hardware register map Address Block Register label 0x00 5050 to 0x00 5059 Register name Reset status Reserved area (10 bytes) 0x00 505A FLASH_CR1 Flash control register 1 0x00 0x00 505B FLASH_CR2 Flash control register 2 0x00 0x00 505C FLASH_NCR2 Flash complementary control register 2 0xFF FLASH _FPR Flash protection register 0x00 0x00 505E FLASH _NFPR Flash complementary protection register 0xFF 0x00 505F FLASH _IAPSR Flash in-application programming status register 0x00 0x00 505D Flash 0x00 5060 to 0x00 5061 0x00 5062 Reserved area (2 bytes) Flash FLASH _PUKR 0x00 5063 0x00 5064 Flash Program memory unprotection register 0x00 Reserved area (1 byte) Flash FLASH _DUKR 0x00 5065 to 0x00 509F Data EEPROM unprotection register 0x00 Reserved area (59 bytes) 0x00 50A0 EXTI_CR1 External interrupt control register 1 0x00 EXTI_CR2 External interrupt control register 2 0x00 ITC 0x00 50A1 0x00 50A2 to 0x00 50B2 0x00 50B3 Reserved area (17 bytes) RST RST_SR 0x00 50B4 to 0x00 50BF Reset status register 0xXX(1) Reserved area (12 bytes) 0x00 50C0 CLK_ICKR Internal clock control register 0x01 CLK_ECKR External clock control register 0x00 CLK 0x00 50C1 0x00 50C2 Reserved area (1 byte) 0x00 50C3 CLK_CMSR Clock master status register 0xE1 0x00 50C4 CLK_SWR Clock master switch register 0xE1 0x00 50C5 CLK_SWCR Clock switch control register 0xXX 0x00 50C6 CLK_CKDIVR Clock divider register 0x18 CLK_PCKENR1 Peripheral clock gating register 1 0xFF 0x00 50C8 CLK_CSSR Clock security system register 0x00 0x00 50C9 CLK_CCOR Configurable clock control register 0x00 0x00 50CA CLK_PCKENR2 Peripheral clock gating register 2 0xFF 0x00 50CB CLK_CANCCR CAN clock control register 0x00 0x00 50C7 36/103 CLK Doc ID 14733 Rev 12 STM8S207xx, STM8S208xx Table 9. Memory and register map General hardware register map (continued) Address Block 0x00 50CC Register label Register name Reset status CLK_HSITRIMR HSI clock calibration trimming register 0x00 CLK_SWIMCCR SWIM clock control register 0bXXXX XXX0 CLK 0x00 50CD 0x00 50CE to 0x00 50D0 Reserved area (3 bytes) 0x00 50D1 WWDG_CR WWDG control register 0x7F WWDG_WR WWDR window register 0x7F WWDG 0x00 50D2 0x00 50D3 to 0x00 50DF Reserved area (13 bytes) 0x00 50E0 0x00 50E1 IWDG 0x00 50E2 IWDG_KR IWDG key register 0xXX(2) IWDG_PR IWDG prescaler register 0x00 IWDG_RLR IWDG reload register 0xFF 0x00 50E3 to 0x00 50EF Reserved area (13 bytes) 0x00 50F0 0x00 50F1 AWU 0x00 50F2 0x00 50F3 BEEP AWU_CSR1 AWU control/status register 1 0x00 AWU_APR AWU asynchronous prescaler buffer register 0x3F AWU_TBR AWU timebase selection register 0x00 BEEP_CSR BEEP control/status register 0x1F 0x00 50F4 to 0x00 50FF Reserved area (12 bytes) 0x00 5200 SPI_CR1 SPI control register 1 0x00 0x00 5201 SPI_CR2 SPI control register 2 0x00 0x00 5202 SPI_ICR SPI interrupt control register 0x00 SPI_SR SPI status register 0x02 0x00 5204 SPI_DR SPI data register 0x00 0x00 5205 SPI_CRCPR SPI CRC polynomial register 0x07 0x00 5206 SPI_RXCRCR SPI Rx CRC register 0xFF 0x00 5207 SPI_TXCRCR SPI Tx CRC register 0xFF 0x00 5203 SPI 0x00 5208 to 0x00 520F Reserved area (8 bytes) 0x00 5211 0x00 5212 I2C control register 1 I2C_CR1 0x00 5210 I2C_CR2 I2C I 2C I2C I2C_FREQR 2C 0x00 control register 2 0x00 frequency register 0x00 0x00 5213 I2C_OARL I own address register low 0x00 0x00 5214 I2C_OARH I2C own address register high 0x00 0x00 5215 Reserved Doc ID 14733 Rev 12 37/103 Memory and register map Table 9. STM8S207xx, STM8S208xx General hardware register map (continued) Address Block 0x00 5216 Register label Register name Reset status I2C_DR I2C data register 0x00 2 0x00 5217 I2C_SR1 I C status register 1 0x00 0x00 5218 I2C_SR2 I2C status register 2 0x00 I2C_SR3 I2 0x00 0x00 5219 I2C 0x00 521A I2C_ITR C status register 3 2 I C interrupt control register 0x00 2 0x00 521B I2C_CCRL I C clock control register low 0x00 0x00 521C I2C_CCRH I2C clock control register high 0x00 0x00 521D I2C_TRISER 0x00 521E to 0x00 522F I 2C TRISE register 0x02 Reserved area (18 bytes) 0x00 5230 UART1_SR UART1 status register 0xC0 0x00 5231 UART1_DR UART1 data register 0xXX 0x00 5232 UART1_BRR1 UART1 baud rate register 1 0x00 0x00 5233 UART1_BRR2 UART1 baud rate register 2 0x00 0x00 5234 UART1_CR1 UART1 control register 1 0x00 UART1_CR2 UART1 control register 2 0x00 0x00 5236 UART1_CR3 UART1 control register 3 0x00 0x00 5237 UART1_CR4 UART1 control register 4 0x00 0x00 5238 UART1_CR5 UART1 control register 5 0x00 0x00 5239 UART1_GTR UART1 guard time register 0x00 0x00 523A UART1_PSCR UART1 prescaler register 0x00 0x00 5235 UART1 0x00 523B to 0x00 523F Reserved area (5 bytes) 0x00 5240 UART3_SR UART3 status register C0h 0x00 5241 UART3_DR UART3 data register 0xXX 0x00 5242 UART3_BRR1 UART3 baud rate register 1 0x00 0x00 5243 UART3_BRR2 UART3 baud rate register 2 0x00 UART3_CR1 UART3 control register 1 0x00 0x00 5245 UART3_CR2 UART3 control register 2 0x00 0x00 5246 UART3_CR3 UART3 control register 3 0x00 0x00 5247 UART3_CR4 UART3 control register 4 0x00 0x00 5244 UART3 0x00 5248 0x00 5249 0x00 524A to 0x00 524F 38/103 Reserved UART3_CR6 UART3 control register 6 Reserved area (6 bytes) Doc ID 14733 Rev 12 0x00 STM8S207xx, STM8S208xx Table 9. Memory and register map General hardware register map (continued) Register label Register name Reset status 0x00 5250 TIM1_CR1 TIM1 control register 1 0x00 0x00 5251 TIM1_CR2 TIM1 control register 2 0x00 0x00 5252 TIM1_SMCR TIM1 slave mode control register 0x00 0x00 5253 TIM1_ETR TIM1 external trigger register 0x00 0x00 5254 TIM1_IER TIM1 Interrupt enable register 0x00 0x00 5255 TIM1_SR1 TIM1 status register 1 0x00 0x00 5256 TIM1_SR2 TIM1 status register 2 0x00 0x00 5257 TIM1_EGR TIM1 event generation register 0x00 0x00 5258 TIM1_CCMR1 TIM1 capture/compare mode register 1 0x00 0x00 5259 TIM1_CCMR2 TIM1 capture/compare mode register 2 0x00 0x00 525A TIM1_CCMR3 TIM1 capture/compare mode register 3 0x00 0x00 525B TIM1_CCMR4 TIM1 capture/compare mode register 4 0x00 0x00 525C TIM1_CCER1 TIM1 capture/compare enable register 1 0x00 0x00 525D TIM1_CCER2 TIM1 capture/compare enable register 2 0x00 0x00 525E TIM1_CNTRH TIM1 counter high 0x00 TIM1_CNTRL TIM1 counter low 0x00 0x00 5260 TIM1_PSCRH TIM1 prescaler register high 0x00 0x00 5261 TIM1_PSCRL TIM1 prescaler register low 0x00 0x00 5262 TIM1_ARRH TIM1 auto-reload register high 0xFF 0x00 5263 TIM1_ARRL TIM1 auto-reload register low 0xFF 0x00 5264 TIM1_RCR TIM1 repetition counter register 0x00 0x00 5265 TIM1_CCR1H TIM1 capture/compare register 1 high 0x00 0x00 5266 TIM1_CCR1L TIM1 capture/compare register 1 low 0x00 0x00 5267 TIM1_CCR2H TIM1 capture/compare register 2 high 0x00 0x00 5268 TIM1_CCR2L TIM1 capture/compare register 2 low 0x00 0x00 5269 TIM1_CCR3H TIM1 capture/compare register 3 high 0x00 0x00 526A TIM1_CCR3L TIM1 capture/compare register 3 low 0x00 0x00 526B TIM1_CCR4H TIM1 capture/compare register 4 high 0x00 0x00 526C TIM1_CCR4L TIM1 capture/compare register 4 low 0x00 0x00 526D TIM1_BKR TIM1 break register 0x00 0x00 526E TIM1_DTR TIM1 dead-time register 0x00 0x00 526F TIM1_OISR TIM1 output idle state register 0x00 Address Block 0x00 525F TIM1 0x00 5270 to 0x00 52FF Reserved area (147 bytes) Doc ID 14733 Rev 12 39/103 Memory and register map Table 9. STM8S207xx, STM8S208xx General hardware register map (continued) Register label Register name Reset status 0x00 5300 TIM2_CR1 TIM2 control register 1 0x00 0x00 5301 TIM2_IER TIM2 interrupt enable register 0x00 0x00 5302 TIM2_SR1 TIM2 status register 1 0x00 0x00 5303 TIM2_SR2 TIM2 status register 2 0x00 0x00 5304 TIM2_EGR TIM2 event generation register 0x00 0x00 5305 TIM2_CCMR1 TIM2 capture/compare mode register 1 0x00 0x00 5306 TIM2_CCMR2 TIM2 capture/compare mode register 2 0x00 0x00 5307 TIM2_CCMR3 TIM2 capture/compare mode register 3 0x00 0x00 5308 TIM2_CCER1 TIM2 capture/compare enable register 1 0x00 0x00 5309 TIM2_CCER2 TIM2 capture/compare enable register 2 0x00 TIM2_CNTRH TIM2 counter high 0x00 0x00 530B TIM2_CNTRL TIM2 counter low 0x00 00 530C0x TIM2_PSCR TIM2 prescaler register 0x00 0x00 530D TIM2_ARRH TIM2 auto-reload register high 0xFF 0x00 530E TIM2_ARRL TIM2 auto-reload register low 0xFF 0x00 530F TIM2_CCR1H TIM2 capture/compare register 1 high 0x00 0x00 5310 TIM2_CCR1L TIM2 capture/compare register 1 low 0x00 0x00 5311 TIM2_CCR2H TIM2 capture/compare reg. 2 high 0x00 0x00 5312 TIM2_CCR2L TIM2 capture/compare register 2 low 0x00 0x00 5313 TIM2_CCR3H TIM2 capture/compare register 3 high 0x00 0x00 5314 TIM2_CCR3L TIM2 capture/compare register 3 low 0x00 Address 0x00 530A Block TIM2 0x00 5315 to 0x00 531F Reserved area (11 bytes) 0x00 5320 TIM3_CR1 TIM3 control register 1 0x00 0x00 5321 TIM3_IER TIM3 interrupt enable register 0x00 0x00 5322 TIM3_SR1 TIM3 status register 1 0x00 0x00 5323 TIM3_SR2 TIM3 status register 2 0x00 0x00 5324 TIM3_EGR TIM3 event generation register 0x00 TIM3_CCMR1 TIM3 capture/compare mode register 1 0x00 0x00 5326 TIM3_CCMR2 TIM3 capture/compare mode register 2 0x00 0x00 5327 TIM3_CCER1 TIM3 capture/compare enable register 1 0x00 0x00 5328 TIM3_CNTRH TIM3 counter high 0x00 0x00 5329 TIM3_CNTRL TIM3 counter low 0x00 0x00 532A TIM3_PSCR TIM3 prescaler register 0x00 0x00 5325 40/103 TIM3 Doc ID 14733 Rev 12 STM8S207xx, STM8S208xx Table 9. Memory and register map General hardware register map (continued) Register label Register name Reset status 0x00 532B TIM3_ARRH TIM3 auto-reload register high 0xFF 0x00 532C TIM3_ARRL TIM3 auto-reload register low 0xFF TIM3_CCR1H TIM3 capture/compare register 1 high 0x00 0x00 532E TIM3_CCR1L TIM3 capture/compare register 1 low 0x00 0x00 532F TIM3_CCR2H TIM3 capture/compare register 2 high 0x00 0x00 5330 TIM3_CCR2L TIM3 capture/compare register 2 low 0x00 Address Block 0x00 532D TIM3 0x00 5331 to 0x00 533F Reserved area (15 bytes) 0x00 5340 TIM4_CR1 TIM4 control register 1 0x00 0x00 5341 TIM4_IER TIM4 interrupt enable register 0x00 0x00 5342 TIM4_SR TIM4 status register 0x00 TIM4_EGR TIM4 event generation register 0x00 0x00 5344 TIM4_CNTR TIM4 counter 0x00 0x00 5345 TIM4_PSCR TIM4 prescaler register 0x00 0x00 5346 TIM4_ARR TIM4 auto-reload register 0xFF 0x00 5343 TIM4 0x00 5347 to 0x00 53FF Reserved area (185 bytes) 0x00 5400 ADC _CSR ADC control/status register 0x00 0x00 5401 ADC_CR1 ADC configuration register 1 0x00 0x00 5402 ADC_CR2 ADC configuration register 2 0x00 ADC_CR3 ADC configuration register 3 0x00 0x00 5404 ADC_DRH ADC data register high 0xXX 0x00 5405 ADC_DRL ADC data register low 0xXX 0x00 5406 ADC_TDRH ADC Schmitt trigger disable register high 0x00 0x00 5407 ADC_TDRL ADC Schmitt trigger disable register low 0x00 0x00 5403 ADC2 0x00 5408 to 0x00 541F Reserved area (24 bytes) 0x00 5420 CAN_MCR CAN master control register 0x02 0x00 5421 CAN_MSR CAN master status register 0x02 0x00 5422 CAN_TSR CAN transmit status register 0x00 CAN_TPR CAN transmit priority register 0x0C 0x00 5424 CAN_RFR CAN receive FIFO register 0x00 0x00 5425 CAN_IER CAN interrupt enable register 0x00 0x00 5426 CAN_DGR CAN diagnosis register 0x0C 0x00 5427 CAN_FPSR CAN page selection register 0x00 0x00 5423 beCAN Doc ID 14733 Rev 12 41/103 Memory and register map Table 9. STM8S207xx, STM8S208xx General hardware register map (continued) Register label Register name Reset status 0x00 5428 CAN_P0 CAN paged register 0 0xXX(3) 0x00 5429 CAN_P1 CAN paged register 1 0xXX(3) 0x00 542A CAN_P2 CAN paged register 2 0xXX(3) 0x00 542B CAN_P3 CAN paged register 3 0xXX(3) 0x00 542C CAN_P4 CAN paged register 4 0xXX(3) 0x00 542D CAN_P5 CAN paged register 5 0xXX(3) 0x00 542E CAN_P6 CAN paged register 6 0xXX(3) CAN_P7 CAN paged register 7 0xXX(3) 0x00 5430 CAN_P8 CAN paged register 8 0xXX(3) 0x00 5431 CAN_P9 CAN paged register 9 0xXX(3) 0x00 5432 CAN_PA CAN paged register A 0xXX(3) 0x00 5433 CAN_PB CAN paged register B 0xXX(3) 0x00 5434 CAN_PC CAN paged register C 0xXX(3) 0x00 5435 CAN_PD CAN paged register D 0xXX(3) 0x00 5436 CAN_PE CAN paged register E 0xXX(3) 0x00 5437 CAN_PF CAN paged register F 0xXX(3) Address Block 0x00 542F beCAN 0x00 5438 to 0x00 57FF Reserved area (968 bytes) 1. Depends on the previous reset source. 2. Write only register. 3. If the bootloader is enabled, it is initialized to 0x00. 42/103 Doc ID 14733 Rev 12 STM8S207xx, STM8S208xx Table 10. Memory and register map CPU/SWIM/debug module/interrupt controller registers Register Label Register Name Reset Status 0x00 7F00 A Accumulator 0x00 0x00 7F01 PCE Program counter extended 0x00 0x00 7F02 PCH Program counter high 0x00 0x00 7F03 PCL Program counter low 0x00 XH X index register high 0x00 XL X index register low 0x00 0x00 7F06 YH Y index register high 0x00 0x00 7F07 YL Y index register low 0x00 0x00 7F08 SPH Stack pointer high 0x17(2) 0x00 7F09 SPL Stack pointer low 0xFF 0x00 7F0A CCR Condition code register 0x28 Address Block 0x00 7F04 0x00 7F05 CPU(1) 0x00 7F0B to 0x00 7F5F 0x00 7F60 Reserved area (85 bytes) CPU CFG_GCR Global configuration register 0x00 0x00 7F70 ITC_SPR1 Interrupt software priority register 1 0xFF 0x00 7F71 ITC_SPR2 Interrupt software priority register 2 0xFF 0x00 7F72 ITC_SPR3 Interrupt software priority register 3 0xFF ITC_SPR4 Interrupt software priority register 4 0xFF 0x00 7F74 ITC_SPR5 Interrupt software priority register 5 0xFF 0x00 7F75 ITC_SPR6 Interrupt software priority register 6 0xFF 0x00 7F76 ITC_SPR7 Interrupt software priority register 7 0xFF 0x00 7F77 ITC_SPR8 Interrupt software priority register 8 0xFF 0x00 7F73 ITC 0x00 7F78 to 0x00 7F79 0x00 7F80 Reserved area (2 bytes) SWIM SWIM_CSR 0x00 7F81 to 0x00 7F8F SWIM control status register 0x00 Reserved area (15 bytes) 0x00 7F90 DM_BK1RE DM breakpoint 1 register extended byte 0xFF 0x00 7F91 DM_BK1RH DM breakpoint 1 register high byte 0xFF 0x00 7F92 DM_BK1RL DM breakpoint 1 register low byte 0xFF DM_BK2RE DM breakpoint 2 register extended byte 0xFF 0x00 7F94 DM_BK2RH DM breakpoint 2 register high byte 0xFF 0x00 7F95 DM_BK2RL DM breakpoint 2 register low byte 0xFF 0x00 7F96 DM_CR1 DM debug module control register 1 0x00 0x00 7F97 DM_CR2 DM debug module control register 2 0x00 0x00 7F93 DM Doc ID 14733 Rev 12 43/103 Memory and register map Table 10. STM8S207xx, STM8S208xx CPU/SWIM/debug module/interrupt controller registers (continued) Address Block Register Label Register Name Reset Status DM_CSR1 DM debug module control/status register 1 0x10 DM_CSR2 DM debug module control/status register 2 0x00 DM_ENFCTR DM enable function register 0xFF 0x00 7F98 0x00 7F99 0x00 7F9A DM 0x00 7F9B to 0x00 7F9F Reserved area (5 bytes) 1. Accessible by debug module only 2. Product dependent value, see Figure 8: Memory map. 44/103 Doc ID 14733 Rev 12 STM8S207xx, STM8S208xx Interrupt vector mapping 7 Interrupt vector mapping Table 11. Interrupt mapping IRQ no. Source block RESET TRAP Wakeup from Wakeup from Halt mode Active-halt mode Description Reset Vector address Yes Yes 0x00 8000 Software interrupt - - 0x00 8004 External top level interrupt - - 0x00 8008 Yes 0x00 800C - 0x00 8010 Yes(1) 0x00 8014 0 TLI 1 AWU Auto wake up from halt - 2 CLK Clock controller (1) 3 EXTI0 Port A external interrupts Yes 4 EXTI1 Port B external interrupts Yes Yes 0x00 8018 5 EXTI2 Port C external interrupts Yes Yes 0x00 801C 6 EXTI3 Port D external interrupts Yes Yes 0x00 8020 7 EXTI4 Port E external interrupts Yes Yes 0x00 8024 8 beCAN beCAN RX interrupt Yes Yes 0x00 8028 9 beCAN beCAN TX/ER/SC interrupt - - 0x00 802C 10 SPI Yes Yes 0x00 8030 11 TIM1 TIM1 update/overflow/underflow/ trigger/break - - 0x00 8034 12 TIM1 TIM1 capture/compare - - 0x00 8038 13 TIM2 TIM2 update /overflow - - 0x00 803C 14 TIM2 TIM2 capture/compare - - 0x00 8040 15 TIM3 Update/overflow - - 0x00 8044 16 TIM3 Capture/compare - - 0x00 8048 17 UART1 Tx complete - - 0x00 804C 18 UART1 Receive register DATA FULL - - 0x00 8050 19 I2C I2C interrupt Yes Yes 0x00 8054 20 UART3 Tx complete - - 0x00 8058 21 UART3 Receive register DATA FULL - - 0x00 805C 22 ADC2 ADC2 end of conversion - - 0x00 8060 23 TIM4 TIM4 update/overflow - - 0x00 8064 24 Flash EOP/WR_PG_DIS - - 0x00 8068 End of transfer 0x00 806C to 0x00 807C Reserved 1. Except PA1 Doc ID 14733 Rev 12 45/103 Option bytes 8 STM8S207xx, STM8S208xx Option bytes Option bytes contain configurations for device hardware features as well as the memory protection of the device. They are stored in a dedicated block of the memory. Except for the ROP (read-out protection) byte, each option byte has to be stored twice, in a regular form (OPTx) and a complemented one (NOPTx) for redundancy. Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address shown in Table 12: Option bytes below. Option bytes can also be modified `on the fly' by the application in IAP mode, except the ROP option that can only be modified in ICP mode (via SWIM). Refer to the STM8S Flash programming manual (PM0051) and STM8 SWIM communication protocol and debug module user manual (UM0470) for information on SWIM programming procedures. Table 12. Addr. Option bytes Option name Option byte no. Option bits 7 6 5 4 3 2 1 0 Factory default setting Read-out 4800h protection OPT0 ROP[7:0] 00h UBC[7:0] 00h NUBC[7:0] FFh (ROP) 4801h User boot OPT1 4802h code(UBC) NOPT1 4803h Alternate OPT2 AFR7 AFR6 AFR5 AFR4 AFR3 AFR2 AFR1 AFR0 00h NAFR7 NAFR6 NAFR5 NAFR4 NAFR3 NAFR2 NAFR1 NAFR0 FFh function 4804h remapping NOPT2 (AFR) 4805h OPT3 Reserved 4806h NOPT3 Reserved 4807h OPT4 Reserved NOPT4 Reserved Watchdog option LSI IWDG WWDG WWDG _EN _HW _HW _HALT NLSI NIWDG _HW NWWDG _EN _HW NWWDG _HALT EXT CKAWU PRS PRS CLK SEL C1 C0 NEXT NCKAWUS NPR NPR CLK EL SC1 SC0 00h FFh 00h Clock option 4808h 4809h HSE clock OPT5 480Ah startup NOPT5 480Bh FFh HSECNT[7:0] 00h NHSECNT[7:0] FFh OPT6 Reserved 00h NOPT6 Reserved FFh Reserved 480Ch 480Dh Flash wait OPT7 Reserved Wait state 00h 480Eh states NOPT7 Reserved Nwait state FFh 487Eh OPTBL BL[7:0] 00h NBL[7:0] FFh Bootloader 487Fh 46/103 NOPTBL Doc ID 14733 Rev 12 STM8S207xx, STM8S208xx Table 13. Option bytes Option byte description Option byte no. Description OPT0 ROP[7:0] Memory readout protection (ROP) 0xAA: Enable readout protection (write access via SWIM protocol) Note: Refer to the family reference manual (RM0016) section on Flash/EEPROM memory readout protection for details. OPT1 UBC[7:0] User boot code area 0x00: no UBC, no write-protection 0x01: Pages 0 to 1 defined as UBC, memory write-protected 0x02: Pages 0 to 3 defined as UBC, memory write-protected 0x03: Pages 0 to 4 defined as UBC, memory write-protected ... 0xFE: Pages 0 to 255 defined as UBC, memory write-protected 0xFF: Reserved Note: Refer to the family reference manual (RM0016) section on Flash/EEPROM write protection for more details. OPT2 AFR7Alternate function remapping option 7 0: Port D4 alternate function = TIM2_CH1 1: Port D4 alternate function = BEEP AFR6 Alternate function remapping option 6 0: Port B5 alternate function = AIN5, port B4 alternate function = AIN4 1: Port B5 alternate function = I2C_SDA, port B4 alternate function = I2C_SCL AFR5 Alternate function remapping option 5 0: Port B3 alternate function = AIN3, port B2 alternate function = AIN2, port B1 alternate function = AIN1, port B0 alternate function = AIN0 1: Port B3 alternate function = TIM1_ETR, port B2 alternate function = TIM1_CH3N, port B1 alternate function = TIM1_CH2N, port B0 alternate function = TIM1_CH1N AFR4 Alternate function remapping option 4 0: Port D7 alternate function = TLI 1: Port D7 alternate function = TIM1_CH4 AFR3 Alternate function remapping option 3 0: Port D0 alternate function = TIM3_CH2 1: Port D0 alternate function = TIM1_BKIN AFR2 Alternate function remapping option 2 0: Port D0 alternate function = TIM3_CH2 1: Port D0 alternate function = CLK_CCO Note: AFR2 option has priority over AFR3 if both are activated AFR1 Alternate function remapping option 1 0: Port A3 alternate function = TIM2_CH3, port D2 alternate function TIM3_CH1 1: Port A3 alternate function = TIM3_CH1, port D2 alternate function TIM2_CH3 AFR0 Alternate function remapping option 0 0: Port D3 alternate function = TIM2_CH2 1: Port D3 alternate function = ADC_ETR Doc ID 14733 Rev 12 47/103 Option bytes STM8S207xx, STM8S208xx Table 13. Option byte description (continued) Option byte no. Description LSI_EN: Low speed internal clock enable 0: LSI clock is not available as CPU clock source 1: LSI clock is available as CPU clock source IWDG_HW: Independent watchdog 0: IWDG Independent watchdog activated by software 1: IWDG Independent watchdog activated by hardware OPT3 WWDG_HW: Window watchdog activation 0: WWDG window watchdog activated by software 1: WWDG window watchdog activated by hardware WWDG_HALT: Window watchdog reset on halt 0: No reset generated on halt if WWDG active 1: Reset generated on halt if WWDG active EXTCLK: External clock selection 0: External crystal connected to OSCIN/OSCOUT 1: External clock signal on OSCIN OPT4 CKAWUSEL: Auto wakeup unit/clock 0: LSI clock source selected for AWU 1: HSE clock with prescaler selected as clock source for for AWU PRSC[1:0] AWU clock prescaler 00: 24 MHz to 128 kHz prescaler 01: 16 MHz to 128 kHz prescaler 10: 8 MHz to 128 kHz prescaler 11: 4 MHz to 128 kHz prescaler 48/103 OPT5 HSECNT[7:0]: HSE crystal oscillator stabilization time This configures the stabilisation time. 0x00: 2048 HSE cycles 0xB4: 128 HSE cycles 0xD2: 8 HSE cycles 0xE1: 0.5 HSE cycles OPT6 Reserved OPT7 WAITSTATE Wait state configuration This option configures the number of wait states inserted when reading from the Flash/data EEPROM memory. 1 wait state is required if fCPU > 16 MHz. 0: No wait state 1: 1 wait state Doc ID 14733 Rev 12 STM8S207xx, STM8S208xx Table 13. Option bytes Option byte description (continued) Option byte no. OPTBL Description BL[7:0] Bootloader option byte For STM8S products, this option is checked by the boot ROM code after reset. Depending on the content of addresses 0x487E, 0x487F, and 0x8000 (reset vector), the CPU jumps to the bootloader or to the reset vector. Refer to the UM0560 (STM8L/S bootloader manual) for more details. For STM8L products, the bootloader option bytes are on addresses 0xXXXX and 0xXXXX+1 (2 bytes). These option bytes control whether the bootloader is active or not. For more details, refer to the UM0560 (STM8L/S bootloader manual) for more details. Doc ID 14733 Rev 12 49/103 Unique ID 9 STM8S207xx, STM8S208xx Unique ID The devices feature a 96-bit unique device identifier which provides a reference number that is unique for any device and in any context. The 96 bits of the identifier can never be altered by the user. The unique device identifier can be read in single bytes and may then be concatenated using a custom algorithm. The unique device identifier is ideally suited: For use as serial numbers For use as security keys to increase the code security in the program memory while using and combining this unique ID with software crytograhic primitives and protocols before programming the internal memory. To activate secure boot processes Table 14. Address 0x48CD 0x48CE 0x48CF Content description Unique ID bits 7 6 5 4 3 U_ID[7:0] X co-ordinate on the wafer U_ID[15:8] U_ID[23:16] 0x48D0 Y co-ordinate on the wafer 0x48D1 Wafer number U_ID[39:32] U_ID[31:24] 0x48D2 U_ID[47:40] 0x48D3 U_ID[55:48] 0x48D4 U_ID[63:56] 0x48D5 50/103 Unique ID registers (96 bits) Lot number U_ID[71:64] 0x48D6 U_ID[79:72] 0x48D7 U_ID[87:80] 0x48D8 U_ID[95:88] Doc ID 14733 Rev 12 2 1 0 STM8S207xx, STM8S208xx Electrical characteristics 10 Electrical characteristics 10.1 Parameter conditions Unless otherwise specified, all voltages are referred to VSS. 10.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100 % of the devices with an ambient temperature at TA = 25 C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean 3 ). 10.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 C, VDD = 5 V. They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean 2 ). 10.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 10.1.4 Typical current consumption For typical current consumption measurements, VDD, VDDIO and VDDA are connected together in the configuration shown in Figure 9. Figure 9. Supply current measurement conditions 5 V or 3.3 V A VDD VDDA VDDIO VSS VSSA VSSIO Doc ID 14733 Rev 12 51/103 Electrical characteristics 10.1.5 Pin loading conditions 10.1.6 Loading capacitor STM8S207xx, STM8S208xx The loading conditions used for pin parameter measurement are shown in Figure 10. Figure 10. Pin loading conditions STM8 pin 50 pF 10.1.7 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 11. Figure 11. Pin input voltage STM8 pin VIN 52/103 Doc ID 14733 Rev 12 STM8S207xx, STM8S208xx 10.2 Electrical characteristics Absolute maximum ratings Stresses above those listed as `absolute maximum ratings' may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 15. Symbol VDDx - VSS Voltage characteristics Ratings Supply voltage (including VDDA and VDDIO)(1) Input voltage on true open drain pins (PE1, PE2) VIN Input voltage on any other pin(2) (2) Min Max -0.3 6.5 VSS - 0.3 6.5 VSS - 0.3 VDD + 0.3 |VDDx - VDD| Variations between different power pins 50 |VSSx - VSS| Variations between all the different ground pins 50 VESD Electrostatic discharge voltage Unit V mV see Absolute maximum ratings (electrical sensitivity) on page 86 1. All power (VDD, VDDIO, VDDA) and ground (VSS, VSSIO, VSSA) pins must always be connected to the external power supply 2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. For true open-drain pads, there is no positive injection current, and the corresponding VIN maximum must always be respected Doc ID 14733 Rev 12 53/103 Electrical characteristics Table 16. STM8S207xx, STM8S208xx Current characteristics Symbol Max.(1) Ratings IVDD Total current into VDD power lines (source)(2) 60 IVSS (2) Total current out of VSS ground lines (sink) 60 Output current sunk by any I/O and control pin 20 Output current source by any I/Os and control pin 20 Total output current sourced (sum of all I/O and control pins) for devices with two VDDIO pins(3) 200 Total output current sourced (sum of all I/O and control pins) for devices with one VDDIO pin(3) 100 Total output current sunk (sum of all I/O and control pins) for devices with two VSSIO pins(3) 160 Total output current sunk (sum of all I/O and control pins) for devices with one VSSIO pin(3) 80 Injected current on NRST pin 4 IIO IIO IINJ(PIN)(4)(5) IINJ(PIN)(4) mA Injected current on OSCIN pin Injected current on any other Unit 4 pin(6) 4 Total injected current (sum of all I/O and control pins)(6) 20 1. Data based on characterization results, not tested in production. 2. All power (VDD, VDDIO, VDDA) and ground (VSS, VSSIO, VSSA) pins must always be connected to the external supply. 3. I/O pins used simultaneously for high current source/sink must be uniformly spaced around the package between the VDDIO/VSSIO pins. 4. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. For true open-drain pads, there is no positive injection current, and the corresponding VIN maximum must always be respected 5. Negative injection disturbs the analog performance of the device. See note in Section 10.3.10: 10-bit ADC characteristics on page 82. 6. When several inputs are submitted to a current injection, the maximum IINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values). These results are based on characterization with IINJ(PIN) maximum current injection on four I/O port pins of the device. Table 17. 54/103 Thermal characteristics Symbol Ratings Value TSTG Storage temperature range -65 to 150 TJ Maximum junction temperature 150 Unit C Doc ID 14733 Rev 12 STM8S207xx, STM8S208xx 10.3 Electrical characteristics Operating conditions The device must be used in operating conditions that respect the parameters in Table 18. In addition, full account must be taken of all physical capacitor characteristics and tolerances. Table 18. General operating conditions Symbol Parameter fCPU Internal CPU clock frequency Conditions TA 105 C VDD/VDD_IO Standard operating voltage CEXT: capacitance of external capacitor VCAP(1) ESR of external capacitor at 1 MHz(2) ESL of external capacitor PD(3) TA TJ Power dissipation at TA = 85 C for suffix 6 or TA = 125 C for suffix 3 Min Max Unit 0 24 MHz 0 16 MHz 2.95 5.5 V 470 3300 nF - 0.3 - 15 nH 44, 48, 64, and 80-pin devices, with output on 8 standard ports, 2 high sink ports and 2 open drain ports simultaneously(4) 443 32-pin package, with output on 8 standard ports and 2 high sink ports simultaneously(4) 360 mW Ambient temperature for 6 suffix version Maximum power dissipation -40 85 Ambient temperature for 3 suffix version Maximum power dissipation -40 125 6 suffix version -40 105 3 suffix version -40 130(5) Junction temperature range C 1. Care should be taken when selecting the capacitor, due to its tolerance, as well as the parameter dependency on temperature, DC bias and frequency in addition to other factors. The parameter maximum value must be respected for the full application range. 2. This frequency of 1 MHz as a condition for VCAP parameters is given by design of internal regulator. 3. To calculate PDmax(TA), use the formula PDmax = (TJmax - TA)/JA (see Section 11.2: Thermal characteristics on page 95) with the value for TJmax given in Table 18 above and the value for JA given in Table 57: Thermal characteristics. 4. Refer to Section 11.2: Thermal characteristics on page 95 for the calculation method. 5. TJmax is given by the test limit. Above this value the product behavior is not guaranteed. Doc ID 14733 Rev 12 55/103 Electrical characteristics STM8S207xx, STM8S208xx Figure 12. fCPUmax versus VDD fCPU [MHz] 24 FUNCTIONALITY NOT GUARANTEED IN THIS AREA FUNCTIONALITY GUARANTEED @ TA -40 to 105 C 16 FUNCTIONALITY GUARANTEED @ TA -40 to 125 C 12 8 4 0 2.95 4.0 5.0 5.5 SUPPLY VOLTAGE [V] Table 19. Symbol tVDD Operating conditions at power-up/power-down Parameter Conditions Min Typ Max VDD rise time rate 2(1) VDD fall time rate 2(1) tTEMP Reset release delay VIT+ Power-on reset threshold 2.65 VIT- Brown-out reset threshold 2.58 VHYS(BOR) Brown-out reset hysteresis Unit s/V 1.7(1) ms 2.8 2.95 V 2.73 2.88 V VDD rising 70 mV 1. Guaranteed by design, not tested in production. 10.3.1 VCAP external capacitor Stabilization for the main regulator is achieved connecting an external capacitor CEXT to the VCAP pin. CEXT is specified in Table 18. Care should be taken to limit the series inductance to less than 15 nH. Figure 13. External capacitor CEXT ESR C ESL Rleak 1. Legend: ESR is the equivalent series resistance and ESL is the equivalent inductance. 56/103 Doc ID 14733 Rev 12 STM8S207xx, STM8S208xx 10.3.2 Electrical characteristics Supply current characteristics The current consumption is measured as described in Figure 9 on page 51. Total current consumption in run mode The MCU is placed under the following conditions: All I/O pins in input mode with a static value at VDD or VSS (no load) All peripherals are disabled (clock stopped by Peripheral Clock Gating registers) except if explicitly mentioned. When the MCU is clocked at 24 MHz, TA 105 C and the WAITSTATE option bit is set. Subject to general operating conditions for VDD and TA. Table 20. Symbol Total current consumption with code execution in run mode at VDD = 5 V Parameter Conditions IDD(RUN) Supply current in run mode, code executed from Flash Max HSE crystal osc. (24 MHz) 4.4 HSE user ext. clock (24 MHz) 3.7 HSE crystal osc. (16 MHz) 3.3 HSE user ext. clock (16 MHz) 2.7 5.8 HSI RC osc. (16 MHz) 2.5 3.4 HSE user ext. clock (16 MHz) 1.2 4.1(1) HSI RC osc. (16 MHz) 1.0 1.3(1) fCPU = fMASTER/128 = 15.625 kHz HSI RC osc. (16 MHz/8) 0.55 fCPU = fMASTER = 128 kHz LSI RC osc. (128 kHz) 0.45 fCPU = fMASTER = 24 MHz, TA 105 C HSE crystal osc. (24 MHz) 11.4 HSE user ext. clock (24 MHz) 10.8 HSE crystal osc. (16 MHz) 9.0 HSE user ext. clock (16 MHz) 8.2 15.2(1) HSI RC osc.(16 MHz) 8.1 13.2(1) fCPU = fMASTER = 2 MHz. HSI RC osc. (16 MHz/8)(2) 1.5 fCPU = fMASTER/128 = 125 kHz HSI RC osc. (16 MHz) 1.1 fCPU = fMASTER/128 = 15.625 kHz HSI RC osc. (16 MHz/8) 0.6 fCPU = fMASTER = 128 kHz LSI RC osc. (128 kHz) 0.55 fCPU = fMASTER = 24 MHz, TA 105 C Supply current in run mode, code executed from RAM Typ fCPU = fMASTER = 16 MHz fCPU = fMASTER/128 = 125 kHz fCPU = fMASTER = 16 MHz Unit 7.3(1) mA 18(1) 1. Data based on characterization results, not tested in production. 2. Default clock configuration measured with all peripherals off. Doc ID 14733 Rev 12 57/103 Electrical characteristics Table 21. Symbol STM8S207xx, STM8S208xx Total current consumption with code execution in run mode at VDD = 3.3 V Parameter Conditions IDD(RUN) Supply current in run mode, code executed from Flash 4.0 HSE user ext. clock (24 MHz) 3.7 HSE crystal osc. (16 MHz) 2.9 HSE user ext. clock (16 MHz) 2.7 5.8 HSI RC osc. (16 MHz) 2.5 3.4 HSE user ext. clock (16 MHz) 1.2 4.1 HSI RC osc. (16 MHz) 1.0 1.3 fCPU = fMASTER/128 = 15.625 kHz HSI RC osc. (16MHz/8) 0.55 fCPU = fMASTER = 128 kHz LSI RC osc. (128 kHz) 0.45 fCPU = fMASTER = 24 MHz, TA 105 C HSE crystal osc. (24 MHz) 11.0 HSE user ext. clock (24 MHz) 10.8 HSE crystal osc. (16 MHz) 8.4 HSE user ext. clock (16 MHz) 8.2 15.2 HSI RC osc. (16 MHz) 8.1 13.2 fCPU = fMASTER = 2 MHz. HSI RC osc. (16 MHz/8)(2) 1.5 fCPU = fMASTER/128 = 125 kHz HSI RC osc. (16 MHz) 1.1 fCPU = fMASTER/128 = 15.625 kHz HSI RC osc. (16 MHz/8) 0.6 fCPU = fMASTER = 128 kHz LSI RC osc. (128 kHz) 0.55 fCPU = fMASTER = 16 MHz fCPU = fMASTER/128 = 125 kHz fCPU = fMASTER = 16 MHz Unit 7.3 mA 1. Data based on characterization results, not tested in production. 2. Default clock configuration. 58/103 Max(1) HSE crystal osc. (24 MHz) fCPU = fMASTER = 24 MHz, TA 105 C Supply current in run mode, code executed from RAM Typ Doc ID 14733 Rev 12 18.0 STM8S207xx, STM8S208xx Electrical characteristics Total current consumption in wait mode Table 22. Symbol Total current consumption in wait mode at VDD = 5 V Parameter Conditions IDD(WFI) Max(1) Unit HSE crystal osc. (24 MHz) 2.4 HSE user ext. clock (24 MHz) 1.8 HSE crystal osc. (16 MHz) 2.0 HSE user ext. clock (16 MHz) 1.4 4.4 HSI RC osc. (16 MHz) 1.2 1.6 mA fCPU = fMASTER/128 = 125 kHz HSI RC osc. (16 MHz) 1.0 fCPU = fMASTER/128 = 15.625 kHz HSI RC osc. (16 MHz/8)(2) 0.55 fCPU = fMASTER = 128 kHz LSI RC osc. (128 kHz) 0.5 Max(1) Unit fCPU = fMASTER = 24 MHz, TA 105 C Supply current in wait mode Typ fCPU = fMASTER = 16 MHz 4.7 1. Data based on characterization results, not tested in production. 2. Default clock configuration measured with all peripherals off. Table 23. Symbol Total current consumption in wait mode at VDD = 3.3 V Parameter Conditions HSE crystal osc. (24 MHz) 2.0 HSE user ext. clock (24 MHz) 1.8 HSE crystal osc. (16 MHz) 1.6 HSE user ext. clock (16 MHz) 1.4 4.4 HSI RC osc. (16 MHz) 1.2 1.6 fCPU = fMASTER/128 = 125 kHz HSI RC osc. (16 MHz) 1.0 fCPU = fMASTER/128 = 15.625 kHz HSI RC osc. (16 MHz/8)(2) 0.55 fCPU = fMASTER/128 = 15.625 kHz LSI RC osc. (128 kHz) 0.5 fCPU = fMASTER = 24 MHz, TA 105 C IDD(WFI) Supply current in wait mode Typ fCPU = fMASTER = 16 MHz 4.7 mA 1. Data based on characterization results, not tested in production. 2. Default clock configuration measured with all peripherals off. Doc ID 14733 Rev 12 59/103 Electrical characteristics STM8S207xx, STM8S208xx Total current consumption in active halt mode Table 24. Total current consumption in active halt mode at VDD = 5 V, TA -40 to 85 C Conditions Symbol Parameter Main voltage regulator (MVR)(2) Typ (3) Flash mode Max(1) Unit Clock source HSE crystal oscillator (16 MHz) 1000 LSI RC oscillator (128 kHz) 200 HSE crystal oscillator (16 MHz) 940 LSI RC oscillator (128 kHz) 140 Operating mode 260 On IDD(AH) Supply current in active halt mode A Powerdown mode Operating mode Off Powerdown mode LSI RC oscillator 128 kHz) 68 11 45 1. Data based on characterization results, not tested in production. 2. Configured by the REGAH bit in the CLK_ICKR register. 3. Configured by the AHALT bit in the FLASH_CR1 register. Table 25. Total current consumption in active halt mode at VDD = 3.3 V Conditions Symbol Parameter Main voltage regulator (MVR)(2) Flash mode(3) Typ(1) Unit Clock source HSE crystal osc. (16 MHz) 600 LSI RC osc. (128 kHz) 200 HSE crystal osc. (16 MHz) 540 LSI RC osc. (128 kHz) 140 Operating mode On IDD(AH) Supply current in active halt mode Powerdown mode A Operating mode Off Powerdown mode 1. Data based on characterization results, not tested in production. 2. Configured by the REGAH bit in the CLK_ICKR register. 3. Configured by the AHALT bit in the FLASH_CR1 register. 60/103 66 LSI RC osc. (128 kHz) Doc ID 14733 Rev 12 9 STM8S207xx, STM8S208xx Electrical characteristics Total current consumption in halt mode Table 26. Symbol IDD(H) Table 27. Symbol IDD(H) Total current consumption in halt mode at VDD = 5 V Parameter Supply current in halt mode Conditions Typ Flash in operating mode, HSI clock after wakeup Max at 85 C Max at 125 C Unit 63.5 A Flash in powerdown mode, HSI clock after wakeup 6.5 35 100 Total current consumption in halt mode at VDD = 3.3 V Parameter Conditions Typ Flash in operating mode, HSI clock after wakeup 61.5 Flash in powerdown mode, HSI clock after wakeup 4.5 Supply current in halt mode Unit A Low power mode wakeup times Table 28. Symbol tWU(WFI) Wakeup times Parameter Conditions Typ MVR voltage regulator on(4) Wakeup time active halt mode to run mode.(3) MVR voltage regulator off(4) tWU(H) Wakeup time from halt mode to run mode(3) Unit See note(2) Wakeup time from wait mode to run mode(3) fCPU = fMASTER = 16 MHz. tWU(AH) Max(1) 0.56 Flash in operating mode(5) Flash in powerdown mode(5) Flash in operating mode(5) Flash in powerdown mode(5) Flash in operating mode(5) (5) Flash in powerdown mode 1(6) 2(6) 3(6) HSI (after wakeup) s 48(6) 50(6) 52 54 1. Data guaranteed by design, not tested in production. 2. tWU(WFI) = 2 x 1/fmaster + 7 x 1/fCPU 3. Measured from interrupt event to interrupt vector fetch. 4. Configured by the REGAH bit in the CLK_ICKR register. 5. Configured by the AHALT bit in the FLASH_CR1 register. 6. Plus 1 LSI clock depending on synchronization. Doc ID 14733 Rev 12 61/103 Electrical characteristics STM8S207xx, STM8S208xx Total current consumption and timing in forced reset state Table 29. Total current consumption and timing in forced reset state Symbol Parameter Conditions IDD(R) Supply current in reset state tRESETBL Reset release to bootloader vector fetch Typ VDD = 5 V 1.6 VDD = 3.3 V 0.8 Max(1) Unit mA 150 s 1. Data guaranteed by design, not tested in production. Current consumption of on-chip peripherals Subject to general operating conditions for VDD and TA. HSI internal RC/fCPU = fMASTER = 16 MHz. Table 30. Peripheral current consumption Symbol Parameter Typ. IDD(TIM1) TIM1 supply current (1) 220 IDD(TIM2) TIM2 supply current (1) 120 IDD(TIM3) TIM3 timer supply current (1) IDD(TIM4) (1) TIM4 timer supply current 100 25 UART1 supply current (2) 90 IDD(UART3) UART3 supply current (2) 110 IDD(SPI) SPI supply current (2) IDD(I2C) I2C IDD(UART1) IDD(CAN) IDD(ADC2) supply current A 40 (2) beCAN supply current Unit 50 (2) ADC2 supply current when converting 210 (3) 1000 1. Data based on a differential IDD measurement between reset configuration and timer counter running at 16 MHz. No IC/OC programmed (no I/O pads toggling). Not tested in production. 2. Data based on a differential IDD measurement between the on-chip peripheral when kept under reset and not clocked and the on-chip peripheral when clocked and not kept under reset. No I/O pads toggling. Not tested in production. 3. Data based on a differential IDD measurement between reset configuration and continuous A/D conversions. Not tested in production. 62/103 Doc ID 14733 Rev 12 STM8S207xx, STM8S208xx Electrical characteristics Current consumption curves Figure 14 and Figure 15 show typical current consumption measured with code executing in RAM. Figure 14. Typ. IDD(RUN) vs VDD, HSI RC osc, fCPU = 16 MHz -40C 25C 4 85C 3.5 IDD(RUN)HSI [mA] 125C 3 2.5 2 1.5 1 0.5 0 2.5 3 3.5 4 4.5 5 5.5 6 VDD [V] Figure 15. Typ. IDD(WFI) vs VDD, HSI RC osc, fCPU = 16 MHz -40C 25C 2.5 85C 125C IDD(WFI)HSI [mA] 2 1.5 1 0.5 0 2.5 3 3.5 4 4.5 5 5.5 6 VDD [V] Doc ID 14733 Rev 12 63/103 Electrical characteristics 10.3.3 STM8S207xx, STM8S208xx External clock sources and timing characteristics HSE user external clock Subject to general operating conditions for VDD and TA. Table 31. HSE user external clock characteristics Symbol Parameter Conditions fHSE_ext User external clock source frequency VHSEH(1) OSCIN input pin high level voltage Min Typ Max Unit 0 24 MHz 0.7 x VDD VDD + 0.3 V V VHSEL (1) ILEAK_HSE OSCIN input pin low level voltage OSCIN input leakage current VSS < VIN < VDD VSS 0.3 x VDD -1 1 A 1. Data based on characterization results, not tested in production. Figure 16. HSE external clock source VHSEH VHSEL fHSE External clock source OSCIN STM8 HSE crystal/ceramic resonator oscillator The HSE clock can be supplied with a 1 to 24 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph is based on characterization results with specified typical external components. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. Refer to the crystal resonator manufacturer for more details (frequency, package, accuracy...). 64/103 Doc ID 14733 Rev 12 STM8S207xx, STM8S208xx Table 32. Electrical characteristics HSE oscillator characteristics Symbol Parameter Conditions External high speed oscillator frequency fHSE Min 1 Feedback resistor RF C(1) gm Max Unit 24 MHz 220 Recommended load capacitance IDD(HSE) Typ k (2) HSE oscillator power consumption 20 pF C = 20 pF, fOSC = 24 MHz 6 (startup) 2 (stabilized)(3) C = 10 pF, fOSC = 24 MHz 6 (startup) 1.5 (stabilized)(3) Oscillator transconductance mA 5 tSU(HSE)(4) Startup time mA/V VDD is stabilized 1 ms 1. C is approximately equivalent to 2 x crystal Cload. 2. The oscillator selection can be optimized in terms of supply current using a high quality resonator with small Rm value. Refer to crystal manufacturer for more details 3. Data based on characterization results, not tested in production. 4. tSU(HSE) is the start-up time measured from the moment it is enabled (by software) to a stabilized 24 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer. Figure 17. HSE oscillator circuit diagram fHSE to core Rm RF CO Lm CL1 OSCIN Cm gm Resonator Resonator Consumption control STM8 OSCOUT CL2 HSE oscillator critical gm formula g mcrit = ( 2 x x f HSE ) 2 x R m ( 2Co + C ) 2 Rm: Notional resistance (see crystal specification) Lm: Notional inductance (see crystal specification) Cm: Notional capacitance (see crystal specification) Co: Shunt capacitance (see crystal specification) CL1=CL2=C: Grounded external capacitance gm >> gmcrit Doc ID 14733 Rev 12 65/103 Electrical characteristics 10.3.4 STM8S207xx, STM8S208xx Internal clock sources and timing characteristics Subject to general operating conditions for VDD and TA. fHSE High speed internal RC oscillator (HSI) Table 33. Symbol fHSI HSI oscillator characteristics Parameter Conditions Min Typ Frequency 16 Trimmed by the CLK_HSITRIMR register Accuracy of HSI oscillator for given VDD and TA conditions ACCHSI tsu(HSI) HSI oscillator wakeup time including calibration IDD(HSI) HSI oscillator power consumption 1.0 VDD = 5 V, TA = 25 C -1.5 1.5 VDD = 5 V, 25 C TA 85 C -2.2 2.2 -3.0(2) 3.0(2) 170 1. Guaranteeed by design, not tested in production. 2. Data based on characterization results, not tested in production Figure 18. Typical HSI frequency variation vs VDD at 4 temperatures -40C 25C 3% 85C % accuracy 2% 125C 1% 0% -1% -2% -3% 2.5 3 3.5 4 4.5 5 5.5 6 VDD (V) ai15067 Doc ID 14733 Rev 12 Unit MHz -1.0(1) Accuracy of HSI oscillator 2.95 V VDD 5.5 V, (factory calibrated) -40 C TA 125 C 66/103 Max % 1.0(1) s 250(2) A STM8S207xx, STM8S208xx Electrical characteristics Low speed internal RC oscillator (LSI) Subject to general operating conditions for VDD and TA. Table 34. LSI oscillator characteristics Symbol fLSI Parameter Conditions Frequency tsu(LSI) LSI oscillator wakeup time IDD(LSI) LSI oscillator power consumption Min Typ Max Unit 110 128 146 kHz 7(1) s 5 A 1. Guaranteeed by design, not tested in production. Figure 19. Typical LSI frequency variation vs VDD @ 25 C 3% % accuracy 2% 1% 0% -1% -2% -3% 2.5 3 3.5 4 4.5 5 5.5 6 VDD [V] ai15070 Doc ID 14733 Rev 12 67/103 Electrical characteristics 10.3.5 STM8S207xx, STM8S208xx Memory characteristics RAM and hardware registers Table 35. RAM and hardware registers Symbol Parameter Conditions Min Unit VRM Data retention mode(1) Halt mode (or reset) VIT-max(2) V 1. Minimum supply voltage without losing data stored in RAM (in halt mode or under reset) or in hardware registers (only in halt mode). Guaranteed by design, not tested in production. 2. Refer to Table 19 on page 56 for the value of VIT-max. Flash program memory/data EEPROM memory General conditions: TA = -40 to 125 C. Table 36. Symbol VDD tprog terase Flash program memory/data EEPROM memory Parameter Operating voltage (all modes, execution/write/erase) Conditions fCPU 24 MHz tRET IDD 2.95 Max Unit 5.5 V Standard programming time (including erase) for byte/word/block (1 byte/4 bytes/128 bytes) 6 6.6 ms Fast programming time for 1 block (128 bytes) 3 3.3 ms Erase time for 1 block (128 bytes) 3 3.3 ms cycles(2) NRW Min(1) Typ Erase/write (program memory) TA = 85 C 10 k Erase/write cycles (data memory)(2) TA = 125 C 300 k Data retention (program memory) after 10 k erase/write cycles at TA = 85 C TRET = 55 C 20 Data retention (data memory) after 10 k erase/write cycles at TA = 85 C TRET = 55 C 20 Data retention (data memory) after 300k erase/write cycles at TA = 125 C TRET = 85 C 1 Supply current (Flash programming or erasing for 1 to 128 bytes) cycles 1M years 2 1. Data based on characterization results, not tested in production. 2. The physical granularity of the memory is 4 bytes, so cycling is performed on 4 bytes even when a write/erase operation addresses a single byte. 68/103 Doc ID 14733 Rev 12 mA STM8S207xx, STM8S208xx 10.3.6 Electrical characteristics I/O port pin characteristics General characteristics Subject to general operating conditions for VDD and TA unless otherwise specified. All unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or an external pull-up or pull-down resistor. Table 37. Symbol I/O static characteristics Parameter VIL Input low level voltage VIH Input high level voltage Vhys Hysteresis(1) Rpu Pull-up resistor Conditions Min Typ -0.3 Max Unit 0.3 x VDD V tR, tF Rise and fall time (10% - 90%) VDD = 5 V VDD + 0.3 V 0.7 x VDD 700 VDD = 5 V, VIN = VSS 30 55 mV 80 Fast I/Os Load = 50 pF 20 (2) Standard and high sink I/Os Load = 50 pF 125 (2) k ns Fast I/Os Load = 20 pF 35(3) Standard and high sink I/Os Load = 20 pF 125(3) Input leakage current, analog and digital VSS VIN VDD 1 A Ilkg ana Analog input leakage current VSS VIN VDD 250 (2) nA Ilkg(inj) Leakage current in adjacent I/O(2) Injection current 4 mA 1(2) A Ilkg 1. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested in production. 2. Data based on characterization results, not tested in production. 3. Guaranteed by design. Doc ID 14733 Rev 12 69/103 Electrical characteristics STM8S207xx, STM8S208xx Figure 20. Typical VIL and VIH vs VDD @ 4 temperatures -40C 6 25C 85C 5 VIL/VIH [V] 125C 4 3 2 1 0 2.5 3 3.5 4 4.5 5 5.5 6 VDD [V] Figure 21. Typical pull-up resistance vs VDD @ 4 temperatures -40C 25C 60 Pull-up resistance [W] 85C 55 125C 50 45 40 35 30 2.5 3 3.5 4 4.5 5 5.5 6 VDD [V] Figure 22. Typical pull-up current vs VDD @ 4 temperatures 140 Pull-Up current [A] 120 100 80 -40C 60 25C 40 85C 125C 20 0 0 1 2 3 4 5 6 VDD [V] ai15068 1. The pull-up is a pure resistor (slope goes through 0). 70/103 Doc ID 14733 Rev 12 STM8S207xx, STM8S208xx Table 38. Symbol VOL VOH Electrical characteristics Output driving current (standard ports) Parameter Conditions Min Max Output low level with 8 pins sunk IIO = 10 mA, VDD = 5 V 2 Output low level with 4 pins sunk IIO = 4 mA, VDD = 3.3 V 1(1) Output high level with 8 pins sourced IIO = 10 mA, VDD = 5 V 2.8 Output high level with 4 pins sourced IIO = 4 mA, VDD = 3.3 V 2.1(1) Unit V V 1. Data based on characterization results, not tested in production Table 39. Symbol Output driving current (true open drain ports) Parameter Conditions Max IIO = 10 mA, VDD = 5 V VOL Output low level with 2 pins sunk Unit 1 1.5(1) IIO = 10 mA, VDD = 3.3 V V 2(1) IIO = 20 mA, VDD = 5 V 1. Data based on characterization results, not tested in production Table 40. Symbol VOL VOH Output driving current (high sink ports) Parameter Conditions Min Max Output low level with 8 pins sunk IIO = 10 mA,VDD = 5 V 0.8 Output low level with 4 pins sunk IIO = 10 mA,VDD = 3.3 V 1(1) Output low level with 4 pins sunk IIO = 20 mA,VDD = 5 V Output high level with 8 pins sourced IIO = 10 mA, VDD = 5 V Output high level with 4 pins sourced IIO = 10 mA, VDD = 3.3 V 2.1(1) Output high level with 4 pins sourced IIO = 20 mA, VDD = 5 V 3.3(1) Unit 1.5(1) V 4.0 1. Data based on characterization results, not tested in production Doc ID 14733 Rev 12 71/103 Electrical characteristics STM8S207xx, STM8S208xx Typical output level curves Figure 24 to Figure 31 show typical output level curves measured with output on a single pin. Figure 23. Typ. VOL @ VDD = 5 V (standard ports) -40C 1.5 25C 85C 1.25 125C VOL [V] 1 0.75 0.5 0.25 0 0 2 4 6 8 10 12 IOL [mA] Figure 24. Typ. VOL @ VDD = 3.3 V (standard ports) -40C 1.5 25C 85C 1.25 125C VOL [V] 1 0.75 0.5 VOL [V] 0.25 0 0 1 2 3 4 5 6 7 IOL [mA] Figure 25. Typ. VOL @ VDD = 5 V (true open drain ports) -40C 2 VOL [V] 25C 1.75 85C 1.5 125C 1.25 1 0.75 0.5 0.25 0 0 5 10 15 IOL [mA] 72/103 Doc ID 14733 Rev 12 20 25 STM8S207xx, STM8S208xx Electrical characteristics Figure 26. Typ. VOL @ VDD = 3.3 V (true open drain ports) -40C 2 IOL [mA] 25C 1.75 85C 1.5 125C 1.25 1 0.75 0.5 0.25 0 0 2 4 6 8 10 12 14 VOL [V] Figure 27. Typ. VOL @ VDD = 5 V (high sink ports) -40C 1.5 25C 85C 1.25 125C VOL [V] 1 0.75 0.5 0.25 0 0 5 10 15 20 25 IOL [mA] Figure 28. Typ. VOL @ VDD = 3.3 V (high sink ports) -40C 1.5 25C 85C 1.25 125C VOL [V] 1 0.75 0.5 0.25 0 0 2 4 6 8 10 12 14 IOL [mA] Doc ID 14733 Rev 12 73/103 Electrical characteristics STM8S207xx, STM8S208xx Figure 29. Typ. VDD - VOH @ VDD = 5 V (standard ports) -40C 2 VDD - VOH [V] 25C 1.75 85C 1.5 125C 1.25 1 0.75 0.5 0.25 0 0 2 4 6 8 10 12 IOL [mA] Figure 30. Typ. VDD - VOH @ VDD = 3.3 V (standard ports) -40C 2 VDD - VOH [V] 25C 1.75 85C 1.5 125C 1.25 1 0.75 0.5 0.25 0 0 1 2 3 4 5 6 7 IOL [mA] Figure 31. Typ. VDD - VOH @ VDD = 5 V (high sink ports) -40C 2 VDD - VOH [V] 25C 1.75 85C 1.5 125C 1.25 1 0.75 0.5 0.25 0 0 5 10 15 IOL [mA] 74/103 Doc ID 14733 Rev 12 20 25 STM8S207xx, STM8S208xx Electrical characteristics Figure 32. Typ. VDD - VOH @ VDD = 3.3 V (high sink ports) -40C 2 VDD - VOH [V] 25C 1.75 85C 1.5 125C 1.25 1 0.75 0.5 0.25 0 0 2 4 6 8 10 12 14 IOL [mA] 10.3.7 Reset pin characteristics Subject to general operating conditions for VDD and TA unless otherwise specified. Table 41. Symbol VIL(NRST) VIH(NRST) VOL(NRST) NRST pin characteristics Parameter Conditions NRST Input low level voltage (1) NRST Input high level voltage tIFP(NRST) NRST Input filtered pulse (3) NRST Input not filtered NRST output pulse (1) Typ 1) Max -0.3 V 0.3 x VDD 0.7 x VDD VDD + 0.3 IOL= 2 mA Unit V 0.5 (2) NRST Pull-up resistor tOP(NRST) (1) NRST Output low level voltage RPU(NRST) tINFP(NRST) Min 30 pulse (3) (1) 55 80 k 75 ns 500 ns 15 s 1. Data based on characterization results, not tested in production. 2. The RPU pull-up equivalent resistor is based on a resistive transistor Data guaranteed by design, not tested in production. Figure 33. Typical NRST VIL and VIH vs VDD @ 4 temperatures -40C 6 25C 85C 5 125C 4 VIL/VIH [V] 3. 3 2 1 0 2.5 3 3.5 4 4.5 5 5.5 6 VDD [V] Doc ID 14733 Rev 12 75/103 Electrical characteristics STM8S207xx, STM8S208xx Figure 34. Typical NRST pull-up resistance vs VDD @ 4 temperatures -40C 25C 60 NRESET pull-up resistance [W] 85C 55 125C 50 45 40 35 30 2.5 3 3.5 4 4.5 5 5.5 6 VDD [V] Figure 35. Typical NRST pull-up current vs VDD @ 4 temperatures 140 NRESET Pull-Up current [A] 120 100 80 -40C 60 25C 40 85C 20 125C 0 0 1 2 3 VDD [V] 4 5 6 ai15069 The reset network shown in Figure 36 protects the device against parasitic resets. The user must ensure that the level on the NRST pin can go below the VIL max. level specified in Table 41. Otherwise the reset is not taken into account internally. For power consumption sensitive applications, the capacity of the external reset capacitor can be reduced to limit charge/discharge current. If the NRSTsignal is used to reset the external circuitry, care must be taken of the charge/discharge time of the external capacitor to fulfill the external device's reset timing conditions. The minimum recommended capacity is 10 nF. Figure 36. Recommended reset pin protection STM8 VDD RPU External reset circuit (optional) 76/103 NRST 0.1F Doc ID 14733 Rev 12 Filter Internal reset STM8S207xx, STM8S208xx Electrical characteristics SPI serial peripheral interface 10.3.8 Unless otherwise specified, the parameters given in Table 42 are derived from tests performed under ambient temperature, fMASTER frequency and VDD supply voltage conditions. tMASTER = 1/fMASTER. Refer to I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). Table 42. SPI characteristics Symbol Parameter fSCK 1/tc(SCK) SPI clock frequency tr(SCK) tf(SCK) Conditions Min Max Master mode 0 10 Slave mode 0 6 Unit MHz SPI clock rise and fall time Capacitive load: C = 30 pF 25 tsu(NSS)(1) NSS setup time Slave mode 4 x tMASTER th(NSS)(1) NSS hold time Slave mode 70 SCK high and low time Master mode tSCK/2 - 15 Master mode 5 Slave mode 5 Master mode 7 Slave mode 10 (1) tw(SCKH) tw(SCKL)(1) tsu(MI) (1) tsu(SI)(1) Data input setup time th(MI) (1) th(SI)(1) Data input hold time (1)(2) Data output access time Slave mode tdis(SO)(1)(3) Data output disable time Slave mode ta(SO) tSCK/2 + 15 ns 3 x tMASTER 25 (1) Data output valid time Slave mode (after enable edge) 75 tv(MO)(1) Data output valid time Master mode (after enable edge) 30 tv(SO) th(SO) (1) th(MO)(1) Slave mode (after enable edge) 31 Master mode (after enable edge) 12 Data output hold time 1. Values based on design simulation and/or characterization results, and not tested in production. 2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. 3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z. Doc ID 14733 Rev 12 77/103 Electrical characteristics STM8S207xx, STM8S208xx Figure 37. SPI timing diagram - slave mode and CPHA = 0 NSS input tSU(NSS) SCK Input CPHA= 0 CPOL=0 tc(SCK) th(NSS) tw(SCKH) tw(SCKL) CPHA= 0 CPOL=1 tv(SO) ta(SO) MISO OUT P UT tr(SCK) tf(SCK) th(SO) MS B O UT BI T6 OUT tdis(SO) LSB OUT tsu(SI) MOSI I NPUT M SB IN LSB IN B I T1 IN th(SI) ai14134 Figure 38. SPI timing diagram - slave mode and CPHA = 1(1) NSS input tSU(NSS) SCK Input CPHA=1 CPOL=0 CPHA=1 CPOL=1 tc(SCK) tw(SCKH) tw(SCKL) tv(SO) ta(SO) MISO OUT P UT MS B O UT tsu(SI) MOSI I NPUT th(NSS) th(SO) BI T6 OUT tr(SCK) tf(SCK) tdis(SO) LSB OUT th(SI) B I T1 IN M SB IN LSB IN ai14135 1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD. 78/103 Doc ID 14733 Rev 12 STM8S207xx, STM8S208xx Electrical characteristics Figure 39. SPI timing diagram - master mode(1) High NSS input SCK Input SCK Input tc(SCK) CPHA= 0 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=0 CPHA=1 CPOL=1 tsu(MI) MISO INP UT tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) MS BIN BI T6 IN LSB IN th(MI) MOSI OUTUT M SB OUT tv(MO) B I T1 OUT LSB OUT th(MO) ai14136 1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD. Doc ID 14733 Rev 12 79/103 Electrical characteristics 10.3.9 STM8S207xx, STM8S208xx I2C interface characteristics Table 43. I2C characteristics Standard mode I2C Fast mode I2C(1) Symbol Parameter Min(2) Max(2) Min(2) Max(2) Unit tw(SCLL) SCL clock low time 4.7 1.3 tw(SCLH) SCL clock high time 4.0 0.6 tsu(SDA) SDA setup time 250 100 th(SDA) SDA data hold time 0(3) 0(4) tr(SDA) tr(SCL) SDA and SCL rise time 1000 300 tf(SDA) tf(SCL) SDA and SCL fall time 300 300 th(STA) START condition hold time 4.0 0.6 tsu(STA) Repeated START condition setup time 4.7 0.6 tsu(STO) STOP condition setup time 4.0 0.6 s STOP to START condition time (bus free) 4.7 1.3 s tw(STO:STA) Cb s 900(3) s Capacitive load for each bus line 1. fMASTER, must be at least 8 MHz to achieve max fast 400 I 2C 400 speed (400kHz) 2. Data based on standard I2C protocol requirement, not tested in production 3. The maximum hold time of the start condition has only to be met if the interface does not stretch the low time 4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL 80/103 ns Doc ID 14733 Rev 12 pF STM8S207xx, STM8S208xx Electrical characteristics Figure 40. Typical application with I2C bus and timing diagram 6$$ 6$$ 34-3XXX 3$! )# BUS 3#, 3 4!24 2%0%!4%$ 3 4!24 3 4!24 TSU34! 3$! TF3$! TR3$! TH34! 3#, TW3#,( TSU3$! TW3#,, TR3#, TH3$! TF3#, TSU34!34/ 3 4/0 TSU34/ AI 1. Measurement points are made at CMOS levels: 0.3 x VDD and 0.7 x VDD Doc ID 14733 Rev 12 81/103 Electrical characteristics 10.3.10 STM8S207xx, STM8S208xx 10-bit ADC characteristics Subject to general operating conditions for VDDA, fMASTER, and TA unless otherwise specified. Table 44. Symbol fADC ADC characteristics Parameter Conditions Min Typ Max VDDA = 3 to 5.5 V 1 4 VDDA = 4.5 to 5.5 V 1 6 3 5.5 V ADC clock frequency Unit MHz VDDA Analog supply VREF+ Positive reference voltage 2.75(1) VDDA V VREF- Negative reference voltage VSSA 0.5(1) V VSSA VDDA V VAIN Conversion voltage range(2) VREF- VREF+ V CADC Internal sample and hold capacitor tS(2) Sampling time tSTAB Wakeup time from standby tCONV Total conversion time (including sampling time, 10-bit resolution) Devices with external VREF+/VREF- pins 3 fADC = 4 MHz 0.75 fADC = 6 MHz 0.5 pF s 7 s fADC = 4 MHz 3.5 s fADC = 6 MHz 2.33 s 14 1/fADC 1. Data guaranteed by design, not tested in production.. 2. During the sample time the input capacitance CAIN (3 pF max) can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion result. Values for the sample clock tS depend on programming. 82/103 Doc ID 14733 Rev 12 STM8S207xx, STM8S208xx Table 45. Symbol |ET| |EO| |EG| |ED| |EL| Electrical characteristics ADC accuracy with RAIN < 10 k , VDDA = 5 V Parameter Total unadjusted error Offset error (2) (2) Gain error (2) Differential linearity Integral linearity error (2) error (2) Conditions Typ Max(1) fADC = 2 MHz 1 2.5 fADC = 4 MHz 1.4 3 fADC = 6 MHz 1.6 3.5 fADC = 2 MHz 0.6 2 fADC = 4 MHz 1.1 2.5 fADC = 6 MHz 1.2 2.5 fADC = 2 MHz 0.2 2 fADC = 4 MHz 0.6 2.5 fADC = 6 MHz 0.8 2.5 fADC = 2 MHz 0.7 1.5 fADC = 4 MHz 0.7 1.5 fADC = 6 MHz 0.8 1.5 fADC = 2 MHz 0.6 1.5 fADC = 4 MHz 0.6 1.5 fADC = 6 MHz 0.6 1.5 Unit LSB 1. Data based on characterisation results for LQFP80 device with VREF+/VREF-, not tested in production. 2. ADC accuracy vs. negative injection current: Injecting negative current on any of the analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 10.3.6 does not affect the ADC accuracy. Table 46. Symbol ADC accuracy with RAIN < 10 k RAIN, VDDA = 3.3 V Parameter |ET| Total unadjusted error(2) |EO| Offset error(2) |EG| Gain error(2) |ED| Differential linearity error(2) |EL| Integral linearity error(2) Conditions Typ Max(1) fADC = 2 MHz 1.1 2 fADC = 4 MHz 1.6 2.5 fADC = 2 MHz 0.7 1.5 fADC = 4 MHz 1.3 2 fADC = 2 MHz 0.2 1.5 fADC = 4 MHz 0.5 2 fADC = 2 MHz 0.7 1 fADC = 4 MHz 0.7 1 fADC = 2 MHz 0.6 1.5 fADC = 4 MHz 0.6 1.5 Doc ID 14733 Rev 12 Unit LSB 83/103 Electrical characteristics STM8S207xx, STM8S208xx Figure 41. ADC accuracy characteristics EG 1023 1022 1021 1LSB IDEAL V -V DDA SSA = ----------------------------------------1024 (2) ET 7 (3) (1) 6 5 EO 4 EL 3 ED 2 1 LSBIDEAL 1 0 1 VSSA 2 3 4 5 6 7 1021102210231024 VDDA 1. Example of an actual transfer curve. 2. The ideal transfer curve 3. End point correlation line ET = Total unadjusted error: maximum deviation between the actual and the ideal transfer curves. EO = Offset error: deviation between the first actual transition and the first ideal one. EG = Gain error: deviation between the last ideal transition and the last actual one. ED = Differential linearity error: maximum deviation between actual steps and the ideal one. EL = Integral linearity error: maximum deviation between any actual transition and the end point correlation line. Figure 42. Typical application with ADC VDD VT 0.6V RAIN AINx VAIN CAIN 84/103 STM8 10-bit A/D conversion VT 0.6V Doc ID 14733 Rev 12 IL 1A CADC STM8S207xx, STM8S208xx 10.3.11 Electrical characteristics EMC characteristics Susceptibility tests are performed on a sample basis during product characterization. Functional EMS (electromagnetic susceptibility) While executing a simple application (toggling 2 LEDs through I/O ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the LEDs). ESD: Electrostatic discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. This test conforms with the IEC 61000-4-2 standard. FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test conforms with the IEC 61000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in the table below based on the EMS levels and classes defined in application note AN1709. Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as: Corrupted program counter Unexpected reset Critical data corruption (control registers...) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be recovered by applying a low state on the NRST pin or the oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Table 47. Symbol EMS data Parameter Conditions Level/class VFESD VDD = 5 V, TA = 25 C, Voltage limits to be applied on any I/O pin to fMASTER = 16 MHz, induce a functional disturbance conforming to IEC 61000-4-2 2B VEFTB Fast transient voltage burst limits to be VDD = 5 V, TA = 25 C, applied through 100pF on VDD and VSS pins fMASTER = 16 MHz, to induce a functional disturbance conforming to IEC 61000-4-4 4A Doc ID 14733 Rev 12 85/103 Electrical characteristics STM8S207xx, STM8S208xx Electromagnetic interference (EMI) Emission tests conform to the SAE IEC 61967-2 standard for test software, board layout and pin loading. Table 48. EMI data Conditions Symbol Max fHSE/fCPU(1) Parameter Monitored frequency band General conditions Peak level SEMI SAE EMI level VDD = 5 V TA = 25 C LQFP80 package conforming to SAE IEC 61967-2 Unit 8 MHz/ 8 MHz/ 8 MHz/ 8 MHz 16 MHz 24 MHz 0.1MHz to 30 MHz 15 20 24 30 MHz to 130 MHz 18 21 16 130 MHz to 1 GHz -1 1 4 SAE EMI level 2 2.5 2.5 dBV 1. Data based on characterization results, not tested in production. Absolute maximum ratings (electrical sensitivity) Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. For more details, refer to the application note AN1181. Electrostatic discharge (ESD) Electrostatic discharges (3 positive then 3 negative pulses separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). This test conforms to the JESD22-A114A/A115A standard. For more details, refer to the application note AN1181. Table 49. Symbol ESD absolute maximum ratings Ratings Conditions Class VESD(HBM) Electrostatic discharge voltage (Human body model) TA = 25C, conforming to JESD22-A114 A 2000 V VESD(CDM) Electrostatic discharge voltage (Charge device model) TA= 25C, conforming to JESD22-C101 IV 1000 V 1. Data based on characterization results, not tested in production. 86/103 Maximum Unit value(1) Doc ID 14733 Rev 12 STM8S207xx, STM8S208xx Electrical characteristics Static latch-up Two complementary static tests are required on 10 parts to assess the latch-up performance: A supply overvoltage (applied to each power supply pin) A current injection (applied to each input, output and configurable I/O pin) is performed on each sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the application note AN1181. Table 50. Symbol LU Electrical sensitivities Parameter Conditions Static latch-up class Class(1) TA = 25 C A TA = 85 C A TA = 125 C A 1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC specifications, that means when a device belongs to class A it exceeds the JEDEC standard. B class strictly covers all the JEDEC criteria (international standard). Doc ID 14733 Rev 12 87/103 Package characteristics 11 STM8S207xx, STM8S208xx Package characteristics To meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at www.st.com. ECOPACK(R) is an ST trademark. 88/103 Doc ID 14733 Rev 12 STM8S207xx, STM8S208xx Package characteristics 11.1 Package mechanical data 11.1.1 LQFP package mechanical data Figure 43. 80-pin low profile quad flat package (14 x 14) D ccc C D1 A A2 D3 41 60 40 61 b L1 E3 E1 E L A1 K 80 Pin 1 identification Table 51. 1 c 1S_ME 80-pin low profile quad flat package mechanical data inches(1) mm Symbol Min Typ A Max Min Typ 1.600 A1 0.050 A2 1.350 b 0.220 c 0.090 D 15.800 D1 13.800 D3 Max 0.0630 0.150 0.0020 1.400 1.450 0.0531 0.0551 0.0571 0.320 0.380 0.0087 0.0126 0.0150 0.200 0.0035 16.000 16.200 0.6220 0.6299 0.6378 14.000 14.200 0.5433 0.5512 0.5591 12.350 0.0059 0.0079 0.4862 E 15.800 16.000 16.200 0.6220 0.6299 0.6378 E1 13.800 14.000 14.200 0.5433 0.5512 0.5591 E3 12.350 0.4862 e 0.650 0.0256 L 0.450 L1 k ccc 0.600 0.750 0.0177 1.000 0.0 3.5 0.0236 0.0295 0.0394 7.0 0.0 0.100 3.5 7.0 0.0039 1. Values in inches are converted from mm and rounded to four decimal places. Doc ID 14733 Rev 12 89/103 Package characteristics STM8S207xx, STM8S208xx Figure 44. 64-pin low profile quad flat package (14 x 14) D ccc C D1 A A2 D3 33 48 32 49 b L1 E3 E1 E L A1 K 64 17 Pin 1 identification Table 52. 16 1 c 1R_ME 64-pin low profile quad flat package mechanical data (14 x 14) inches(1) mm Symbol Min Typ A Max Min 1.600 A1 0.050 A2 1.350 b 0.300 C 0.090 D 15.800 D1 13.800 D3 Max 0.0630 0.150 0.0020 1.400 1.450 0.0531 0.0551 0.0571 0.370 0.450 0.0118 0.0146 0.0177 0.200 0.0035 16.000 16.200 0.6220 0.6299 0.6378 14.000 14.200 0.5433 0.5512 0.5591 12.000 0.0059 0.0079 0.4724 E 15.800 16.000 16.200 0.6220 0.6299 0.6378 E1 13.800 14.000 14.200 0.5433 0.5512 0.5591 E3 12.000 0.4724 e 0.800 0.0315 L 0.450 L1 k ccc 0.600 0.750 0.0177 1.000 0.0 3.5 0.0236 0.0295 0.0394 7.0 0.0 0.100 1. Values in inches are converted from mm and rounded to four decimal places. 90/103 Typ Doc ID 14733 Rev 12 3.5 7.0 0.0039 STM8S207xx, STM8S208xx Package characteristics Figure 45. 64-pin low profile quad flat package (10 x 10) D ccc C D1 A A2 D3 33 48 32 49 b L1 E3 E1 E L A1 K 64 17 Pin 1 identification Table 53. 16 1 c 5W_ME 64-pin low profile quad flat package mechanical data (10 x 10) inches(1) mm Symbol Min Typ A Max Min Typ 1.600 A1 0.050 A2 1.350 b 0.170 C 0.090 Max 0.0630 0.150 0.0020 0.0059 1.400 1.450 0.0531 0.0551 0.0571 0.220 0.270 0.0067 0.0087 0.0106 0.200 0.0035 0.0079 D 12.000 0.4724 D1 10.000 0.3937 E 12.000 0.4724 E1 10.000 0.3937 e 0.500 0.0197 K 0.000 3.500 7.000 0.0000 3.5000 7.0000 L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 1.000 0.0394 1. Values in inches are converted from mm and rounded to four decimal places. Doc ID 14733 Rev 12 91/103 Package characteristics STM8S207xx, STM8S208xx Figure 46. 48-pin low profile quad flat package (7 x 7) D ccc C D1 D3 A A2 25 36 24 37 L1 b E3 E1 E 48 Pin 1 identification 13 1 L A1 K c 12 5B_ME Table 54. 48-pin low profile quad flat package mechanical data inches(1) mm Symbol Min Typ A Max Min 1.600 A1 0.050 A2 1.350 b 0.170 c 0.090 D 8.800 D1 6.800 D3 Max 0.0630 0.150 0.0020 1.400 1.450 0.0531 0.0551 0.0571 0.220 0.270 0.0067 0.0087 0.0106 0.200 0.0035 9.000 9.200 0.3465 0.3543 0.3622 7.000 7.200 0.2677 0.2756 0.2835 5.500 0.0059 0.0079 0.2165 E 8.800 9.000 9.200 0.3465 0.3543 0.3622 E1 6.800 7.000 7.200 0.2677 0.2756 0.2835 E3 5.500 0.2165 e 0.500 0.0197 L 0.450 L1 k ccc 0.600 0.750 0.0177 1.000 0.0 3.5 0.0236 0.0295 0.0394 7.0 0.0 0.080 1. Values in inches are converted from mm and rounded to four decimal places. 92/103 Typ Doc ID 14733 Rev 12 3.5 7.0 0.0031 STM8S207xx, STM8S208xx Package characteristics Figure 47. 44-pin low profile quad flat package (10 x 10) D ccc C D1 D3 A A2 23 33 22 34 L1 b E3 E1 E 44 Pin 1 identification 12 1 L A1 K c 11 4Y_ME Table 55. 44-pin low profile quad flat package mechanical data inches(1) mm Symbol Min Typ A Max Min Typ 1.600 A1 0.050 A2 1.350 b 0.300 c 0.090 D 11.800 D1 9.800 D3 Max 0.0630 0.150 0.0020 1.400 1.450 0.0531 0.0551 0.0571 0.370 0.450 0.0118 0.0146 0.0177 0.200 0.0035 12.000 12.200 0.4646 0.4724 0.4803 10.000 10.200 0.3858 0.3937 0.4016 8.000 0.0059 0.0079 0.3150 E 11.800 12.000 12.200 0.4646 0.4724 0.4803 E1 9.800 10.000 10.200 0.3858 0.3937 0.4016 E3 8.000 0.3150 e 0.800 0.0315 L 0.450 L1 k ccc 0.600 0.750 0.0177 1.000 0.0 3.5 0.0236 0.0295 0.0394 7.0 0.0 0.100 3.5 7.0 0.0039 1. Values in inches are converted from mm and rounded to four decimal places. Doc ID 14733 Rev 12 93/103 Package characteristics STM8S207xx, STM8S208xx Figure 48. 32-pin low profile quad flat package (7 x 7) ccc C D D1 D3 24 A A2 17 16 25 L1 b E3 32 9 Pin 1 identification Table 56. E1 E L A1 1 K c 8 32-pin low profile quad flat package mechanical data inches(1) mm Symbol Min Typ A Max Min 1.600 A1 0.050 A2 1.350 b 0.300 c 0.090 D 8.800 D1 6.800 D3 Max 0.0630 0.150 0.0020 1.400 1.450 0.0531 0.0551 0.0571 0.370 0.450 0.0118 0.0146 0.0177 0.200 0.0035 9.000 9.200 0.3465 0.3543 0.3622 7.000 7.200 0.2677 0.2756 0.2835 5.600 0.0059 0.0079 0.2205 E 8.800 9.000 9.200 0.3465 0.3543 0.3622 E1 6.800 7.000 7.200 0.2677 0.2756 0.2835 E3 5.600 0.2205 e 0.800 0.0315 L 0.450 L1 k ccc 0.600 0.750 0.0177 1.000 0.0 3.5 0.0236 0.0295 0.0394 7.0 0.0 0.100 1. Values in inches are converted from mm and rounded to four decimal places. 94/103 Typ Doc ID 14733 Rev 12 3.5 7.0 0.0039 STM8S207xx, STM8S208xx 11.2 Package characteristics Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 18: General operating conditions on page 55. The maximum chip-junction temperature, TJmax, in degrees Celsius, may be calculated using the following equation: TJmax = TAmax + (PDmax x JA) Where: TAmax is the maximum ambient temperature in C JA is the package junction-to-ambient thermal resistance in C/W PDmax is the sum of PINTmax and PI/Omax (PDmax = PINTmax + PI/Omax) PINTmax is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power. PI/Omax represents the maximum power dissipation on output pins, where: PI/Omax = (VOL*IOL) + ((VDD-VOH)*IOH), and taking account of the actual VOL/IOL and VOH/IOH of the I/Os at low and high level in the application. Table 57. Thermal characteristics(1) Symbol Parameter Value Unit JA Thermal resistance junction-ambient LQFP 80 - 14 x 14 mm 38 C/W JA Thermal resistance junction-ambient LQFP 64 - 14 x 14 mm 45 C/W JA Thermal resistance junction-ambient LQFP 64 - 10 x 10 mm 46 C/W JA Thermal resistance junction-ambient LQFP 48 - 7 x 7 mm 57 C/W JA Thermal resistance junction-ambient LQFP 44 - 10 x 10 mm 54 C/W JA Thermal resistance junction-ambient LQFP 32 - 7 x 7 mm 60 C/W 1. Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in a natural convection environment. 11.2.1 Reference document JESD51-2 integrated circuits thermal test method environment conditions - natural convection (still air). Available from www.jedec.org. Doc ID 14733 Rev 12 95/103 Package characteristics 11.2.2 STM8S207xx, STM8S208xx Selecting the product temperature range When ordering the microcontroller, the temperature range is specified in the order code (see Figure 49: STM8S207xx/208xx performance line ordering information scheme(1) on page 99). The following example shows how to calculate the temperature range needed for a given application. Assuming the following application conditions: Maximum ambient temperature TAmax= 82 C (measured according to JESD51-2) IDDmax = 15 mA, VDD = 5.5 V Maximum eight standard I/Os used at the same time in output at low level with IOL = 10 mA, VOL= 2 V Maximum four high sink I/Os used at the same time in output at low level with IOL = 20 mA, VOL= 1.5 V Maximum two true open drain I/Os used at the same time in output at low level with IOL = 20 mA, VOL= 2 V PINTmax = 15 mA x 5.5 V = 82.5 mW PIOmax = (10 mA x 2 V x 8 ) + (20 mA x 2 V x 2) + (20 mA x 1.5 V x 4) = 360 mW This gives: PINTmax = 82.5 mW and PIOmax 360 mW: PDmax = 82.5 mW + 360 mW Thus: PDmax = 443 mW Using the values obtained in Table 57: Thermal characteristics on page 95 TJmax is calculated as follows for LQFP64 10 x 10 mm = 46 C/W: TJmax = 82 C + (46 C/W x 443 mW) = 82 C + 20 C = 102 C This is within the range of the suffix 6 version parts (-40 < TJ < 105 C). In this case, parts must be ordered at least with the temperature range suffix 6. 96/103 Doc ID 14733 Rev 12 STM8S207xx, STM8S208xx 12 STM8 development tools STM8 development tools Development tools for the STM8 microcontrollers include the full-featured STice emulation system supported by a complete software tool package including C compiler, assembler and integrated development environment with high-level language debugger. In addition, the STM8 is to be supported by a complete range of tools including starter kits, evaluation boards and a low-cost in-circuit debugger/programmer. 12.1 Emulation and in-circuit debugging tools The STice emulation system offers a complete range of emulation and in-circuit debugging features on a platform that is designed for versatility and cost-effectiveness. In addition, STM8 application development is supported by a low-cost in-circuit debugger/programmer. The STice is the fourth generation of full featured emulators from STMicroelectronics. It offers new advanced debugging capabilities including profiling and coverage to help detect and eliminate bottlenecks in application execution and dead code when fine tuning an application. In addition, STice offers in-circuit debugging and programming of STM8 microcontrollers via the STM8 single wire interface module (SWIM), which allows non-intrusive debugging of an application while it runs on the target microcontroller. For improved cost effectiveness, STice is based on a modular design that allows you to order exactly what you need to meet your development requirements and to adapt your emulation system to support existing and future ST microcontrollers. STice key features Occurrence and time profiling and code coverage (new features) Advanced breakpoints with up to 4 levels of conditions Data breakpoints Program and data trace recording up to 128 KB records Read/write on the fly of memory during emulation In-circuit debugging/programming via SWIM protocol 8-bit probe analyzer 1 input and 2 output triggers Power supply follower managing application voltages between 1.62 to 5.5 V Modularity that allows you to specify the components you need to meet your development requirements and adapt to future requirements Supported by free software tools that include integrated development environment (IDE), programming software interface and assembler for STM8. Doc ID 14733 Rev 12 97/103 STM8 development tools 12.2 STM8S207xx, STM8S208xx Software tools STM8 development tools are supported by a complete, free software package from STMicroelectronics that includes ST Visual Develop (STVD) IDE and the ST Visual Programmer (STVP) software interface. STVD provides seamless integration of the Cosmic and Raisonance C compilers for STM8. A free version that outputs up to 32 Kbytes of code is available. 12.2.1 STM8 toolset STM8 toolset with STVD integrated development environment and STVP programming software is available for free download at www.st.com/mcu. This package includes: ST Visual Develop - Full-featured integrated development environment from ST, featuring Seamless integration of C and ASM toolsets Full-featured debugger Project management Syntax highlighting editor Integrated programming interface Support of advanced emulation features for STice such as code profiling and coverage ST Visual Programmer (STVP) - Easy-to-use, unlimited graphical interface allowing read, write and verify of your STM8 microcontroller's Flash program memory, data EEPROM and option bytes. STVP also offers project mode for saving programming configurations and automating programming sequences. 12.2.2 C and assembly toolchains Control of C and assembly toolchains is seamlessly integrated into the STVD integrated development environment, making it possible to configure and control the building of your application directly from an easy-to-use graphical interface. Available toolchains include: 12.3 Cosmic C compiler for STM8 - One free version that outputs up to 32 Kbytes of code is available. For more information, see www.cosmic-software.com. Raisonance C compiler for STM8 - One free version that outputs up to 32 Kbytes of code. For more information, see www.raisonance.com. STM8 assembler linker - Free assembly toolchain included in the STVD toolset, which allows you to assemble and link your application source code. Programming tools During the development cycle, STice provides in-circuit programming of the STM8 Flash microcontroller on your application board via the SWIM protocol. Additional tools are to include a low-cost in-circuit programmer as well as ST socket boards, which provide dedicated programming platforms with sockets for programming your STM8. For production environments, programmers will include a complete range of gang and automated programming solutions from third-party tool developers already supplying programmers for the STM8 family. 98/103 Doc ID 14733 Rev 12 STM8S207xx, STM8S208xx 13 Ordering information Ordering information Figure 49. STM8S207xx/208xx performance line ordering information scheme(1) Example: STM8 S 208 M B T 6 B TR Product class STM8 microcontroller Family type S = Standard Sub-family type(2) 208 = Full peripheral set 207 = Intermediate peripheral set Pin count K = 32 pins S = 44 pins C = 48 pins R = 64 pins M = 80 pins Program memory size 6 = 32 Kbyte 8 = 64 Kbyte B = 128 Kbyte Package type T = LQFP Temperature range 3 = -40 C to 125 C 6 = -40 C to 85 C Package pitch No character = 0.5 mm B = 0.65 mm C = 0.8 mm Packing No character = Tray or tube TR = Tape and reel 1. For a list of available options (e.g. memory size, package) and orderable part numbers or for further information on any aspect of this device, please go to www.st.com or contact the ST Sales Office nearest to you. 2. Refer to Table 2: STM8S20xxx performance line features for detailed description. Doc ID 14733 Rev 12 99/103 Revision history 14 STM8S207xx, STM8S208xx Revision history Table 58. Document revision history Date Revision 23-May-2008 1 Initial release. 05-Jun-2008 2 Added part numbers on page 1 and in Table 2 on page 11. Updated Section 4: Product overview. Updated Section 10: Electrical characteristics. 22-Jun-2008 3 Added part numbers on page 1 and in Table 2 on page 11. 4 Added 32 pin device pinout and ordering information. Updated UBC option description in Table 13 on page 47. USART renamed UART1, LINUART renamed UART3. Max. ADC frequency increased to 6 MHz. 5 Removed STM8S207K4 part number. Removed LQFP64 14 x 14 mm package. Added medium and high density Flash memory categories. Added Section 6: Memory and register map on page 33. Replaced beCAN3 by beCAN in Section 4.14.5: beCAN. Updated Section 10: Electrical characteristics on page 51. Updated LQFP44 (Figure 47 and Table 55), and LQFP32 outline and mechanical data (Figure 48, and Table 56). 6 Changed VDD minimum value from 3.0 to 2.95 V. Updated number of High Sink I/Os in pinout. Removed FLASH _NFPR and FLASH _FPR registers in Table 9: General hardware register map. 7 Removed preliminary status. Removed VQFN32 package. Added STM8S207C6, STM8S207S6. Updated external interrupts in Table 2 on page 11. Updated Section 10: Electrical characteristics. 8 Document status changed from "preliminary data" to "datasheet". Added LQFP64 14 x 14 mm package. Added STM8S207M8, STM8S207SB, STM8S208R8, STM8S208R6, STM8S208C8, and STM8S208C6, STM8S208SB, STM8S208S8, and STM8S208S6. Replaced "CAN" with "beCAN". Added Table 3 to Section 4.5: Clock controller. Updated Section 4.8: Auto wakeup counter. Added beCAN peripheral (impacting Table 1 and Figure 6). Added footnote about CAN_RX/TX to pinout figures 3, 4, and 6. Table 6: Removed `X' from wpu column of I2C pins (no wpu available). Added Table 11: Interrupt mapping. 12-Aug-2008 20-Oct-2008 08-Dec-2008 30-Jan-2009 10-Jul-2009 100/103 Changes Doc ID 14733 Rev 12 STM8S207xx, STM8S208xx Table 58. Revision history Document revision history (continued) Date 10-Jul-2009 13-Apr-2010 Revision Changes 8 cont'd Section 10: Electrical characteristics: Added data for TBD values; updated Table 15: Voltage characteristics and Table 18: General operating conditions; updated VCAP specifications in Table 18 and in Section 10.3.1: VCAP external capacitor; updated Figure 18; replaced Figure 19; updated Table 35: RAM and hardware registers; updated Figure 22 and Figure 35; added Figure 40: Typical application with I2C bus and timing diagram. Removed Table 56: Junction temperature range. Added link between ordering information Figure 49 and STM8S20xx features Table 2. 9 Document status changed from "preliminary data" to "datasheet". Table 2: STM8S20xxx performance line features: high sink I/O for STM8S207C8 is 16 (not 13). Table 3: Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers: updated bit positions for TIM2 and TIM3. Figure 5: LQFP 48-pin pinout: added CAN_TX and CAN_RX to pins 35 and 36; noted that these pins are available only in STM8S208xx devices. Figure 7: LQFP 32-pin pinout: replaced uart2 with uart3. Table 6: Pin description: added footnotes concerning beCAN availability and UART1_RX and UART3_RX pins. Table 13: Option byte description: added description of STM8L bootloader option bytes to the option byte description table. Added Section 9: Unique ID (and listed this attribute in Features). Section 10.3: Operating conditions: added introductory text. Table 18: General operating conditions: replaced "CEXT" with "VCAP" and added data for ESR and ESL; removed "low power dissipation" condition for TA. Table 26: Total current consumption in halt mode at VDD = 5 V: replaced max value of IDD(H) at 85 C from 30 A to 35 A for the condition "Flash in powerdown mode, HSI clock after wakeup". Table 33: HSI oscillator characteristics: updated the ACCHSI factory calibrated values. Functional EMS (electromagnetic susceptibility) and Table 47: replaced "IEC 1000" with "IEC 61000". Electromagnetic interference (EMI) and Table 48: replaced "SAE J1752/3" with "IEC 61967-2". Table 57: Thermal characteristics: changed the thermal resistance junction-ambient value of LQFP32 (7x7 mm) from 59 C/W to 60 C/W. Doc ID 14733 Rev 12 101/103 Revision history STM8S207xx, STM8S208xx Table 58. Document revision history (continued) Date 14-Sep-2010 22-Mar-2011 10-Feb-2012 102/103 Revision Changes 10 Added part number STM8S208M8 to Table 1: Device summary. Updated "reset state" of Table 5: Legend/abbreviations for pinout table. Added footnote 4 to Table 6: Pin description. Table 9: General hardware register map: standardized all reset state values; updated the reset state values of RST_SR, CLK_SWCR, CLK_HSITRIMR, CLK_SWIMCCR, IWDG_KR, and ADC_DRx registers; added the reset values of the CAN paged registers. Figure 36: Recommended reset pin protection: replaced 0.01 F with 0.1 F. Figure 40: Typical application with I2C bus and timing diagram: tw(SCKH), tw(SCKL), tr(SCK), and tf(SCK) replaced by tw(SCLH), tw(SCLL), tr(SCL), and tf(SCL) respectively. 11 Table 1: Device summary: added STM8S207K8. Table 2: STM8S20xxx performance line features: added STM8S207K8 device and changed the RAM value of all other devices to 6 Kbytes. Figure 3, Figure 4, Figure 5, and Figure 7: removed TIM1_CH4 from pins 80, 64, 48, and 32 respectively. Table 6: Pin description: updated note 3 and added note 5. Table 9: General hardware register map: removed I2C_PECR register. Section 10.3.7: Reset pin characteristics: added text regarding the rest network. 12 Figure 1: STM8S20xxx performance line block diagram: updated POR/PDR and BOR; updated LINUART input; added legend. Table 18: General operating conditions: updated VCAP. Table 26: Total current consumption in halt mode at VDD = 5 V: updated title, modified existing max column, and added new max column (at 125 C) with data. Table 37: I/O static characteristics: added new condition and new max values for rise and fall time; added footnote 3; updated typ and max pull-up resistor values. Section 10.3.7: Reset pin characteristics: updated cross reference in text below Figure 35 Table 41: NRST pin characteristics: updated typ and max values of the NRST pull-up resistor. Doc ID 14733 Rev 12 STM8S207xx, STM8S208xx Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. 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