SN65LVDS33, SN65LVDT33 SN65LVDS34, SN65LVDT34 www.ti.com SLLS490B - MARCH 2001 - REVISED NOVEMBER 2004 HIGH-SPEED DIFFERENTIAL RECEIVERS Check for Samples: SN65LVDS33, SN65LVDT33, SN65LVDS34, SN65LVDT34 FEATURES 1 * * * * * * * * * * * * (1) (1) 400-Mbps Signaling Rate and 200-Mxfr/s Data Transfer Rate Operates With a Single 3.3-V Supply -4 V to 5 V Common-Mode Input Voltage Range Differential Input Thresholds <50 mV With 50 mV of Hysteresis Over Entire Common-Mode Input Voltage Range Integrated 110- Line Termination Resistors On LVDT Products TSSOP Packaging (33 Only) Complies With TIA/EIA-644 (LVDS) Active Failsafe Assures a High-Level Output With No Input Bus-Pin ESD Protection Exceeds 15 kV HBM Input Remains High-Impedance on Power Down TTL Inputs Are 5 V Tolerant Pin-Compatible With the AM26LS32, SN65LVDS32B, A9637, SN65LVDS9637B The high-speed switching of LVDS signals usually necessitates the use of a line impedance matching resistor at the receiving-end of the cable or transmission media. The SN65LVDT series of receivers eliminates this external resistor by integrating it with the receiver. The nonterminated SN65LVDS series is also available for multidrop or other termination circuits. SN65LVDS33D, SN65LVDT33D SN65LVDS33PW, SN65LVDT33PW D OR PW PACKAGE (TOP VIEW) 1B 1A 1Y G 2Y 2A 2B GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC 4B 4A 4Y G 3Y 3A 3B logic diagram (positive logic) G G SN65LVDT33 ONLY 1A 1Y 1B 2A 2Y 2B 3A 3Y 3B The signalling rate of a line, is the number of voltage transitions that are made per second expressed in the units bps (bits per second). 4A 4Y 4B DESCRIPTION This family of four LVDS data line receivers offers the widest common-mode input voltage range in the industry. These receivers provide an input voltage range specification compatible with a 5-V PECL signal as well as an overall increased ground-noise tolerance. They are in industry standard footprints with integrated termination as an option. Precise control of the differential input voltage thresholds allows for inclusion of 50 mV of input voltage hysteresis to improve noise rejection on slowly changing input signals. The input thresholds are still no more than 50 mV over the full input common-mode voltage range. SN65LVDS34D, SN65LVDT34D D PACKAGE (TOP VIEW) VCC 1Y 2Y GND 1 8 2 7 3 6 4 5 logic diagram (positive logic) 1A 1B 2A 2B 1A 1Y 1B SN65LVDT34 ONLY 2A 2Y 2B 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2001-2004, Texas Instruments Incorporated SN65LVDS33, SN65LVDT33 SN65LVDS34, SN65LVDT34 SLLS490B - MARCH 2001 - REVISED NOVEMBER 2004 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. AVAILABLE OPTIONS (1) PART NUMBER (2) NUMBER OF RECEIVERS TERMINATION RESISTOR SYMBOLIZATION SN65LVDS33D 4 No LVDS33 SN65LVDS33PW 4 No LVDS33 SN65LVDTS33D 4 Yes LVDT33 SN65LVDT33PW 4 Yes LVDT33 SN65LVDS34D 2 No LVDS34 SN65LVDT34D 2 Yes LVDT34 (1) (2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. Add the suffix R for taped and reeled carrier. DESCRIPTION (CONTINUED) The receivers can withstand 15 kV human-body model (HBM) and 600 V machine model (MM) electrostatic discharges to the receiver input pins with respect to ground without damage. This provides reliability in cabled and other connections where potentially damaging noise is always a threat. The receivers also include a (patent pending) failsafe circuit that will provide a high-level output within 600 ns after loss of the input signal. The most common causes of signal loss are disconnected cables, shorted lines, or powered-down transmitters. The failsafe circuit prevents noise from being received as valid data under these fault conditions. This feature may also be used for Wired-Or bus signaling. See The Active Failsafe Feature of the SN65LVDS32B application note. The intended application and signaling technique of these devices is point-to-point baseband data transmission over controlled impedance media of approximately 100 . The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment. The SN65LVDS33, SN65LVDT33, SN65LVDS34 and SN65LVDT34 are characterized for operation from -40C to 85C. Table 1. Function Tables (1) SN65LVDS33 and SN65LVDT33 DIFFERENTIAL INPUT VID = VA - VB VID -32 mV -100 mV < VID -32 mV VID -100 mV X Open (1) 2 ENABLES SN65LVDS34 and SN65LVDT34 OUTPUT DIFFERENTIAL INPUT G G Y VID = VA - VB OUTPUT Y H X H VID -32 mV H ? X L H -100 mV < VID -32 mV H X ? VID -100 mV L X L ? Open H H X L X L L L H Z H X H X L H H = high level, L = low level, X = irrelevant, Z = high impedance (off), ? = indeterminate Submit Documentation Feedback Copyright (c) 2001-2004, Texas Instruments Incorporated Product Folder Link(s): SN65LVDS33 SN65LVDT33 SN65LVDS34 SN65LVDT34 SN65LVDS33, SN65LVDT33 SN65LVDS34, SN65LVDT34 www.ti.com SLLS490B - MARCH 2001 - REVISED NOVEMBER 2004 EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS VCC Attenuation Network Attenuation Network 1 pF 60 k A Input 200 k 3 pF 6.5 k 250 k Attenuation Network 6.5 k VCC B Input 7V 7V 7V 7V LVDT Only 110 VCC VCC 300 k (G Only) Enable Inputs 100 37 Y Output 7V 7V 300 k (G Only) Copyright (c) 2001-2004, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN65LVDS33 SN65LVDT33 SN65LVDS34 SN65LVDT34 3 SN65LVDS33, SN65LVDT33 SN65LVDS34, SN65LVDT34 SLLS490B - MARCH 2001 - REVISED NOVEMBER 2004 www.ti.com ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) UNIT Supply voltage range, VCC (2) Voltage range -0.5 V to 4 V Enables or Y -1 V to 6 V A or B -5 V to 6 V |VA - VB| (LVDT) Electrostatic discharge A, B, and GND Charged-device mode All pins (4) 1V (3) Class 3, A: 15 kV, B: 500 V 500 V Continuous power dissipation See Dissipation Rating Table Storage temperature range (1) (2) (3) (4) -65C to 150C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. Tested in accordance with JEDEC Standard 22, Test Method A114-A. Tested in accordance with JEDEC Standard 22, Test Method C101. DISSIPATION RATING TABLE (1) PACKAGE TA 25C POWER RATING OPERATING FACTOR (1) ABOVE TA = 25C TA = 85C POWER RATING D8 725 mW 5.8 mW/C 377 mW PW16 774 mW 6.2 mW/C 402 mW D16 950 mW 7.6 mW/C 494 mW This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. RECOMMENDED OPERATING CONDITIONS MIN VCC Supply voltage 3 VIH High-level input voltage Enables VIL Low-level input voltage Enables LVDS | VID| Magnitude of differential input voltage VI or VIC Voltage at any bus terminal (separately or common-mode) TA Operating free-air temperature 4 Submit Documentation Feedback NOM MAX UNIT 3.6 V 2 5 V 0 0.8 V 0.1 3 LVDT 3.3 0.8 V -4 5 V -40 85 C Copyright (c) 2001-2004, Texas Instruments Incorporated Product Folder Link(s): SN65LVDS33 SN65LVDT33 SN65LVDS34 SN65LVDT34 SN65LVDS33, SN65LVDT33 SN65LVDS34, SN65LVDT34 www.ti.com SLLS490B - MARCH 2001 - REVISED NOVEMBER 2004 ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS VIT1 Positive-going differential input voltage threshold VIT2 Negative-going differential input voltage threshold VIT3 Differential input failsafe voltage threshold VID(HYS) Differential input voltage hysteresis, VIT1 - VIT2 VOH High-level output voltage IOH = -4 mA VOL Low-level output voltage IOL = 4 mA ICC SN65LVDx33 Supply current SN65LVDx34 SN65LVDS Input current (A or B inputs) II SN65LVDT Differential input current (IIA - IIB) IID -50 See Table 2 and Figure 5 -32 2.4 V 0.4 G at GND 1.1 5 No load, Steady-state 8 20 VI = 2.4 V, Other input open 20 VI = -4 V, Other input open 75 VI = 5 V, Other input open 40 VI = 0 V, Other input open 40 VI = 2.4 V, Other input open 40 VI = -4 V, Other input open 150 VI = 5 V, Other input open 80 1.55 mA 50 VA or VB = 0 V or 2.4 V, VCC = 0 V 30 VA or VB = -4 V or 5 V, VCC = 0 V 100 Low-level input current (enables) VIL = 0.8 V High-impedance output current CI Input capacitance, A or B input to GND (1) All typical values are at 25C and with a 3.3 V supply. -10 VI = 0.4 sin (4E6pt) + 0.5 V A 10 A 10 A 10 A 5 Submit Documentation Feedback Product Folder Link(s): SN65LVDS33 SN65LVDT33 SN65LVDS34 SN65LVDT34 A 2.22 VA or VB = -4 or 5 V, VCC = 0 V IOZ A A 20 IIL mA 3 VA or VB = 0 V or 2.4 V, VCC = 0 V VIH = 2 V V 12 VI = 0 V, Other input open High-level input current (enables) mV mV 23 IIH Copyright (c) 2001-2004, Texas Instruments Incorporated -100 16 VID = 200 mV, VIC = -4 V or 5 V UNIT mV G at VCC, No load, Steady-state SN65LVDT SN65LVDT MAX 50 VID = 100 mV, VIC = -4 V or 5 V Power-off input current (A or B inputs) TYP (1) 50 VIB = -4 V or 5 V, See Figure 1 and Figure 2 SN65LVDS SN65LVDS II(OFF) MIN pF 5 SN65LVDS33, SN65LVDT33 SN65LVDS34, SN65LVDT34 SLLS490B - MARCH 2001 - REVISED NOVEMBER 2004 www.ti.com SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX 2.5 4 6 ns 2.5 4 6 ns 9 ns 1.5 s UNIT tPLH(1) Propagation delay time, low-to-high-level output tPHL(1) Propagation delay time, high-to-low-level output td1 Delay time, failsafe deactivate time td2 Delay time, failsafe activate time tsk(p) Pulse skew (|tPHL(1) - tPLH(1)|) 200 ps tsk(o) Output skew (2) 150 ps See Figure 3 CL = 10 pF, See Figure 3 and Figure 6 (3) 0.3 tsk(pp) Part-to-part skew tr Output signal rise time 0.8 ns tf Output signal fall time 0.8 ns tPHZ Propagation delay time, high-level-to-high-impedance output 5.5 9 ns tPLZ Propagation delay time, low-level-to-high-impedance output 4.4 9 ns tPZH Propagation delay time, high-impedance -to-high-level output 3.8 9 ns tPZL Propagation delay time, high-impedance-to-low-level output 7 9 ns (1) (2) (3) See Figure 3 1 See Figure 4 ns All typical values are at 25C and with a 3.3-V supply. tsk(o) is the magnitude of the time difference between the tPLH or tPHL of all receivers of a single device with all of their inputs driven together. tsk(pp) is the magnitude of the time difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. PARAMETER MEASUREMENT INFORMATION IIA A VO Y VID B (VIA + VIB)/2 VIA VIC IIB VIB VO Figure 1. Voltage and Current Definitions 6 Submit Documentation Feedback Copyright (c) 2001-2004, Texas Instruments Incorporated Product Folder Link(s): SN65LVDS33 SN65LVDT33 SN65LVDS34 SN65LVDT34 SN65LVDS33, SN65LVDT33 SN65LVDS34, SN65LVDT34 www.ti.com SLLS490B - MARCH 2001 - REVISED NOVEMBER 2004 PARAMETER MEASUREMENT INFORMATION (continued) 1000 100 100 1000 VIC + - VID 10 pF, 2 Places VO 10 pF Remove for testing LVDT device. VIT1 0V VID -100 mV VO 100 mV VID 0V VIT2 VO NOTE: Input signal of 3 Mpps, duration of 167 ns, and transition time of <1 ns. Figure 2. VIT1 and VIT2 Input Voltage Threshold Test Circuit and Definitions Copyright (c) 2001-2004, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN65LVDS33 SN65LVDT33 SN65LVDS34 SN65LVDT34 7 SN65LVDS33, SN65LVDT33 SN65LVDS34, SN65LVDT34 SLLS490B - MARCH 2001 - REVISED NOVEMBER 2004 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) VID VIA CL = 10 pF VIB VO VIA 1.4 V VIB 1V 0.4 V VID 0V -0.4 V tPHL tPLH 80% VO 20% tf A. VOH 80% 1.4 V VOL 20% tr All input pulses are supplied by a generator having the following characteristics: tr or tf 1 ns, pulse repetition rate (PRR) = 50 Mpps, pulsewidth = 10 0.2 ns. CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T. Figure 3. Timing Test Circuit and Waveforms 8 Submit Documentation Feedback Copyright (c) 2001-2004, Texas Instruments Incorporated Product Folder Link(s): SN65LVDS33 SN65LVDT33 SN65LVDS34 SN65LVDT34 SN65LVDS33, SN65LVDT33 SN65LVDS34, SN65LVDT34 www.ti.com SLLS490B - MARCH 2001 - REVISED NOVEMBER 2004 PARAMETER MEASUREMENT INFORMATION (continued) 1.2 V B 500 A 10 pF Inputs VO G VTEST G NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf 1 ns, pulse repetition rate (PRR) = 0.5 Mpps, pulsewidth = 500 10 ns . CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T. VTEST 2.5 V A 1V 2V 1.4 V 0.8 V G 2V 1.4 V 0.8 V G tPLZ tPLZ tPZL tPZL Y VTEST 2.5 V 1.4 V VOL +0.5 V VOL 0 1.4 V A 2V 1.4 V 0.8 V 2V 1.4 V 0.8 V G G tPHZ tPZH Y tPHZ tPZH VOH VOH -0.5 V 1.4 V 0 Figure 4. Enable/Disable Time Test Circuit and Waveforms Copyright (c) 2001-2004, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN65LVDS33 SN65LVDT33 SN65LVDS34 SN65LVDT34 9 SN65LVDS33, SN65LVDT33 SN65LVDS34, SN65LVDT34 SLLS490B - MARCH 2001 - REVISED NOVEMBER 2004 www.ti.com Table 2. Receiver Minimum and Maximum VIT3 Input Threshold Test Voltages APPLIED VOLTAGES (1) (1) RESULTANT INPUTS VIA (mV) VIB (mV) VID (mV) VIC (mV) Output -4000 -3900 -100 -3950 L -4000 -3968 -32 -3984 H 4900 5000 -100 4950 L 4968 5000 -32 4984 H These voltages are applied for a minimum of 1.5 s. VIA -100 mV @ 250 KHz VIB VO a) No Failsafe VIA -32 mV @ 250 KHz VIB VO Failsafe Asserted b) Failsafe Asserted Figure 5. VIT3 Failsafe Threshold Test 1.4 V 1V 0.4 V >1.5 s 0V -0.2 V -0.4 V td1 td2 VOH 1.4 V VOL Figure 6. Waveforms for Failsafe Activate and Deactivate 10 Submit Documentation Feedback Copyright (c) 2001-2004, Texas Instruments Incorporated Product Folder Link(s): SN65LVDS33 SN65LVDT33 SN65LVDS34 SN65LVDT34 SN65LVDS33, SN65LVDT33 SN65LVDS34, SN65LVDT34 www.ti.com SLLS490B - MARCH 2001 - REVISED NOVEMBER 2004 TYPICAL CHARACTERISTICS LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT 4 VCC = 3.3 V TA = 25C VCC = 3.3 V TA = 25C VOH - High-Level Output Voltage - V VOL - Low-Level Output Voltage - V 5 4 3 2 1 3 2 1 0 0 0 10 20 30 40 -40 -30 -20 -10 Figure 7. Figure 8. LOW-TO-HIGH PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE HIGH-TO-LOW PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE 5 4.5 VCC = 3 V 4 VCC = 3.3 V VCC = 3.6 V 3.5 3 -50 0 50 TA - Free-Air Temperature - C Figure 9. Copyright (c) 2001-2004, Texas Instruments Incorporated 0 IOH - High-Level Output Current - mA t PHL - High-To-Low Propagation Delay Time - ns t PLH - Low-To-High Propagation Delay Time - ns IOL - Low-Level Output Current - mA 100 5 4.5 VCC = 3 V VCC = 3.3 V 4 VCC = 3.6 V 3.5 3 -50 0 50 TA - Free-Air Temperature - C 100 Figure 10. Submit Documentation Feedback Product Folder Link(s): SN65LVDS33 SN65LVDT33 SN65LVDS34 SN65LVDT34 11 SN65LVDS33, SN65LVDT33 SN65LVDS34, SN65LVDT34 SLLS490B - MARCH 2001 - REVISED NOVEMBER 2004 www.ti.com TYPICAL CHARACTERISTICS (continued) SUPPLY CURRENT vs FREQUENCY 140 120 VCC = 3.3 V I CC - Supply Current - mA 100 80 VCC = 3.6 V 60 VCC = 3 V 40 20 0 0 150 100 200 f - Switching Frequency - MHz Figure 11. APPLICATION INFORMATION 0.01 F 1 VCC 16 0.1 F (see Note A) 1B 100 2 3 VCC 4 5 6 1A 4B 2Y 4Y G 2A 100 7 4A 3Y 2B 3A GND 3B 5V 1N645 (2 places) 15 1Y G 3.6 V 14 100 (see Note B) 13 12 11 See Note C 10 100 8 9 A. Place a 0.1-F Z5U ceramic, mica or polystyrene dielectric, 0805 size, chip capacitor between VCC and the ground plane. The capacitor should be located as close as possible to the device terminals. B. The termination resistance value should match the nominal characteristic impedance of the transmission media with 10%. C. Unused enable inputs should be tied to VCC or GND as appropriate. Figure 12. Operation With 5-V Supply 12 Submit Documentation Feedback Copyright (c) 2001-2004, Texas Instruments Incorporated Product Folder Link(s): SN65LVDS33 SN65LVDT33 SN65LVDS34 SN65LVDT34 SN65LVDS33, SN65LVDT33 SN65LVDS34, SN65LVDT34 www.ti.com SLLS490B - MARCH 2001 - REVISED NOVEMBER 2004 RELATED INFORMATION IBIS modeling is available for this device. Contact the local TI sales office or the TI Web site at www.ti.com for more information. For more application guidelines, see the following documents: * Low-Voltage Differential Signalling Design Notes (SLLA014) * Interface Circuits for TIA/EIA-644 (LVDS) (SLLA038) * Reducing EMI With LVDS (SLLA030) * Slew Rate Control of LVDS Circuits (SLLA034) * Using an LVDS Receiver With RS-422 Data (SLLA031) * Evaluating the LVDS EVM (SLLA033) ACTIVE FAILSAFE FEATURE A differential line receiver commonly has a failsafe circuit to prevent it from switching on input noise. Current LVDS failsafe solutions require either external components with subsequent reductions in signal quality or integrated solutions with limited application. This family of receivers has a new integrated failsafe that solves the limitations seen in present solutions. A detailed theory of operation is presented in application note The Active Failsafe Feature of the SN65LVDS32B, (SLLA082A). The following figure shows one receiver channel with active failsafe. It consists of a main receiver that can respond to a high-speed input differential signal. Also connected to the input pair are two failsafe receivers that form a window comparator. The window comparator has a much slower response than the main receiver and it detects when the input differential falls below 80 mV. A 600-ns failsafe timer filters the window comparator outputs. When failsafe is asserted, the failsafe logic drives the main receiver output to logic high. Output Buffer Main Receiver A B + _ R Reset Failsafe Timer A > B + 80 mV + _ Failsafe B > A + 80 mV + _ Window Comparator Figure 13. Receiver With Active Failsafe ECL/PECL-TO-LVTTL CONVERSION WITH TI's LVDS RECEIVER The various versions of emitter-coupled logic (i.e., ECL, PECL and LVPECL) are often the physical layer of choice for system designers. Designers know of the established technology and that it is capable of high-speed data transmission. In the past, system requirements often forced the selection of ECL. Now technologies like Copyright (c) 2001-2004, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN65LVDS33 SN65LVDT33 SN65LVDS34 SN65LVDT34 13 SN65LVDS33, SN65LVDT33 SN65LVDS34, SN65LVDT34 SLLS490B - MARCH 2001 - REVISED NOVEMBER 2004 www.ti.com LVDS provide designers with another alternative. While the total exchange of ECL for LVDS may not be a design option, designers have been able to take advantage of LVDS by implementing a small resistor divider network at the input of the LVDS receiver. TI has taken the next step by introducing a wide common-mode LVDS receiver (no divider network required) which can be connected directly to an ECL driver with only the termination bias voltage required for ECL termination (VCC-2 V). Figure 14 and Figure 15 show the use of an LV/PECL driver driving 5 meters of CAT-5 cable and being received by TI's wide common-mode receiver and the resulting eye-pattern. The values for R3 are required in order to provide a resistor path to ground for the LV/PECL driver. With no resistor divider, R1 simply needs to match the characteristic load impedance of 50 . The R2 resistor is a small value and is intended to minimize any possible common-mode current reflections. VCC R1 = 50 R2 = 50 ICC 5 Meters of CAT-5 LV/PECL R3 VEE R3 VB VCC ICC LVDS VB R1 R1 R2 R3 = 240 Figure 14. LVPECL or PECL to Remote Wide Common-Mode LVDS Receiver Figure 15. LV/PECL to Remote SN65LVDS33 at 500 Mbps Receiver Output (CH1) TEST CONDITIONS * * * 14 VCC = 3.3 V TA = 25C (ambient temperature) All four channels switching simultaneously with NRZ data. Scope is pulse-triggered simultaneously with NRZ data. Submit Documentation Feedback Copyright (c) 2001-2004, Texas Instruments Incorporated Product Folder Link(s): SN65LVDS33 SN65LVDT33 SN65LVDS34 SN65LVDT34 SN65LVDS33, SN65LVDT33 SN65LVDS34, SN65LVDT34 www.ti.com SLLS490B - MARCH 2001 - REVISED NOVEMBER 2004 EQUIPMENT * * * Tektronix PS25216 programmable power supply Tektronix HFS 9003 stimulus system Tektronix TDS 784D 4-channel digital phosphor oscilloscope - DPO Tektronix PS25216 Programmable Power Supply Tektronix HFS 9003 Stimulus System Trigger Bench Test Board Tektronix TDS 784D 4-Channel Digital Phosphor Oscilloscope - DPO Figure 16. Equipment Setup 100 Mbit/s 200 Mbit/s Figure 17. Typical Eye Pattern SN65LVDS33 Copyright (c) 2001-2004, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN65LVDS33 SN65LVDT33 SN65LVDS34 SN65LVDT34 15 PACKAGE OPTION ADDENDUM www.ti.com 5-Feb-2010 PACKAGING INFORMATION (1) Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN65LVDS33D ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVDS33DG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVDS33DR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVDS33DRG4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVDS33PW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVDS33PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVDS33PWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVDS33PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVDS34D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVDS34DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVDS34DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVDS34DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVDT33D ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVDT33DG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVDT33DR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVDT33DRG4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVDT33PW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVDT33PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVDT33PWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVDT33PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVDT34D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVDT34DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVDT34DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVDT34DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM The marketing status values are defined as follows: Addendum-Page 1 Lead/Ball Finish MSL Peak Temp (3) PACKAGE OPTION ADDENDUM www.ti.com 5-Feb-2010 ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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OTHER QUALIFIED VERSIONS OF SN65LVDS33 : * Enhanced Product: SN65LVDS33-EP NOTE: Qualified Version Definitions: * Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN65LVDS33DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN65LVDS33PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN65LVDS34DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 SN65LVDT33DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN65LVDT33PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN65LVDT34DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN65LVDS33DR SOIC D 16 2500 333.2 345.9 28.6 SN65LVDS33PWR TSSOP PW 16 2000 367.0 367.0 35.0 SN65LVDS34DR SOIC D 8 2500 340.5 338.1 20.6 SN65LVDT33DR SOIC D 16 2500 367.0 367.0 38.0 SN65LVDT33PWR TSSOP PW 16 2000 367.0 367.0 35.0 SN65LVDT34DR SOIC D 8 2500 340.5 338.1 20.6 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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