1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1B
1A
1Y
G
2Y
2A
2B
GND
VCC
4B
4A
4Y
G
3Y
3A
3B
1
2
3
4
8
7
6
5
VCC
1Y
2Y
GND
1A
1B
2A
2B
D OR PW PACKAGE
(TOP VIEW)
D PACKAGE
(TOP VIEW)
SN65LVDS33D, SN65LVDT33D
SN65LVDS33PW, SN65LVDT33PW
G
G
1A
1B
2A
2B
3A
3B
4A
4B
1Y
2Y
3Y
4Y
logic diagram (positive logic)
SN65LVDT33 ONL Y
1A
1B
2A
2B
1Y
2Y
SN65LVDT34 ONLY
logic diagram (positive logic)
SN65LVDS34D, SN65LVDT34D
SN65LVDS33, SN65LVDT33
SN65LVDS34, SN65LVDT34
www.ti.com
SLLS490B –MARCH 2001–REVISED NOVEMBER 2004
HIGH-SPEED DIFFERENTIAL RECEIVERS
Check for Samples: SN65LVDS33,SN65LVDT33,SN65LVDS34,SN65LVDT34
The high-speed switching of LVDS signals usually
1FEATURES necessitates the use of a line impedance matching
• 400-Mbps Signaling Rate(1) and 200-Mxfr/s resistor at the receiving-end of the cable or
Data Transfer Rate transmission media. The SN65LVDT series of
• Operates With a Single 3.3-V Supply receivers eliminates this external resistor by
integrating it with the receiver. The nonterminated
• -4 V to 5 V Common-Mode Input Voltage SN65LVDS series is also available for multidrop or
Range other termination circuits.
• Differential Input Thresholds <±50 mV With 50
mV of Hysteresis Over Entire Common-Mode
Input Voltage Range
• Integrated 110-ΩLine Termination Resistors
On LVDT Products
• TSSOP Packaging (33 Only)
• Complies With TIA/EIA-644 (LVDS)
• Active Failsafe Assures a High-Level Output
With No Input
• Bus-Pin ESD Protection Exceeds 15 kV HBM
• Input Remains High-Impedance on Power
Down
• TTL Inputs Are 5 V Tolerant
• Pin-Compatible With the AM26LS32,
SN65LVDS32B, µA9637, SN65LVDS9637B
(1) The signalling rate of a line, is the number of voltage
transitions that are made per second expressed in the units
bps (bits per second).
DESCRIPTION
This family of four LVDS data line receivers offers the
widest common-mode input voltage range in the
industry. These receivers provide an input voltage
range specification compatible with a 5-V PECL
signal as well as an overall increased ground-noise
tolerance. They are in industry standard footprints
with integrated termination as an option.
Precise control of the differential input voltage
thresholds allows for inclusion of 50 mV of input
voltage hysteresis to improve noise rejection on
slowly changing input signals. The input thresholds
are still no more than ±50 mV over the full input
common-mode voltage range.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 2001–2004, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN65LVDS33, SN65LVDT33
SN65LVDS34, SN65LVDT34
SLLS490B –MARCH 2001–REVISED NOVEMBER 2004
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
AVAILABLE OPTIONS(1)
PART NUMBER OF TERMINATION SYMBOLIZATION
NUMBER(2) RECEIVERS RESISTOR
SN65LVDS33D 4 No LVDS33
SN65LVDS33PW 4 No LVDS33
SN65LVDTS33D 4 Yes LVDT33
SN65LVDT33PW 4 Yes LVDT33
SN65LVDS34D 2 No LVDS34
SN65LVDT34D 2 Yes LVDT34
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) Add the suffix R for taped and reeled carrier.
DESCRIPTION (CONTINUED)
The receivers can withstand ±15 kV human-body model (HBM) and ±600 V machine model (MM) electrostatic
discharges to the receiver input pins with respect to ground without damage. This provides reliability in cabled
and other connections where potentially damaging noise is always a threat.
The receivers also include a (patent pending) failsafe circuit that will provide a high-level output within 600 ns
after loss of the input signal. The most common causes of signal loss are disconnected cables, shorted lines, or
powered-down transmitters. The failsafe circuit prevents noise from being received as valid data under these
fault conditions. This feature may also be used for Wired-Or bus signaling. See The Active Failsafe Feature of
the SN65LVDS32B application note.
The intended application and signaling technique of these devices is point-to-point baseband data transmission
over controlled impedance media of approximately 100 Ω. The transmission media may be printed-circuit board
traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation
characteristics of the media and the noise coupling to the environment.
The SN65LVDS33, SN65LVDT33, SN65LVDS34 and SN65LVDT34 are characterized for operation from –40°C
to 85°C.
Table 1. Function Tables(1)
SN65LVDS33 and SN65LVDT33 SN65LVDS34 and SN65LVDT34
DIFFERENTIAL INPUT ENABLES OUTPUT DIFFERENTIAL INPUT OUTPUT
VID = VA- VBG G Y VID = VA– VBY
H X H VID ≥–32 mV H
VID ≥–32 mV X L H –100 mV < VID≤–32 mV ?
H X ? VID ≤–100 mV L
–100 mV < VID ≤–32 mV X L ? Open H
H X L
VID ≤–100 mV X L L
X L H Z
H X H
Open X L H
(1) H = high level, L = low level, X = irrelevant, Z = high impedance (off), ? = indeterminate
2Submit Documentation Feedback Copyright © 2001–2004, Texas Instruments Incorporated
Product Folder Link(s): SN65LVDS33 SN65LVDT33 SN65LVDS34 SN65LVDT34
VCC
37 Ω
7 V
Y Output
7 V
300 kΩ
100 Ω
VCC
Enable
Inputs
300 kΩ
(G Only)
(G Only)
LVDT Only 110 Ω
7 V
VCC
Attenuation
Network
A Input
Attenuation
Network
B Input
7 V
7 V
7 V
6.5 kΩ6.5 kΩ
VCC
Attenuation
Network
60 kΩ
250 kΩ
200 kΩ
1 pF
3 pF
SN65LVDS33, SN65LVDT33
SN65LVDS34, SN65LVDT34
www.ti.com
SLLS490B –MARCH 2001–REVISED NOVEMBER 2004
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
Copyright © 2001–2004, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): SN65LVDS33 SN65LVDT33 SN65LVDS34 SN65LVDT34
SN65LVDS33, SN65LVDT33
SN65LVDS34, SN65LVDT34
SLLS490B –MARCH 2001–REVISED NOVEMBER 2004
www.ti.com
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
UNIT
Supply voltage range, VCC (2) –0.5 V to 4 V
Enables or Y –1 V to 6 V
Voltage range A or B –5 V to 6 V
|VA– VB| (LVDT) 1 V
Electrostatic discharge A, B, and GND (3) Class 3, A: 15 kV, B: 500 V
Charged-device mode All pins(4) ±500 V
Continuous power dissipation See Dissipation Rating Table
Storage temperature range –65°C to 150°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
(3) Tested in accordance with JEDEC Standard 22, Test Method A114-A.
(4) Tested in accordance with JEDEC Standard 22, Test Method C101.
DISSIPATION RATING TABLE
TA≤25°C OPERATING FACTOR(1) TA= 85°C
PACKAGE POWER RATING ABOVE TA= 25°C POWER RATING
D8 725 mW 5.8 mW/°C 377 mW
PW16 774 mW 6.2 mW/°C 402 mW
D16 950 mW 7.6 mW/°C 494 mW
(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air
flow.
RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT
VCC Supply voltage 3 3.3 3.6 V
VIH High-level input voltage Enables 2 5 V
VIL Low-level input voltage Enables 0 0.8 V
LVDS 0.1 3
| VID| Magnitude of differential input voltage V
LVDT 0.8
VIor VIC Voltage at any bus terminal (separately or common-mode) –4 5 V
TAOperating free-air temperature –40 85 °C
4Submit Documentation Feedback Copyright © 2001–2004, Texas Instruments Incorporated
Product Folder Link(s): SN65LVDS33 SN65LVDT33 SN65LVDS34 SN65LVDT34
SN65LVDS33, SN65LVDT33
SN65LVDS34, SN65LVDT34
www.ti.com
SLLS490B –MARCH 2001–REVISED NOVEMBER 2004
ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
VIT1 Positive-going differential input voltage threshold 50
VIB = –4 V or 5 V, mV
Negative-going differential input voltage See Figure 1 and Figure 2
VIT2 –50
threshold
VIT3 Differential input failsafe voltage threshold See Table 2 and Figure 5 –32 –100 mV
Differential input voltage hysteresis,
VID(HYS) 50 mV
VIT1 – VIT2
VOH High-level output voltage IOH = –4 mA 2.4 V
VOL Low-level output voltage IOL = 4 mA 0.4 V
G at VCC, No load, Steady-state 16 23
SN65LVDx33
ICC Supply current G at GND 1.1 5 mA
SN65LVDx34 No load, Steady-state 8 12
VI= 0 V, Other input open ±20
VI= 2.4 V, Other input open ±20
SN65LVDS µA
VI= –4 V, Other input open ±75
VI= 5 V, Other input open ±40
Input current
II(A or B inputs) VI= 0 V, Other input open ±40
VI= 2.4 V, Other input open ±40
SN65LVDT µA
VI= –4 V, Other input open ±150
VI= 5 V, Other input open ±80
SN65LVDS VID = 100 mV, VIC = –4 V or 5 V ±3 µA
Differential input current
IID (IIA – IIB)SN65LVDT VID = 200 mV, VIC = –4 V or 5 V 1.55 2.22 mA
VAor VB= 0 V or 2.4 V, VCC = 0 V ±20
SN65LVDS VAor VB= –4 or 5 V, VCC = 0 V ±50
Power-off input current
II(OFF) µA
(A or B inputs) VAor VB= 0 V or 2.4 V, VCC = 0 V ±30
SN65LVDT VAor VB= –4 V or 5 V, VCC = 0 V ±100
IIH High-level input current (enables) VIH = 2 V 10 µA
IIL Low-level input current (enables) VIL = 0.8 V 10 µA
IOZ High-impedance output current –10 10 µA
CIInput capacitance, A or B input to GND VI= 0.4 sin (4E6pt) + 0.5 V 5 pF
(1) All typical values are at 25°C and with a 3.3 V supply.
Copyright © 2001–2004, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): SN65LVDS33 SN65LVDT33 SN65LVDS34 SN65LVDT34
VID
A
B
Y
VO
VIB
VIA
VIC
(VIA + VIB)/2 IIB
IIA VO
SN65LVDS33, SN65LVDT33
SN65LVDS34, SN65LVDT34
SLLS490B –MARCH 2001–REVISED NOVEMBER 2004
www.ti.com
SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
tPLH(1) Propagation delay time, low-to-high-level output 2.5 4 6 ns
See Figure 3
tPHL(1) Propagation delay time, high-to-low-level output 2.5 4 6 ns
td1 Delay time, failsafe deactivate time 9 ns
CL= 10 pF, See Figure 3
and Figure 6
td2 Delay time, failsafe activate time 0.3 1.5 µs
tsk(p) Pulse skew (|tPHL(1) - tPLH(1)|) 200 ps
tsk(o) Output skew(2) 150 ps
tsk(pp) Part-to-part skew(3) See Figure 3 1 ns
trOutput signal rise time 0.8 ns
tfOutput signal fall time 0.8 ns
tPHZ Propagation delay time, high-level-to-high-impedance output 5.5 9 ns
tPLZ Propagation delay time, low-level-to-high-impedance output 4.4 9 ns
See Figure 4
tPZH Propagation delay time, high-impedance -to-high-level output 3.8 9 ns
tPZL Propagation delay time, high-impedance-to-low-level output 7 9 ns
(1) All typical values are at 25°C and with a 3.3-V supply.
(2) tsk(o) is the magnitude of the time difference between the tPLH or tPHL of all receivers of a single device with all of their inputs driven
together.
(3) tsk(pp) is the magnitude of the time difference in propagation delay times between any specified terminals of two devices when both
devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
PARAMETER MEASUREMENT INFORMATION
Figure 1. Voltage and Current Definitions
6Submit Documentation Feedback Copyright © 2001–2004, Texas Instruments Incorporated
Product Folder Link(s): SN65LVDS33 SN65LVDT33 SN65LVDS34 SN65LVDT34
VID
VO
10 pF,
2 Places 10 pF
100 Ω†
1000 Ω
1000 Ω
100 Ω
VIC
VID
VO
VID
VO
VIT1
0 V
–100 mV
100 mV
0 V
VIT2
†Remove for testing LVDT device.
NOTE: Input signal of 3 Mpps, duration of 167 ns, and transition time of <1 ns.
+
–
SN65LVDS33, SN65LVDT33
SN65LVDS34, SN65LVDT34
www.ti.com
SLLS490B –MARCH 2001–REVISED NOVEMBER 2004
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 2. VIT1 and VIT2 Input Voltage Threshold Test Circuit and Definitions
Copyright © 2001–2004, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): SN65LVDS33 SN65LVDT33 SN65LVDS34 SN65LVDT34
tPHL tPLH
tftr
80%
20%
80%
20%
VIA
VIB
VID
VO
1.4 V
1 V
0.4 V
0 V
−0.4 V
VOH
1.4 V
VOL
VID
VO
VIB
VIA CL = 10 pF
SN65LVDS33, SN65LVDT33
SN65LVDS34, SN65LVDT34
SLLS490B –MARCH 2001–REVISED NOVEMBER 2004
www.ti.com
PARAMETER MEASUREMENT INFORMATION (continued)
A. All input pulses are supplied by a generator having the following characteristics: tror tf≤1 ns, pulse repetition rate
(PRR) = 50 Mpps, pulsewidth = 10 ±0.2 ns. CLincludes instrumentation and fixture capacitance within 0,06 mm of the
D.U.T.
Figure 3. Timing Test Circuit and Waveforms
8Submit Documentation Feedback Copyright © 2001–2004, Texas Instruments Incorporated
Product Folder Link(s): SN65LVDS33 SN65LVDT33 SN65LVDS34 SN65LVDT34
B
A
G
G
VO±
500 Ω
VTEST
10 pF
1.2 V
tPZL
tPLZ
tPZL
tPLZ
tPZH
tPHZ
tPZH
tPHZ
2.5 V
1 V
2 V
1.4 V
0.8 V
2 V
1.4 V
0.8 V
2.5 V
1.4 V
VOL +0.5 V
VOL
0
1.4 V
2 V
1.4 V
0.8 V
2 V
1.4 V
0.8 V
VOH
VOH –0.5 V
1.4 V
0
VTEST
A
G
G
Y
VTEST
A
G
Y
Inputs
G
NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse
repetition rate (PRR) = 0.5 Mpps, pulsewidth = 500 ±10 ns . CL includes instrumentation and fixture
capacitance within 0,06 mm of the D.U.T.
SN65LVDS33, SN65LVDT33
SN65LVDS34, SN65LVDT34
www.ti.com
SLLS490B –MARCH 2001–REVISED NOVEMBER 2004
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 4. Enable/Disable Time Test Circuit and Waveforms
Copyright © 2001–2004, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Link(s): SN65LVDS33 SN65LVDT33 SN65LVDS34 SN65LVDT34
VIA
VIB
VO
–100 mV @ 250 KHz
–32 mV @ 250 KHz
Failsafe Asserted
VIA
VIB
VO
a) No Failsafe
b) Failsafe Asserted
td1 td2
1.4 V
1 V
0.4 V
0 V
–0.4 V
VOH
1.4 V
VOL
–0.2 V
>1.5 µs
SN65LVDS33, SN65LVDT33
SN65LVDS34, SN65LVDT34
SLLS490B –MARCH 2001–REVISED NOVEMBER 2004
www.ti.com
Table 2. Receiver Minimum and Maximum VIT3
Input Threshold Test Voltages
APPLIED VOLTAGES(1) RESULTANT INPUTS
VIA (mV) VIB (mV) VID (mV) VIC (mV) Output
–4000 –3900 –100 –3950 L
–4000 –3968 –32 –3984 H
4900 5000 –100 4950 L
4968 5000 –32 4984 H
(1) These voltages are applied for a minimum of 1.5 µs.
Figure 5. VIT3 Failsafe Threshold Test
Figure 6. Waveforms for Failsafe Activate and Deactivate
10 Submit Documentation Feedback Copyright © 2001–2004, Texas Instruments Incorporated
Product Folder Link(s): SN65LVDS33 SN65LVDT33 SN65LVDS34 SN65LVDT34
IOH − High-Level Output Current − mA
VOH− High-Level Output Voltage − V
4
3
0
2
1
−30 −20−40 0−10
VCC = 3.3 V
TA = 25°C
SN65LVDS33, SN65LVDT33
SN65LVDS34, SN65LVDT34
www.ti.com
SLLS490B –MARCH 2001–REVISED NOVEMBER 2004
TYPICAL CHARACTERISTICS
LOW-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT VOLTAGE
vs vs
LOW-LEVEL OUTPUT CURRENT HIGH-LEVEL OUTPUT CURRENT
Figure 7. Figure 8.
LOW-TO-HIGH PROPAGATION DELAY TIME HIGH-TO-LOW PROPAGATION DELAY TIME
vs vs
FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE
Figure 9. Figure 10.
Copyright © 2001–2004, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Link(s): SN65LVDS33 SN65LVDT33 SN65LVDS34 SN65LVDT34
80
60
20
00 100
100
120
150 200
40
− Supply Current − mAICC
f − Switching Frequency − MHz
VCC = 3 V
VCC = 3.6 V
VCC = 3.3 V
140
1B
1A
1Y
G
2Y
2A
2B
GND
VCC
4B
4A
4Y
G
3Y
3A
3B
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
100 Ω
100 Ω
100 Ω
(see Note B)
100 Ω
VCC
See Note C
≈3.6 V
0.1 µF
(see Note A) 1N645
(2 places)
0.01 µF
5 V
SN65LVDS33, SN65LVDT33
SN65LVDS34, SN65LVDT34
SLLS490B –MARCH 2001–REVISED NOVEMBER 2004
www.ti.com
TYPICAL CHARACTERISTICS (continued)
SUPPLY CURRENT
vs
FREQUENCY
Figure 11.
APPLICATION INFORMATION
A. Place a 0.1-µF Z5U ceramic, mica or polystyrene dielectric, 0805 size, chip capacitor between VCC and the ground
plane. The capacitor should be located as close as possible to the device terminals.
B. The termination resistance value should match the nominal characteristic impedance of the transmission media with
±10%.
C. Unused enable inputs should be tied to VCC or GND as appropriate.
Figure 12. Operation With 5-V Supply
12 Submit Documentation Feedback Copyright © 2001–2004, Texas Instruments Incorporated
Product Folder Link(s): SN65LVDS33 SN65LVDT33 SN65LVDS34 SN65LVDT34
_
+
Main Receiver
_
+
_
+
A > B + 80 mV
B > A + 80 mV
Failsafe
Timer
Failsafe
Output
Buffer
Reset
Window Comparator
A
BR
SN65LVDS33, SN65LVDT33
SN65LVDS34, SN65LVDT34
www.ti.com
SLLS490B –MARCH 2001–REVISED NOVEMBER 2004
RELATED INFORMATION
IBIS modeling is available for this device. Contact the local TI sales office or the TI Web site at www.ti.com for
more information.
For more application guidelines, see the following documents:
•Low-Voltage Differential Signalling Design Notes (SLLA014)
•Interface Circuits for TIA/EIA-644 (LVDS) (SLLA038)
•Reducing EMI With LVDS (SLLA030)
•Slew Rate Control of LVDS Circuits (SLLA034)
•Using an LVDS Receiver With RS-422 Data (SLLA031)
•Evaluating the LVDS EVM (SLLA033)
ACTIVE FAILSAFE FEATURE
A differential line receiver commonly has a failsafe circuit to prevent it from switching on input noise. Current
LVDS failsafe solutions require either external components with subsequent reductions in signal quality or
integrated solutions with limited application. This family of receivers has a new integrated failsafe that solves the
limitations seen in present solutions. A detailed theory of operation is presented in application note The Active
Failsafe Feature of the SN65LVDS32B, (SLLA082A).
The following figure shows one receiver channel with active failsafe. It consists of a main receiver that can
respond to a high-speed input differential signal. Also connected to the input pair are two failsafe receivers that
form a window comparator. The window comparator has a much slower response than the main receiver and it
detects when the input differential falls below 80 mV. A 600-ns failsafe timer filters the window comparator
outputs. When failsafe is asserted, the failsafe logic drives the main receiver output to logic high.
Figure 13. Receiver With Active Failsafe
ECL/PECL-TO-LVTTL CONVERSION WITH TI's LVDS RECEIVER
The various versions of emitter-coupled logic (i.e., ECL, PECL and LVPECL) are often the physical layer of
choice for system designers. Designers know of the established technology and that it is capable of high-speed
data transmission. In the past, system requirements often forced the selection of ECL. Now technologies like
Copyright © 2001–2004, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): SN65LVDS33 SN65LVDT33 SN65LVDS34 SN65LVDT34
R3 R3
VCCICC
5 Meters
of CAT-5
R1 R1
VEE R2
VCCICC
R3 = 240 Ω
R1 = 50 Ω
R2 = 50 Ω
VB
VBLVDSLV/PECL
SN65LVDS33, SN65LVDT33
SN65LVDS34, SN65LVDT34
SLLS490B –MARCH 2001–REVISED NOVEMBER 2004
www.ti.com
LVDS provide designers with another alternative. While the total exchange of ECL for LVDS may not be a design
option, designers have been able to take advantage of LVDS by implementing a small resistor divider network at
the input of the LVDS receiver. TI has taken the next step by introducing a wide common-mode LVDS receiver
(no divider network required) which can be connected directly to an ECL driver with only the termination bias
voltage required for ECL termination (VCC–2 V).
Figure 14 and Figure 15 show the use of an LV/PECL driver driving 5 meters of CAT-5 cable and being received
by TI's wide common-mode receiver and the resulting eye-pattern. The values for R3 are required in order to
provide a resistor path to ground for the LV/PECL driver. With no resistor divider, R1 simply needs to match the
characteristic load impedance of 50 Ω. The R2 resistor is a small value and is intended to minimize any possible
common-mode current reflections.
Figure 14. LVPECL or PECL to Remote Wide Common-Mode LVDS Receiver
Figure 15. LV/PECL to Remote SN65LVDS33 at 500 Mbps Receiver Output (CH1)
TEST CONDITIONS
• VCC = 3.3 V
• TA= 25°C (ambient temperature)
• All four channels switching simultaneously with NRZ data. Scope is pulse-triggered simultaneously with NRZ
data.
14 Submit Documentation Feedback Copyright © 2001–2004, Texas Instruments Incorporated
Product Folder Link(s): SN65LVDS33 SN65LVDT33 SN65LVDS34 SN65LVDT34
Tektronix PS25216
Programmable
Power Supply
Bench Test Board
Tektronix HFS 9003
Stimulus System
Tektronix TDS 784D 4-Channel
Digital Phosphor Oscilloscope
– DPO
Trigger
100 Mbit/s 200 Mbit/s
SN65LVDS33, SN65LVDT33
SN65LVDS34, SN65LVDT34
www.ti.com
SLLS490B –MARCH 2001–REVISED NOVEMBER 2004
EQUIPMENT
• Tektronix PS25216 programmable power supply
• Tektronix HFS 9003 stimulus system
• Tektronix TDS 784D 4-channel digital phosphor oscilloscope – DPO
Figure 16. Equipment Setup
Figure 17. Typical Eye Pattern SN65LVDS33
Copyright © 2001–2004, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): SN65LVDS33 SN65LVDT33 SN65LVDS34 SN65LVDT34
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
SN65LVDS33D ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS33DG4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS33DR ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS33DRG4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS33PW ACTIVE TSSOP PW 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS33PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS33PWR ACTIVE TSSOP PW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS33PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS34D ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS34DG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS34DR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS34DRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDT33D ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDT33DG4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDT33DR ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDT33DRG4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDT33PW ACTIVE TSSOP PW 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDT33PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDT33PWR ACTIVE TSSOP PW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDT33PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDT34D ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDT34DG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDT34DR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDT34DRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
PACKAGE OPTION ADDENDUM
www.ti.com 5-Feb-2010
Addendum-Page 1
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN65LVDS33 :
•Enhanced Product: SN65LVDS33-EP
NOTE: Qualified Version Definitions:
•Enhanced Product - Supports Defense, Aerospace and Medical Applications
PACKAGE OPTION ADDENDUM
www.ti.com 5-Feb-2010
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN65LVDS33DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
SN65LVDS33PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN65LVDS34DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN65LVDT33DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
SN65LVDT33PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN65LVDT34DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN65LVDS33DR SOIC D 16 2500 333.2 345.9 28.6
SN65LVDS33PWR TSSOP PW 16 2000 367.0 367.0 35.0
SN65LVDS34DR SOIC D 8 2500 340.5 338.1 20.6
SN65LVDT33DR SOIC D 16 2500 367.0 367.0 38.0
SN65LVDT33PWR TSSOP PW 16 2000 367.0 367.0 35.0
SN65LVDT34DR SOIC D 8 2500 340.5 338.1 20.6
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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