469
SED1600
CMOS 80-SEGMENT LCD DRIVER
• 80-bit High Voltage Output
• 1/100 to 1/300 Display Duty
■FEATURES
•Low-power CMOS technology
•80-bit segment (column) driver
•High-speed 4-bit data bus with enable chain tech-
nology
•Duty cycle ............................... 1/100 to 1/300
•Shift clock frequency .............. 6MHz max
•Ability to adjust offset bias of the LCD source from
VDD
■DESCRIPTION
The SED1600 is a dot matrix LCD segment (column) driver for driving a high-capacity LCD panel at duty
cycles higher than 1/100 (up to 1/300). The LSI has a wide range of LCD driving voltages. Due to the
architecture of the SED1600, the LCD driving voltage, V0, is isolated from the VDD supply. This provides the
ability to adjust the offset bias independently of VDD. These unique features allow the SED1600 to interface
with a variety of LCD panels. The SED1600 does not require a controller to output an enable signal to
implement daisy chain technology. This provides for easy interfacing with the LCD controllers such as the
SED1330, SED1351, SED1335, or the SED1341.
The SED1600 is used in conjunction with the SED1610 (86-row driver), SED1630 (68-bit row driver),
SED1631 (100-row driver), SED1632 (86-bit row driver), SED1633 (100-bit row driver), and SED1634 (100-
bit driver) to drive a large-capacity dot matrix LCD panel.
•Daisy chain enable support
•Selectable output shift direction
•No enable signal by controller is required
•Wide range of LCD voltage .... –12 to –28V
•Supply voltage ........................ 5.0V ± 10%
•Package.....QFP5-100 pin (FAA)
DIE: Al pad chip (DAA)
Au bump (DAB)
■SYSTEM BLOCK DIAGRAM
SED1600F
(n)
SED1600F
(1)
LCD
CONTR
n*80 SEG
DUTY: 1/100 ~ 1/300
8080
D0 ~ D3
XSCL
YSCL
YD
LP, FR
100~300
ROW
DRIVER
470
SED1600
■BLOCK DIAGRAM
SEG0
LCD Driver
80 bit
Level Shifter
80 bit
Register 2
80 bit
Register 1
Clock Generator
SEG1
SEG2
SEG79
VDD
VSS
V0
V2
V3
V5
FR
LP
D0
D1
D2
D3
SHL
EIO1
EIO2
XSCL
Data
Control
Enable
Control
Voltage
Control
4
ø1 ø2 ø20
■PINOUT
Index
80
SEG49
SEG48
SEG47
SEG46
SEG45
SEG44
SEG43
SEG42
SEG41
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
1
100
EIO2
D0
D1
D2
D3
NC
NC
NC
NC
V
DD
V
SS
V0
V2
V3
V5
SHL
XSCL
LP
FR
EIO1
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG79
SEG78
SEG77
SEG76
SEG75
SEG74
SEG73
SEG72
SEG71
SEG70
SEG69
SEG68
SEG67
SEG66
SEG65
SEG64
SEG63
SEG62
SEG61
SEG60
SEG59
SEG58
SEG57
SEG56
SEG55
SEG54
SEG53
SEG52
SEG51
SEG50
70 60 50
40
30
10 20
90
SED1600
75
5
65
15
55
25
85 45
95 35
* NC: No Connection
*
471
Parameter Symbol Ratings Unit
Supply voltage (1) VSS –7.0 to +0.3 V
Supply voltage (2) V5 –30.0 to +0.3 V
Supply voltage (2) V0, V2, V3* V5 –0.3 to +0.3 V
Input voltage (1) VIVSS –0.3 to +0.3 V
Output voltage (1) VOVSS –0.3 to +0.3 V
Output current (1) IO20 mA
Output current (2) IOSEG 20 mA
Allowable power dissipation PD300 mW
Operating temperature Topr –20 to +75 °C
Storage temperature Tstg –65 to +150 °C
Soldering temperature, time Tsol 260°C, 10 sec (at lead) —
SED1600
■PIN DESCRIPTION
Pin Name I/O Function
SEG0 to SEG79 O LCD driving segment (column) outputs
Each output changes at the falling edge of LP.
D0 TO D3 I Display data inputs.
XSCL I Shift clock of display data (falling edge trigger).
LP I Latch pulse of display data (falling edge trigger).
EI01, EI02 I/O Enable I/O, which is controlled by SHL input . Output is reset by LP, and
automatically falls when 80 bits of data are taken in.
SHL I Shift direction selection and EIO pin I/O control.
When data (a, b, c, d) (e, f, g, h)······(w, x, y, z) are input to pins (D3, D2, D1,
D0) respectively, the following relation is established between the data and
segment outputs:
SHL SEG EIO
79 78 77 76 75 74 73 72 ...... 3 2 1 0 1 2
L a b c d e f g h ...... w x y z Output Input
H z y x w v u t s ...... d c b a Input Output
FR I AC signal of LCD driving outputs.
VDD, VSS Power Logic circuit power. VDD: 0 V (GND)
Supplies VSS: –5.0 V
V0, V2, V3, V5 Power LCD driving power. V5: –12 to –28 V
Supplies VDD ≥ V0 ≥ V2 > V3 ≥ V5
■ELECTRICAL CHARACTERISTICS
•Absolute Maximum Ratings (VDD = 0V)
* V0, V2 and V3 must always satisfy the condition VDD ≥ V0 ≥ V2 ≥ V3 ≥ V5.
472
SED1600
•DC Electrical Characteristics
Parameter Symbol Condition Pin Min Typ Max Unit
Operating voltage VSS VSS –5.5 –5.0 –4.5 V
Recommended op. voltage V5 V5 –28.0 —–12.0 V
Minimum operating voltage –8.0
Operating voltage — Recommended value V0 –2.5 — 0 V
Operating voltage V2 Recommended value V2 3/9·V5 — V0 V
Operating voltage V3 Recommended value V3 V5 — 6/9·V5 V
“H” input voltage VIH 0.2VSS ——V
“L” input voltage VIL — — 0.8VSS V
“H” output voltage VOH IOH = –0.6 mA EI01, EI02 –0.4 — — V
“L” output voltage VOL IOL = 0.6 mA — — VSS+0.4 V
Input leakage current ILI VSS ≤ VI ≤ 0 V — — 2.0 µA
ILI/O VSS ≤ VI ≤ 0 V EI01, EI02 — — 5.0 µA
Stand–by current IDDS V5 = –12.0 to –28.0 V VDD ——25µA
V
IH = VDD, VIL = VSS
–20.0V — 1.5 3.5
Output resistance RSEG |∆VON| = 0.5V V5 –14.0V SEG0 to — 2.0 4.5 kΩ
–8.0V SEG79 — 3.0 8.0
Current dissipation (1) ISSO1 VSS — 120 500 µA
Current dissipation (2) ISSO2 V5 — 20 100 µA
Input capacitance CITa = 25°C— — 8.0 pF
CI/O EI01, EI02 — — 15.0 pF
D0 to D3, LP
XSCL, SHL, FR
EI01, EI02,
XSCL, LP,
D0 to D3,
FR, SHL
VSS = –5.0 V, VIH = VDD
VIL = VSS, fXSCL =1.92 MHz
fLP = 12 kHz, Frame period
= 60 Hz; Input data:
Inverted bit by bit, No-load
VSS = –5.0 V, V2 = –4.0 V
V3 = –16.0 V, V5 = –20.0 V
All other conditions are
same as ISSO1 D0 to D3, LP
XSCL, SHL, FR
(Unless otherwise specified, VDD = V0 = 0V,
VSS = –5.0 V ± 10%, Ta = –20 to 85°C)
473
SED1600
•AC Electrical Characteristics (VSS = –5.0 V ±10%, Ta = –20 to 85°C)
Parameter Symbol Conditions Min Typ Max Unit
XSCL period tCCL tr, tf ≤ 10 ns 166 — — ns
XSCL “H” pulse width tWCLH 70 — — ns
XSCL “L” pulse width tWCLL 70 — — ns
Data setup time tDS 60 — — ns
Data hold time tDH 40 — — ns
XSCL-rise to LP-rise time tLD 0——ns
XSCL-fall to LP-fall time tSL 70 — — ns
LP-rise to XSCL-rise time tLS 70 — — ns
LP-fall to XSCL-fall time tLH 70 — — ns
LP “H” pulse width tWLPH 70 — — ns
LP “L” pulse width tWLPL 230 — — ns
Allowable FR delay time tDFR –500 — 500 ns
Enable “H” setup time tsuEIH 40 — — ns
Enable “H” hold time thEIH 0——ns
Enable “L” setup time tsuEIL 0——ns
Enable “L” hold time thEIL 0——ns
Input signal rise time tr— — 50* ns
Input signal fall time tf— — 50* ns
* Note: The specifications for tr and tf are provided to prevent a malfunction which may occur when noise is mixed with a slow-
down signal. To assure high-speed XSCL, both tr and tf must satisfy the following relation:
tCCL – (tWCLH + tWCLL)
2
tr, tf <
474
• Timing Chart
° Input Timing
20 1 2 20 1 2 20 1 2 20 1 2
t
DFR
FR
LP
XSCL
D0 to D3
EIO output 1
EIO output 2
123
FR
LP
XSCL
D0 to D3
EIO1
EIO2
V
IH
= 0.2 V
SS
V
IL
= 0.8 V
SS
t
WLPL
t
WLPH
t
LS
t
LH
t
WCLH
t
f
t
r
t
CCL
t
DS
t
DH
t
WCLL
t
suEIL
t
hEIH
t
suEIH
t
hEIL
t
SL
t
LD
1 through 3 each show a cascade number of the driver.
SED1600
475
°Output Timing
SED1600
FR
LP
XSCL
EIO1
EIO2
SEG output
V
IH
= 0.2 V
SS
V
IL
= 0.8 V
SS
t
pdEOLLP
V
OH
= 0.2 V
SS
V
OL
= 0.8 V
SS
t
pd
EOHCL
t
pd
EOLCL
t
pd
SLP
t
pd
SFR
Vn –0.5V
Vn +0.5V
Vn = V0, V2, V3, V5
Parameter Symbol Conditions Min Typ Max Unit
(LP-rise to disable) time tpdEOLLP XSCL = “L” — — 70 ns
(XSCL-fall to disable) time tpdEOLCL LP = “H” CL = 15 pF — — 70 ns
(XSCL-fall to enable) time tpdEOHCL — — 100 ns
(LP-fall to SEG output) time tpdSLP V5 = –12.0 to –28.0 V — — 4.5 µs
(FR to SEG output) delay time tpdSFR CL = 100 pF — — 4.5 µs
(VSS = –5.0 V ±10%, Ta = –20 to 85°C)
476
SED1600
■EXAMPLE OF APPLICATION (SED1600) (for 200 × 640 DOT MATRIX LCD)
Note:
* Be sure to connect a current limiter resistor. Also, connect decoupling capacitors (0.01µF) near pins VSS and V5 of each LSI
for noise protection.
EIO1
SHL
079
EIO2 8
EIO1
SHL
079
EIO2 2
EIO1
SHL
SEG
079
EIO2 1
DIO1
DIO2 FR
SHL
YSCL 3
SED1600
DIO1
DIO2 FR
SHL
YSCL 2
DIO1
DIO2 FR
SHL
YSCL 1
COM
67
+++++
R
V
SS
YD
WF
XSCL
XD0 to XD3
LP
6
6
V
DD
V
DD
V0
V1
V2
V3
V4
V5
V
SSH
R
11R
R
R
22Ω
4
200 × 640 DOT MATRIX
LCD PANEL
CONTROLLER (SED1330, SED1341)
V
SS
22Ω*
+
SED1630
SED1630
0067063
XSCL
D0 to 3
LP
FR
XSCL
D0 to 3
LP
FR
XSCL
D 0to 3
LP
FR
SED1600
SED1600
477
■PAD LAYOUT / PAD COORDINATION
•SED1600DAA (AL PAD)
Pad X Y Pad X Y Pad X Y
No. Name (µm) (µm) No. Name (µm) (µm) No. Name (µm) (µm)
1 SEG0 –2461 –1588 35 SEG34 2632 –881 69 SEG68 –560 1588
2 SEG1 –2261 –1588 36 SEG35 2632 –721 70 SEG69 –720 1588
3 SEG2 –2069 –1588 37 SEG36 2632 –561 71 SEG70 –880 1588
4 SEG3 –1886 –1588 38 SEG37 2632 –401 72 SEG71 –1040 1588
5 SEG4 –1709 –1588 39 SEG38 2632 –241 73 SEG72 –1203 1588
6 SEG5 –1538 –1588 40 SEG39 2632 –81 74 SEG73 –1366 1588
7 SEG6 –1366 –1588 41 SEG40 2632 79 75 SEG74 –1538 1588
8 SEG7 –1203 –1588 42 SEG41 2632 239 76 SEG75 –1709 1588
9 SEG8 –1040 –1588 43 SEG42 2632 399 77 SEG76 –1885 1588
10 SEG9 –880 –1588 44 SEG43 2632 559 78 SEG77 –2069 1588
11 SEG10 –720 –1588 45 SEG44 2632 719 79 SEG78 –2261 1588
12 SEG11 –560 –1588 46 SEG45 2632 879 80 SEG79 –2461 1588
13 SEG12 –400 –1588 47 SEG46 2632 1039 81 EI02 –2632 1546
14 SEG13 –240 –1588 48 SEG47 2632 1204 82 D0 –2632 1372
15 SEG14 –80 –1588 49 SEG48 2632 1372 83 D1 –2632 1204
16 SEG15 80 –1588 50 SEG49 2632 1546 84 D2 –2632 1039
17 SEG16 240 –1588 51 SEG50 2461 1588 85 D3 –2632 879
18 SEG17 400 –1588 52 SEG51 2261 1588 86 (D4) –2632 719
19 SEG18 560 –1588 53 SEG52 2069 1588 87 (D5) –2632 559
20 SEG19 720 –1588 54 SEG53 1885 1588 88 (D6) –2632 399
21 SEG20 880 –1588 55 SEG54 1709 1588 89 (D7) –2632 239
22 SEG21 1040 –1588 56 SEG55 1538 1588 90 VDD –2632 79
23 SEG22 1203 –1588 57 SEG56 1366 1588 91 VSS –2632 –81
24 SEG23 1366 –1588 58 SEG57 1203 1588 92 V0 –2632 –241
25 SEG24 1538 –1588 59 SEG58 1040 1588 93 V2 –2632 –401
26 SEG25 1709 –1588 60 SEG59 880 1588 94 V3 –2632 –561
27 SEG26 1885 –1588 61 SEG60 720 1588 95 V5 –2632 –721
28 SEG27 2069 –1588 62 SEG61 560 1588 96 SHL –2632 –881
29 SEG28 2261 –1588 63 SEG62 400 1588 97 XSCL –2632 –1041
30 SEG29 2461 –1588 64 SEG63 240 1588 98 LP –2632 –1206
31 SEG30 2632 –1548 65 SEG64 80 1588 99 FR –2632 –1374
32 SEG31 2632 –1374 66 SEG65 –80 1588 100 EI01 –2632 –1548
33 SEG32 2632 –1206 67 SEG66 –240 1588
34 SEG33 2632 –1040 68 SEG67 –400 1588
Chip Specification Dimension (mm)
Chip size 5.59 × 3.50
Pad pitch 0.160 min.
Chip thickness 0.40 ±0.025
Pad surface area 0.10mm
1 5 10 15 20 25 30
80 75 70 65 60 55
50
45
40
35
85
90
95
100
(0,0)
D1600D
AA
X
Y
•SED1600DAB (AU PAD)
Chip Specification Dimension (mm)
Chip size 5.59 × 3.50
Pad pitch 0.153 min.
Chip thickness 0.525 ±0.025
Pad X Y Pad X Y Pad X Y
No. Name (µm) (µm) No. Name (µm) (µm) No. Name (µm) (µm)
1 SEG0 –2227 –1578 35 SEG34 2622 –871 69 SEG68 –538 1578
2 SEG1 –2074 –1578 36 SEG35 2622 –713 70 SEG69 –691 1578
3 SEG2 –1920 –1578 37 SEG36 2622 –554 71 SEG70 –845 1578
4 SEG3 –1766 –1578 38 SEG37 2622 –396 72 SEG71 –998 1578
5 SEG4 –1613 –1578 39 SEG38 2622 –238 73 SEG72 –1152 1578
6 SEG5 –1459 –1578 40 SEG39 2622 –79 74 SEG73 –1305 1578
7 SEG6 –1305 –1578 41 SEG40 2622 79 75 SEG74 –1459 1578
8 SEG7 –1152 –1578 42 SEG41 2622 238 76 SEG75 –1613 1578
9 SEG8 –998 –1578 43 SEG42 2622 396 77 SEG76 –1766 1578
10 SEG9 –845 –1578 44 SEG43 2622 554 78 SEG77 –1920 1578
11 SEG10 –691 –1578 45 SEG44 2622 713 79 SEG78 –2074 1578
12 SEG11 –538 –1578 46 SEG45 2622 871 80 SEG79 –2227 1578
13 SEG12 –384 –1578 47 SEG46 2622 1030 81 EI02 –2381 1578
14 SEG13 –230 –1578 48 SEG47 2622 1188 82 D0 –2622 1346
15 SEG14 –77 –1578 49 SEG48 2622 1346 83 D1 –2622 1193
16 SEG15 77 –1578 50 SEG49 2381 1578 84 D2 –2622 1039
17 SEG16 230 –1578 51 SEG50 2227 1578 85 D3 –2622 886
18 SEG17 384 –1578 52 SEG51 2074 1578 86 (D4) –2622 732
19 SEG18 538 –1578 53 SEG52 1920 1578 87 (D5) –2622 578
20 SEG19 691 –1578 54 SEG53 1766 1578 88 (D6) –2622 425
21 SEG20 845 –1578 55 SEG54 1613 1578 89 (D7) –2622 271
22 SEG21 998 –1578 56 SEG55 1459 1578 90 VDD –2622 106
23 SEG22 1152 –1578 57 SEG56 1305 1578 91 VSS –2622 –58
24 SEG23 1305 –1578 58 SEG57 1152 1578 92 V0 –2622 –223
25 SEG24 1459 –1578 59 SEG58 998 1578 93 V2 –2622 –388
26 SEG25 1613 –1578 60 SEG59 845 1578 94 V3 –2622 –553
27 SEG26 1766 –1578 61 SEG60 691 1578 95 V5 –2622 –718
28 SEG27 1920 –1578 62 SEG61 538 1578 96 SHL –2622 –886
29 SEG28 2074 –1578 63 SEG62 384 1578 97 XSCL –2622 –1039
30 SEG29 2227 –1578 64 SEG63 230 1578 98 LP –2622 –1193
31 SEG30 2381 –1578 65 SEG64 77 1578 99 FR –2622 –1346
32 SEG31 2622 –1346 66 SEG65 –77 1578 100 EI01 –2381 –1578
33 SEG32 2622 –1188 67 SEG66 –230 1578
34 SEG33 2622 –1030 68 SEG67 –384 1578
1 5 10 15 20 25 30
80 75 70 65 60 55
45
40
35
85
90
95
100
(0,0)
D1600D
AB
X
Y
50
153.6µ Pitch
153.6µ Pitch 20/1
158.4µ Pitch
153.6µ
Pitch
164.8µ
Pitch
153.6µ
Pitch
168µ
SED1600
478
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