128K x 32 Synchronous-Pipelined RAM
CY7C1340A/
GVT71128C32
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05153 Rev. *B Revised January 19, 2003
Features
• Fast access times: 5, 6, and 7 ns
• Fast clock speed: 100, 83, and 66 MHz
• Provides high performance 3-1-1-1 access rate
•Fast OE
access times: 5, 6, and 7 ns
• Optimal for performance (two-cycle chip deselect,
depth expansion without wait state)
• Single +3.3V –5% and +10%power supply
• Supports +2.5V I/O
• 5V tolerant inputs except I/Os
• Clamp diodes to VSSQ at all outputs
• Common data inputs and outputs
• Byte Write Enable and Global Write control
• Three chip enables for depth expansion and address
pipeline
• Address, control, input, and output pipeline registers
• Internally self-timed Write Cycle
• Burst control pins (interleaved or linear burst
sequence)
• Automatic power-down for portable applications
• High-den sity, high-spee d pack ages
• Low-capacitive bus loading
• High 30-pF output drive c apability at rate d access time
Functional Description
The Cypress Synchronous Burst SRAM family employs
high-speed, low-power CMOS designs using advanced
triple-layer polysilicon, double-layer metal technology. Each
memory cell consists of four transistors and two high valued
resistors.
The CY7C1340A/GVT71128C32 SRAM integrates
131,072 ×32 SRAM cells with advanced synchronous
peripheral circuitry and a two-bit counter for internal burst
operation. All synchronous inputs are gated by registers
controlled by a positive-edge-triggered Clock Input (CLK). The
synchronous inputs include all addresses, all data inputs,
address-pipelining chip enable (CE), depth-expansion Chip
Enables (CE2 and CE2), Burst Control Inputs (ADSC, ADSP,
and ADV), W rite Enables (B W1, BW2, BW3, BW4, and BWE ),
and Global Wri te (GW).
Asynchronous inputs include the Output Enable (OE) and
Burst Mode Control (MODE). The data outputs (Q), enabled
by OE, are also asynchronous.
Addresses and chip enables are registered with either
Address Status Processor (ADSP) or Address Status
Controller (ADSC) input pins. Subsequent burst addresses
can be internally generated as controlled by the Burst Advance
Pin (ADV).
Address, data inputs, and Write controls are registered on-chip
to initiate self-timed Write cycle. Write cycles can be one to
four bytes wide as controlled by the Write control inputs.
Individ ual byt e W r i te al lows ind iv idu al b yte to be w rit ten. BW 1
controls DQ1–DQ8. BW2 controls DQ9–DQ16. BW3 controls
DQ17–DQ24. BW4 controls DQ25–DQ32. BW1, BW2, BW3,
and BW4 can be ac tive on ly with BW E being LO W. GW being
LOW causes all bytes to be written. This device also incorpo-
rates pipelined enable circuit for easy depth expansion without
penalizing system performance.
The CY7C1340A/GVT71128C32 operates from a +3.3V
power sup pl y. All i npu ts and outputs are TTL -co mp ati ble . Th e
device is ideally suited for 486, Pentium®, 680 × 0, and
PowerPC™ system s an d f or s ys tem s tha t b ene fit from a w id e
synchronous data bus.
Selection Guide
7C1340A-100
71128C36-5 7C1340A-83
71128C36-6 7C1340A -6 6
71128C36-7 Unit
Maximum Access Time 5 6 7 ns
Maximum Operating Current 225 185 120 mA
Maximum CMOS Standby Current 2 2 2 mA