1PS8505B 11/18/09
Block Diagram
PI6C2510-133E
Low-Noise, Phase-Locked Loop
Clock Driver with 10 Clock Outputs
Features
• Operating Frequency up to 150 MHz
• Low-Noise Phase-Locked Loop Clock Distribution that meets
133 MHz Registered DIMM Synchronous DRAM modules
for server/workstation/PC applications
• Allows Clock Input to have Spread Spectrum modulation for
EMI reduction
• Low jitter: Cycle-to-Cycle jitter ±75ps max.
• On-chip series damping resistor at clock output drivers for
low noise and EMI reduction
• Operates at 3.3V VCC, 0–85°C
• Packages (Pb-free & Green available):
– Plastic 24-pin TSSOP (L)
Description
The PI6C2510-133E is a “enhanced,” low-skew, low-jitter,
phase-locked loop (PLL) clock driver, distributing high-frequency
clock signals for SDRAM and server applications. By connecting
the feedback FB_OUT output to the feedback FB_IN input, the
propagation delay from the CLK_IN input to any clock output
will be nearly zero. This zero-delay feature allows the CLK_IN
input clock to be distributed, providing one clock input to one
bank of ten outputs, with an output enable.
This clock driver is designed to meet the PC133 SDRAM
Registered DIMM specifi cation. For test purposes, the PLL can
be bypassed by strapping AVCC to ground.
Pin Confi guration
G10
CLK_IN
FB_IN PLL
AVcc
FB_OUT
Y[0:9]
24-Pin
L
AGND
VCC
Y0
Y1
Y2
GND
GND
Y3
Y4
VCC
G
FB_OUT
CLK_IN
AVCC
VCC
Y9
Y8
GND
GND
Y7
Y6
Y5
VCC
FB_IN
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
Functional Table
Inputs Outputs
G Y[0:9] FB_OUT
L L CLK_IN
H CLK_IN CLK_IN
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2PS8505B 11/18/09
PI6C2510-133E
Low–noise, Phase –Locked Loop
Clock Driver with 10 Clock Outputs
Pin Functions
Pin
Name Pin
Number Type Description
CLK_IN 24 I Reference Clock input. CLK_IN allows spread spectrum.
FB_IN 13 I Feedback input. FB_IN provides the feedback signal to the internal PLL.
G11I
Output bank enable. When G is LOW, outputs Y[0:9] are disabled to a logic
low state.
When G is HIGH, all outputs Y[0:9] are enabled.
FB_OUT 12 O
Feedback output. FB_OUT is dedicated for external feedback.
FB_OUT has an embedded series-damping resistor of same value as clock
outputs Y[0:9].
Y[0:9]
3, 4, 5, 8,
9, 15, 16,
17, 20,
21
OClock outputs. These outputs provide low-skew copies of CLK_IN.
Each output has an embedded series-damping resistor.
AV CC 23 Power
Analog power supply. AVcc can be also used to bupass the PLL for test
purposes. When AVcc is strapped to ground, PLL is bypassed and CLK_IN
bufferef directly to the device outputs.
AGND 1 Ground Analog ground. AGND provides thr ground referencefor the analog cir-
cuitry/
VCC
2, 10, 14,
22 Power Power Supply
GND 6, 7, 18,
19 Ground Ground
DC Specifi cations - Absolute maximum ratings over operating free-air temperature range.
Symbol Parameter Min. Max. Units
VIInput voltage range
–0.5
VCC + 0.5
V
VOOutput voltage range
VI_DC DC input voltage +5.0
IO_DC DC output current 100 mA
Power Maximum power dissipation at TA = 59˚C in
still airr 1.0 W
TSTG Storage temperature –65 160 °C
Note: Stress beyond those listed under “absolute maximum ratings” may cause permanent damage to the device.
Parameter Test Conditions VCC Min Typ Max Units
ICC VI = VCC or GND; IO = 0 3.6V 10 uA
CIVI = VCC or GND 3.3V 4pF
COVO = VCC or GND 6
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3PS8505B 11/18/09
PI6C2510-133E
Low–noise, Phase –Locked Loop
Clock Driver with 10 Clock Outputs
Recommended Operating Conditions
Symbol Parameter Min. Max. Units
VCC Supply voltage 3.0 3.6
V
VIH High level input voltage 2.0
VIL Low level input voltage 0.8
VIInput Voltage 0.0 VCC
TAOperating free-air temperature 0 85 °C
Electrical Characteristics (Over recommended operating free-air temperature range.)
Pull Up/Down Currents of PI6C2510-133E, VCC = 3.0V
Symbol Parameter Condition Min Max Units
ICH Pull-up current VOUT = 2.4V –13.6
mA
Pull-up current VOUT = 2.0V –22
ICIL
Pull-down current VOUT = 0.8V 19
Pull-down current VOUT = 0.55V 13
AC Specifi cations - Timing requirements over recommended ranges of supply voltage and operating
free-air temperature.
Symbol Parameter Min Max Units
FCLK Input Clock Frequency 25 150 MHz
Input Clock Duty Cycle 40 60 %
Stabilization Time after power up 1 ms
Switching Characteristics (Over recommended ranges of supply voltage and operating free-air temperature,
CL=30pF.)
Parameter From To VCC = 3.3V ± 0.3V,
0–85˚CUnits
Min. Typ. Max.
tphase error, with and without
spread spectrum CLK_IN↑ at 133MHz FB_IN↑–150 +150
psJitter, cycle-to-cycle, with and
without spread spectrum
Any Output or FB_
OUT in CLKn at 133
MHz
Output or FB_OUT
in CLKn+1 –75 +75
Skew, at 133 MHz Any Y or FB_OUT
Any Y or FB_OUT
150
Duty Cycle 45 50 55 %
tr, rise-time, 0.4V to 2.0V 1.0 ns
tf, fall-time, 2.0V to 0.4V 1.1
Note: These switching parameters are guaranteed, but not production tested.
09-0006
4PS8505B 11/18/09
PI6C2510-133E
Low–noise, Phase –Locked Loop
Clock Driver with 10 Clock Outputs
.303
.311
.047
1.20
.002
.006
SEATING
PLANE
.0256
BSC
.018
.030
.004
.008
.252
BSC
1
24
.169
.177
0.05
0.15
6.4
0.45
0.75
0.09
0.20
4.3
4.5
7.7
7.9
0.65 0.19
0.30
.007
.012
Max
DESCRIPTION: 24-Pin, 173-Mil Wide, TSSOP
PACKAGE CODE: L
DOCUMENT CONTROL NO.
PD - 1312
REVISION: E
DATE: 03/09/05
Pericom Semiconductor Corporation
3545 N. 1st Street, San Jose, CA 95134
1-800-435-2335 • www.pericom.com
Note:
1. Package Outline Exclusive of Mold Flash and Metal Burr
2. Controlling dimentions in millimeters
3. Ref: JEDEC MO-153F/AD
Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com
Order Information
Ordering Code Packaging Code Packaging Description Frequency Range
PI6C2510-133EL L 24-pin plastic TSSOP 25MHz - 150MHz
PI6C2510-133ELEX L Pb-Free & Green 24-pin plastic TSSOP 25MHz - 150MHz
Notes:
• Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
• E = Pb-free and Green
• Adding an X suffi x = Tape/Reel
Note:
• For latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php
09-0006
