2GB (x72, ECC, SR) 240-Pin DDR3 SDRAM VLP RDIMM Features DDR3 SDRAM VLP RDIMM MT18JBF25672P - 2GB MT18JBZF25672P - 2GB For component data sheets, refer to Micron's Web site: www.micron.com Features Figure 1: * DDR3 functionality and operations supported as defined in the component data sheet * 240-pin, very low profile registered dual in-line memory module (VLP RDIMM) * Compatible with ATCA form factors * Fast data transfer rates: PC3-10600, PC3-8500, or PC3-6400 * 2GB (256 Meg x 72) * VDD = 1.5V 0.075V * VDDSPD = +3.0V to +3.6V * Supports ECC error detection and correction * Nominal and dynamic on-die termination (ODT) for data and strobe signals * Single rank * On-board I2C temperature sensor with integrated serial presence-detect (SPD) EEPROM * 8 internal device banks * Fixed burst chop (BC) of 4 and burst length (BL) of 8 via the mode register set (MRS) * Selectable BC4 or BL8 on-the-fly (OTF) * Gold edge contacts * Pb-free * Fly-by topology * Terminated control, command, and address bus Table 1: 240-Pin VLP RDIMM (ATCA Compatible R/C M) PCB height: 17.9mm (0.705in) Options Marking * Full module heat spreader Z * Operating temperature1 - Commercial (0C TA +70C) None - Industrial (-40C TA +85C) I * Package - 240-pin DIMM Y * Frequency/CAS latency - 1.5ns @ CL = 8 (DDR3-1333)2 -1G5 - 1.5ns @ CL = 9 (DDR3-1333) -1G4 - 1.5ns @ CL = 10 (DDR3-1333)2 -1G3 - 1.87ns @ CL = 7 (DDR3-1066) -1G1 - 1.87ns @ CL = 8 (DDR3-1066)2 -1G0 - 2.5ns @ CL = 5 (DDR3-800)2 -80C - 2.5ns @ CL = 6 (DDR3-800)2 -80B Notes: 1. Contact Micron for industrial temperature module offerings. 2. Not recommended for new designs. Key Timing Parameters Data Rate (MT/s) t t RC (ns) Industry Nomenclature CL = 10 CL = 9 CL = 8 CL = 7 CL = 6 CL = 5 -1G5 PC3-10600 1333 1333 1333 1066 800 800 12 12 48 -1G4 PC3-10600 1333 1333 1066 1066 800 - 13.5 13.5 49.5 -1G3 PC3-10600 1333 - 1066 - 800 - 15 15 51 -1G1 PC3-8500 - - 1066 1066 800 - 13.125 13.125 50.625 -1G0 PC3-8500 - - 1066 - 800 - 15 15 52.5 -80C PC3-6400 - - - - 800 800 12.5 12.5 50 -80B PC3-6400 - - - - 800 - 15 15 52.5 PDF: 09005aef83244ee6/Source: 09005aef83244f69 JBF18C256x72PY.fm - Rev. B 6/08 EN 1 RCD (ns) t RP (ns) Speed Grade Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2008 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 2GB (x72, ECC, SR) 240-Pin DDR3 SDRAM VLP RDIMM Features Table 2: Addressing Parameter 2GB Refresh count 8K Row address 16K (A[13:0]) Device bank address 8 (BA[2:0]) Device configuration 1Gb (256 Meg x 4) Column address 2K (A[11, 9:0]) Module rank address Table 3: 1 (S0#) Part Numbers and Timing Parameters - 2GB Modules Base device: MT41J256M4,1 1Gb DDR3 SDRAM Part Number2 Module Density Configuration Module Bandwidth Memory Clock/ Data Rate Clock Cycles (CL-tRCD-tRP) MT18JBF25672P(I)Y-1G5__ 2GB 256 Meg x 72 10.6 GB/s 1.5ns/1333 MT/s 8-8-8 MT18JBF25672P(I)Y-1G4__ 2GB 256 Meg x 72 10.6 GB/s 1.5ns/1333 MT/s 9-9-9 MT18JBF25672P(I)Y-1G3__ 2GB 256 Meg x 72 10.6 GB/s 1.5ns/1333 MT/s 10-10-10 MT18JBF25672P(I)Y-1G1__ 2GB 256 Meg x 72 8.5 GB/s 1.87ns/1066 MT/s 7-7-7 MT18JBF25672P(I)Y-1G0__ 2GB 256 Meg x 72 8.5 GB/s 1.87ns/1066 MT/s 8-8-8 MT18JBF25672P(I)Y-80C__ 2GB 256 Meg x 72 6.4 GB/s 2.5ns/800 MT/s 5-5-5 MT18JBF25672P(I)Y-80B__ 2GB 256 Meg x 72 6.4 GB/s 2.5ns/800 MT/s 6-6-6 Table 4: Part Numbers and Timing Parameters - 2GB Modules With Heat Spreader Base device: MT41J256M4,1 1Gb DDR3 SDRAM Part Number2 Module Density Configuration Module Bandwidth Memory Clock/ Data Rate Clock Cycles (CL-tRCD-tRP) MT18JBZF25672P(I)Y-1G5__ 2GB 256 Meg x 72 10.6 GB/s 1.5ns/1333 MT/s 8-8-8 MT18JBZF25672P(I)Y-1G4__ 2GB 256 Meg x 72 10.6 GB/s 1.5ns/1333 MT/s 9-9-9 MT18JBZF25672P(I)Y-1G3__ 2GB 256 Meg x 72 10.6 GB/s 1.5ns/1333 MT/s 10-10-10 MT18JBZF25672P(I)Y-1G1__ 2GB 256 Meg x 72 8.5 GB/s 1.87ns/1066 MT/s 7-7-7 MT18JBZF25672P(I)Y-1G0__ 2GB 256 Meg x 72 8.5 GB/s 1.87ns/1066 MT/s 8-8-8 MT18JBZF25672P(I)Y-80C__ 2GB 256 Meg x 72 6.4 GB/s 2.5ns/800 MT/s 5-5-5 MT18JBZF25672P(I)Y-80B__ 2GB 256 Meg x 72 6.4 GB/s 2.5ns/800 MT/s 6-6-6 Notes: PDF: 09005aef83244ee6/Source: 09005aef83244f69 JBF18C256x72PY.fm - Rev. B 6/08 EN 1. The data sheet for the base device can be found on Micron's Web site. 2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions. Consult factory for current revision codes. Example: MT18JBF25672PY-1G1D1. 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2008 Micron Technology, Inc. All rights reserved 2GB (x72, ECC, SR) 240-Pin DDR3 SDRAM VLP RDIMM Pin Assignments and Descriptions Pin Assignments and Descriptions Table 5: Pin Assignments 240-Pin DDR3 VLP RDIMM Front 240-Pin DDR3 VLP RDIMM Back Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol 1 VREFDQ 31 DQ25 61 A2 91 DQ41 121 VSS 151 VSS 181 A1 211 VSS 2 VSS 32 VSS 62 VDD 92 VSS 122 DQ4 152 DQS12 182 VDD 212 DQS14 3 DQ0 33 DQS3# 63 NC 93 DQS5# 123 DQ5 153 DQS12# 183 VDD 213 DQS14# 4 DQ1 34 DQS3 64 NC 94 DQS5 124 VSS 154 184 CK0 214 VSS VSS 5 VSS 35 VSS 65 VDD 95 VSS 125 DQS9 155 DQ30 185 CK0# 215 DQ46 6 DQS0# 36 DQ26 66 VDD 96 DQ42 126 DQS9# 156 DQ31 186 VDD 216 DQ47 7 DQS0 37 DQ27 67 VREFCA 97 DQ43 127 VSS 157 VSS 187 EVENT# 217 8 VSS 38 VSS 68 PAR_IN 98 VSS 128 DQ6 158 CB4 188 9 DQ2 39 CB0 69 VDD 99 DQ48 129 DQ7 159 CB5 189 10 DQ3 40 CB1 70 A10 100 DQ49 130 VSS 160 VSS 190 DQS17 A0 VSS 218 DQ52 VDD 219 DQ53 BA1 220 VSS DQS15 11 VSS 41 VSS 71 BA0 101 VSS 131 DQ12 161 191 VDD 221 12 DQ8 42 DQS8# 72 VDD 102 DQS6# 132 DQ13 162 DQS17# 192 RAS# 222 DQS15# 13 DQ9 43 DQS8 73 WE# 103 DQS6 133 VSS 163 VSS 193 S0# 223 VSS 14 VSS 44 VSS 74 CAS# 104 VSS 134 DQS10 164 CB6 194 VDD 224 DQ54 15 DQS1# 45 CB2 75 VDD 105 DQ50 135 DQS10# 165 CB7 195 ODT0 225 DQ55 16 DQS1 46 CB3 76 NC 106 DQ51 136 VSS 196 A13 226 VSS VSS 166 17 VSS 47 VSS 77 NC 107 VSS 137 DQ14 167 NC 197 VDD 227 DQ60 18 DQ10 48 VTT 78 VDD 108 DQ56 138 DQ15 168 RESET# 198 NC 228 DQ61 19 DQ11 49 VTT 79 NC 109 DQ57 139 VSS 169 NC 199 VSS 229 VSS 20 VSS 50 CKE0 80 VSS 110 VSS 140 DQ20 170 VDD 200 DQ36 230 DQS16 21 DQ16 51 VDD 81 DQ32 111 DQS7# 141 DQ21 171 A15 201 DQ37 22 DQ17 52 BA2 82 DQ33 112 DQS7 142 VSS 172 A14 202 VSS 232 143 DQS11 DQS13 53 ERR_OUT# 83 231 DQS16# VSS 23 VSS VSS 113 VSS 173 VDD 203 233 DQ62 24 DQS2# 54 VDD 84 DQS4# 114 DQ58 144 DQS11# 174 A12 204 DQS13# 234 DQ63 25 DQS2 55 A11 85 DQS4 115 DQ59 145 VSS 175 A9 205 VSS 235 VSS 26 VSS 56 A7 86 VSS 116 VSS 146 DQ22 176 VDD 206 DQ38 236 VDDSPD 27 DQ18 57 VDD 87 DQ34 117 SA0 147 DQ23# 177 A8 207 DQ39 237 SA1 28 DQ19 58 A5 88 DQ35 118 SCL 148 VSS 178 A6 208 VSS 238 SDA 29 VSS 59 A4 89 VSS 119 SA2 149 DQ28 179 VDD 209 DQ44 239 VSS 30 DQ24 60 VDD 90 DQ40 120 VTT 150 DQ29 180 A3 210 DQ45 240 VTT PDF: 09005aef83244ee6/Source: 09005aef83244f69 JBF18C256x72PY.fm - Rev. B 6/08 EN 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2008 Micron Technology, Inc. All rights reserved 2GB (x72, ECC, SR) 240-Pin DDR3 SDRAM VLP RDIMM Pin Assignments and Descriptions Table 6: Pin Descriptions Symbol Type Description A[15:0] Input Address inputs: Provide the row address for ACTIVATE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA. A12 is also used for BC4/BL8 identification as "BL on-the-fly" during CAS commands. The address inputs also provide the op-code during the mode register command set. A[13:0] address the 1Gb DDR3 devices. A[15:14] are needed to calculate parity on the command/address bus. BA[2:0] Input Bank address inputs: BA[2:0] define the device bank to which an ACTIVATE, READ, WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode register (MR0, MR1, MR2, and MR3) is loaded during the LOAD MODE command. BA[1:0] are used as part of the parity calculation. CK0, CK0# Input Clock: CK and CK# are differential clock inputs. All control, command, and address input signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#. CKE0 Input Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal circuitry and clocks on the DRAM. ODT0 Input On-die termination: ODT enables (registered HIGH) and disables (registered LOW) termination resistance internal to the DRAM. When enabled in normal operation, ODT is only applied to the following pins: DQ, DQS, DQS#, and DM. The ODT input will be ignored if disabled via the LOAD MODE command. PAR_IN Input Parity input: Parity bit for the address, RAS#, CAS#, and WE#. RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered. RESET# Input (LVCMOS) S0# Input Chip select: S# enables (registered LOW) and disables (registered HIGH) the command decoder. SA[2:0] Input Serial address inputs: These pins are used to configure the temperature sensor/SPD EEPROM address range on the I2C bus. SCL Input Serial clock for temperature sensor/SPD EEPROM: SCL is used to synchronize communication to and from the temperature sensor/SPD EEPROM. CB[7:0] I/O Check bits: Data used for ECC. Reset: RESET# is an active LOW CMOS input referenced to VSS. The RESET# input receiver is a CMOS input defined as a rail-to-rail signal with DC HIGH 0.8 x VDD and DC LOW 0.2 x VDD. RESET# assertion and deassertion are asynchronous. System applications will most likely be unterminated, heavily loaded, and have very slow slew rates. A slow slew rate receiver design is recommended along with implementing on-chip noise filtering to prevent false triggering (RESET# assertion minimum pulse width is 100ns). DQ[63:0] I/O Data input/output: Bidirectional data bus. DQS[17:0], DQS#[17:0] I/O Data strobe: DQS and DQS# are differential data strobes. Output with read data. Edgealigned with read data. Input with write data. Center-aligned with write data. SDA I/O Serial data: SDA is a bidirectional pin used to transfer addresses and data into and out of the temperature sensor/SPD EEPROM on the module on the I2C bus. ERR_OUT# EVENT# Output Parity error output: Parity error found on the command and address bus. (open drain) Output Temperature event: The EVENT# pin is asserted by the temperature sensor when critical (open drain) temperature thresholds have been exceeded. PDF: 09005aef83244ee6/Source: 09005aef83244f69 JBF18C256x72PY.fm - Rev. B 6/08 EN 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2008 Micron Technology, Inc. All rights reserved 2GB (x72, ECC, SR) 240-Pin DDR3 SDRAM VLP RDIMM Pin Assignments and Descriptions Table 6: Pin Descriptions (continued) Symbol Type VDD Supply Description Power supply: 1.5V 0.075V. The component VDD and VDDQ are connected to the module VDD. VDDSPD Supply Temperature sensor/SPD EEPROM power supply: +3.0V to +3.6V. VREFCA Supply Reference voltage: Control, command, and address (VDD/2). VREFDQ Supply Reference voltage: DQ, DM (VDD/2). VSS Supply Ground. VTT Supply NC - No connect: These pins are not connected on the module. NF - No function: Connected within the module, but provides no functionality. PDF: 09005aef83244ee6/Source: 09005aef83244f69 JBF18C256x72PY.fm - Rev. B 6/08 EN Termination voltage: Used for control, command, and address (VDD/2). 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2008 Micron Technology, Inc. All rights reserved 2GB (x72, ECC, SR) 240-Pin DDR3 SDRAM VLP RDIMM Functional Block Diagram Functional Block Diagram Figure 2: Functional Block Diagram VSS RS0# DQS9 DQS9# DQS0 DQS0# DM CS# DQS DQS# DM CS# DQS DQS# DQ DQ DQ DQ DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U1 ZQ DQS1 DQS1# VSS VSS DQ12 DQ13 DQ14 DQ15 VSS DQ DQ DQ DQ ZQ ZQ ZQ ZQ ZQ ZQ CK0 CK0# RESET# P L L ZQ VSS CB4 CB5 CB6 CB7 ZQ DQ DQ DQ DQ U16 ZQ VSS RS0#: DDR3 SDRAM RBA[2:0]: DDR3 SDRAM RA[13:0]: DDR3 SDRAM RRAS#: DDR3 SDRAM RCAS#: DDR3 SDRAM RWE#: DDR3 SDRAM RCKE0: DDR3 SDRAM RODT0: DDR3 SDRAM ERR_OUT# R e g i s t e r a n d U11 DM CS# DQS DQS# U5 U6 S0# BA[2:0] A[15:0] RAS# CAS# WE# CKE0 ODT0 PAR_IN DQ DQ DQ DQ DQS17 DQS17# DM CS# DQS DQS# DQ DQ DQ DQ ZQ VSS DQ60 DQ61 DQ62 DQ63 VSS CB0 CB1 CB2 CB3 U12 DM CS# DQS DQS# U10 DQS8 DQS8# DQ DQ DQ DQ DQS16 DQS16# DM CS# DQS DQS# DQ DQ DQ DQ ZQ VSS DQ52 DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 U13 DM CS# DQS DQS# U9 DQS7 DQS7# DQ DQ DQ DQ DQS15 DQS15# DM CS# DQS DQS# DQ DQ DQ DQ ZQ VSS DQ44 DQ45 DQ46 DQ47 VSS DQ48 DQ49 DQ50 DQ51 U14 DM CS# DQS DQS# U8 DQS6 DQS6# DQ DQ DQ DQ DQS14 DQS14# DM CS# DQS DQS# DQ DQ DQ DQ ZQ VSS DQ36 DQ37 DQ38 DQ39 VSS DQ40 DQ41 DQ42 DQ43 U17 DM CS# DQS DQS# U7 DQS5 DQS5# DQ DQ DQ DQ DQS13 DQS13# DM CS# DQS DQS# DQ DQ DQ DQ ZQ VSS DQ28 DQ29 DQ30 DQ31 VSS DQ32 DQ33 DQ34 DQ35 U18 DM CS# DQS DQS# U4 DQS4 DQS4# DQ DQ DQ DQ DQS12 DQS12# DM CS# DQS DQS# DQ DQ DQ DQ ZQ VSS DQ20 DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 U19 DM CS# DQS DQS# U3 DQS3 DQS3# DQ DQ DQ DQ DQS11 DQS11# DM CS# DQS DQS# DQ16 DQ17 DQ18 DQ19 ZQ DM CS# DQS DQS# ZQ DQS2 DQS2# U20 DQS10 DQS10# DM CS# DQS DQS# DQ DQ U2 DQ DQ DQ8 DQ9 DQ10 DQ11 DQ DQ DQ DQ VSS VDDSPD U15 SCL DDR3 SDRAM VTT DDR3 SDRAM A1 A2 VREFCA DDR3 SDRAM SA0 SA1 SA2 VREFDQ DDR3 SDRAM VSS DDR3 SDRAM EVT A0 SDA EVENT# CK DDR3 SDRAM CK# DDR3 SDRAM Temperature sensor/SPD EEPROM VDD Temperature sensor/ SPD EEPROM Clock, control, command, and address line terminations: RS#, RCKE, RA[13:0], RRAS#, RCAS#, RWE#, RODT, RBA[2:0] DDR3 SDRAM VTT DDR3 SDRAM CK CK# Notes: PDF: 09005aef83244ee6/Source: 09005aef83244f69 JBF18C256x72PY.fm - Rev. B 6/08 EN VDD 1. The ZQ ball on each DDR3 component is connected to an external 240 1% resistor that is tied to ground. It is used for the calibration of the component's on-die termination and output driver. 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2008 Micron Technology, Inc. All rights reserved 2GB (x72, ECC, SR) 240-Pin DDR3 SDRAM VLP RDIMM General Description General Description The MT18JBF25672P and MT18JBZF25672P DDR3 SDRAM modules are high-speed, CMOS dynamic random access 2GB memory modules organized in x72 configurations. These DDR3 SDRAM modules use internally configured, 8-bank 1Gb DDR3 SDRAM devices. DDR3 SDRAM modules use double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR3 SDRAM module effectively consists of a single 8n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. The differential data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the DDR3 SDRAM input receiver. DQS is center-aligned with data for WRITEs. The read data is transmitted by the DDR3 SDRAM and edge-aligned to the data strobes. DDR3 SDRAM modules operate from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Control, command, and address signals are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. Fly-By Topology These DDR3 modules use faster clock speeds than earlier DDR technologies, making signal quality more important than ever. For improved signal quality, the clock, control, command, and address buses have been routed in a fly-by topology, where each clock, control, command, and address pin on each DRAM is connected to a single trace and terminated (rather than a tree structure, where the termination is off the module near the connector). Inherent to fly-by topology, the timing skew between the clock and DQS signals can be easily accounted for by using the write leveling feature of DDR3. Registering Clock Driver Operation Registered DDR3 SDRAM modules use a registering clock driver consisting of a register and a phase-lock loop (PLL) and comply with the JEDEC standard, "Definition of the SSTE32882 Registering Clock Driver with Parity and Quad Chip Selects for DDR3 RDIMM Applications" (pending approval). The register section of the registering clock driver latches command and address input signals on the rising clock edge. The PLL section of the registering clock driver receives and redrives the differential clock signals (CK, CK#) to the DDR3 SDRAM devices. The register(s) and PLL reduce clock, control, command, and address signals loading by isolating DRAM from the system controller. Parity Operations The registering clock driver can accept a parity bit from the system's memory controller, providing even parity for the control, command, and address bus. Parity errors are flagged on the ERR_OUT# pin. Systems not using parity are expected to function without issue if PAR_IN and ERR_OUT# are left as no connects to the system. PDF: 09005aef83244ee6/Source: 09005aef83244f69 JBF18C256x72PY.fm - Rev. B 6/08 EN 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2008 Micron Technology, Inc. All rights reserved 2GB (x72, ECC, SR) 240-Pin DDR3 SDRAM VLP RDIMM General Description Temperature Sensor with Serial Presence-Detect EEPROM Thermal Sensor Operations The temperature from the integrated thermal sensor is monitored and converted into a digital word via the I2C bus. System designers can use the user-programmable registers to create a custom temperature-sensing solution based on system requirements. Programming and configuration details comply with JEDEC Standard No. 21-C, page 4.7-1, "Mobile Platform Memory Module Thermal Sensor Component Specification." Serial Presence-Detect EEPROM Operation DDR3 SDRAM modules incorporate serial presence-detect. The SPD data is stored in a 256-byte EEPROM. The first 128 bytes are programmed by Micron to comply with JEDEC Standard JC-45 "Appendix X: Serial Presence-Detect (SPD) for DDR3 SDRAM Modules" (pending approval). These bytes identify module-specific timing parameters, configuration information, and physical attributes. User-specific information can be written into the remaining 128 bytes of storage. System READ/WRITE operations between the master (system logic) and the slave EEPROM device occur via a standard I2C bus using the DIMM's SCL (clock) and SDA (data) signals, together with SA[2:0], which provide eight unique DIMM/EEPROM addresses. Write protect (WP) is connected to VSS, permanently disabling hardware write protect. PDF: 09005aef83244ee6/Source: 09005aef83244f69 JBF18C256x72PY.fm - Rev. B 6/08 EN 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2008 Micron Technology, Inc. All rights reserved 2GB (x72, ECC, SR) 240-Pin DDR3 SDRAM VLP RDIMM Electrical Specifications Electrical Specifications Stresses greater than those listed in Table 7 may cause permanent damage to the module. This is a stress rating only, and functional operation of the module at these or any other conditions outside those indicated in each device's data sheet is not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability. Table 7: Absolute Maximum Ratings Symbol Parameter Min Max Units VDD VDD supply voltage relative to VSS -0.4 +1.975 V VIN, VOUT Voltage on any pin relative to VSS -0.4 +1.975 V Min Nom Max Table 8: Operating Conditions Symbol Parameter Units Notes VDD VDD supply voltage 1.425 1.5 1.575 V IVTT Termination reference current from VTT -600 - +600 mA VTT Termination reference voltage (DC) - command/address bus II Input leakage current; Any input 0V VIN VDD; VREF input 0V VIN 0.95V (All other pins not under test = 0V) Address inputs, RAS#, CAS#, WE#, S#, CKE, ODT, BA, CK, CK# IOZ Output leakage current; 0V VOUT VDD; DQ and ODT are disabled; ODT is HIGH DQ, DQS, DQS# IVREF TA TC 0.49 x VDD - 20mV 0.5 x VDD 0.51 x VDD + 20mV VREF supply leakage current; VREFDQ = VDD/2 or VREFCA = VDD/2 (All other pins not under test = 0V) Module ambient operating temperature Commercial Industrial DDR3 SDRAM component case Commercial operating temperature Industrial Notes: PDF: 09005aef83244ee6/Source: 09005aef83244f69 JBF18C256x72PY.fm - Rev. B 6/08 EN V TBD TBD TBD A -5 0 +5 A -18 0 +18 A 0 - +70 C -40 - +85 C 0 - +95 C -40 - +95 C 1 2, 3 2, 3, 4 1. VTT termination voltage in excess of the stated limit will adversely affect the command and address signals' voltage margin and will reduce timing margins. 2. TA and TC are simultaneous requirements. 3. For further information, refer to technical note TN-00-08: "Thermal Applications," available on Micron's Web site. 4. The refresh rate is required to double when 85C < TC 95C. 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2008 Micron Technology, Inc. All rights reserved 2GB (x72, ECC, SR) 240-Pin DDR3 SDRAM VLP RDIMM Electrical Specifications DRAM Operating Conditions Recommended AC operating conditions are given in the DDR3 component data sheets. Component specifications are available on Micron's Web site. Module speed grades correlate with component speed grades, as shown in Table 9. Table 9: Module and Component Speed Grades DDR3 components may exceed the listed module speed grades Module Speed Grade Component Speed Grade -1G5 -15F -1G4 -15E -1G3 -15 -1G1 -187E -1G0 -187 -80C -25E -80B -25 Design Considerations Simulations Micron memory modules are designed to optimize signal integrity through carefully designed terminations, controlled board impedances, routing topologies, trace length matching, and decoupling. However, good signal integrity starts at the system level. Micron encourages designers to simulate the signal characteristics of the system's memory bus to ensure adequate signal integrity of the entire memory system. Power Operating voltages are specified at the DRAM, not at the edge connector of the module. Designers must account for any system voltage drops at anticipated power levels to ensure the required supply voltage is maintained. PDF: 09005aef83244ee6/Source: 09005aef83244f69 JBF18C256x72PY.fm - Rev. B 6/08 EN 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2008 Micron Technology, Inc. All rights reserved 2GB (x72, ECC, SR) 240-Pin DDR3 SDRAM VLP RDIMM Electrical Specifications IDD Specifications Table 10: DDR3 IDD Specifications and Conditions - 2GB Values are for the MT41J256M4 DDR3 SDRAM only and are computed from values specified in the 1Gb (256 Meg x 4) component data sheet Parameter Symbol 1333 1066 800 Units Operating current 0: One bank ACTIVATE-to-PRECHARGE IDD0 1,530 1,350 1,170 mA Operating current 1: One bank ACTIVATE-to-READ-to-PRECHARGE IDD1 1,890 1,710 1,530 mA Precharge power-down current: Slow exit IDD2P 180 180 180 mA Precharge power-down current: Fast exit IDD2P 450 450 450 mA Precharge quiet standby current IDD2Q 900 810 720 mA Precharge standby current IDD2N 990 900 810 mA Active power-down current IDD3P 630 540 450 mA Active standby current IDD3N 1,080 990 900 mA 3,600 2,880 2,340 mA Burst read operating current IDD4R Burst write operating current IDD4W 3,420 2,880 2,340 mA Refresh current IDD5B 4,320 3,960 3,600 mA mA Self refresh temperature current: MAX TC = 85C Self refresh temperature current (SRT-enabled): MAX TC = 95C All banks interleaved read current PDF: 09005aef83244ee6/Source: 09005aef83244f69 JBF18C256x72PY.fm - Rev. B 6/08 EN 11 IDD6 108 108 108 IDD6ET 162 162 162 mA IDD7 5,670 4,500 4,140 mA Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2008 Micron Technology, Inc. All rights reserved 2GB (x72, ECC, SR) 240-Pin DDR3 SDRAM VLP RDIMM Registering Clock Driver Specifications Registering Clock Driver Specifications Table 11: Registering Clock Driver Electrical Characteristics SSTE32882 devices or equivalent Symbol Parameter Pins Min Nom Max Units VDD DC supply voltage - 1.425 1.5 1.575 V VREF DC reference voltage - 0.49 x VDD - 20mV 0.5 x VDD 0.51 x VDD + 20mV V VTT DC termination voltage - 0.49 x VDD - 20mV 0.5 x VDD 0.51 x VDD + 20mV V VIH(AC) AC high-level input voltage Control, command, address VREF + 175mV - VDD + 400mV V VIL(AC) AC low-level input voltage Control, command, address -0.4 - VREF - 175mV V VIH(DC) DC high-level input voltage Control, command, address VREF + 100mV - VDD + 0.4 V VIL(DC) DC low-level input voltage Control, command, address -0.4 - VREF - 100mV V VIH (CMOS) High-level input voltage RESET#, MIRROR 0.65 x VDD - VDD V VIL (CMOS) Low-level input voltage RESET#, MIRROR 0 - 0.35 x VDD V CK, CK#, FBIN, FBIN# 0.5 x VDD - 175mV 0.5 x VDD 0.5 x VDD + 175mV V VIX(AC) Differential input crosspoint voltage range VID(AC) Differential input voltage CK, CK# 350 - VDD + TBD mV IOH High-level output current ERR_OUT# - - TBD mA IOL Low-level output current ERR_OUT# TBD - TBD mA Notes: PDF: 09005aef83244ee6/Source: 09005aef83244f69 JBF18C256x72PY.fm - Rev. B 6/08 EN 1. Timing and switching specifications for the register listed above are critical for proper operation of the DDR3 SDRAM RDIMMs. These are meant to be a subset of the parameters for the specific device used on the module. 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2008 Micron Technology, Inc. All rights reserved 2GB (x72, ECC, SR) 240-Pin DDR3 SDRAM VLP RDIMM Temperature Sensor with Serial Presence-Detect EEPROM Temperature Sensor with Serial Presence-Detect EEPROM The temperature sensor continuously monitors the module's temperature and can be read back at any time over the I2C bus shared with the SPD EEPROM. Table 12: Temperature Sensor with Serial Presence-Detect EEPROM Operating Conditions Parameter/Condition Supply voltage Symbol Min Max Units VDDSPD +3.0 +3.6 V Supply current: VDD = 3.3V IDD - +2.0 mA Input high voltage: Logic 1; SCL, SDA VIH +1.45 VDDSPD + 1 V Input low voltage: Logic 0; SCL, SDA VIL - +0.55 V Output low voltage: IOUT = 2.1mA VOL - +0.4 V Input current IIN -5.0 +5.0 A Temperature sensing range - -40 +125 C Temperature sensor accuracy (class B) - -1.0 +1.0 C Symbol Min Max Units tBUF 4.7 - s SDA fall time tF 20 300 ns SDA rise time tR - 1,000 ns tHD:DAT 200 900 ns Start condition hold time tH:STA 4.0 - s Clock HIGH period tHIGH 4.0 50 s Clock LOW period tLOW Table 13: Sensor and EEPROM Serial Interface Timing Parameter/Condition Time bus must be free before a new transition can start Data hold time 4.7 - s fSCL 10 100 kHz Data setup time tSU:DAT 250 - ns Start condition setup time tSU:STA 4.7 - s Stop condition setup time tSU:STO 4.0 - s SCL clock frequency EVENT# Pin The temperature sensor also adds the EVENT# pin (open drain). Not used by the SPD EEPROM, EVENT# is a temperature sensor output used to flag critical events that can be set up in the sensor's configuration register. EVENT# has three defined modes of operation: interrupt mode, compare mode, and critical temperature mode. The open-drain output of EVENT# under the three separate operating modes is illustrated in Figure 3 on page 14. Event thresholds are programmed in the 0x01 register using a hysteresis. The alarm window provides a comparison window, with upper and lower limits set in the alarm upper boundary register and the alarm lower boundary register, respectively. When the alarm window is enabled, EVENT# will trigger whenever the temperature is outside the MIN or MAX values set by the user. The interrupt mode enables software to reset EVENT# after a critical temperature threshold has been detected. Threshold points are set in the configuration register by the user. This mode triggers the critical temperature limit and both the MIN and MAX of the temperature window. PDF: 09005aef83244ee6/Source: 09005aef83244f69 JBF18C256x72PY.fm - Rev. B 6/08 EN 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2008 Micron Technology, Inc. All rights reserved 2GB (x72, ECC, SR) 240-Pin DDR3 SDRAM VLP RDIMM Temperature Sensor with Serial Presence-Detect EEPROM The compare mode is similar to the interrupt mode, except EVENT# cannot be reset by the user and only returns to the logic HIGH state when the temperature falls below the programmed thresholds. Critical temperature mode triggers EVENT# only when the temperature has exceeded the programmed critical trip point. When the critical trip point has been reached, the temperature sensor goes into comparator mode, and the critical EVENT# cannot be cleared through software. SM Bus Slave Subaddress Decoding The temperature sensor's physical address differs from the SPD EEPROM's physical address: 0011 for A0, A1, A2, and RW# in binary where A2, A1, and A0 are the three slave subaddress pins and the RW# bit is the READ/WRITE flag. If the slave base address is fixed for the temperature sensor/SPD EEPROM, then the pins set the subaddress bits of the slave address, enabling the devices to be located anywhere within the eight slave address locations. For example, they could be set from 30h to 3Eh. Figure 3: EVENT# Pin Functionality Temperature Critical Hysteresis affects these trip points Alarm window (MAX) Alarm window (MIN) Clears event Time EVENT# interrupt mode EVENT# comparator mode EVENT# critical temperature only mode PDF: 09005aef83244ee6/Source: 09005aef83244f69 JBF18C256x72PY.fm - Rev. B 6/08 EN 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2008 Micron Technology, Inc. All rights reserved 2GB (x72, ECC, SR) 240-Pin DDR3 SDRAM VLP RDIMM Temperature Sensor with Serial Presence-Detect EEPROM Table 14: Temperature Sensor Registers Name Address Power-On Default Not applicable Undefined Capability register 0x00 0x0001 Configuration register 0x01 0x0000 Alarm temperature upper boundary register 0x02 0x0000 Pointer register Alarm temperature lower boundary register 0x03 0x0000 Critical temperature register 0x04 0x0000 Temperature register 0x05 Undefined Pointer Register The pointer register selects which of the 16-bit registers is being accessed in subsequent READ and WRITE operations. This register is a write-only register. Table 15: Pointer Register Bits 0-7 Bit 7 6 5 4 3 2 1 0 0 0 0 0 Register select Register select Register select Register select Table 16: Pointer Register Bits 0-2 Descriptions Bit 2 1 0 Register 0 0 0 Capability register 0 0 1 Configuration register 0 1 0 Alarm temperature upper boundary register 0 1 1 Alarm temperature lower boundary register 1 0 0 Critical temperature register 1 0 1 Temperature register PDF: 09005aef83244ee6/Source: 09005aef83244f69 JBF18C256x72PY.fm - Rev. B 6/08 EN 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2008 Micron Technology, Inc. All rights reserved 2GB (x72, ECC, SR) 240-Pin DDR3 SDRAM VLP RDIMM Temperature Sensor with Serial Presence-Detect EEPROM Capability Register The capability register indicates the features and functionality supported by the temperature sensor. This register is a read-only register. Table 17: Capability Register (Address: 0x00) Bit 15 14 13 12 11 10 9 8 RFU RFU RFU RFU RFU RFU RFU RFU 3 2 1 0 Wider range Precision Has alarm and critical temperature 10 9 8 Bit 7 6 5 RFU RFU RFU Table 18: Bit 4 Temperature resolution Capability Register Bit Descriptions Description 0 Basic capability 1: Has alarm and critical trip point capabilities 1 Accuracy 0: 2C over the active range and 3C over the monitor range 1: 1C over the active range and 2C over the monitor range 2 Wider range 0: Temperatures lower than 0C are clamped to a binary value of 0 1: Temperatures below 0C can be read 4:3 Temperature resolution 00: 0.5C LSB 01: 0.25C LSB 10: 0.125C LSB 11: 0.0625C LSB 15:5 0: Must be set to zero Configuration Register Table 19: Configuration Register (Address: 0x01) Bit 15 14 13 12 11 RFU RFU RFU RFU RFU Hysteresis Shutdown mode Bit 7 6 5 4 3 Critical lock bit Alarm lock bit Clear event Event output status Event output control PDF: 09005aef83244ee6/Source: 09005aef83244f69 JBF18C256x72PY.fm - Rev. B 6/08 EN 16 2 1 Critical event Event polarity only 0 Event mode Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2008 Micron Technology, Inc. All rights reserved 2GB (x72, ECC, SR) 240-Pin DDR3 SDRAM VLP RDIMM Temperature Sensor with Serial Presence-Detect EEPROM Table 20: Bit Configuration Register Bit Descriptions Description Notes 0 Event mode 0: Comparator mode 1: Interrupt mode Event mode cannot be changed if either of the lock bits is set. 1 EVENT# polarity 0: Active LOW 1: Active HIGH EVENT# polarity cannot be changed if either of the lock bits is set. 2 Critical event only 0: EVENT# trips on alarm or critical temperature event 1: EVENT# trips only if critical temperature is reached 3 Event output control 0: Event output disabled 1: Event output enabled 4 Event status This is a read-only field in the register. The event 0: EVENT# has not been asserted by this device causing the event can be determined from the read 1: EVENT# is being asserted due to an alarm window or temperature register. critical temperature condition 5 Clear event 0: No effect 1: Clears the event when the temperature sensor is in the interrupt mode 6 Alarm window lock bit 0: Alarm trips are not locked and can be changed 1: Alarm trips are locked and cannot be changed 7 Critical trip lock bit 0: Critical trip is not locked and can be changed 1: Critical trip is locked and cannot be changed 8 Shutdown mode 0: Enabled 1: Shutdown The shutdown mode is a power-saving mode that disables the temperature sensor. Hysteresis enable 00: Disable 01: Enable at 1.5C 10: Enable at 3C 11: Enable at 6C When enabled, a hysteresis is applied to temperature movement around the trip points. As an example, if the hysteresis register is enabled to a delta of 6C, the preset trip points will toggle when the temperature reaches the programmed value. These values will reset when the temperature drops below the trip points minus the set hysteresis level. In this case, this would be critical temperature minus 6C. 10:9 The hysteresis is applied both to the above alarm window and the below alarm window bits found in the read-only temperature register. EVENT# is also affected by this register. PDF: 09005aef83244ee6/Source: 09005aef83244f69 JBF18C256x72PY.fm - Rev. B 6/08 EN 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2008 Micron Technology, Inc. All rights reserved 2GB (x72, ECC, SR) 240-Pin DDR3 SDRAM VLP RDIMM Temperature Sensor with Serial Presence-Detect EEPROM Figure 4: Hysteresis TH 1 TH - Hyst TL 3 2 TL - Hyst Below window bit Above window bit Notes: Table 21: 1. TH is the value set in the alarm temperature upper boundary trip register. 2. TL is the value set in the alarm temperature lower boundary trip register. 3. Hyst is the value set in the hysteresis bits of the configuration register. Hysteresis Below Alarm Window Bit Above Alarm Window Bit Condition Temperature Gradient Critical Temperature Sets Falling TL - Hyst Rising TH Clears Rising TL Falling TH - Hyst PDF: 09005aef83244ee6/Source: 09005aef83244f69 JBF18C256x72PY.fm - Rev. B 6/08 EN 18 Temperature Gradient Critical Temperature Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2008 Micron Technology, Inc. All rights reserved 2GB (x72, ECC, SR) 240-Pin DDR3 SDRAM VLP RDIMM Temperature Sensor with Serial Presence-Detect EEPROM Temperature Format The temperature trip point registers and temperature readout register use a "2's complement" format to enable negative numbers. The least significant bit (LSB) is equal to 0.0625C or 0.25C depending on which register is referenced. As an example, assuming an LSB of 0.0625C: * A value of 0x018C would equal 24.75C * A value of 0x06C0 would equal 108C * A value of 0x1E74 would equal -24.75C Temperature Trip Point Registers The upper and lower temperature boundary registers are used to set the maximum and minimum values of the alarm window. LSB for these registers is 0.25C. All RFU bits in the register will always report zero. Table 22: Alarm Temperature Lower Boundary Register (Address: 0x02) Bit 15 14 13 12 11 0 0 0 MSB 10 9 8 7 6 5 4 3 2 1 0 LSB RFU RFU 2 1 0 LSB RFU RFU Alarm window upper boundary temperature Table 23: Alarm Temperature Lower Boundary Register (Address: 0x03) Bit 15 14 13 12 11 0 0 0 MSB 10 9 8 7 6 5 4 3 Alarm window lower boundary temperature Critical Temperature Register The critical temperature register is used to set the maximum temperature above the alarm window. The LSB for this register is 0.25C. All RFU bits in the register will always report zero. Table 24: Critical Temperature Register (Address: 0x04) Bit 15 14 13 12 0 0 0 MSB 11 10 9 8 7 6 5 4 3 2 1 0 LSB RFU RFU Critical temperature trip point PDF: 09005aef83244ee6/Source: 09005aef83244f69 JBF18C256x72PY.fm - Rev. B 6/08 EN 19 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2008 Micron Technology, Inc. All rights reserved 2GB (x72, ECC, SR) 240-Pin DDR3 SDRAM VLP RDIMM Temperature Sensor with Serial Presence-Detect EEPROM Temperature Register The temperature register is a read-only register that provides the current temperature detected by the temperature sensor. The LSB for this register is 0.0625C with a resolution of 0.0625C. The most significant bit (MSB) is 128C in the readout section of this register. The upper three bits of the register are used to monitor the trip points that are set in the previous three registers. Table 25: Temperature Register (Address: 0x05) Bit 15 14 13 12 Above critical trip Above alarm window Below alarm window MSB Table 26: 11 10 9 8 7 6 5 4 3 2 1 0 LSB Temperature Temperature Register Bit Descriptions Bit Description 13 Below alarm window 0: Temperature is equal to or above the lower boundary 1: Temperature is below alarm window 14 Above alarm window 0: Temperature is equal to or below the upper boundary 1: Temperature is above alarm window 15 Above critical trip point 0: Temperature is below critical trip point 1: Temperature is above critical trip point Serial Presence-Detect Data For the latest serial presence-detect data, refer to Micron's SPD page: www.micron.com/SPD. PDF: 09005aef83244ee6/Source: 09005aef83244f69 JBF18C256x72PY.fm - Rev. B 6/08 EN 20 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2008 Micron Technology, Inc. All rights reserved 2GB (x72, ECC, SR) 240-Pin DDR3 SDRAM VLP RDIMM Module Dimensions Module Dimensions Figure 5: 240-Pin DDR3 VLP RDIMM 4.0 (0.157) MAX Front view 133.50 (5.256) 133.20 (5.244) 0.75 (0.03) R (6X) U1 U2 U3 U4 U5 2.5 (0.098) D (2X) U6 U7 U8 U9 U10 18.0 (0.709) 17.8 (0.701) 2.3 (0.091) TYP 1.37 (0.054) 1.17 (0.046) 0.76 (0.03) R Pin 1 2.2 (0.087) TYP 1.0 (0.039) TYP 1.45 (0.057) TYP 9.5 (0.374) TYP 0.8 (0.031) TYP 54.68 (2.15) TYP Pin 120 123.0 (4.84) TYP Back view U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 3.0 (0.118) 4X TYP 3.05 (0.12) TYP Pin 240 Pin 121 5.0 (0.197) TYP 47.0 (1.85) TYP 71.0 (2.79) TYP 9.1 (0.358) MAX Module with heat spreader U1 U6 U10 1.37 (0.054) 1.17 (0.046) U11 Notes: U20 U15 1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted. 2. The dimensional diagram is for reference only. 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF: 09005aef83244ee6/Source: 09005aef83244f69 JBF18C256x72PY.fm - Rev. B 6/08 EN 21 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2008 Micron Technology, Inc. All rights reserved.