MT18JBF25672PY-1G1XX - Micron Technology, Inc.

Products and specifications discussed herein are subject to change by Micron without notice.

2GB (x72, ECC, SR) 240-Pin DDR3 SDRAM VLP RDIMM

Features

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DDR3 SDRAM VLP RDIMM

MT18JBF25672P – 2GB

MT18JBZF25672P – 2GB

For component data sheets, refer to Micron’s Web site: www.micron.com

Features

• DDR3 functionality and operations supported as

defined in the component data sheet

• 240-pin, very low profil e registered dual in-line

memory module (VLP RDIMM)

• Compatible with AT CA form factors

• Fast data transfer rates: PC3-10600, PC3-8500,

or PC3-6400

• 2GB (256 Meg x 72)

•V

DD = 1.5V ±0.075V

•V

DDSPD = +3.0V to +3.6V

• S upports ECC error detection and correction

• N ominal and dynamic on-die termination (ODT) for

data and strobe signals

• Si n gle rank

•On-board I

2C temperature sensor with integrated

serial presence-detec t (SPD ) EEPROM

•8 internal device banks

• Fixed burst chop (BC) of 4 and burst length (BL) of 8

via the mode register set (MRS)

• Selectable BC4 or BL8 on-the-fly (OTF)

• Gold edge contacts

•Pb-free

• Fly-by topology

• Terminated control, command, and address bus

Figure 1: 240-Pin VLP RDIMM

(ATCA Compatible R/C M)

Notes: 1. Contact Micron for industrial temperature

module offerings.

2. Not recommended for new designs.

Options Marking

• Full module heat spreader Z

• Operating temperature1

–Commercial (0°C ≤ TA ≤ +70°C) None

–Industrial (–40°C ≤ TA ≤ +85°C) I

•Package

–240-pin DIMM Y

• Frequency/CAS latency

–1.5ns @ CL = 8 (DDR3-1333)2-1G5

–1.5ns @ CL = 9 (DDR3-1333) -1G4

–1.5ns @ CL = 10 (DDR3-1333)2-1G3

–1.87ns @ CL = 7 (DDR3-1066) -1G1

–1.87ns @ CL = 8 (DDR3-1066)2-1G0

–2.5ns @ CL = 5 (DDR3-800)2-80C

–2.5ns @ CL = 6 (DDR3-800)2-80B

PCB height: 17.9mm (0.705in)

Table 1: Key Timing Parameters

Speed

Grade Industry

Nomenclature

Data Rate (MT/s) tRCD

(ns) tRP

(ns) tRC

(ns)CL = 10 CL = 9 CL = 8 CL = 7 CL = 6 CL = 5

-1G5 PC3-10600 1333 1333 1333 1066 800 800 12 12 48

-1G4 PC3-10600 1333 1333 1066 1066 800 – 13.5 13.5 49.5

-1G3 PC3-10600 1333 – 1066 – 800 – 15 15 51

-1G1 PC3-8500 – – 1066 1066 800 – 13.125 13.125 50.625

-1G0 PC3-8500 – – 1066 – 800 – 15 15 52.5

-80C PC3-6400 – – – – 800 800 12.5 12.5 50

-80B PC3-6400 – – – – 800 – 15 15 52.5

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2GB (x72, ECC, SR) 240-Pin DDR3 SDRAM VLP RDIMM

Features

Notes: 1. The data sheet for the base device can be found on Micron’s Web site.

2. All part numbers end with a two-place code (not shown) that designates component and

PCB revisions. Consult factory for current revision codes. Example: MT18JBF25672PY-1G1D1.

Table 2: Addressing

Parameter 2GB

Refresh count 8K

Row address 16K (A[13:0])

Device bank address 8 (BA[2:0])

Device configuration 1Gb (256 Meg x 4)

Column address 2K (A[11, 9:0])

Module rank address 1 (S0#)

Table 3: Part Numbers and Timing Parameters – 2GB Modules

Base device: MT41J256 M4,1 1Gb DDR3 SDRAM

Part Number2Module

Density Configuration Module

Bandwidth Memory Clock/

Data Rate Clock Cycles

(CL-tRCD-tRP)

MT18JBF25672P(I)Y-1G5__ 2GB 256 Meg x 72 10.6 GB/s 1.5ns/1333 MT /s 8-8 - 8

MT18JBF25672P(I)Y-1G4__ 2GB 256 Meg x 72 10.6 GB/s 1.5ns/1333 MT /s 9-9 - 9

MT18JBF25672P(I)Y-1G3__ 2GB 256 Meg x 72 10.6 GB/s 1.5ns/1333 MT/s 10-10-10

MT18JBF25672P(I)Y-1G1__ 2GB 256 Meg x 72 8.5 GB/s 1.87ns/1066 MT/s 7-7-7

MT18JBF25672P(I)Y-1G0__ 2GB 256 Meg x 72 8.5 GB/s 1.87ns/1066 MT/s 8-8-8

MT18JBF25672P(I)Y-80C__ 2GB 256 Meg x 72 6.4 GB/s 2.5ns/800 MT/s 5-5-5

MT18JBF25672P(I)Y-80B__ 2GB 256 Meg x 72 6.4 GB/s 2.5ns/800 MT/s 6-6-6

Table 4: Part Numbers and Timing Parameters – 2GB Modules With Heat Spreader

Base device: MT41J256 M4,1 1Gb DDR3 SDRAM

Part Number2Module

Density Configuration Module

Bandwidth Memory Clock/

Data Rate Clock Cycles

(CL-tRCD-tRP)

MT18JBZF25672P(I)Y-1G5__ 2GB 256 Meg x 72 10.6 GB/s 1.5ns/1333 MT/s 8-8-8

MT18JBZF25672P(I)Y-1G4__ 2GB 256 Meg x 72 10.6 GB/s 1.5ns/1333 MT/s 9-9-9

MT18JBZF25672P(I)Y- 1G3__ 2GB 256 Meg x 72 10.6 GB/s 1.5ns/1333 MT/s 10-10-10

MT18JBZF25672P(I)Y-1G1__ 2GB 256 Meg x 72 8.5 GB/s 1.87ns/1066 MT/s 7-7-7

MT18JBZF25672P(I)Y-1G0__ 2GB 256 Meg x 72 8.5 GB/s 1.87ns/1066 MT/s 8-8-8

MT18JBZF25672P(I)Y-80C__ 2GB 256 Meg x 72 6.4 GB/s 2.5ns/800 MT/s 5 -5 -5

MT18JBZF25672P(I)Y-80B__ 2GB 256 Meg x 72 6.4 GB/s 2.5ns/800 MT/s 6 -6 -6

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2GB (x72, ECC, SR) 240-Pin DDR3 SDRAM VLP RDIMM

Pin Assignments and Descriptions

Table 5: Pin Assignments

240-Pin DDR3 VLP RDIMM Front 240-Pin DDR3 VLP RDIMM Back

Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol

REFDQ 31 DQ25 61 A2 91 DQ41 121 VSS 151 VSS 181A1211VSS

2VSS 32 VSS 62 VDD 92 VSS 122 DQ4 152 DQS12 182 VDD 212 DQS14

3 DQ0 33 DQS3# 63 NC 93 DQS5# 123 DQ5 153 DQS12# 183 VDD 213 DQS14#

4 DQ1 34 DQS3 64 NC 94 DQS5 124 VSS 154 VSS 184 CK0 214 VSS

5VSS 35 VSS 65 VDD 95 VSS 125 DQS9 155 DQ30 185 CK0# 215 DQ46

6 DQS0# 36 DQ26 66 VDD 96 DQ42 126 DQS9# 156 DQ31 186 VDD 216 DQ47

7 DQS0 37 DQ27 67 VREFCA 97 DQ43 127 VSS 157 VSS 187 EVENT# 217 VSS

8VSS 38 VSS 68 PAR_IN98 VSS 128 DQ6 158 CB4 188 A0 218 DQ52

9DQ239CB069V

DD 99 DQ48 129 DQ7 159 CB5 189 VDD 219 DQ53

10 DQ3 40 CB1 70 A10 100 DQ49 130 VSS 160 VSS 190 BA1 220 VSS

11 VSS 41 VSS 71 BA0 101 VSS 131 DQ12 161 DQS17 191 VDD 221 DQS15

12 DQ8 42 DQS8# 72 VDD 102 DQS6# 132 DQ13 162 DQS17# 192 RAS# 222 DQS15#

13 DQ9 43 DQS8 73 WE# 103 DQS6 133 VSS 163 VSS 193 S0# 223 VSS

14 VSS 44 VSS 74 CAS# 104 VSS 134 DQS10 164 CB6 194 VDD 224 DQ54

15 DQS1# 45 CB2 75 VDD 105 DQ50 135 DQS10# 165 CB7 195 ODT0 225 DQ55

16 DQS1 46 CB3 76 NC 106 DQ51 136 VSS 166 VSS 196 A13 226 VSS

17 VSS 47 VSS 77 NC 107 VSS 137 DQ14 167 NC 197 VDD 227 DQ60

18 DQ10 48 VTT 78 VDD 108 DQ56 138 DQ15 168 RESET# 198 NC 228 DQ61

19 DQ11 49 VTT 79 NC 109 DQ57 139 VSS 169 NC 199 VSS 229 VSS

20 VSS 50 CKE0 80 VSS 110 VSS 140 DQ20 170 VDD 200 DQ36 230 DQS16

21 DQ16 51 VDD 81 DQ32 111 DQS7# 141 DQ21 171 A15 201 DQ37 231 DQS16#

22 DQ17 52 BA2 82 DQ33 112 DQS7 142 VSS 172 A14 202 VSS 232 VSS

23 VSS 53 ERR_OUT#83 VSS 113 VSS 143 DQS11 173 VDD 203 DQS13 233 DQ62

24 DQS2# 54 VDD 84 DQS4# 114 DQ58 144 DQS11# 174 A12 204 DQS13# 234 DQ63

25 DQS2 55 A11 85 DQS4 115 DQ59 145 VSS 175A9205VSS 235 VSS

26 VSS 56 A7 86 VSS 116 VSS 146 DQ22 176 VDD 206 DQ38 236 VDDSPD

27 DQ18 57 VDD 87 DQ34 117 SA0 147 DQ23# 177 A8 207 DQ39 237 SA1

28 DQ19 58 A5 88 DQ35 118 SCL 148 VSS 178A6208VSS 238 SDA

29 VSS 59 A4 89 VSS 119 SA2 149 DQ28 179 VDD 209 DQ44 239 VSS

30 DQ24 60 VDD 90 DQ40 120 VTT 150 DQ29 180 A3 210 DQ45 240 VTT

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2GB (x72, ECC, SR) 240-Pin DDR3 SDRAM VLP RDIMM

Pin Assignments and Descriptions

Table 6: Pin Descriptions

Symbol Type Description

A[15:0] Input Address inpu ts : Provide the row address for ACTIVATE commands, and the column

address and auto precharge bit (A10) for READ/WRITE commands, to select one location

out of the memory array in the respective bank . A10 is sampled during a PRECHARGE

command to determine whether the PRECHARGE applies to one bank (A10 LOW, bank

selected by BA[2:0]) or all banks (A10 HIGH). If only one bank is to be precharged, the

bank is selected by BA. A12 is also used for BC4/BL8 identification as “BL on-the-fly”

during CAS commands. The address inputs also provide the op-code during the mode

calculate parity on the command/address bus.

BA[2:0] Input Bank address inputs: BA[2:0] define the device bank to which an ACTIVATE, READ,

WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode register

(MR0, MR1, MR2, and MR3) is loaded during the LOAD MODE command. BA[1:0] are used

as part of the parity calculation.

CK0, CK0# Inp ut Clock: CK and CK# are differential clock inputs. All control, command, and address input

signals are sampled on the crossing of the positive edge of CK and the negative edge of

CK#.

CKE0 Input Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal

circuitry and clocks on the DRAM.

ODT0 Input On-die termination: ODT enables (registered HIGH) and disables (registered LOW)

termin a tion resistance internal to the DRAM. When enabled in normal operation, ODT is

only applied to the following pins: DQ, DQS, DQS#, an d DM. The ODT input will be

ignored if disabled via the LOAD MO DE co mmand .

PAR_INInput Parity input: Parity bit for the address, RAS#, CAS#, and WE#.

RAS#, CAS#,

WE# Input Command inputs: RAS#, CAS#, and WE# (along wit h S#) define the command bein g

entered.

RESET# Input

(LVCMOS) Reset: RESET# is an active LOW CMOS input referenced to VSS. The RESET# input receiver

is a CMOS input defined as a rail-to-rail signal with DC HIGH ≥0.8 × VDD and

DC LOW ≤0.2 × VDD. RESET# assertion and deassertion are asynchronous. System

applications will most likely be unterminated, heavily loaded, and have very slow slew

rates. A slow slew rate receiver design is recommended al on g with impl ementin g on -ch ip

noise filtering to prevent false triggering (RESET# assertion minimum pulse width is

100ns).

S0# Input Chip select: S# enables (registered LOW) and disables (registered HIGH) the command

decoder.

SA[2:0] Input Serial address inputs: These pins are used to configure the temperature sensor/SPD

EEPROM address range on the I2C bus.

SCL Input Serial clock for temperature sensor/SPD EEPROM: SCL is used to synchronize

communication to and from the temperature sensor/SPD EEPROM.

CB[7:0] I/O Check bits: Data used for ECC.

DQ[63:0] I/O Data input/output: Bidirectional data bus.

DQS[17:0],

DQS#[17:0] I/O Data strobe: DQS and DQS# are differential data strobes. Output with read data. Edge-

aligned with read data. Input with write data. Center-aligned with write data.

SDA I/O Serial data: SDA is a bidirectional pin used to transfer addresses and data into and out of

the temperature sensor/SPD EEPR OM on the module on the I2C bus.

ERR_OUT# Output

(open drain) Parity error output: Parity error found on the command and address bus.

EVENT# Output

(open drain) Temperature event: The EVENT# pin is asserted by the temperature sensor when critical

temperature thresholds have been exceeded.

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2GB (x72, ECC, SR) 240-Pin DDR3 SDRAM VLP RDIMM

Pin Assignments and Descriptions

VDD Supply Power supply: 1.5V ±0.075V. The component VDD and VDDQ are connected to the

module VDD.

VDDSPD Supply Temperature sensor/SPD EEPROM power supply: +3.0V to +3.6V.

VREFCA Supply Reference voltage: Control, command, and address (VDD/2).

VREFDQ Supply Reference voltage: DQ, DM (VDD/2).

VSS Supply Ground.

VTT Supply Termination voltage: Used for control, command, and address (VDD/2).

NC – No connect: These pins are not connected on the module.

NF – No function: Connected withi n the module, but provides no functionality.

Table 6: Pin Descriptions (continued)

Symbol Type Description

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2GB (x72, ECC, SR) 240-Pin DDR3 SDRAM VLP RDIMM

Functional Block Diagram

Figure 2: Functional Block Diagram

Notes: 1. The ZQ ball on each DDR3 component is connected to an external 240Ω ±1% resistor that is

tied to ground. It is used for the calibration of the component’s on-die termination and out-

put driver.

VREFCA

VSS

DDR3 SDRAM

VDD

DDR3 SDRAM

VDDSPD Temperature sensor/SPD EEPROM

VTT

DDR3 SDRAM

VREFDQ

DM CS# DQS DQS#

DQ0

DQ1

DQ2

DQ3

U1 DQ

DQ4

DQ5

DQ6

DQ7

U20

DQ8

DQ9

DQ10

DQ11

U2 DQ

DQ12

DQ13

DQ14

DQ15

U19

DQ16

DQ17

DQ18

DQ19

U3 DQ

DQ20

DQ21

DQ22

DQ23

U18

DQ24

DQ25

DQ26

DQ27

U4 DQ

DQ28

DQ29

DQ30

DQ31

U17

DQ32

DQ33

DQ34

DQ35

U7 DQ

DQ36

DQ37

DQ38

DQ39

U14

DQ40

DQ41

DQ42

DQ43

U8 DQ

DQ44

DQ45

DQ46

DQ47

U13

DQ48

DQ49

DQ50

DQ51

U9 DQ

DQ52

DQ53

DQ54

DQ55

U12

DQ56

DQ57

DQ58

DQ59

U10 DQ

DQ60

DQ61

DQ62

DQ63

U11

CB4

CB5

CB6

CB7

U16

CB0

CB1

CB2

CB3

VSS

RS0# DQS0

DQS0#

DQS1

DQS1#

DQS2

DQS2#

DQS3

DQS3#

DQS4

DQS4#

DQS5

DQS5#

DQS6

DQS6#

DQS7

DQS7#

DQS8

DQS8#

DQS9

DQS9#

DQS10

DQS10#

DQS11

DQS11#

DQS12

DQS12#

DQS13

DQS13#

DQS14

DQS14#

DQS15

DQS15#

DQS16

DQS16#

DQS17

DQS17#

DM CS# DQS DQS#

DM CS# DQS DQS# DM CS# DQS DQS#

VSS

ZQ ZQ

S0#

BA[2:0]

A[15:0]

RAS#

CAS#

WE#

CKE0

ODT0

PAR_IN

RESET#

CK0

CK0#

RS0#: DDR3 SDRAM

RBA[2:0]: DDR3 SDRAM

RA[13:0]: DDR3 SDRAM

RRAS#: DDR3 SDRAM

RCAS#: DDR3 SDRAM

RWE#: DDR3 SDRAM

RCKE0: DDR3 SDRAM

RODT0: DDR3 SDRAM

ERR_OUT#

CK#

DDR3 SDRAM

VSS

VSS VSS

RS#, RCKE, RA[13:0],

RRAS#, RCAS#, RWE#,

RODT, RBA[2:0]

CK#

Clock, control, command, and address line terminations:

DDR3

SDRAM

VTT

DDR3

SDRAM

VDD

U15

Temperature

sensor/

SPD EEPROM

A1 A2

SA0 SA1 SA2

SDA

SCL

EVT

EVENT#

DDR3 SDRAM

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2GB (x72, ECC, SR) 240-Pin DDR3 SDRAM VLP RDIMM

General Description

The MT18JBF25672P and MT18JBZF25672P DDR3 SDRAM modules ar e high-speed,

CMOS dynamic random access 2GB memory modules organized in x72 config urations.

These DDR3 SDRAM modules use internally configured, 8-bank 1Gb DDR3 SDRAM

devices.

DDR3 SDRAM modules use double data ra te architecture to achieve high-speed opera-

tion. The double data rate ar c hitecture is essentially an 8n-prefetch architecture with an

interface designed to transfer two data words per clock cycle at the I/O pins. A single

read or write access for the DDR3 SDRAM module effectively consis ts of a single

8n-bit-wide, one-clock-cycle dat a transfer at the inte rnal DRAM core and eight corre-

sponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins.

The differential data strobe (DQS, DQS#) is transmitted ext ernally, along with data, for

use in data capture at the DDR3 SDRAM input receiver. DQS is center-aligned with data

for WRITEs. The read data is tr ansmitted by the DDR3 SDRAM and edge-aligned to the

data strobes.

DDR3 SDRAM modul es operate from a differential clock (CK and CK#); the crossing of

CK going HIGH and CK# going LOW will be referred to as the positive edge of CK.

Control, command, and ad dress signals ar e r egister ed at every positive edge of CK. Input

data is registered on both edges of DQS, and output data is referenced to both edges of

DQS, as well as to both edges of CK.

Fly-By Topology

These DDR3 modules use faster clock speeds than earlier DDR technologies, making

signal quality more important than ever. For improved signal quality, the clock, control,

command, and address buses have been routed in a fly-by topology, where each clock,

control, command, and address pin on each DRAM is connected to a single trace and

terminated (rather than a tree structure, where the termination is off the module near

the connector). Inherent to fly-by topology, the timing skew between the clock and DQS

signals can be easily accounted for by using the write leveling feature of DDR3.

Registering Clock Driver Operation

Registered DDR3 SDRAM modules use a registering clock driver consisting of a register

and a phase-lock loop (PLL) and comply with the JEDEC standard, “Definition of the

SSTE32882 Registering Clock Driver with Parity and Quad Chip Selects for DDR3

RDIMM Applications” (pending approval).

The register section of the registering clock driver latches command and ad dress input

signals on the rising clock edge. The PLL section of the registering clock driver receives

and redrives the differential clock signals (CK, CK#) to the DDR3 SDRAM devices. The

isolating DR A M from the system controller.

Parity Operations

The registering clock driv er can accept a parity bit from the system’s memory controller,

providing even pari ty for th e c ontrol, command, and address bus. Parity errors are

flagged on the ERR_OUT# pin. Systems not using parity are expected to function without

issue if PAR_IN and ERR_OUT# are left as no connects to the system.

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2GB (x72, ECC, SR) 240-Pin DDR3 SDRAM VLP RDIMM

General Description

Temperature Sensor with Serial Presence-Detect EEPROM

Thermal Sensor Operations

The temperature from the integrated thermal sensor is monitored and converted into a

digital word via the I2C bus. System designers can use the user-pr o grammable registers

to create a custom temperature-sensing solution based on system requir ements .

Progr amming and configuration details comply with JEDEC Standard No. 21-C, page

4.7-1, “Mobile Platform Memory Module Thermal Sensor C omponent Specification.”

Serial Presence-Detect EEPROM Operation

DDR3 SDRAM modules incorporate ser i al presence -d etect. The SPD data is stored in a

256-b yte EEPROM. The first 128 b ytes ar e programmed b y M icron to comply with JEDEC

S tandar d JC-45 “Appendix X: Serial Presence-Detect (SPD) for DDR3 SDRAM Modules”

(pending approval). These bytes identify module-specific timing parameters, configura-

tion information, and physical attributes. User-specific information can be written into

the remaining 128 bytes of storage. System READ/WRITE operations between the

master (system logic) and the slave EEPROM device occur via a standard I2C bus using

the DIMM’s SCL (clock) and SDA (data) signal s, together with SA[2:0], which provide

eight unique DIMM/EEPROM addresses. Write protect (WP) is connected to VSS, perma-

nently disabling hardware write protect.

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2GB (x72, ECC, SR) 240-Pin DDR3 SDRAM VLP RDIMM

Electrical Specifications

S tresses greater than those listed in Table7 may cause permanent damage to the

module. This is a stre ss rating only, and functional operation of the module at these or

any other conditions outside those indicated in each device’s data sheet is not implied.

Exposure to absolute maximum rating conditions for extended periods may adversely

affect reli ability.

Notes: 1. VTT termination voltage in excess of the stated limit will adversely affect the command and

address signals’ voltage margin and will reduce timing margins.

2. TA and TC are simultaneous requirements.

3. For further information, refer to technical note TN-00-08: “Thermal Applications,” available

on Micron’s Web site.

4. The refresh rate is required to double when 85°C < TC ≤ 95°C.

Table 7: Absolute Maximum Ratings

Symbol Parameter Min Max Units

VDD VDD supply voltage relative to VSS –0.4 +1.975 V

VIN, VOUT Voltage on any pin relative to VSS –0.4 +1.975 V

Table 8: Operating Condition s

Symbol Parameter Min Nom Max Units Notes

VDD VDD supply voltage 1.425 1.5 1.575 V

IVTT Termination reference current from VTT –600 – +600 mA

VTT Termination reference voltage (DC) –

command/address bus 0.49 × VDD - 20mV 0.5 × VDD 0.51 × VDD + 20mV V 1

IIInput leakage current ;

Any input 0V ≤VIN ≤VDD;

VREF input 0V ≤ VIN ≤ 0.95V

(All other pins not under

test = 0V)

Address

inputs,

RAS#, CAS#,

WE#, S#,

CKE, ODT,

BA, CK, CK#

TBD TBD TBD µA

IOZ Output leakage current;

0V ≤ VOUT ≤ VDD;

DQ and ODT are disabled;

ODT is HIGH

DQ, DQS,

DQS# –5 0 +5 µA

IVREF VREF supply leakage current;

VREFDQ = VDD/2 or VREFCA = VDD/2

(All other pins not un der test = 0V)

–18 0 +18 µA

TAModule ambient operating

temperature Commercial 0 – +70 °C 2, 3

Industrial –40 – +85 °C

TCDDR3 SDRAM component case

operating temperature Commercial 0 – +95 °C 2, 3, 4

Industrial –40 – +95 °C

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2GB (x72, ECC, SR) 240-Pin DDR3 SDRAM VLP RDIMM

Electrical Specifications

DRAM Operating Conditions

Re commended AC operating conditions are given in the DDR3 component data sheets.

Component specifications are available on Micron’s Web site. Module speed grades

correlate with component speed grades, as shown in Table 9.

Design Considerations

Simulations

Micron memor y mod u le s are designed to optimize signal integrity through carefully

designed terminations, controlled board impedances, routing topologies, trace length

matching, and decoupling. However, good signal integrity starts at the system level.

Micron encourages designers to simulate the signal characteristics of the system’s

memory bus to ensure adequate signal integrity of the entire memory system.

Power

Operating v oltages ar e specified at the DRAM, not at the edge connector of the module.

Designers must account for any system voltage drops at anticipated power levels to

ensure the required supply voltag e is maintained.

Table 9: Module and Component Speed Grades

DDR3 components may exce ed the listed module sp eed grades

Module Speed Grade Component Speed Grade

-1G5 -15F

-1G4 -15E

-1G3 -15

-1G1 -187E

-1G0 -187

-80C -25E

-80B -25

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2GB (x72, ECC, SR) 240-Pin DDR3 SDRAM VLP RDIMM

Electrical Specifications

IDD Specifications

Table 10: DDR3 IDD Specifications and Conditions – 2GB

Values are for the MT41J256M4 DDR3 SDRAM only and are computed from values specified in the

1Gb (256 Meg x 4) component data sheet

Parameter Symbol 1333 1066 800 Units

Operating current 0: One bank ACTIVATE-to-PRECHARGE IDD0 1,530 1,350 1,170 mA

Operating current 1: One bank ACTIVATE-to-READ-to-PRECHARGE IDD1 1,890 1,710 1,530 mA

Precharge power-down current: Slow exit IDD2P 180 180 180 mA

Precharge power-down current: Fast exit IDD2P 450 450 450 mA

Precharge quiet standby current IDD2Q 900 810 720 mA

Precharge standby current IDD2N 990 900 810 mA

Active power-down current IDD3P 630 540 450 mA

Active standby current IDD3N 1,080 990 900 mA

Burst read operating current IDD4R 3,600 2,880 2,340 mA

Burst write operat ing current IDD4W 3,420 2,880 2,340 mA

Refresh current IDD5B 4,320 3,960 3,600 mA

Self refresh temperature current: MAX TC = 85°C IDD6 108 108 108 mA

Self refresh temperature current (SRT-enabled): MAX TC = 95°C IDD6ET 162 162 162 mA

All banks interleaved read current IDD7 5,670 4,500 4,140 mA

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2GB (x72, ECC, SR) 240-Pin DDR3 SDRAM VLP RDIMM

Registering Clock Driver Specifications

Notes: 1. Timing and switching specifications for the register listed above are critical for proper oper-

ation of the DDR3 SDRAM RDIMMs. These are meant to be a subset of the parameters for

the specific device used on the module.

Table 11: Registering Clock Driver Electrical Characteristics

SSTE32882 devices or equivalent

Symbol Parameter Pins Min Nom Max Units

VDD DC supply voltage – 1.425 1.5 1.575 V

VREF DC reference voltage – 0.49 × VDD - 20mV 0.5 × VDD 0.51 × VDD + 20mV V

VTT DC termination voltage – 0.49 × VDD - 20mV 0.5 × VDD 0.51 × VDD + 20mV V

VIH(AC) AC high-level input

voltage Control,

command, address VREF + 175mV – VDD + 400mV V

VIL(AC) AC low-level input

voltage Control,

command, address –0.4 – VREF - 175mV V

VIH(DC) DC high-level input

voltage Control,

command, address VREF + 100mV – VDD + 0.4 V

VIL(DC) DC low-level input

voltage Control,

command, address –0.4 – VREF - 100mV V

VIH (CMOS) High-level input voltage RESET#, MIRROR 0.65 × VDD – VDD V

VIL (CMOS) Low-level input voltage RESET#, MIRROR 0 – 0.35 × VDD V

VIX(AC) Differential input

crosspoint vo ltage range CK, CK#, FBIN,

FBIN# 0.5 × VDD - 175mV 0.5 × VDD 0.5 × VDD + 175mV V

VID(AC) Differential input voltage CK, CK# 350 – VDD + TBD mV

IOH High-level output current ERR_OUT#– –TBDmA

IOL Low-level output current ERR_OUT# TBD – TBD mA

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2GB (x72, ECC, SR) 240-Pin DDR3 SDRAM VLP RDIMM

Temperature Sensor with Serial Presence-Detect EEPROM

The temperature sensor continuousl y monitors the modul e’s temperatur e and can be

read back at any time over the I2C bus shared with the SPD EEPROM.

EVENT# Pin

The temperature sensor also adds the EVENT# pin (open drain). Not used by the SPD

EEPR OM, EVENT# is a temperature sensor output used to flag critical events that can be

set up in the sensor’s configuration register.

EVENT# has thre e defined modes of operati o n: interrupt mode, compare mode , and

critical temperature mode. The open-drain output of EVENT# under the three separate

operating modes is illustrated in Figure 3 on page 14. Event thresholds are programmed

in the 0x01 register using a hysteresis. The alarm window provides a comparison

window, with upper and lower limits set in the alarm upper boundary register and the

alarm lower boundary register, respectively. When the alarm window is enabled,

EVENT# will trigger whenever the temperature is outside the MIN or MAX va lues set by

the user.

The interrupt mode enables software to reset EVENT# after a critical temperature

threshold has been detected. Threshold points ar e set in the configuration r egister b y the

user. This mode triggers the critical temper ature limit and both the MIN and MAX of the

temperature window.

Table 12: Temperature Sensor with Serial Presence-Detect EEPROM Operating Conditions

Parameter/Condition Symbol Min Max Units

Supply voltage VDDSPD +3.0 +3.6 V

Supply current: V DD = 3.3V IDD –+2.0mA

Input high voltage: Logic 1; SCL, SDA VIH +1.45 VDDSPD + 1 V

Input low voltage: Logic 0; SCL, SDA VIL –+0.55V

Output low voltage: IOUT = 2.1mA VOL –+0.4V

Input current IIN –5.0 +5.0 µA

Temperature sensing range – –40 +125 °C

Temperature sensor accuracy (class B) – –1.0 +1.0 °C

Table 13: Sensor and EEPROM Serial Interface Timing

Parameter/Condition Symbol Min Max Units

Time bus must be free before a new transition can start tBUF 4.7 – µs

SDA fall time tF20300ns

SDA rise time tR – 1,000 ns

Data hold time tHD:DAT 200 900 ns

Start condition hold time tH:STA 4.0 – µs

Clock HIGH period tHIGH 4.0 50 µs

Clock LOW period tLOW 4.7 – µs

SCL clock frequency fSCL 10 100 kHz

Data setup time tSU:DAT 250 – ns

Start condition setup time tSU:STA 4.7 – µs

Stop condition setup time tSU:STO 4.0 – µs

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2GB (x72, ECC, SR) 240-Pin DDR3 SDRAM VLP RDIMM

Temperature Sensor with Serial Presence-Detect EEPROM

The compar e mode is similar to the interrupt mode, except EVENT # cannot be reset by

the user and only returns to the logic HIGH state when the temperature falls below the

programmed thresholds.

Critical te m perature mode tr iggers EVENT# only when the te mperature has exceeded

the programmed critical trip point. When the critical trip point has bee n reached, the

temperature sensor goes into comparator mode, and the critical EVENT# cannot be

cleare d th rou gh software.

SM Bus Slave Subaddress Decoding

The temperature sensor’s physical address differs from the SPD EEPROM’s physical

address: 0011 for A0, A1, A2, and RW# in binary where A2, A1, and A0 are the three slave

subaddress pins and the R W# bit is the READ/WRITE flag.

If the slave base addr ess is fixed for the temper atur e sensor/SPD EEPR OM, then the pins

set the subaddr ess bits of the sl ave ad dr es s, e nabling the device s to be located anywhere

within the eight slave address locations. For example, they could be set from 30h to 3Eh.

Figure 3: EVENT# Pin Functionality

Time

Temperature

Critical

Alarm window (MAX)

Alarm window (MIN)

EVENT#

interrupt mode

EVENT#

comparator mode

EVENT#

critical temperature only mode

Clears event

Hysteresis affects

these trip points

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2GB (x72, ECC, SR) 240-Pin DDR3 SDRAM VLP RDIMM

Temperature Sensor with Serial Presence-Detect EEPROM

Pointer Register

The pointer r eg ister selec ts which of the 16-bit registers is being accessed in subsequent

READ and WRITE operations. This register is a write-only register.

Table 14: Temperature Sensor Registers

Name Address Power-On Default

Pointer register Not applicable Undefined

Capability register 0x00 0x0001

Configuration register 0x01 0x0000

Alarm temperature upper boundary register 0x02 0x0000

Alarm temperature lower boundary register 0x03 0x0000

Critical temperature register 0x04 0x0000

Temperature register 0x05 Undefined

Table 15: Pointer Register Bits 0–7

Bit

76543210

0000Register

select Register

select

Table 16: Pointer Register Bits 0–2 Descriptions

Bit

Register210

0 0 0 Capability register

0 0 1 Configuration register

0 1 0 Alarm temperature upper boundary register

0 1 1 Alarm temperature lo wer boundary register

1 0 0 Critical temperature register

1 0 1 Temperature reg i s te r

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2GB (x72, ECC, SR) 240-Pin DDR3 SDRAM VLP RDIMM

Temperature Sensor with Serial Presence-Detect EEPROM

Capability Register

The capability register indicates the features and functionality supported b y the temper-

ature sensor. This register is a read-only register.

Configuration Register

Table 17: Capability Register (Address: 0x00)

Bit

15 14 13 12 11 10 9 8

RFU RFU RFU RFU RFU RFU RFU RFU

Bit

765432 1 0

RFU RFU RFU Temperature resolution Wider range Precision Has alarm

and critic al

temperature

Table 18: Capability Register Bit Descriptions

Bit Description

0 Basic capability

1: Has alarm and critical trip point capabilities

1Accuracy

0: ±2°C over the active range and ±3°C over the monitor range

1: ±1°C over the active range and ±2°C over the monitor range

2 Wider range

0: Temperatures lower than 0°C are clamped to a binary value of 0

1: Temperatures below 0°C can be read

4:3 Temperature resolution

00: 0.5°C LSB

01: 0.25°C LSB

10: 0.125°C LSB

11: 0.0625°C LSB

15:5 0: Must be set to zero

Table 19: Configuration Register (Address: 0x01)

Bit

15 14 13 12 11 10 9 8

RFU RFU RFU RFU RFU Hysteresis Shutdown

mode

Bit

76543210

Critical lock

bit Alarm lock bit Clear event Event output

status Event output

control Critical event

only Event polarity Event mode

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2GB (x72, ECC, SR) 240-Pin DDR3 SDRAM VLP RDIMM

Temperature Sensor with Serial Presence-Detect EEPROM

Table 20: Configuration Register Bit Descriptions

Bit Description Notes

0 Event mode

0: Comparator mode

1: Interrupt mode

Event mode cannot be c hanged if either of the lock bits

is set.

1 EVENT# polarity

0: Active LOW

1: Active HIGH

EVENT# polarity cannot be changed if either of the lock

bits is set.

2 Critical event only

0: EVENT# trips on alarm or critical temperature event

1: EVENT# trips only if critical temperature is re ached

3 Event output control

0: Event output disabled

1: Event output enabled

4Event status

0: EVENT# has not been asserted by this device

1: EVENT# is being asserted due to an alarm window or

critical temperature cond ition

This is a read-only field in the register. The event

causing the event can be determined from the read

temper a ture register.

5 Clear event

0: No effect

1: Clears the event when the temperature sensor is in

the interrupt mode

6 Alarm window lock bit

0: Alarm trips are not locked and can be changed

1: Alarm trips are locked and cannot be changed

7 Critical trip lock bit

0: Critical trip is not locked and can be changed

1: Critical trip is locked and cannot be changed

8 Shutdown mode

0: Enabled

1: Shutdown

The shutdo wn mode is a power-saving mode that

disables the temperature sensor.

10:9 Hysteres is enable

00: Disable

01: Enable at 1.5°C

10: Enable at 3°C

11: Enable at 6°C

When enabled, a hysteresis is applied to temperature

movement around the trip points. As an example, if the

hysteresis register is enabled to a delta of 6°C, the

preset trip points will toggle when the temperature

reaches th e programme d va lue. These values will reset

when the temperature drops below the trip points

minus the set hysteresis level. In this case, this would be

critical temperature minus 6°C.

The hysteresis is applied both to the above alarm

window and the below alarm window bits found in the

read-only temperature register. EVENT# is also affected

by this register.

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2GB (x72, ECC, SR) 240-Pin DDR3 SDRAM VLP RDIMM

Temperature Sensor with Serial Presence-Detect EEPROM

Figure 4: Hysteresis

Notes: 1. TH is the value set in the alarm temperature upper boundary trip registe r.

2. TL is the value set in the alarm tempera ture lower boundary trip register.

3. Hyst is the value set in the hysteresis bits of th e configuration register.

Table 21: Hysteresis

Condition

Below Alarm Window Bit Above Alarm Window Bit

Temperature

Gradient Critical Temperature Temperature

Gradient Critical Temperature

Sets Falling TL - Hyst Rising TH

Clears Rising TLFalling TH - Hyst

TH - Hyst

TL - Hyst

Below window bit

Above window bit

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2GB (x72, ECC, SR) 240-Pin DDR3 SDRAM VLP RDIMM

Temperature Sensor with Serial Presence-Detect EEPROM

Temperature Format

The temperature trip point registers and temper ature readout register use a

“2’s complement” format to enable negative numbers. The least significant bit (LSB) is

equal to 0.0625°C or 0.25°C depending on which register is referenced. As an example,

assuming an LSB of 0.0625°C:

• A value of 0x018C would equal 24.75°C

• A value of 0x06C0 would equal 108°C

• A value of 0x1E74 would equal –24.75°C

Temperature Trip Point Registers

The upper and lower temperature boundary registe r s are used to set the maximum and

minimum values of the alarm window. LSB for these registers is 0.25°C. All RFU bits in

the register will always r eport zero.

Critical Temperature Register

The critical temperature register is used to set the maximum temperature above the

alarm window. The LSB for this register is 0.25°C. All RFU bits in the register will always

report zero.

Table 22: Alarm Temperature Lower Boundary Register (Address: 0x02)

Bit

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

000MSB LSB RFU RFU

Alarm window upper boundary temperature

Table 23: Alarm Temperature Lower Boundary Register (Address: 0x03)

Bit

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

000MSB LSB RFU RFU

Alarm window lower boundary temperature

Table 24: Critical Temperature Register (Address: 0x04)

Bit

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

000MSB LSB RFU RFU

Critical temperature trip point

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2GB (x72, ECC, SR) 240-Pin DDR3 SDRAM VLP RDIMM

Temperature Sensor with Serial Presence-Detect EEPROM

Temperature Register

The temperature r egister is a read -only register that provides the current temperature

detected by the temperature sensor. The LSB for this register is 0.0625°C with a resolu-

tion of 0.0625°C. The most significant bit (MSB) is 128°C in the readout section of this

The upper three bits of the register are used to monitor the trip points that are set in the

previous t hre e re gisters.

Serial Presence-Detect Data

For the latest serial presence-detect data, refer to Micron’s SPD page:

www.micron.com/SPD.

Table 25: Temperature Register (Address: 0x05)

Bit

15 14 13 12 11 10 9876543210

Above

critical

trip

Above

alarm

window

Below

alarm

window

MSB LSB

Temperature

Table 26: Temperature Register Bit Descriptions

Bit Description

13 Below alarm window

0: Temperature is equal to or above the lower boundary

1: Temperature is below alarm window

14 Above alarm window

0: Temperature is equal to or below the upper boun dary

1: Temperature is above alarm window

15 Above critical trip point

0: Temperature is below critical trip point

1: Temperature is above critical trip point

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992

Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respec-

tive owners.

This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although

considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.

2GB (x72, ECC, SR) 240-Pin DDR3 SDRAM VLP RDIMM

Module Dimensions

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Module Dimensions

Figure 5: 240-Pin DDR3 VLP RDIMM

Notes: 1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted.

2. The dimensional diagram is for reference only.

18.0 (0.709)

17.8 (0.701)

Pin 1

2.5 (0.098) D

(2X)

2.3 (0.091) TYP

5.0 (0.197) TYP

123.0 (4.84)

TYP

1.0 (0.039)

TYP 0.8 (0.031)

TYP

0.75 (0.03) R

(6X)

0.76 (0.03) R

Pin 120

Front view

133.50 (5.256)

133.20 (5.244)

47.0 (1.85)

TYP

71.0 (2.79)

TYP

9.5 (0.374)

TYP

Back view

Pin 240 Pin 121

1.37 (0.054)

1.17 (0.046)

4.0 (0.157)

MAX

2.2 (0.087) TYP

1.45 (0.057) TYP

3.05 (0.12) TYP

54.68 (2.15)

TYP

3.0 (0.118) 4X TYP

U1 U2 U3 U4 U5 U6 U7 U8 U9 U10

U11 U12 U13 U14 U15 U16 U17 U18 U19 U20

1.37 (0.054)

1.17 (0.046)

9.1 (0.358)

MAX

Module with heat spreader

U10

U11

U15

U20