Standard Products UT54ACS245S Schmitt Octal Bus Transceiver with Three-State Outputs Datasheet November 2010 www.aeroflex.com/logic PINOUTS FEATURES Three-state outputs drive bus line directly 1.2 CMOS - Latchup immune High speed Low power consumption Single 5 volt supply Available QML Q or V processes Flexible package - 20-pin DIP - 20-lead flatpack UT54ACS245S - SMD 5962-96572 20-Pin DIP Top View DESCRIPTION The UT54ACS245S is a non-inverting octal bus transceiver with Schmitt Trigger input levels. The circuit is designed for asynchronous two-way communication between data buses. The control function implementation minimizes external timing requirements. The device is characterized over full military temperature range of -55C to +125C. FUNCTION TABLE DIRECTION CONTROL DIR OPERATION L L B Data To A Bus L H A Data To B Bus H X 1 2 20 19 VDD G A2 3 18 B1 A3 4 17 B2 A4 5 16 B3 A5 A6 6 7 15 14 B4 B5 A7 A8 8 9 13 12 B6 B7 VSS 10 11 B8 20-Lead Flatpack Top View The device allows data transmission from the A bus to the B bus or from the B bus to the A bus depending upon the logic level at the direction control (DIR) input. The enable input (G) disables the device so that the buses are effectively isolated. ENABLE G DIR A1 DIR 1 20 VDD A1 2 19 G A2 3 18 B1 A3 A4 4 5 17 16 B2 B3 A5 6 15 B4 A6 7 14 B5 A7 A8 VSS 8 9 10 13 12 11 B6 B7 B8 LOGIC SYMBOL G Isolation DIR A1 A2 A3 A4 A5 A6 A7 A8 1 (19) (1) (2) (3) G3 3 EN1 (BA) 3 EN2 (AB) (18) 1 B1 2 (17) (4) (16) (5) (6) (15) (7) (8) (9) (14) B2 B3 B4 B5 (13) B6 (12) B7 (11) B8 Note: 1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. LOGIC DIAGRAM DIR (1) A1 (19) (2) (18) A2 B6 (8) (12) A8 B5 (7) (13) A7 B4 (6) (14) A6 B3 (5) (15) A5 B2 (4) (16) A4 B1 (3) (17) A3 G B7 (9) (11) 2 B8 OPERATIONAL ENVIRONMENT1 PARAMETER LIMIT UNITS Total Dose 1.0E6 rads(Si) SEU Threshold 2 80 MeV-cm2/mg SEL Threshold 3 120 MeV-cm2/mg Neutron Fluence 1.0E14 n/cm2 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. Device storage elements are immune to SEU affects. ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage -0.3 to 7.0 V VI/O Voltage any pin -.3 to VDD +.3 V TSTG Storage Temperature range -65 to +150 C TJ Maximum junction temperature +175 C TLS Lead temperature (soldering 5 seconds) +300 C JC Thermal resistance junction to case 20 C/W II DC input current 10 mA PD Maximum power dissipation 1 W Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage 4.5 to 5.5 V VIN Input voltage any pin 0 to VDD V TC Temperature range -55 to + 125 C 3 DC ELECTRICAL CHARACTERISTICS 7 (VDD = 5.0V 10%; VSS = 0V 6, -55C < TC < +125C); Unless otherwise noted, Tc is per the temperature range ordered. SYMBOL PARAMETER VT+ Schmitt Trigger, positive going threshold1 ACS VT- Schmitt Trigger, negative going threshold1 ACS VH Schmitt Trigger, typical range of hysteresis CONDITION VOL VOH IOL MAX UNIT .7VDD V .3VDD V 2 ACS IIN MIN Input leakage current ACS VIN = VDD or VSS Low-level output voltage 3 ACS IOL = 100A High-level output voltage 3 ACS IOH = -100A Output current (Sink)10 VIN=VDD or VSS 0.6 1.5 V -1 1 A 0.25 V VDD - 0.25 V 12 mA -12 mA VOL=0.4V IOH Output current (Source)10 VIN=VDD or VSS VOH=VDD - 0.4 IOZ Three-state output leakage current VO = VDD and VSS -30 30 A IOS Short-circuit output current 2, 4 ACS VO = VDD and VSS -300 300 mA Ptotal Power dissipation 2, 8, 9 CL = 50pF 2.0 mW/ MHz IDDQ Quiescent Supply Current VDD = 5.5V 10 A CIN Input capacitance 5 = 1MHz @ 0V 15 pF Output capacitance 5 = 1MHz @ 0V 15 pF COUT 4 Notes: 1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 2. Supplied as a design limit, but not guaranteed or tested. 3. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pF/MHz. 4.Not more than one output may be shorted at a time for maximum duration of one second. 5.Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at frequency of 1MHz and a signal amplitude of 50mV rms maximum. 6. Maximum allowable relative shift equals 50mV. 7. All specifications valid for radiation dose 1E6 rads(Si). 8. Power does not include power contribution of any TTL output sink current. 9. Power dissipation specified per switching output. 10.Guaranteed based on characterization data, but not tested. 5 AC ELECTRICAL CHARACTERISTICS 2 (VDD = 5.0V 10%; VSS = 0V 6, -55C < TC < +125C); Unless otherwise noted, Tc is per the temperature range ordered. SYMBOL PARAMETER MINIMUM MAXIMUM UNIT tPLH Data to bus 2 15 ns tPHL Data to bus 2 15 ns tPZL G low to bus active 2 12 ns tPZH G low to bus active 2 12 ns tPLZ G high to bus three-state 2 15 ns tPHZ G high to bus three-state 2 15 ns Notes: 1. Maximum allowable relative shift equals 50mV. 2. All specifications valid for radiation dose 1E6 rads(Si) 6 PACKAGING Side-Brazed Packages 7 FLATPACK PACKAGES 8 UT54ACS245S: SMD 5962 * ***** ** * * * Lead Finish: (Notes 1 & 2) A = Solder C = Gold X = Optional Package Type: X = 20-lead ceramic bottom-brazed dual-in-line Flatpack C = 20-lead ceramic side-brazed dip Class Designator: Q = QML Class Q V = QML Class V Device Type: 01 Drawing Number: 96572 = UT54ACS245S Total Dose: (Notes 3 & 4) R = 1E5 rads(Si) F = 3E5 rads(Si) G = 5E5 rads(Si) H = 1E6 rads(Si) Notes: 1. Lead finish (A,C, or X) must be specified. 2. If an "X" is specified when ordering, part marking will match the lead finish and will be either "A" (solder) or "C" (gold). 3. Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening. For prototype inquiries, contact factory. 4. Device type 02 is only offered with a TID tolerance guarantee of 3E5 rads(Si) or 1E6 rads(Si) and is tested in accordance with MIL-STD-883 Test Method 1019 Condition A and section 3.11.2. Device type 03 is only offered with a TID tolerance guarantee of 1E5 rads(Si), 3E5 rads(Si), and 5E5 rads(Si), and is tested in accordance with MIL-STD-883 Test Method 1019 Condition A. 9 Aeroflex Colorado Springs - Datasheet Definition Advanced Datasheet - Product In Development Preliminary Datasheet - Shipping Prototype Datasheet - Shipping QML & Reduced Hi-Rel COLORADO Toll Free: 800-645-8862 Fax: 719-594-8468 INTERNATIONAL Tel: 805-778-9229 Fax: 805-778-1980 NORTHEAST Tel: 603-888-3975 Fax: 603-888-4585 SE AND MID-ATLANTIC Tel: 321-951-4164 Fax: 321-951-4254 WEST COAST Tel: 949-362-2260 Fax: 949-362-2266 CENTRAL Tel: 719-594-8017 Fax: 719-594-8468 www.aeroflex.com info-ams@aeroflex.com Aeroflex UTMC Microelectronic Systems Inc. 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