SRAM
MT5C1005
Austin Semiconductor, Inc.
MT5C1005
Rev. 3.1 1/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
FEATURES
• High Speed: 20, 25, 35, and 45
• Battery Backup: 2V data retention
• Low power standby
• High-performance, low-power CMOS double-metal
process
• Single +5V (+10%) Power Supply
• Easy memory expansion with CE\ and OE\ options.
• All inputs and outputs are TTL compatible
OPTIONS MARKING
• Timing
20ns access -20
25ns access -25
35ns access -35
45ns access -45
55ns access -55*
70ns access -70*
• Package(s)
Ceramic DIP (400 mil) C No. 109
Ceramic Quad LCC (contact factory)E C W No. 206
Ceramic LCC EC No. 207
Ceramic Flatpack F No. 303
Ceramic SOJ D C J No. 501
• Operating T emperature Ranges
Industrial (-40oC to +85oC) IT
Military (-55oC to +125oC) XT
• 2V data retention/low power L
*Electrical characteristics identical to those provided for the
45ns access devices.
PIN ASSIGNMENT
(Top View)
AVAILABLE AS MILITARY
SPECIFICATIONS
•MIL-STD-883
28-Pin DIP (C)
(400 MIL)
32-Pin LCC (EC)
32-Pin SOJ (DCJ)
32-Pin Flat P ack (F) 32-Pin LCC (ECW)
GENERAL DESCRIPTION
The Austin Semiconductor SRAM family employs
high-speed, low power CMOS designs fabricated using double-
layer metal, double-layer polysilicon technology .
For flexibility in high-speed memory applications, ASI
offers chip enable (CE\) and output enable (OE\) capability.
These enhancements can place the outputs in High-Z for addi-
tional flexibility in system design. Writing to these devices is
accomplished when write enable (WE\) and CE\ inputs are both
LOW. Reading is accomplished when WE\ remains HIGH while
CE\ and OE\ go LOW. The devices offer a reduced power
standby mode when disabled. This allows system designs to
achieve low standby power requirements.
All devices operation from a single +5V power supply
and all inputs and outputs are fully TTL compatible.
256K x 4 SRAM
SRAM MEMORY ARRAY
For more products and information
please visit our web site at
www.austinsemiconductor.com
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
CE\
OE\
Vss
Vcc
A6
A5
A4
A3
A2
A1
A0
NC
DQ4
DQ3
DQ2
DQ1
WE\
4 3 2 1 31 32 30
14 15 16 17 18 19 20
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
A10
A11
A12
A13
A14
A15
A16
A17
CE\
A2
A4
A3
A1
A0
NC
NC
NC
DQ4
DQ3
DQ2
DQ1
WE\
Vss
OE\
NC
A9
A8
A7
NC
Vcc
A6
A5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A7
A8
A9
A12
A10
A11
A13
NC
A14
A15
A16
A17
NC
CE\
OE\
Vss
Vcc
A6
A5
A2
A4
A3
A1
NC
NC
A0
NC
DQ4
DQ3
DQ2
DQ1
WE\
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A7
A8
A9
A12
A10
A11
A13
NC
A14
A15
A16
A17
NC
CE\
OE\
Vss
Vcc
A6
A5
A2
A4
A3
A1
NC
NC
A0
NC
DQ4
DQ3
DQ2
DQ1
WE\
SRAM
MT5C1005
Austin Semiconductor, Inc.
MT5C1005
Rev. 3.1 1/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
2
FUNCTIONAL BLOCK DIAGRAM
TRUTH TABLE
MODE OE\ CE\ WE\ DQ POWER
STANDBY X H X HIGH-Z STANDBY
READ L L H Q ACTIVE
READ H L H HIGH-Z ACTIVE
WRITE X L L D ACTIVE
ROW DECODER
262,144 x 4-BIT
MEMORY ARRAY
I/O CONTROL
V
CC
GND
D
Q
4
D
Q
1
CE\
OE\
WE\
A
A
A
A
A
A
A
A
A
A
COLUMN DECODER
A A A A A A A A POWER
DOWN
SRAM
MT5C1005
Austin Semiconductor, Inc.
MT5C1005
Rev. 3.1 1/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
3
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage Range (Vcc)................................-.5V to +7.0V
Storage Temperature......................................-65°C to +150°C
Voltage on any Pin Relative to Vss................-.5V to Vcc+.5V
Max Junction T emperature............................................+175°C
Lead Temperature (soldering 10 seconds)..................+260oC
Power Dissipation ...............................................................1 W
*Stresses greater than those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the
operation section of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods
may affect reliability .
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(-55oC < TC < 125oC; VCC = 5V +10%)
CAPACITANCE
SYM -20 -25 -35 -45 UNITS NOTES
I
cc
180 180 180 180 mA 3
Power Supply
Current: Standby I
SBT2
25 25 25 25 mA
I
SBC
16 16 16 16 mA
MAX
CONDITIONS
WE\, CE\ < V
IL
; V
CC
= MAX
Output Open
Power Supply
Current: Operating
PARAMETER
CE\ > V
CC
-0.2V; V
CC
= MAX
V
IL
< V
SS
+0.2V
V
IH
> V
CC
-0.2V; f = 0 Hz*
CE\ > V
IH
; All Other Inputs
< V
IL
or > V
IH
, V
CC
= MAX
PARAMETER CONDITIONS SYM MAX UNITS NOTES
Input Capacitance C
I
12 pF 4
Output Capacitance (DQ1-DQ4) C
O
14 pF 4
V
IN
= 0V,
T
A
= 25°C, f = 1MHz
V
CC
= 5V
DESCRIPTION CONDITIONS SYM MIN MAX UNITS NOTES
Input High (Logic 1) Voltage V
IH
2.2 V
CC
+0.5 V1
Input Low (Logic 0) Voltage V
IL
-0.5 0.8 V 1
Input Leakage Current 0V<V
IN
<V
CC
IL
I
-10 10 µA
Output Leakage Current Output(s) disabled
0V<V
OUT
<V
CC
IL
O
-10 10 µA
Output High Voltage I
OH
= -4.0mA V
OH
2.4 V 1
Output Low Voltage I
OL
= 8.0mA V
OL
0.4 V 1
* “L” version only.
SRAM
MT5C1005
Austin Semiconductor, Inc.
MT5C1005
Rev. 3.1 1/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
4
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Note 5) (-55oC < TC < 125oC; VCC = 5V +10%)
MIN MAX MIN MAX MIN MAX MIN MAX UNITS NOTES
READ CYCLE
READ cycle time tRC 20 25 35 45 ns
Address access time tAA 20 25 35 45 ns
Chip Enable access time tACE 20 25 35 45 ns
Output hold from address change tOH 3333 ns
Chip Enable to output in Low-Z tLZCE 3333 ns4, 6, 7
Chip disable to output in High-Z tHZCE 10 12 20 25 ns 4, 6, 7
Chip Enable to power-up time tPU 0000 ns4
Chip disable to power-down time tPD 20 25 35 45 ns 4
Output Enable access time tAOE 8 102025ns
Output Enable to output in Low-Z tLZOE 0000 ns4, 6, 7
Output disable to output in High-Z tHZOE 8 10 20 25 ns 4, 6, 7
WRITE CYCLE
WRITE cycle time tWC 20 25 35 45 ns
Chip Enable to end of write tCW 15 20 30 35 ns
Address valid to end of write tAW 15 20 30 35 ns
Address setup time tAS 0000 ns
Address hold from end of write tAH 0000 ns
WRITE pulse width tWP 15 20 30 35 ns
Data setup time tDS 12 15 20 25 ns
Data hold time tDH 0000 ns
Write disable to output in Low-Z tLZWE 3333 ns4, 6, 7
Write Enable to output in High-Z tHZWE 0 8 0 10 0 15 0 20 ns 4, 6, 7
-35 -45
DESCRIPTION -20
SYMBOL -25
SRAM
MT5C1005
Austin Semiconductor, Inc.
MT5C1005
Rev. 3.1 1/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
AC TEST CONDITIONS
Input pulse levels ................................... Vss to 3.0V
Input rise and fall times ....................................... 5ns
Input timing reference levels ............................. 1.5V
Output reference levels ..................................... 1.5V
Output load .............................. See Figures 1 and 2
NOTES
1 . All voltages referenced to VSS (GND).
2 . -3V for pulse width < 20ns
3. ICC is dependent on output loading and cycle rates.
The specified value applies with the outputs
unloaded, and f = 1 Hz.
tRC (MIN)
4. This parameter is guaranteed but not tested.
5. Test conditions as specified with the output loading
as shown in Fig. 1 unless otherwise noted.
6 . Minimum of 5pF for tEHQZ, tOHQZ, tELQX, tOLQX,
and tWHQX.
7. At any given temperature and voltage condition,
tHZCE is less than tLZCE, and tHZWE is less than
tLZWE and tHZOE is less than tLZOE.
8 . WE\ is HIGH for READ cycle.
9. Device is continuously selected. Chip enables and
output enables are held in their active state.
10. Address valid prior to, or coincident with, latest
occurring chip enable.
11. tRC = Read Cycle Time.
1 2 . Chip enable (CE\) and write enable (WE\) can initiate and
terminate a WRITE cycle.
Fig. 1 Output Load
Equivalent Fig. 2 Output Load
Equivalent
DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)
123
1
2
3
1
2
3
123
1
23
4
1
23
4
1
23
4
1234
DON’T CARE
UNDEFINED
LOW Vcc DATA RETENTION WAVEFORM
12345678
12345678
12345678
12345678
123
1
2
3
1
2
3
123
1234
1
23
4
1
23
4
1234
123456789
123456789
123456789
123456789
123
1
2
3
1
2
3
123
1234
1
23
4
1
23
4
1234
DA TA RETENTION MODE
VDR > 2V
4.5V 4.5V
VDR
tCDR tR
VIH
VIL
VCC
CE\
DESCRIPTION SYM MIN MAX UNITS NOTES
V
CC
for Retention Data V
DR
2V
Data Retention Current
CE\ > (V
CC
-0.2V)
and
V
IN
> (V
CC
-0.2V)
or < 0.2V
V
CC
= 2V I
CCDR
5mA
Chip Deselect to Data
Retention Time t
CDR
0--ns4
Operation Recovery Time t
R
t
RC
ns 4, 11
CONDITIONS
VTH = 1.73V
Q
167Ω
30pF VTH = 1.73V
Q
167Ω
5pF
SRAM
MT5C1005
Austin Semiconductor, Inc.
MT5C1005
Rev. 3.1 1/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
6
tAA
tOH
tRCtRC
PREVIOUS DATA VALID
VALID
DATA VALID
ADDRESS
DQ
READ CYCLE NO. 1 8, 9
tRC
tAA
tOH
tPD
tPU
tHZCEtACE
tLZCE
tHZOE
tLZOE
tAOE
tRCtRC
DATA VALID
CE\
OE\
DQ
Icc
READ CYCLE NO. 2 7, 8, 10
tRC
tAOE
tLZOE
tHZOE
tHZCE
tLZCE tACE
tPU tPD
1234
1
23
4
1234
1234
1
23
4
1
23
4
1234
DON’T CARE
UNDEFINED
SRAM
MT5C1005
Austin Semiconductor, Inc.
MT5C1005
Rev. 3.1 1/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
7
NOTE: Output enable (OE\) is inactive (HIGH).
WRITE CYCLE NO. 2 7, 12
(Write Enabled Controlled)
1234
1
23
4
1
23
4
1234
12345
1
234
5
1
234
5
12345
DON’T CARE
UNDEFINED
WRITE CYCLE NO. 1 12
(Chip Enabled Controlled)
tDHtDS
tWP1tWP1
tAH
tCW
tAW
tCWtAS
tWCtWC
HIGH Z
DATA VAILD
ADDRESS
CE\
WE\
D
Q
tWC
tAW
tAS tCW
tAH
tWP
tDS tDH
1234567890123456789012
1234567890123456789012
1
1
1
1
1
123456789012345678901234567890121234567890
123456789012345678901234567890121234567890
1
1
1
1
1
tDH
tWP1tWP1
tAS
tAW
tCW tAH
tCW
tWCtWC
DATA VALID
ADDRESS
CE\
WE\
D
Q
HIGH-Z
tDH
tDS
tWC
tAW tAH
tCW
tWP
12345678901234567
1
234567890123456
7
12345678901234567
12
12
12
1
1
1
1
12345678901234567890123
1
234567890123456789012
3
12345678901234567890123
12
1
1
1
1
tAS
SRAM
MT5C1005
Austin Semiconductor, Inc.
MT5C1005
Rev. 3.1 1/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
8
MECHANICAL DEFINITIONS*
ASI Case #109 (Package Designator C)
*All measurements are in inches.
D
Pin 1
eb
b1
A
Q
L
c
E
E1
MIN MAX
A 0.090 0.110
b 0.016 0.020
b1 0.040 0.060
c 0.008 0.012
D 1.386 1.414
E 0.385 0.405
E1 0.390 0.410
e 0.090 0.110
L 0.125 0.175
Q 0.040 0.060
SYMBOL ASI PACKAGE SPECIFICATIONS
SRAM
MT5C1005
Austin Semiconductor, Inc.
MT5C1005
Rev. 3.1 1/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
9
ASI Case #206 (Package Designator ECW)
MECHANICAL DEFINITIONS*
*All measurements are in inches.
b1
D1
L1
b
E1
L
e
D
E
A
b2
MIN MAX
A 0.077 0.093
b 0.022 0.028
b1 0.004 0.014
b2 0.054 0.066
D 0.742 0.758
D1 0.395 0.405
E 0.442 0.458
E1 0.295 0.305
e 0.045 0.055
L 0.045 0.055
L1 0.077 0.093
SYMBOL ASI PACKAGE SPECIFICATIONS
SRAM
MT5C1005
Austin Semiconductor, Inc.
MT5C1005
Rev. 3.1 1/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
10
MECHANICAL DEFINITIONS*
ASI Case #207 (Package Designator EC)
*All measurements are in inches.
A
b2
D
E
L1
L
ebb1
MIN MAX
A 0.080 0.100
b 0.022 0.028
b1 0.004 0.014
b2 0.054 0.066
D 0.815 0.835
E 0.392 0.408
e 0.045 0.055
L 0.070 0.080
L1 0.090 0.110
SYMBOL ASI PACKAGE SPECIFICATIONS
SRAM
MT5C1005
Austin Semiconductor, Inc.
MT5C1005
Rev. 3.1 1/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
11
MECHANICAL DEFINITIONS*
ASI Case #303 (Package Designator F)
*All measurements are in inches.
Pin 1
Index
32
17 16
1
Bottom View
T op View
D
E
L
e
b
D1
c
E2
A
Q
MIN MAX
A --- 0.125
b 0.015 0.019
c 0.004 0.006
D 0.812 0.828
D1 0.745 0.755
E 0.405 0.415
E2 0.324 0.336
e 0.045 0.055
L 0.290 0.310
Q 0.027 0.033
SYMBOL ASI PACKAGE SPECIFICATIONS
SRAM
MT5C1005
Austin Semiconductor, Inc.
MT5C1005
Rev. 3.1 1/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
12
*All measurements are in inches.
ASI Case #501 (Package Designator DCJ)
MECHANICAL DEFINITIONS*
A
A2
e
b
D
E
D1
E1
E2
R
MIN MAX
A 0.135 0.153
A2 0.026 0.036
b 0.015 0.019
D 0.812 0.828
D1 0.740 0.755
E 0.405 0.415
e 0.045 0.055
E1 0.435 0.445
E2 0.360 0.380
R 0.030 0.040
SYMBOL ASI PACKAGE SPECIFICATIONS
SRAM
MT5C1005
Austin Semiconductor, Inc.
MT5C1005
Rev. 3.1 1/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
13
*AVAILABLE PROCESSES
IT = Industrial Temperature Range -40oC to +85oC
XT = Extended T emperature Range -55oC to +125oC
883C = Full Military Processing -55oC to +125oC
** OPTIONS
L = 2V Data Retention/Low Power
ORDERING INFORMA TION
EXAMPLE:
MT5C1005EC-45/XT
Device
Number Package
Type Speed
ns Options** Process Device
Number Package
Type Speed
ns Options** Process
MT5C1005 C -20 L /* MT5C1005 EC
ECW -20 L /*
MT5C1005 C -25 L /* MT5C1005 EC
ECW -25 L /*
MT5C1005 C -35 L /* MT5C1005 EC
ECW -35 L /*
MT5C1005 C -40 L /* MT5C1005 EC
ECW -40 L /*
MT5C1005 C -55 L /* MT5C1005 EC
ECW -55 L /*
MT5C1005 C -70 L /* MT5C1005 EC
ECW -70 L /*
EXAMPLE:
MT5C1005DCJ-70/XT
Device
Number Package
T
yp
eSpeed
ns Options** Process Device
Number Package
T
yp
eSpeed
ns Options** Process
MT5C1005 F -20 L /* MT5C1005 DCJ -20 L /*
MT5C1005 F -25 L /* MT5C1005 DCJ -25 L /*
MT5C1005 F -35 L /* MT5C1005 DCJ -35 L /*
MT5C1005 F -40 L /* MT5C1005 DCJ -40 L /*
MT5C1005 F -55 L /* MT5C1005 DCJ -55 L /*
MT5C1005 F -70 L /* MT5C1005 DCJ -70 L /*
EXAMPLE: MT5C1005C-20L/IT
EXAMPLE: MT5C1005F-25L/883C
