73M1903
Modem Analog Front End
Simplifying System Integration
TM
D ATA SHEET
March 2010
Rev. 2.1 © 2010 Teridian Semiconduct or C or por ati on 1
DESCRIPTION
The Terid ian 73M1903 Analog Front End (AFE) IC
includes fully differential hybrid driver outputs, which
connect to the t elephone line in terface t hr ough a
transformer-b ased DAA. The r eceive pins ar e also
fully differential for maximum flexibility an d
performance. This arrangement allows for the
design of a high performance hybrid circuit to
impr ove sign al t o noi se performance under low
receive level conditions, and compatibility with any
standard transformer i ntended for PSTN
communications applications.
The devic e in corporates a programmable sample
rate ci r cuit to suppor t s oft modem and DS P based
impl ementat i ons of all speeds up to V.92 (56 kbps).
The sampli ng r ates supported are from 7.2 kHz t o
14.4 kHz by programming pre-scaler N CO and PLL
NCO.
The 73M1903 devic e i ncorporates a digital hos t
interface that is com patible wi th the ser ial ports
fou nd on most commerc i ally a vail abl e DS Ps and
proc essor s and exchanges both payload and control
information with t he host .
Cost-saving features of the device i nclude an input
referenc e frequency circuit, whi ch accept s a range
of crystal s f r om 9-27 MHz. It also accepts external
referenc e clock values betwe en 9-40 MHz
generated by the host processor. In most
applications , this eliminates the need for a dedicated
cr ystal oscill ator and r educes the bill of material
(BOM).
The 73M1903 al so s upports t wo an alog loop bac k
and on e digital l oop back tes t modes.
Receive
Mux/
Filters
Transmit
Drivers/
Filters
TXAP
TXAN
(HYBRID)
DAA
Controls
RXAP
RXAN
HOOK
Analog
Sigma
Delta
Control
Registers
Ref.
Clocks Control
Logic
DAC
VBG
Serial
Port
SCLK
SDIN
SDOUT
FSB
Crystal
GPIO
FEATURES
• Up to 56 kbps (V.92) performance
• P r ogr ammable sampl e r ates (7.2 - 14.4 kHz)
• Reference cl ock range of 9 -40 MHz
• Crystal frequency ran ge of 9-27 MHz
• Hos t synchronous serial interface oper ation
• Pin compatible with 73M2901CL/CE
modems
• Low power modes
• O n boar d l i ne int er fac e dr iver s
• Ful l y differential r eceiver and trans mitt er
• Drivers for transformer i nterfac e
• 3.0 V – 3.6 V op er ati on
• 5 V tolerant I/O
• I ndust r ial temperature range ( -40 to + 85 °C)
• JATE compliant transmit sp ectrum
• P ack age options:
• 32-pin QFN
• 20-pin TSSOP
• RoHS compliant (6 /6) lead-free pack ages
APPLICATIONS
• S et Top Boxes
• P er sonal Vi deo R ecorders (PVR)
• M ult ifuncti o n P e r i phe r a l s (M F P)
• Fax Mac hi nes
• Internet Appliances
• G ame Cons oles
• P oint of Sale Termi nal s
• A utomati c Teller Machines
• S peaker Phones
• RF M odems
73M19 03 Data She e t DS_1903_032
2 R ev. 2.1
Table of Contents
1 Signal Desc ription ......................................................................................................................... 4
1.1 Seri al I nterface ........................................................................................................................ 5
2 Control and S tatus Re gisters ........................................................................................................ 8
2.1 GPIO .................................................................................................................................... 10
2.1.1 GPIO Data (GPIO): Address 02h .............................................................................. 10
2.1.2 GPIO D irec tion ( DI R ) : Address 03h .......................................................................... 10
2.2 Analog I/O ............................................................................................................................. 10
2.2.1 Control Register (CTRL 11): Address 0Bh ................................................................. 11
2.2.2 Con trol Regist er (CTRL 12): Address 0Ch ................................................................. 11
2.2.3 Control Register (CTRL 13): Address 0Dh ................................................................. 12
2.2.4 Control Register (CTRL 14): Address 0Eh ................................................................. 12
3 Clock Generation ......................................................................................................................... 13
3.1 Crystal Os c illator and Pre-scaler NCO................................................................................... 13
3.1.1 C ontrol Register (C TRL 8): Address 08h .................................................................... 13
3.1.2 C ontrol Register (CTRL 9) : Address 09h .................................................................... 13
3.1.3 Control Register (CTRL 10): Address 0Ah ................................................................. 13
4 Modem Receiver .......................................................................................................................... 18
5 Modem Tr ans mitter ..................................................................................................................... 21
5.1 T ransmit Levels..................................................................................................................... 22
5.2 T ransmit Power - dBm........................................................................................................... 23
5.3 Con trol Reg ister ( CTRL 1) : Address 00h ............................................................................... 23
5.4 Control Regi st er ( CTRL 2) : Address 01h ............................................................................... 24
5.5 Revision R egi ster: A ddr ess 06h ............................................................................................ 24
6 Test Mod es................................................................................................................................... 25
7 P ower S aving Mod es ................................................................................................................... 25
8 Electrical Specifications .............................................................................................................. 26
8.1 Abs olu te Maximum Ratings ................................................................................................... 26
8.2 Recommend ed Operati ng C ondi ti ons .................................................................................... 26
8.3 Digital S pecifications ............................................................................................................. 27
8.3.1 DC Characteristics ..................................................................................................... 27
8.3.2 AC Timing ................................................................................................................. 28
8.4 Analog Specificat i ons ............................................................................................................ 29
8.4.1 DC Sp ecifications ...................................................................................................... 29
8.4.2 AC Specifications ...................................................................................................... 29
8.5 Performance ......................................................................................................................... 30
8.5.1 Receiver .................................................................................................................... 30
8.5.2 Transmitter ................................................................................................................ 31
9 Pinouts ......................................................................................................................................... 33
9.1 32-Pin QFN Pinout ................................................................................................................ 33
9.2 20-Pi n T SSO P Pi no ut ........................................................................................................... 34
10 Mechanical Specifications .......................................................................................................... 35
10.1 32-Pin QFN Mechanical Drawing s ......................................................................................... 37
10.2 20-Pin TSSOP Mechanical Drawings .................................................................................... 38
11 Orderi ng Information ................................................................................................................... 39
Appendix A – 73M1903 DAA R esistor Cal culat io n Guid e .................................................................. 40
Appendix B – Crystal Oscillator .......................................................................................................... 42
Revisi on H istor y .................................................................................................................................. 47
DS_1903_032 73M 1903 Da ta She e t
Rev. 2.1 3
Figures
Figure 1: Effect of the TYPE (FS m ode) pin on FS with SckM ode = 0 ....................................................... 7
Figure 2: Control Frame P osition versus SPOS ........................................................................................ 7
Figure 3: S erial Port Timing Diagram ....................................................................................................... 9
Fi gur e 4: Analog Block D iagram ............................................................................................................. 11
Fi gur e 5: Cl ock Generation .................................................................................................................... 17
Fi gur e 6: Overall Receiver Frequency Response ................................................................................... 19
Figure 7: Rx Passband Response .......................................................................................................... 19
Figure 8: RXD Spectrum of 1 kHz Tone ................................................................................................. 20
Fi gur e 9: RXD Spect ru m of 0.5 kHz, 1 kHz, 2 kHz, 3 kHz and 3. 5 kHz Tones of Equal A m plitudes ......... 20
Fi gur e 10: Fr equency Response of TX Pat h for DC to 4 kH z in Band Signal ........................................... 21
Fi gur e 11: Seri al P or t D ata T i ming ......................................................................................................... 28
Fi gur e 12: 32-Pi n QFN Pi no ut ................................................................................................................ 33
Fi gur e 13: 20-Pin TSSOP Pin out .......................................................................................................... 34
Figure 14: 73M1903 Schematic ............................................................................................................. 35
Fi gur e 14: 32-Pin Q F N Mechanical Specifications .................................................................................. 37
Fi gur e 15: 20-Pin TSSOP Mechanical Specifications ............................................................................. 38
Fi gur e 16: NCO Block D iagram .............................................................................................................. 42
Figure 17: PLL Block Diagram ............................................................................................................... 43
Tables
Tabl e 1: Input s Selec ted i n R egul ar and Al ternate Mul ti pl exer Cyc les ....................................................... 4
Tabl e 2: Memory M ap .............................................................................................................................. 8
Tabl e 3: PLL Loop Fi lt er Sett ings ........................................................................................................... 11
Table 4: Kvco versus Settings at Vc=1.6 V, 25 °C .................................................................................. 13
Tabl e 5: PLL Power Do wn ..................................................................................................................... 14
Tabl e 6: Examp les of NCO Settings ....................................................................................................... 14
Tabl e 7: Clock G ener ation Regis ter Settings for Fxtal = 27 M Hz ............................................................ 15
Tabl e 8: Clock G ener ation Regis ter Settings for Fxtal = 24.576 MHz ...................................................... 16
Tabl e 9: Clock G ener ation Regis ter Settings for Fxtal = 9.216 MHz ........................................................ 16
Tabl e 10: Cl ock Generation Reg ister Settings for Fxtal = 24.000 MH z .................................................... 17
Tabl e 11: Cl ock Generation Reg ister Settings for Fxtal = 25.35 MH z ...................................................... 17
Table 12: Receiv e Gai n ......................................................................................................................... 18
Table 13: Peak to RM S R ati os for Various Modulation Types ................................................................. 23
Table 14: Serial I/F Timing ..................................................................................................................... 28
Tabl e 15: Reference Voltage S pecifications ........................................................................................... 29
Table 16: Maximum Transmit Levels ...................................................................................................... 29
Tabl e 17: Receiver Performance Speci fi cat ions ..................................................................................... 30
Tabl e 18: Tran smi tter Performance Speci fi cat ions ................................................................................. 31
Tabl e 19: 32-Pin QFN Pin Def initions ..................................................................................................... 33
Tabl e 20: 20-Pin TSSOP Pin Defin itions ................................................................................................ 34
Tabl e 21: Bil l of Materials ....................................................................................................................... 36
Tabl e 22: Orderi ng Information .............................................................................................................. 39
73M19 03 Data She e t DS_1903_032
4 Rev. 2.1
1 Signal Description
The Teridian 73M1903 modem AFE IC is avai l abl e in a 20-pin TSSOP or 32-pin QFN package with t he
same pin out. The following table desc r i bes th e funct i on of each p in. There are tw o pai r s of p ower
supply pins, VPA (analog) and VPD (digital). They should be decoupled separately from the suppl y
sour ce in order to isolate digit al noi se from the analog circuits i nternal t o the ch i p. Fail ur e to adequately
is olat e and decouple these suppli es will compromise devic e perfo r mance.
Table 1: Inputs Selected in Regular and Al te r nate Multiplexer Cycles
Pi n Na me Type 32QFN
Pin # 20VT
Pin# Description
VND GND 1,22 2,18 Neg ativ e Digital Grou nd
VNA GND 16 13 N egati ve Analog Ground
VPD PWR 2,25 3 Positive Digital Supply
VPA PWR 10 8 Positive A nalog S uppl y
VPPLL PWR 20 17 Positive PLL Supply, shared with VPD
VNPLL PWR 17 14 Negati ve PLL G r ound
RST
I 9 7 Master reset. When this pin is a l ogic 0 al l regist er s are
res et to t heir defau lt st ates; Weak-pul l e d hi g h- default.
OSCIN I 19 16 Crystal oscillato r inp ut. W hen providing an external clock
sour ce, drive OSCI N.
OSCOUT O 18 15 Crystal oscil lator circuit output p in.
GPIO(0-7) I/O 3, 4, 5, 6,
23,
24,30,31 N/A Soft ware definable di gi tal i nput/outpu t pi ns. Not available in
t he 20VT (TSSOP) pac kage.
VREF O 13 6 Refer ence voltag e pin (Reflects VREF).
RXAP I 15 12 R eceive analog pos it i ve input.
RXAN I 14 11 R eceive analog negative input .
TXAP O 12 10 Transmit analog positive out put.
TXAN O 11 9 Transmit analog negative out put.
SCLK O 8 5 Serial interface cl ock . Wi th SCLK cont in uous s el ected,
Frequency = 256*Fs ( =2.4576 MHz for Fs=9.6 kHz)
SDOUT O 32 1 Ser i al dat a output (or i nput to th e host ) .
SDIN I 29 20 Serial data input (or output from the host).
FS O 7 4 Frame synchr onization. (Act i ve Low)
TYPE I 27 19 Type of frame sync. Open, weak-pulled high = early
(mode1); tied l ow = late (mod e0) .
SckMode I 28 NA Controls the SCLK behavior after FS. Open, weak-pulled
high = SCLK Continuous; tied low = 32 clocks per R/W
cycle. Not availabl e in 20VT.
DS_1903_032 73M 1903 Da ta She e t
Rev. 2.1 5
1.1 Serial Interface
The serial d ata port i s a bi-direct ional port that is su ppo r t e d by many DSP s . Alt hough t he 73M19 03 is a
peripheral t o the DSP (host control l er ) , the 73M1903 is the mas ter of the ser i al port. It generates a serial
bit clock, Sclk, from a system clock, Sysclk, wh ich i s normally an out put from an on-chi p PL L that is
programm ed by the user. The serial bit c lock is derived by dividin g the s ys tem clock by 18. The sclk rate,
Fscl k, is r elat ed to the frame s ynchr onization r ate, Fs, by the relationship F sc l k = 256 x Fs or Fs = Fsclk /
256 = Fsys / 18 / 256 = F sys / 4608, wher e Fsys is the frequency of Sysc l k. Fs is also the rate at which
bot h the transmit and receive d ata byt es are s ent (r eceived) to (by) t he H ost . Th r oughout this doc umen t
t wo p airs of s ample rates, Fs, and c r ys tal frequency, F xtal, will be oft en cited to facilitat e discussions.
They are:
1. Fxtal1 = 27 MHz, Fs1 = 7.2 kHz
2. Fxtal2 = 18.432 MHz, Fs2 = 8 kHz.
3. Fxtal3 = 24.576 MHz, Fs3 = 9.6 kHz – chi p default.
Upon reset, until a switch to the PLL based clock, Pllclk, occurs, the system clock will be at the crystal
frequen cy, Fxtal, and therefore the ser ial bit c lock will be Sclk = Fsys/ 18 = Fxtal/18.
Examples:
1. If Fxtal1 = 27.000 MHz, then sclk=1.500 MHz an d Fs= sclk/256 = 5.859375 kHz.
2. If Fxtal2 = 18.432 MHz, then sclk=1.024 MHz and Fs=sclk/ 256 = 4.00 kHz.
3. If Fxtal3 = 24.576 MHz, then sclk=1.3653 MHz and Fs=s clk/ 256 = 5.33 kHz.
When 73M1903 is programmed through the serial port to a desired Fs and th e PLL has settled out, the
system clock will tr ansition to the PLL-based clock in a glitch-less manner.
Examples:
1. If F s1 = 7.2 kHz, F sys = 4608 * Fs = 33.1776 MHz and sclk = Fsys / 18 = 1.8432 MHz.
2. If F s2 = 8.0 kHz, F sys = 4608 * Fs = 36.8640 MHz and sclk = Fsys / 18 = 2 .048 MHz.
3. If Fs 3 = 9.6 kHz, Fsys = 4608 * Fs = 44.2368 MHz and sclk = Fsys / 18 = 2 .4576 MHz.
This transition is entirely controlled by the host. Upon reset or power down of PLL and/or analog front
end, the chip will automatically run off the crystal until the host forces the transition by setting a bit in a
desi gnated s er ial port regi st er – location bit 7, 0Eh. The t ran sition is forced on or after the second Fr ame
Synch period following the write to a designated PLL programming regis ter (0 Dh).
When reprogramming the PLL the host should first transition the system clock to the crystal before
reprogram ming the PLL so that any transients associated with it will not adversel y impact the serial port
communication.
Power saving is accom plished by disabling the analog front end by clearing bit 7 of CTRL1 (address 00h),
ENFE=0.
Duri ng the normal operation, a data FS i s generated by the 73M1903 at the rate of Fs. F or every d ata FS
t her e ar e 16 bi ts tr ansmi tted and 16 bits rec ei ved. The frame synchroni zat ion (FS) signal is pin
programmable for type. FS can ei ther be ear l y or l ate determi ned by t he stat e of the TYPE input pin.
When th e TYP E pi n i s left open, an ear l y FS is generated i n the bit c lock prior to the first data bit
t r ansmitted or received. When hel d low, a late FS oper ates as a c hi p select ; the FS signal is act ive for al l
bits that are trans mitted or receiv ed. Th e TYP E i nput pin i s s am pl ed when the reset pin i s ac tive (low)
and ignored at all other ti mes. Th e fi nal stat e of the TYPE pin as th e r eset pin is de-asserted determines
t he frame synchr oni zation mode used .
73M19 03 Data She e t DS_1903_032
6 Rev. 2.1
The bi ts transmitted on the SDOUT p in are defined as follows:
Bit15
Bit14 Bit13 Bit12
Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
RX15
RX14 RX13
RX12
RX11 RX10 RX9 RX8 RX7 RX6 RX5 RX4 RX3 RX2 RX1 RX0
I f the Hardware Control bi t (bit 0 of regi ster 01h) is s et to zer o, the 16 bits th at are r eceived on t he SD IN
are defined as follows:
Bit15
Bit14 Bit13 Bit12
Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
TX15 TX14 TX13 TX12 TX11 TX10 TX9 TX8 TX7 TX6 TX5 TX4 TX3 TX2 TX1 CTL
In this case TX0=0 is forced.
I f the Hardware Control bi t (bit 0 of regi ster 01h) is s et to one, the 16 bi ts that are received on t he SD IN
input are defined as fol lows:
Bit15
Bit14 Bit13
Bit12
Bit11
Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
TX15
TX14 TX13
TX12
TX11 TX10 TX9 TX8 TX7 TX6 TX5 TX4 TX3 TX2 TX1 TX0
B it 15 i s transmitted/ r eceived firs t. Bits RX15: 0 ar e the receive code wo r d. Bits TX15:0 are th e transmi t
code word. If the hardware control bit is set to one, a cont r ol frame is ini tiated between every p ai r of data
frames . If the har dware c ontrol bi t i s set to z er o, CTL (TX bit 0) is used by software to request a control
frame. I f CTL is high, a control frame is initiated b efore the next data frame. A c ontrol frame all ows the
control ler to read or write status and cont r ol t o the 73M1903.
The cont r ol word received on the SDIN pin is defined as follows:
Bit15
Bit14 Bit13
Bit12
Bit11
Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
R/W A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
The cont r ol word t r ansmi tted on th e SD OUT pin i s defined as fol l ows:
Bit15
Bit14 Bit13
Bit12
Bit11
Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0
I f the R/W bit i s set to a 0, the data byte transmitted on the S DO U T pin i s all zeros and the data rec ei ved
on t he SD IN pi n is written t o the regi st er point ed to by the r eceived add r ess bi ts; A6-A0. If the R/W bit i s
set to a 1, there is no write t o any register and the d ata byt e transmitted on the SDOUT pin is the d ata
contained i n the register poi nted to by ad dr ess bit s A6-A0. Only one control frame c an occur between
any two data frames.
Writes t o unimplemented regi sters ar e i gnor ed. Reading an unimplemented register returns a value of 0.
The position of a control dat a frame is cont r olled by the SPOS; bi t 1 of register 01h. If SPOS is set to a 0
t he cont r ol frames occur mid way between data frames, i. e., t he time between data frames is equal. If
S POS is set to a 1, t he control frame is ¼ of the way b etw een consecut ive data frames, i. e., t he control
frame is closer to the first data frame. This i s il lustrated in Figure 2.
New to the 73M1903 modem AFE IC i s a feat ure that s huts off th e seri al clock ( SCLK ) after 32 cycles of
SCLK following the frame synch (Fi gur e 1). This feature is unavailable in the 20 TSSOP package
option. This mode is controlled by the SckMode pin. If this pin is left open, the clock will ru n
continu ously. If SckMode is low the cloc k will be gated on for 32 clocks for each FS. The SDOUT and FS
pins change values following a rising edge of SCLK. The SDIN pin is sam pled on the falling edge of
SCLK. Figure 4 s hows the timing diagr ams for the s er ial port.
DS_1903_032 73M 1903 Da ta She e t
Rev. 2.1 7
SCLK and FS in mode 1
SCLK
FS(mode1)
32 Cycles of sclk
SCLK and FS in mode 0
FS(mode0)
SCLK
32 Cycles of sclk
Figure 1: E ffect of the TYPE (F S mode) pin on FS with Sck M ode = 0
Figure 2: Control Fram e Position versus SPOS
73M19 03 Data She e t DS_1903_032
8 Rev. 2.1
2 Control and Status Registers
Table 2 shows t he memory map of ad dr essable regist er s in the 73M1903. Eac h register and i ts bits are
described in detail in the following sections.
Table 2: Me m o ry Ma p
Address
Default Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
00 08h ENFE Unused TXBST1 TXBST0 TXDIS RXG1 RXG0 RXGAIN
01 00h TMEN DIGLB ANALB INTLB Reserved
RXPULL SPOS HC
02 FFh GPIO7 GPIO 6 GPIO 5 GPIO 4 GPIO 3 GPIO 2 GPIO 1 GPIO 0
03 FFh DIR7 DIR6 DIR5 DIR4 DIR3 DIR2 DIR1 DIR0
04 00h Reserved
Reserved Reserved Reserved
Reserved
Reserved
Reserved
Reserved
05 00h Reserved
Reserved Reserved Reserved
Reserved
Reserved
Reserved
Reserved
06 10h Rev3 Rev2 Rev1 Rev0 Unused Reserved
Reserved
Reserved
07 00h Unused Reserved Reserved Reserved
Reserved
Reserved
Reserved
Reserved
08 00h Pseq7 Pseq6 Pseq5 Pseq4 Pseq3 Pseq2 Pseq1 Pseq0
09 0Ah Prst2 Prst1 Prst0 Pdvsr4 Pdvsr3 Pdvsr2 Pdvsr1 Pdvsr0
0A 22h Ichp3 Ichp2 Ichp1 Ichp0 FL Kvco2 Kvco1 Kvco0
0B 12h Unused Ndvsr6 Ndvsr5 Ndvsr4 Ndvsr3 Ndvsr2 Ndvsr1 Ndvsr0
0C 00h Nseq7 Nseq6 Nseq5 Nseq4 Nseq3 Nseq2 Nseq1 Nseq0
0D C0h Xtal1 Xtal0 Reserved Reserved
Unused Nrst2 Nrst1 Nrst0
0E 00h Frcvco PwdnPLL Reserved Unused Unused Unused Unused Unused
0F-7F Unused Unused Unused Unused Unused Unused Unused Unused
To prevent unint ended operati on, do not writ e to reserved or unused locations. These loc ations are for
factory test or fut ure use only and are not intended for cust omer program ming.
DS_1903_032 73M1903 Da ta She e t
Rev. 2.1 9
FS(mode1)
TX15 TX12 TX11 TX10 TX9TX13 TX8 TX7 TX6 TX5 TX4 TX3 TX2 TX1 CTLTX14
RX15 RX12 RX11 RX10 RX9RX13 RX8 RX7 RX6 RX5 RX4 RX3 RX2 RX1 RX0RX14
Data Frame With Early Frame Sync
SCLK
SDIN
SDOUT
R/W A4 A3 A2 A1
A5 A0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
A6
zero zero zero zero zerozero zero DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0zero
Control Frame With Early Frame Sync
SCLK
SDIN
SDOUT
FS(mode1)
R/W A4 A3 A2 A1
A5 A0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
A6
zero zero zero zero zerozero zero DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
zero
Control Frame With Late Frame Sync
SCLK
SDIN
SDOUT
FS(mode0)
SCLK
FS
SDIN
SDOUT
TX TX TX TX TX 1
RX RX RX RX RX RX
R A ADI DI DI
000DO DO DO
A
0
TX TX TX TX TX 0
RX RX RX RX RX RX
7.2KHz (8KHz )
Data Frame Control Frame Data Fram e
Relation Between the Data and Control Frames
Figure 3: Serial Port Timing Diagram
73M19 03 Data She e t DS_1903_032
10 Rev. 2.1
2.1 GPIO
The 73M1903 modem AFE device provides 8 user defined I/O pins. E ach pin is progr ammed s epar ately
as ei ther an in put or an output by a b it i n a direc tion r egi ster. If the bit in the direction register is set high,
the corresponding pin is an input whose val ue i s read from the GPIO data regi ster. If it is low, th e pin will
be t r eated as an output whose val ue i s s et by the GPIO data regi ster.
To avoid unwanted c ur r ent con tention and consum ption in the syst em from the G PIO port before t he
GP IO is confi gur ed after a reset , the GP IO port I/Os are ini tializ ed to a hi gh impedanc e st ate. The input
structu r es are protec ted from floating inputs, and no output l evels are dri ven by any of t he GPIO pin s.
The GPI O pi ns are c onfigur ed as inputs or outputs wh en the hos t cont r ol ler (or DSP ) writes to the GPIO
direct ion regist er . Th e GPIO di r ection and data registers ar e i nit i alized t o al l ones ( FFh) upon r eset .
2.1.1 GPIO Data (GPIO): Ad dr ess 02h
Reset State FFh
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
Bits in this register will be asserted on the GPIO(7:0) pins if the corresponding direction register bit is a 0.
Reading this address will ret ur n data reflecting the values of pins GPIO(7:0).
2.1.2 GP I O Di rection (DIR): Add ress 03h
Reset State FFh
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
DIR7 DIR6 DIR5 DIR4 DIR3 DIR2 DIR1 DIR0
Thi s reg is ter is u sed t o d esig n at e th e G PI O p in s as eit h er in p uts or ou tp ut s . If the reg ister bit is l ow, the
corresponding GPIO pin is programmed as an output. If the register bit is a 1, the corresponding pin will
be t r eated as an i nput.
2.2 Analog I/O
Figure 4 s hows the block diag r am of the anal og front end. The anal og i nterface circuit uses dif fe rential
t r ansmit and receive si gnals to and from the exter nal circuitry.
The hybrid driver in the 73M1903 IC i s capable of connect ing d irec tly, but not l imited to, a t r ansformer-
based D irec t Ac cess Arr angement (DAA ) . The hybri d driver is capable of driving the DAA’s li ne coupli ng
t r ansformer, which carries an i mpedance on the primary si de that is t ypically rated at 600 Ω, depending
on t he transformer and match ing net work. The hybrid drivers can also drive high im pedance loads
without modi fication. The class AB behavior of the ampli fier s provides load dependent power
consumption.
A n on-ch i p band gap voltage is used to provide an internal voltage reference and bias currents for the
analog receive an d transmi t ch annel s. The r eference derived from the bandgap, nom i nally 1 .25 Volts , i s
mul t ipl i e d to 1.3 6 Volts and output at the VRE F pin. Severa l vol tage references, nomin ally 1 .25 Volts, ar e
used i n the analog cir cuits. The band gap and reference cir cuits ar e di sabled after a c hi p r eset since th e
E NFE bit i s res et to a defau lt st ate of z er o. When ENFE=0, the band gap volt age and the analog bi as
cur r ents ar e di sabled. In this case all of the analog circuits are powered down and draw less than 5 μA of
current.
A clock gener ator ( CK GN ) i s us ed to c r eate all of the non-over lapping phas e clocks needed for t he ti me
sampled s witched-cap acit or circuits , ASDM, DAC1, a nd TLPF. The CKGN input is two times the
analog/digital i nterface samp le rate or 3.0 72 MHz clock for Fs=8 kHz.
DS_1903_032 73M1903 Da ta She e t
Rev. 2.1 11
Figure 4: Ana log Block Diagram
Table 3: PLL Loop Fi lter Settings
FL PLLloop Filte r Settings
0 R1=32 kΩ,C1=100 pF,C2=2.5 pF
1 R1=16 kΩ, C1=100 pF,C2=2.5 pF
2.2.1 Control Register (CT RL 11): Ad dr ess 0Bh
Reset State 12h
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Ndvsr6 Ndvsr5 Ndvsr4 Ndvsr3 Ndvsr2 Ndvsr1 Ndvsr0
Ndvsr[6:0] represents the divisor. If Nrst{2:0] =0 this register is ignored.
2.2.2 Control Register (CT RL 12): Ad dr ess 0Ch
Reset State 00h
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Nseq7 Nseq6 Nseq5 Nseq4 Nseq3 Nseq2 Nseq1 Nseq0
Ns e q[7:0] r e pr e s e nts the di vis o r s e que nc e .
73M19 03 Data She e t DS_1903_032
12 Rev. 2.1
2.2.3 Contr o l Registe r (CTRL 13): Ad d ress 0Dh
Reset State 48h
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Xtal1 Xtal0 Reserved Reserved Unused Nrst2 Nrst1 Nrst0
Xtal [1: 0] : 0 0 = Xtal osc. bi as cur r ent at 120 μA
01 = Xtal os c. bias cur r ent at 180 μA
10 = Xtal os c. bias cur r ent at 270 μA
11 = Xtal os c. bias cur r ent at 450 μA
I f OSCIN i s us ed as a Cl ock input , “00” settin g shoul d be used t o save power(=167 μA at 27.648 MHz).
Nrst [3:0] repres ents the rate at which the NCO sequence r egi ster is res et.
The address 0Dh must be the last regist er to be writt en to when effecti ng a change in PLL.
2.2.4 Control Register (CT RL 14): Ad dr ess 0Eh
Reset State 00h
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Frcvco PwdnPLL Reserved Unused Unused Unused Unused Unused
Frcvco = 1 fo rces VCO as system clock. This is reset u pon RST, PwdnPLL = 1 or ENFE = 0. Both
P wdnPL L and EN FE are delayed comi ng out of digital secti on to k eep PLL al i ve long enough to t r ansition
the system clock to c r ys tal clock when Frc vc o i s reset b y PwdnPLL or EN FE .
PwdnPll = 1 forces Power down of PLL analog section.
DS_1903_032 73M1903 Da ta She e t
Rev. 2.1 13
3 Clock Generation
3.1 C ry st al O sc il l at or and Pr e-s caler NC O
The crystal osci llator operates over wide choi ce of crys tals (from 9 M Hz to 27 MH z) and it is first input to
an NC O base d pr e -scaler (divider) pr ior to being pas sed ont o an on-chi p PL L
Appendix B
. The intent of the pre-
scaler is to c onvert the cr ystal osc i llator frequenc y, Fxtal , to a convenient frequenc y to be u sed as a
referenc e frequency, F r ef, for the PLL. The NCO pre-scal er r equires a set of three number s t o be
ent er ed through the s er i al p or t (Pseq[ 7:0], Prs t[2: 0] and Pdvsr[2:0] . Th e PLL al so requir es 3 number s as
for program m ing; Ndvsr[6:0], Nseq[7:0], and Nrst[2:0]. The following is a brief des cri ption of the registers
t hat c ontrol the NCOs, PLLs , and s am ple rates for the 73M1903 IC. Th e tables show some examp les of
t he r egi ster s ettings for differ ent c lock and sam pl e r ates. A mor e detailed dis cus sion on how these values
are derived can be found in .
3.1.1 Control Register (CT RL 8): Ad dr ess 08h
Reset State 00h
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pseq7 Pseq6 Pseq5 Pseq4 Pseq3 Pseq2 Pseq1 Pseq0
Thi s cor r esponds to the s equence of d i visor. I f Prst{2:0] =0 this register is ignored.
3.1.2 Control Register (CT RL 9): Ad dr ess 09h
Reset State 0Ah
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Prst2 Prst1 Prst0 Pdvsr4 Pdvsr3 Pdvsr2 Pdvsr1 Pdvsr0
P r st[ 2:0] represent s th e r ate at whi ch th e sequence r egister i s reset .
Pdvsr [4: 0] r e pr e s e nts the di vis o r .
3.1.3 Control Register (CT RL 10): Ad dr ess 0Ah
Reset State 22h
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Ichp3 Ichp2 Ichp1 Ichp0 FL Kvco2 Kvco1 Kvco0
K vc o2:0 represents the mag nitude of Kvco associated with th e VCO within P LL. This indi cates the c enter
frequen cy o f the VCO when the control voltage is 1.6 Volts and the slope of the VCO freq versus control
voltage (i.e., Kvco.). FL repr esents the PLL loop fil ter sett i ngs.
Table 4: Kvco versus Settings at Vc=1.6 V, 25 °C
Kvco2 Kvco1 Kvco0 Fvco Kvco
0 0 0 33 MHz 38 MHz/v
0 0 1 36 MHz 38 MHz/v
0 1 0 44 MHz 40 MHz/v
0 1 1 48 MHz 40 MHz/v
1 0 0 57 MHz 63 MHz/v
1 0 1 61 MHz 63 MHz/v
1 1 0 69 MHz 69 MHz/v
1 1 1 73 MHz 69 MHz/v
73M19 03 Data She e t DS_1903_032
14 Rev. 2.1
Table 5: PLL Power Down
Addr. 00h bit 7
ENFE Addr. 0E h bit 6
PwdnPLL PLL
0 X P LL Power O ff
1 0 P LL Power O n
1 1 P LL Power O ff
Table 6: Examples o f NCO Settings
Fs
(kHz)
Dnco1
Nnco1
PsDiv
PsSeq(7:0) PsRst
=Dnco1
-1 Dnco2
Nnco2
PllDiv
PllSeq(7:0) PllRst
=Dnco2
-1
Fvco
(Mhz)
PPM
Fxtal(Mhz)=27.0
7.2 8/125 15 11011010 7 5/96 19 XXX10000 4 33.177600 0
8.0 8/125 15 11011010 7 3/64 21 XXXXX100 2 36.864000 0
2.4*8/7*3
=8.22857142858 8/169 21 10000000 7 3/89 29 XXXXX110 2 37.917160* -3
8.4 8/125 15 11011010 7 5/112 22 XXX10100 4 38.707200 0
9.0 8/125 15 11011010 7 1/24 24 XXXXXXXX 0 41.472000 0
9.6 8/125 15 11011010 7 5/128 25 XXX11010 4 44.236800 0
2.4*10/7*3
=10.2857142857 8/125 15 11011010 7 7/192 27 X1010110 6 47.396571 0
2.4*8/7*4
=10.9714285714 7/50 7 X1000000 6 8/107 13 10100100 7 50.557500* 23
11.2* 7/52 7 X1010100 6 5/71 14 XXX10000 4 51.611538* 38
12.0 8/125 15 11011010 7 1/32 32 XXXXXXXX 0 55.296000 0
12.8* 8/65 8 10000000 7 4/71 17 XXXX1110 3 58.984615* 38
2.4*10/7*4
=13.7142857143 7/80 11 X1010100 6 4/107 26 XXXX1110 3 63.196875* 23
14.4 8/125 15 11011010 7 5/192 38 XXX10100 4 66.355200 0
Fxtal(Mhz)=24.576
7.2 1/10 10 XXXXXXXX 0 2/27 13 XXXXXX10 1 33.177600 0
8.0 1/10 10 XXXXXXXX 0 1/15 15 XXXXXXXX 0 36.864000 0
2.4*8/7*3
=8.22857142858 4/35 8 XXXX1110 3 2/27 13 XXXXXX10 1 37.917257… 0
8.4 1/10 10 XXXXXXXX 0 4/63 15 XXXX1110 3 38.707200 0
9.0 1/10 10 XXXXXXXX 0 8/135 16 11111110 7 41.472000 0
9.6 1/10 10 XXXXXXXX 0 1/18 18 XXXXXXXX 0 44.236800 0
2.4*10/7*3
=10.2857142857
3/28 9 XXXXX100 2 1/18 18 XXXXXXXX 0 47.3965714.. 0
2.4*8/7*4
=10.9714285714
4/35 8 XXXX1110 3
1/18 18 XXXXXXXX 0 50.5563429.. 0
11.2 1/10 10 XXXXXXXX 0 1/21 21 XXXXXXXX 0 51.609600 0
12 1/10 10 XXXXXXXX 0 2/45 22 XXXXXX10 1 55.296000 0
12.8 1/10 10 XXXXXXXX 0 1/24 24 XXXXXXXX 0 58.982400 0
2.4*10/7*4
=13.7142857143
1/7 7 XXXXXXXX 0
1/18 18 XXXXXXXX 0 63.19542… 0
14.4 1/10 10 XXXXXXXX 0 1/27 27 XXXXXXXX 0 66.355200 0
Fxtal(Mhz)=9.216
7.2 1/4 4 XXXXXXXX 0 5/72 14 XXX10100 4 33.177600 0
8.0 1/4 4 XXXXXXXX 0 1/16 16 XXXXXXXX 0 36.864000 0
8.4 1/4 4 XXXXXXXX 0 5/84 16 XXX11110 4 38.707200 0
9.0 1/4 4 XXXXXXXX 0 1/18 18 XXXXXXXX 0 41.472000 0
9.6 1/4 4 XXXXXXXX 0 5/96 19 XXX10000 4 44.236800 0
2.4*8/7*4
=10.9714285714 2/7 6 XXXXXX10 4 5/96 19 XXX10000 4 50.556343 0
11.2 1/4 4 XXXXXXXX 0 5/112 22 XXX10100 4 51.609600 0
12 1/4 4 XXXXXXXX 0 1/24 24 XXXXXXXX 0 55.296000 0
DS_1903_032 73M1903 Da ta She e t
Rev. 2.1 15
Fs
(kHz)
Dnco1
Nnco1
PsDiv
PsSeq(7:0) PsRst
=Dnco1
-1 Dnco2
Nnco2
PllDiv
PllSeq(7:0) PllRst
=Dnco2
-1
Fvco
(Mhz)
PPM
12.8 1/4 4 XXXXXXXX 0 5/128 25 XXX11010 4 58.982400 0
14.4 1/8 8 XXXXXXXX 0 5/288 57 XXX11010 4 66.355200 0
Fxtal(Mhz)=24.000
7.2 8/125 15 11011010 7 5/108 21 XXX11010 4 33.1776 0
8.0 2/25 12 XXXXXX10 1 5/96 19 XXX10000 4 36.864 0
2.4*8/7*3
=8.22857142858 4/73 18 XXXX1000 3 6/173 28 XX111110 5 37.91781* 15
8.4 8/125 15 11011010 7 5/126 25 XXX10000 4 38.7072 0
9.0 4/25 6 XXXX1000 3 5/54 10 XXX11110 4 41.472 0
9.6 8/125 15 11011010 7 5/144 28 XXX11110 4 44.2368 0
2.4*10/7*3
=10.2857142857 8/125 15 11011010 7 7/216 30 X1111110 6 47.39657 0
2.4*8/7*4
=10.9714285714 6/59 9 XX111110 5 7/145 20 X1110110 6 50.5569* 12
11.2 8/125 15 11011010 7 5/168 33 XXX11010 4 51.6096 0
12.0 4/25 6 XXXX1000 3 5/72 14 XXX10100 4 55.296 0
12.8 8/125 15 11011010 7 5/192 38 XXX10100 4 58.9824 0
2.4*10/7*4
=13.7142857143 5/61 12 XXX10000 4 8/257 32 10000000 7 63.19672* 21
14.4 7/73 10 X1010100 6 6/173 28 XX111110 5 66.35616* 15
Fxtal(Mhz)=
25.35
7.2 8/163 20 10010010 7 3/80 26 110 2 33.177914* 10
Table 7: Clock Generation Register Settings for Fxtal = 27 MHz
Reg Address
Fs (kHz) 8h 9h Ah
Bh Ch Dh
* Ichp
(μA) Kvco
[2:0]
7.2 DA
EF 20 13 10 C4 8 0
8.0 DA
EF 31 15 04 C2 10 1
2.4*8/7*3
=8.22857142858 80 F5 41 1D 06 C2 12 1
8.4 DA
EF 31 16 14 C4 10 1
9.0 DA
EF 31 18 XX C0 10 1
9.6 DA
EF 32 19 1A C4 10 2
2.4*10/7*3
=10.2857142857 DA
EF 43 1B 54 C6 12 3
2.4*8/7*4
=10.9714285714* 40 C7 23 0D A4 C7 8 3
11.2* 54 C7 23 0E 10 C4 8 3
12.0 DA
EF 24 20 XX C0 8 4
12.8* 80 E8 15 11 0E C3 6 5
2.4*10/7*4
=13.7142857143 54 CB 26 1A 0E C3 8 6
14.4 DA
EF 46 26 14 C4 12 6
73M19 03 Data She e t DS_1903_032
16 Rev. 2.1
Table 8: Clock Generation Register Settings for Fxtal = 24.576 MHz
Reg Address
Fs (kHz) 8h 9h Ah Bh Ch Dh*
Ichp
(μA) Kvco
[2:0]
7.2 XX 0A 10 0D 02 C1 6 0
8.0 XX 0A 11 0F XX C0 6 1
2.4*8/7*3
=8.22857142858
0E 68 11 0D 02 C1 6 1
8.4 XX 0A 21 0F 0E C3 8 1
9.0 XX 0A 21 10 FE C7 8 1
9.6 XX 0A 22 12 XX C0 8 2
2.4*10/7*3
=10.2857142857
04 49 23 12 XX C0 8 3
2.4*8/7*4
=10.9714285714
0E 68 23 12 XX C0 8 3
11.2 XX 0A 23 15 XX C0 8 3
12 XX 0A 14 16 02 C1 6 4
12.8 XX 0A 15 18 XX C0 6 5
2.4*10/7*4
=13.7142857143
XX 07 16 12 XX C0 6 6
14.4 XX 0A 26 1B XX C0 8 6
Table 9: Clock Generation Register Se ttings for Fxtal = 9.216 MHz
Reg
Address
Fs (kHz) 8h 9h Ah Bh Ch
Dh*
Ichp
(μA)
Kvco
[2:0]
7.2 XX
04 20 0E 14 C4 8 0
8.0 XX
04 31 10 XX
C0 10 1
8.4 XX
04 31 10 1E C4 10 1
9.0 XX
04 31 12 XX
C0 10 1
9.6 XX
04 32 13 10 C4 10 2
2.4*8/7*4
=10.9714285714 02 23 33 13 10 C4 10 3
11.2 XX
04 33 16 14 C4 10 3
12 XX
04 24 18 XX
C0 8 4
12.8 XX
04 35 19 1A C4 10 5
14.4 XX
08 66 39 1A C4 16 6
DS_1903_032 73M1903 Da ta She e t
Rev. 2.1 17
Table 10: Clock Generation Register Settings for Fxtal = 24.000 MHz
Reg Address
Fs (kHz) 8h 9h Ah Bh Ch Dh* Ichp
(μA) Kvco
[2:0]
7.2 DA EF 30 15 1A C4 10 0
8.0 02 2C 31 13 10 C4 10 1
2.4*8/7*3
=8.22857142858 08 72 41 1C 3E C5 12 1
8.4 DA EF 41 19 10 C4 12 1
9.0 08 66 11 0A 1E C4 6 1
9.6 DA EF 42 1C 1E C4 12 2
2.4*10/7*3
=10.2857142857 DA EF 43 1E 7E C6 12 3
2.4*8/7*4
=10.9714285714 3E A9 33 14 76 C6 10 3
11.2 DA EF 53 21 1A C4 14 3
12 08 66 14 0E 14 C4 6 4
12.8 DA EF 45 26 14 C4 12 5
2.4*10/7*4
=13.7142857143 10 8C 46 20 80 C7 12 6
14.4 54 CA 46 1C 3E C5 12 6
Table 11: Clock Generation Register Settings for Fxtal = 25.35 MHz
Reg Addr ess
FS (KHz) 8h 9h Ah Bh Ch Dh* Ichp
(μA) Kvco
[2:0]
7.2 92 F4 50 1A 06 C2 14 0
0
1
Xtal Oscillator
System
Clock
NCO
Kd
Up
Dn
Ichp Control
VCO Locked
22
Fref Fvco
Kvco Control
Fxtal
NCO
Prescaler VCO
Kvco
PFD Charge
Pump
Mux
FrcVco
R1
C1 C2
Loop Filter Control 2
Figure 5: Clock Generation
73M19 03 Data She e t DS_1903_032
18 Rev. 2.1
4 Modem Receiver
A differen tial rec eive signal appl i ed at the RXAP and RXAN pin s or the out put signal at TX AP and TXAN
pass t hr ough a m ul ti pl exer, whi ch selects the i nputs to the ADC. In normal mode, RX AP/RXAN ar e
sel ected. In analog l oopback mod e, TX AP/TXAN are sel ect ed. Th e D C bias for the R XAP/ RX AN inputs
is supplied from TXAP/TXAN through the ext er nal DA A i n normal c ondit i ons. (See Appendix A) It can be
suppl ied int er nal ly, in the abs ence of t he ext er nal DA A, by setting RXPULL bit in Cont r ol Reg ister 2.
The output of the mult i pl exer goes into a second-order continuous time, Sallen-Key, l ow-pass filter (AAF)
with a 3 dB poi nt at approximately 40 kHz. The filt ered ou tput s i gnal is the input to an analog sigma-delta
modulator ( ASDM ) , cloc ked at an over sampli ng frequency of 1.536 MHz for Fs = 8 kHz, which converts
t he anal og signal to a s er ial bit st r eam wi th a pulse dens it y t hat is proporti onal to the amplit ude of the
analog input s ignal.
There ar e three gai n control bi ts for the receive pat h. Th e R XGAIN bit i n cont r ol r egister one r esults in a
+20 dB gain of t he r eceive signal when set to a “1” . This 20 dB of gain compens ates for the loss t hr ough
t he D AA wh i le on h ook. I t is us ed for C aller ID r ecept ion. This gai n is realized in the front end of ASDM.
The other gain bits in control register 1, RXG1:0, c ompens ate for differenc es in l oss through the receive
path.
Table 12: Receive Gain
RXG1 RXG0 Rec eive Ga in S ett ing
0 0 6 dB
0 1 9 dB
1 0 12 dB
1 1 0 dB
The output of ASDM i s a s er i al bit stream th at feeds three di gi tal sinc3 filters. Each fil ter has a [ sin(x)/x] 3
frequency response and provides a 16 bit sample every 288 clock cycles. Th e fi l ters are s ync hr oni zed so
t hat there is one sample availabl e after every 96 analog sampl es or at a rate of 1 6 kHz for F s =8 kHz. The
out put of t he sinc3 filter i s a 17 bi t, two’s c ompliment nu m ber r epr esenting the ampl itude of the input
signal. The sinc3 filter, by virtue of hol di ng act ion ( for 96 sampl e period), introduc es a droop in the
passband th at is later correct ed for by a 48 t ap FI R filter that fol l ows. Th e maximum di gi tal word that can
be out put from the filter is 0d800h. Th e minim um word is 12800h.
The output of the sinc3 filter is input to another 48 t ap digital FI R filter that pr ovides an ampli tude
cor r ect ion in the passband t o the output of the s in c3 filter as well as rejec ti ng noi se above Fs/2 or 4 kHz
for Fs=8 kHz. The out put of this filter is then decimated by a factor of 2; so, the final output is 16 bit, two’s
compliment samples at a rate of 8 kHz.
Figure 6 and Figure 7 depict the sinc3 filter’s frequency response of ASDM along with the 48 tap digital
FIR r esponse that com pensates for i t and the res ulting over al l res ponse of the r eceiver.
DS_1903_032 73M1903 Da ta She e t
Rev. 2.1 19
Figure 6: Overall Receiver Frequency Response
Figure 7: Rx Passba nd Response
I t is im por tant t o keep in mind t hat the receive si gnal should not exceed 1.16 Vpk-diff for proper
performanc e for Rxg=11 (0 dB) . In particular , if the input level exceeds a valu e suc h that one’s density of
RBS exceeds 99.5%, sinc3 filter output will exceed t he maximum input range of the deci mat ion fi l ter and
consequent l y the data wi ll be c or r upted. Also for s tability r easons , the receive si gnal should not exceed
1.16 Vpk di fferential ly. Th is value i s set at around 65% of the ful l r eceive sig nal of 1.791 Vpkdiff at
RXAP/ R XAN pin s th at “would” corresponds to ASDM putting out all ones.
Figure 8 and Figure 9 show the spectrum of 1 kHz tone rec eived at R XAP/RXAN of 1.1 6 Vpk-diff and
0.5 kHz and 1.0 kHz t ones of 0 .6 Vpk-diff each, res pectiv ely for Fs=8 kHz. Not e the effect of FIR
suppr essing t he noi se above 4 kHz but at th e same time enhancing (in order to compens ate for the
passband droop of si nc3 filter) it near the passband edge of 4 kHz.
73M19 03 Data She e t DS_1903_032
20 Rev. 2.1
Figure 8: RXD Spect rum of 1 kHz Tone
Figure 9: RXD Spect rum of 0.5 kHz, 1 kHz, 2 kHz, 3 kHz and 3.5 kHz Tones of E qual Amplitudes
DS_1903_032 73M1903 Da ta She e t
Rev. 2.1 21
5 Modem Transmitter
The modem t r ansmitter begins with an 48 tap Transmit Int er pol ati on F ilter (TI F) that tak es in the 16-bit,
t wo’s compliment numbers (TXD) at S DI N pi n at Fs=8 kHz r a te . It up-sam ples ( i nterpol ates) the dat a to
16 kHz rate reject i ng the images at mult i ples of 8 kHz that exis t i n the ori gi nal TXD data s tream and
o utpu t s 16-bit, two’s c ompliment numbers to a dig ital sigma-d elt a modu lat or . The gain of the i nterpol ati on
filter is 0.640625 (–3.8679 dB) at DC.
The digital sigm a-d elt a modu lat or ( D SD M ) takes 16-bit, t wo’s compl i ment numb er s as input and
generates a 1’ s bit str eam whi ch feed s into a D to A c onverter (D AC 1) . Th e gai n through DS D M is 1.0.
DSD M takes 16-bit, t wo’s compliment numbers as i nput and generates a 1’ s bit str eam t hat feeds int o a D
t o A converter ( D AC 1) .
DAC1 consists of a 5-t ap FI R filter and a first or der swit ched capacitor l ow pass filter both operating at
1.536 MHz. It po ssesse s nulls at multiples of 384 kHz t o al low decimati on by t he succeeding fil ter.
DAC1’s differential output is fed to a 3rd-order s witched-c apacitor low pass filter (TLPF) . The out put of
TLPF drives a conti nuous time smoothing fil ter. Th e sampling nat ur e of the transm it ter lead s to an
additional fi l ter response t hat affects the i n-band si gnals. Th e r esponse i s in the form of s in(x)/ x and can
be expressed as 20*log [(sin(PI*f/fs))/(PI*f/fs)] wher e f = signal frequency and fs = sample frequency = 16
kHz. Figure 10 shows the frequenc y resp onse of t he transmit path from TXD to TX AP/TXAN for a dc to 4
kHz in-band signal including the effect of this sampling process plus those of DAC1, TLPF and SMFLT. It
is important t o note that as TXD i s s am pl ed at 8 kHz, i t be band-limited to 4 kHz.
Figure 10: Frequenc y Re sponse of TX Path for DC to 4 kHz in Ba nd Signal
73M19 03 Data She e t DS_1903_032
22 Rev. 2.1
5.1 Transmit Levels
The 16-bi t transmit c ode word wr i tten by the D SP to the Di gi tal Si gma-Delta M odul ator ( DS DM) (via TI F)
has a l inear relationshi p with th e anal og output s ign al. So, decreas i ng a code word by a factor of 0.5 will
res ul t i n a 0.5 (-6 dB) gain change in the anal og output sig nal.
The following formula describes the relationship between the transmit c ode word and th e output level at
the transmit pins (TXAP/TXAN):
V out (V) = 2 * code/32,767 * DSDMgai n * dacG AIN * VR EF * TLPFgain * SMF LTg ain * FreqF ct r
Vout is the differential peak voltage at the TXAP and TXAN pins.
Code is the 16-b i t, two’ s c omp liment transmit code word wr i tten out by the D SP to th e DS DM (via TIF ) .
The code word falls within a range of ± 32,767. For a sinusoidal waveform, the peak code word shoul d
be used in the formul a to obtain the peak output volt age.
DSDMgain is the sc al ing factor us ed on the transmit c ode word to reduce the possib i lity of sat ur ating the
modulator. Th i s value is set t o 0.640625(–3.555821 dB) at dc in the 48 tap transmit interpolation filter
(TIF ) that preced es DSD M .
dacGAIN is the gain of the DAC. The value dacGAIN is calculated based on capacit or values ins id e
DAC1 and dacGAIN=8/9 = 0.8889. The number 32,767 refers t o the c ode word that generates an 82%
“1’s” pulse dens it y at the output of the DSD M . As one can see from the formula, the D to A convers i on is
depen dent on the level of VREF. Also when TXBST1 bit is set, VREF i s inc r eased from 1.36 V to 1. 586 V
t o al low higher transmit l evel or 16.6% inc r ease in gai n. This bit is intended for enhancing the DTMF
transmit level and should not be used in data mode.
TLPFgain is the gain of TLPF and nominally equals to 0.00 dB or 1.0.
SMFLTgain is the gain of SMFLT and nom inally equal to 1.445 or 3.2 dB.
When TXBST0 bit is set, the gain is further increased by 1.65 dB (1.2 1) for the total of 4.85 dB . This is to
accommodate greater hybrid i nsertion l oss encountered in some appli cations .
FreqFctr shows dependen cy of the entire transmit path on frequency. S ee Figure 10.
With the t r ansmit cod e word of +/- 32,767, the nominal differ ential swing at the transmit pins at dc is:
Vout (V) = 2 * code/32,767 * DSDMgain * dacGAIN * VREF * TLPFgain * SMFLTgain * FreqFctr
= 2 * 32,767/32767 * 0.6640625 * 0.8889 * 1.36 * 1.0 * 1.4454 * 1.0 = 2.31Vpk diff.
When TXBST1 bit is set, Vout (V) = 1.166 * 2.31= 2.693 Vpk diff.
When TXBST0 bit is set, Vo u t (V ) = 1. 21 * 2 .3 1= 2. 7 95 V pk di f f, if not limited by power supply or internal
reference.
When both TX BST1 and TXBS T0 ar e set t o 1, Vout (V) = 1.166 * 1. 21 * 2.31 = 3.259 V p k diff.
DS_1903_032 73M1903 Da ta She e t
Rev. 2.1 23
5.2 T r ansm i t P o wer - dBm
To calculate the analog output power, the peak voltage is calculated and the peak to rms ratio (crest
factor) mu st be known . The follo wing formula is used to c alcul ate the out put power, in dBm referenced to
600 Ω.
Pout (dBm) = 10 * log [ ( V out (V) / cf )2 / ( 0.001 * 600 ) ]
The following example demonstrates the calc ulat i on of the analog output p ower given a 1. 2 kHz FSK tone
(s i ne wave) with a p eak c ode wo r d value of 11,87 8 sent out by t he D SP.
The di fferential output volt age at TXAP-TXAN will be:
With FreqFctr = 1.02, (See Figure 10)
Vout (V) = 2 * (11,878/32,767) * 0.6640625 * 0.8889 * 1.36 * 1.0 * 1.4454 * 1.02 = 0.8 41 Vpk.
The output signal power wi ll be:
Pout (dBm) = 10 * log [(0.841 / 1.41)2 / ( 0. 0 01 * 600 ) ] = - 2.29 dBm.
Table 13: Peak to RMS Ratios for Vari ous Modulation Types
Tr ans mit T ype
Cre st Factor
Max Line Level
V.90 4.0 -12 dBm
QAM 2.31 -9 dBm
DPSK 1.81 -9 dBm
FSK 1.41 -9 dBm
DTMF
1.99
-5.7 dBm
5.3 Cont rol Regis t er ( C T RL1): Address 00 h
Reset State 08h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ENFE Unused TXBST1 TXBST0 TXDIS RXG1 RXG0 RXGAIN
ENFE 1 = Enable the digital filters and analog front end.
0 = Disable the analog blocks shut off the clocks to the digital and analog receive/transmit
circuits.
TXBST1 1 = Add a gai n of 1.335 dB (16.6%) to th e transmitter; also t he common m ode voltage of t he
t r ansmit path is inc r eased to 1.37 5 V. This is intended for enhanc ing DTMF transmit
power only and should not be used in data mode.
0 = No gain is added
TXBST0 1 = A gai n of 1.65 dB (21%) is added to the t r ansmi tter
0 = The gain of the trans mitt er i s nominal
TXDIS 1 = Tri-st ate the TXAP and TXAN pi ns, p r ovides a bias of VBG into 80 kΩ for each output pin
RXG1:0 These bi ts control the receive g ain as shown in Table 12.
RXGAIN 1 = I ncrease t he gai n of the rec ei ver by 20 dB .
73M19 03 Data She e t DS_1903_032
24 Rev. 2.1
5.4 Cont rol Regis t er ( C T RL2): Address 01 h
Reset State 00h
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TMEN DIGLB ANALB INTLB CkoutEn RXPULL SPOS HC
TMEN 1 = Enable test modes.
DIGLB 1 = Tie the serial bit st r eam from the digi tal transmi t fil ter output t o the di gi tal r eceive filter
input. DIGITAL LOOPBACK
ANALB 1 = Ti e the analog output of the transmitter to th e analog input of the r eceiver. ANALOG
LOOPBACK
INTLB 1 = Ti e the digital ser i al bit stream from the analog receiver out put to th e analog t r ansmitter
inpu t. INTERNAL LOOPBACK
CkoutEn 1 = Enable the CLKOUT output; 0 = CLKOUT tri-stat ed. F or tes t purposes onl y; do not us e
in normal operation.
RXPULL 1 = Pulls DC Bias to RXAP/RX AN pins, through 100 kΩ each, to VREF, to be us ed in test i ng
Rx path.
0 = No DC Bias t o RX AP/RXAN pins .
SPOS 1 = Control frames occur after one quarter of the t i me between data frames has el apsed.
0 = Control frames occur half way b etwe en data frames.
HC 1 = FS i s under hardware c ontrol , bit 0 of data frames on SDIN i s bi t 0 of the t r ansmit word
and control frames happen automaticall y aft er every d ata frame.
0 = FS is under software control , bit 0 of dat a frames on SD IN i s a c ontrol frame request bi t
and control frames happen only on request.
5.5 Revision Register: Address 06h
Reset State 30h
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Rev3 Rev2 Rev1 Rev0 Unused Reserved Reserved Reserved
Bits 7-4 cont ain the revision l evel of t he 73M1903 device. The rest of this register is for chip development
purposes only and is not intend ed for cus tomer use. Do n ot write t o shaded locat ion s.
DS_1903_032 73M1903 Da ta She e t
Rev. 2.1 25
6 Test Modes
There ar e two loop bac k t est modes that aff ect the configuration of t he anal og front end. The i nternal
loop bac k mode c onnects the s er ial bit s tream generated by the anal og r eceiver to t he i nput of t he anal og
t r ansmitter. This l oop back m ode is similar to a remote analog loop bac k mode and c an be used to
eval uate the operation of th e analog ci r cuits . When us ing th i s loop back mode, the TX AN /TXAP pins
should not be externally coupled to the RXAP/RXAN pins. Set bit 4 (INTLB) in register 1h (CTRL2) to
ent er this loop back m ode.
The second l oop back test m ode i s th e external l oop back m ode, or local anal og loop back m ode. In this
mode, th e anal og transmitter output s are fed bac k into th e in put of the analog receive r . Set bit 5 (ANALB)
in regi ster 1h (CTRL2) to enter this loop bac k mode. In this mode, TBS m ust be kept to bel ow a value
t hat c or r esponds to l ess than 1.16 V/2.31 V x -6 dB = 25% of the full sc al e code of + /- 32768 at TXD in
order to ens ure that the rec eiver is not overdriven beyon d the maximum of 1 .16 Vpkpk diff for Rxg=11(0
dB) s etting. See Table 16 for the maximum al lowed trans mit levels . C heck the transmitted dat a against
rec eived data via s er ial i nterfac e. Th i s tests the functi onal i ty of ess enti al ly all block s, both digit al and
analog, of the chip.
There is a thir d l oopback m ode that bypasses th e analog ci r cuits entir ely. Digital l oop back forces the
t r ansmitter di gi tal seri al bit st r eam (from D SD M ) to be r outed into the digit al r eceiver’s s i nc3 filters. Set bit
6 (DIGLB) in register 1h (CTRL2) to enter this loop bac k mode.
7 Power Saving Modes
The 73M1903 has only one power conservation mode. When the ENFE , bit 7 in r egi st er 0h, i s zer o the
clocks to th e filters and the analog ar e turned off. Th e transmi t pins out put a nominal 80 kΩ impedance.
The cloc k to t he serial p or t i s running and the GP IO and oth er r egisters can be r ead or updated.
73M19 03 Data She e t DS_1903_032
26 Rev. 2.1
8 Electrical Specifications
8.1 Absolute Maximum Ratings
O per ation above maximum r ati ng m ay permanently damage the device.
Parameter Rating
S upply Voltage -0.5 V to +4.0 V
P in Inp ut Voltage (except OS CI N ) -0.5 V to 6.0 V
P in Inp ut Voltage (OSCIN) -0.5 V to VDD + 0.5 V
8.2 Recommended Operating Conditions
Parameter Rating
S upply Vol tage (VDD) wit h respec t to VS S 3.0 V to 3.6 V
O scillator Frequenc y 24.576 MHz ±100ppm
O per ating Temperature -40 C to +85 °C
DS_1903_032 73M1903 Da ta She e t
Rev. 2.1 27
8.3 Digital Specifications
8.3.1 DC Characteristics
Parameter Symbol Conditions Min Nom Max Unit
I nput Low Vol tage VIL -0.5 0.2 * VDD V
I nput Hig h Vol tage
(Excep t OSCIN) VIH1 0.7 VDD 5.5 V
I nput Hig h Vol tage
OSCIN VIH2 0.7 VDD VDD + 5.5 V
O utput Low Voltage
(Excep t OSCOUT, FS,
SCLK, S DOUT)
VOL IOL = 4 mA 0.45 V
O utput Low Voltage
OSCOUT VOLOSC IOL = 3.0 mA 0.7 V
Output Low Voltage
FS,SCLK,SDOUT VOL IOL = 1 mA 0.45 V
Output High Voltage
(Excep t OSCOUT, FS,
SCLK, S DOUT)
VOH IOH = -4 m A VDD - 0.45 V
Output High Voltage
OSCOUT VOHOSC IOH = -3.0 mA VDD - 0.9 V
Output High Voltage
FS, SCLK, SDOUT VOH IOH = -1 mA VDD - 0.45 V
I nput Low Leakage
Current
(Excep t OSCIN)
IIL1 VSS < Vin < VIL1 1 μA
I nput Hig h Leakage
Current
(Excep t OSCIN)
IIH1 V IH 1 < Vi n < 5.5 1 μA
Input Low Leakage
Current
OSCIN
IIL2 VSS < Vin < VIL2 1 30 μA
I nput Hig h Leakage
Current
OSCIN
IIH2 VIH2 < Vin <V DD 1 30 μA
IDD current at 3.0V – 3.6V Nom inal at 3.3V
I D D Total current IDD Fs=8 kHz,
Xtal=27 MHz 9 12.0 mA
I D D Total current IDD Fs=11.2 kHz,
Xtal=27 MHz 10.3 13.4 mA
I D D Total current IDD Fs=14.4 kHz,
Xtal=27 MHz 11.8 14.5 mA
IDD Tot al cur r ent
ENFE=0 IDD 2 2.5 mA
73M19 03 Data She e t DS_1903_032
28 Rev. 2.1
8.3.2 AC Timing
Table 14: Serial I/F Timing
Parameter Min Nom Max Unit
SCLK Period (Tsclk) (Fs=8 kHz)
–
1/ 2.048 MH z – ns
SCLK to FS Delay (td1) – mode1
–
–
20
ns
SCLK to FS Delay (td2) – mode1
–
–
20
ns
SCLK to SDOUT Delay (td3) (With 10pf load)
–
–
20
ns
S etup Time SDIN to SC LK (tsu ) 15
–
–
ns
Hold Time SDIN to SCLK (th ) 10
–
–
ns
SCLK to FS Delay (td4) – mode0
–
–
20
ns
SCLK to FS Delay (td5) – mode0
–
–
20
ns
SCLK
FS
(mode1)
SDOut
SDIN
td1 td2
tsu
td3
td5
FS
(mode0) td4
RX0
RX15 RX14 RX1
th
TX15 TX14 TX1 TX0
Tsclk
Figure 11: Serial Port Data T iming
DS_1903_032 73M1903 Da ta She e t
Rev. 2.1 29
8.4 Analog Specifications
8.4.1 DC S p ecifications
V RE F shoul d be connec ted to an external bypas s capacitor wit h a minim um value of 0.1 μF. This pin is
not i ntended for any other ext er nal use.
Table 15: Reference Voltage Specifications
Parameter Te st Condition Min Nom Max Units
VREF VDD= 3.0 V - 3.6 V. 1.36 V
VREF Noise 300Hz-3.3 kHz -86 -80 dBm600
VREF PSR R 300Hz-30 kHz 40* dB
8.4.2 AC S p ecifications
Table 16 shows the maximum t r ansmit l evels t hat the outp ut dri vers can del iver before distortion through
t he D AA st ar ts to become s i gni fi cant . Th e loss t hough the DAA transmit path is assumed to be 7 dB.
The signals pres ented at TXAP and TXAN ar e sym met r i cal. Th e transmit l evels can be increased by
setting either TXBST0 (+1.5 dB) or/and TXBST1 (+0.83 dB) for the combined total gain of 2.33 dB.
These can be used where higher-level DTMF t ones are requi r ed.
Table 16: Ma xi mu m Tr ansmit L ev els
Transmit Type Maximum Different
Line Level (dBm0) Maximum Single-
Ended Level at
TXA Pins (dBm)
Peak to
rms Ratio Single-Ended
rms Voltage at
TXA Pins (V)
Single-Ended
Peak Voltage
at TXA Pins (v)
VPA=2.7 V to 3.6 V. All rm s and peak voltages are relative to VR EF.
V.90 -12.0 -11.0 4 0.2175 0.87
QAM -7.3 -6.3 2.31 0.377 0.87
DPSK -5.1 -4.1 1.81 0.481 0.87
FSK -3.0 -2.0 1.41 0.616 0.87
DTMF (high tone) -7.8 -6.8 1.41 0.354 0.500
DTMF (low tone) -9.8 -8.8 1.41 0.283 0.400
73M19 03 Data She e t DS_1903_032
30 Rev. 2.1
8.5 Performance
8.5.1 Receiver
Table 17: Receiver Perf ormance Speci f icatio ns
Parameter Te st Conditions Min Nom Max Units
I nput Impedanc e M easured at RXAP/ N r elat i ve to V RE F
RXPULL=HI
230
kΩ
Meas ur ed at RXAP/N rel ati ve t o VR EF
RXPULL=LO
1.0
MΩ
Rec eive Gai n
Boost Rxgain = 1; 1 kHz; RXAP/N=0.116 Vpk-diff
G ai n M easured rel ative to Rxgain=0
RX GAIN=1 for Fs=8 kHz
RX GAIN =1 for Fs=1 2 kHz
RX GAIN =1 for Fs=1 4. 4 kHz
17.0
16.2
15.7
18.5
17.4
17.2
20.0
18.7
18.7
dB
dB
dB
Total H ar monic
Distortion (THD) THD = 2
nd
a nd 3
rd
harmonic.
RXGAIN =1
64
70
RXG Gain
G ai n M easured relative to RXG[1:0]=11
(0 dB) @1 k Hz
RXG[1:0]=00
RXG[1:0]=01
RXG[1:0]=10
5.8
8.8
11.8
6
9
12
6.2
9.2
12.2
dB
dB
dB
P ass band Gain Input 1.16 Vpk-diff a t RXA. Measu r e gain at
0.5 kHz, a nd 2 kHz. Normalized t o 1 kHz.
G ai n at 0.5 kHz
G ai n at 1 kHz (Normalized)
G ai n at 2.0 kHz
-0.29
-0.067
-0.042
0.000
0.183
0.21
0.43
dB
dB
dB
Input o ffse t Short RXAP t o RXAN. Measure i nput
vol tage relat ive to VREF
-30 0
30
mV
Sigma-Delta ADC
Modulation gai n
Normalized t o VBG=1.25 V.
I ncludes the effec t of AA F(-0.4 dB) with
Bits 1, 0 of CTRL2 register (01h) = 00.
41
µV/bit
Max i mum Analog
Signal Level at
RXAP/RXAN
P eak vo l tage measured differential ly
across RXAP/RXAN. 1.16 Vpk-diff
Total H ar monic
Distortion (THD)
1 kHz 1.16 Vpk-diff at RXA with R x g=11
THD = 2 nd and 3rd harmonic.
80
85
dB
Noise Transmit V.22bis low band; FFT run on
ADC s amp les. Noi se in 0 to 4 kHz band
-85
-80
dBm
Crosstalk 0 dBm 1000Hz sine wave at TXA P; F FT
on Rx ADC sam ples, 1st four harm onics
Reflect ed back to receiver inputs . -100 dB
Note: RX G[1:0] and R XGAIN ar e assumed to h ave s ettings of ‘0’ unless they are specified otherwise.
DS_1903_032 73M1903 Da ta She e t
Rev. 2.1 31
8.5.2 Transmitter
Table 18: Transmitter Performance Specifications
Parameter Te st Condition Min Nom Max Units
DAC gain
(Transmit Path Gain) Code w or d of ± 32,767 @1 kHz;
TXBST0=0; TXBST1 =0 70
µv/bit
DC offs et –Differential
Mode Across TXAP and TXAN for
DAC inp ut = 0 -100 100 mV
DC offs et -Common
Mode Aver age of TXAP and TX AN for D AC
input = 0; rel ative to V RE F -80 80 mV
TXBST0 Gain Code word of ± 32,767 @1 kHz;
relative to TXBST0=0; TXBST1=0 1.65 dB
TXBST1 Gain Code word of ± 32,767 @1 kHz;
relative to TXBST0=0; TXBST1=0 1.335 dB
Total H ar monic
Distortion (THD)
Code wor d of ± 32,767 @1 kHz; relative
to TXBST0=0;TXBST1=0 THD = 2nd and
3rd harmonic.
-75
-85 dB
Code wor d of ± ( 32,767*0.8) @1 kHz;
relative to TXBST0=0;TXBST1=0 THD =
2nd and 3rd harmonic. -80 -85 dB
1200 Ω Resistor
across TNAN/TXAP Cod e word of ± ( 32,767*0.9) @1 kHz;
relative to TXBST0=1;TXBST1=1 THD =
2nd and 3rd harmonic. -60 -70 dB
Code wor d of ± 32,767 @1 kHz;
relative to TXBST0=1;TXBST1=1
THD = 2 nd and 3rd harmonic -70
I ntermod Dist or ti on
At output (TXAP-TXAN): DTMF
1.0 kHz, 1.2 kHz sine wa ves , s um med
2.0 Vpk (-2 dBm tone summed with
0 dBm t one)
Refer to TBR 21 speci fi cat ions for
descripti on of c omplete requir ements.
70
dB
below
low
tone
I dl e Chann el Noise 200 Hz - 4.0 kHz 110 μV
PSRR -30 dB m signa l at VP A
300 Hz – 30kHz 40 dB
P ass band R ipp le 300 Hz - 3.2kHz -0.125 0.125 dB
Transmit Gain
Flatness
Code wor d of ± 32,767 @1 kHz.
Meas ur e gai n at 0.5 kHz, and 2 kHz
relative to 1 kHz.
G ai n at 0.5 kHz
G ai n at 1 kHz (Normalized)
G ai n at 2.0 kHz
G ai n at 3.3 kHz
0.17
0
0.193
-0.12
dB
dB
dB
dB
73M19 03 Data She e t DS_1903_032
32 Rev. 2.1
Parameter Te st Condition Min Nom Max Units
TXAP/N Ou tput
Impedance
Differentially
(TXDIS=1)
TXDIS=1
Meas ur e i mpedance di fferential ly
between TXAP and TXAN.
160 kΩ
TXAP/N Common
Output Offset
(TXDIS=1)
TXDIS=1
S hor t TX AP and TXAN . Measure the
vol tage respect to Vbg.
-20 0 20 mV
Note: TXB ST0 and DTMFBS are assumed to have sett i ng 0’ s unless they are s pecified otherwise.
DS_1903_032 73M1903 Da ta She e t
Rev. 2.1 33
9 Pinouts
9.1 32-Pin Q F N Pinout
Figure 12: 32-Pin QFN Pinout
Table 19: 32-Pin QFN Pin Defi ni ti ons
Pin
Name
Pin
Name
1
VND
17
VNPLL
2 VPD 18 OSCOUT
3
GPIO0
19
OSCIN
4 GPIO1 20 VPPLL
5
GPIO2
21
CLKOUT
6
GPIO3
22
VND
7 FS 23 GPIO4
8
SCLK
24
GPIO5
9
RST
25
VPD
10
VPA
26
N/C
11
TXAN
27
TYPE
12 TXAP 28 SckMode
13
VREF
29
SDIN
14
RXAN
30
GPIO6
15
RXAP
31
GPIO7
16
VNA
32
SDOUT
6
7
8
9
5
4
3
2
1
17
18
19
20
24
23
22
21
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
VND
VPD
GPIO0
GPIO1
GPIO2
GPIO3
FS
SCLK
GPIO5
GPIO4
VND
N/C
VPPLL
OSCIN
OSCOUT
VNPLL
RST
VPA
TXAN
TXAP
VREF
RXAN
RXAP
VNA
TERIDIAN
73M1903
VPD
SDOUT
GPIO7
GPIO6
SDIN
SckMode
N/C
TYPE
73M19 03 Data She e t DS_1903_032
34 Rev. 2.1
9.2 20-Pin TSSOP Pinout
73M1903
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
16
17
18
19
20
SDOUT
VPD
SCLK
VREF
VPA
TXAP RXAN
TYPE
VPPLL
VND
OSCOUT
RXAP
VNA
VNPLL
SDIN
TXAN
FS
VND
RST
OSCIN
Figure 13: 20-Pin TSSOP Pi n out
Table 20: 20-Pin TSSOP Pin Defi ni ti ons
Pin Name Pin Name
1 SDOUT 11 RXAN
2 VND 12 RXAP
3 VPD 13 VNA
4 FS 14 VNPLL
5 SCLK 15 OSCOUT
6 VREF 16 OSCIN
7 RST 17 VPPLL
8 VPA 18 VND
9 TXAN 19 TYPE
10 TXAP 20 SDIN
DS_1903_032 73M1903 Da ta She e t
Rev. 2.1 35
R2
20K
R48 210, 1%
R49 210, 1%
R16
100
SDO
H OOK from hos t
R17 38. 3K, 1%
R20
61. 9K, 1%
R22 38. 3K, 1%
R23
61. 9K, 1%
C3
0.15uF
VCCA
SDI
27MH z or other SYSC LK
FS\
SCLK
+C7
10uF
C11
0.1uF
C13
0.1uF
VCCD
C21
0.1uF
C4
2.2nF
U1
73M1903-20VT
SDOUT 1
VND 2
VPD 3
FS 4
SCLK 5
VBG 6
RST 7
VPA 8
TXAN 9
TXAP 10
RXAN
11 RXAP
12 VNA
13 VNPLL
14 OSCOUT
15 OSCIN
16 VPLL/PPD
17 VND
18 SCLKM
19 SDIN
20
RESET\RESET
TIP
RING
-+
BR1
HD04
4
1
3
2
I SOLATI ON BAR R I ER
U2
TLP627
12
43
C22
220pF , 250V
C20
220pF , 3k V
C23
220pF , 3k V
L2
NLV32T-4R7
E1
TISP4350T3BJR
Bourns
Thyristor
1
2
T1
MIT4115V
Sumida
1
4
2
3
C19
0.22uF
250V
R9
63K
L1 NLV32T-4R7
F1
MF-R015/600
Bourns
PTC fuse
+
C9
3.3uF
C10
0.1uF
VCCD
10 73M1903 Schematic and Bill of Material
Figure 14: 73M1903 Schematic
73M19 03 Data She e t DS_1903_032
36 Rev. 2.1
Table 21: Bill of Materials
Item Qty Reference Part Sources
1 1 BR1 400 V, 500 mA Bridge Rec ti fier Diodes, Inc, On Semi
2 1 C3 0.15 µF 25 V P anasonic, AVX, TD K
3 1 C4 2.2 nF 2 5 V P anasonic, AVX, TDK
4 1 C7 10 µF 6.3 V P anasonic, AVX, TDK
5 1 C9 3.3 µF 6.3 V P anasonic, AVX, TDK
6 4 C10,C11,C13,C21 0.1 µF 25 V Panasoni c, AV X, TDK
7 1 C19 0.22 µF 250 V P anasonic, AVX, TDK
8 2 C20,C23 220 pF, 3 kV AVX, TDK, Yageo
9 1 C22 220 pF, 250 V Vi shay, M urata, TDK
10 1 E1 275 V, 200 A Bourns, Tyco, Littelfuse
11 1 F1 150 mA, 600 V Bour ns, Tyco, Vishay
12 2 L1,L2 4.7 µH, 200 mA TDK, Allied
13 1 R2 20 K P anasonic, Yageo, Vishay
14 1 R9 63 K P anasonic, Yageo, Vishay
15 1 R16 100 Panas oni c, Yag eo, Vishay
16 2 R17,R22 38.3 K, 1% Panasonic , Yageo, Vis hay
17 2 R20,R23 61.9 K, 1% Panasonic , Yageo, Vis hay
18 2 R48,R49 210 K, 1% Panasonic, Yageo, Vishay
19 1 T1 600 Ω, 100 m ADC, 1:1 Sumida, Datatronics, Allied
20 1 U1 73M1903-20VT Teridian
21 1 U2 Darlington optocoupler, 300 V Vceo Toshiba, Soli d State Op troni cs
DS_1903_032 73M1903 Da ta She e t
Rev. 2.1 37
11 Mechanical Specifications
11.1 32-Pin Q F N Mech ani ca l Dr a wing s
Dimensions i n mm.
2.5
5
2.5
5
TOP VIEW
1
2
3
Figure 15: 32-Pin QFN Mechanical Specifications
0.85 NOM.
/
0.9MAX. 0.00 / 0.005
0.20 REF.
SEATING
PLANE
SIDE VIEW
0.2 MIN.
0.35 / 0.45
1.5 / 1.875
3.0 / 3.75
0.18 / 0.3
BOTTOM VIEW
1
2
3
0.25
0.5
0.5
0.25
3.0 / 3.75
1.5 / 1.875
0.35 / 0.45
CHAMFERED
0.30
73M19 03 Data She e t DS_1903_032
38 Rev. 2.1
11.2 20-Pin TSSOP Mechanical Drawings
Dimensions i n mm.
Figure 16: 20-P in TSSOP Mech anic al Sp e ci f i cat io n s
DS_1903_032 73M1903 Da ta She e t
Rev. 2.1 39
12 Ordering Information
Table 22: Ordering Information
Part Description Order N umber Package Mark
73M19 03 3 2-Lead QF N Lead Free 73M1903-IM/F 73M1903-M
73M19 03 3 2-Lead QF N , Tap e and R eel, Lead F r ee 73M1903-IMR/F 73M1903-M
73M19 03 2 0-Lead TS SOP Lead F r ee 73M1903-IVT/F 73M190IVT
73M19 03 2 0-Lead TS SOP, Tape and Reel , Lead Fr ee 73M1903-IVTR/F 73M190IVT
73M19 03 Data She e t DS_1903_032
40 Rev. 2.1
Appendix A – 73M1903 DAA Resistor Calculation Guide
The following procedure is used to approximat e the c omponent values for t he D AA. Th e optimal values
will be s omewhat different due to the effects of the react ive components in the DAA ( this is a DC
approximation). Sim ul ati ons with the react i ve c ompon ents accurately modeled will yiel d optimal values .
The procedures for calculating the c omp onent values i n the DAA are as follows. F i r st set up R1. Th e
DAA shoul d be designed to reflect 600 Ω when looking in at TIP/RING. If the transformer is 1 to 1, the
holding coil and ring detect circuit are high impedance, Cblock is a high value so in the frequency band of
interest it is negligible, the sum of R2 and R3 is much greater than R1, and the output impedance of the
drivers dri ving TXAP/TXAN are low then:
Rin 2R1
.
RW Rohswitch 2Rbead
.
RW i s the sum of the win di ng r esist ance of b oth sides of the t r ansformer. Measure each side of the
t r ansformer with an Ohm met er and sum them.
Rohs witch is the on resis tance of the Off Hook Swit ch. M echanical R el ay swi tch es are ignored, but Solid
S tate Rel ays sometimes have an appr eciabl e on r esist ance.
Rbead is th e DC resist ance of what ever s er i es RF bloc king devic es may be in the design.
For Rin equal to 600 Ω:
R1 600 RW Rohswitch 2Rbead
.
2
To maximi ze THL (Trans-Hybrid Loss), or to minimize the amount of transmit signal that shows up back
on t he R eceive pins . The RXAP /RXAN pins get their DC bias from t he TX AP/TXAN pin s. By c ap acit iv ely
coupl ing the R3 res i stors with t he C1 caps, the DC offs et is minimiz ed from t he TXAP/TXAN to the
RXAP/ R XAN because the DC offset will be d ivid ed by th e r ati o of the R1 resist or s to the winding
res i stance on the one s i de of the t r ansformer.
Next make the s um of R2 + R3 m uch hig he r than 600 Ω. Make sure they are lower than the input
impedance of the R XAP/RXAN pi ns; other wis e they can move the frequency respon se of t he i nput fil ter.
S o let R 2 + R3 = 100 K.
DS_1903_032 73M1903 Da ta She e t
Rev. 2.1 41
R3 100 K
1Rwtot 600
1200
where
Rwtot RW Rohswitch 2Rbead
.
R2 100 KR3
Us e 1% resist or s for R1, R2, and R3.
To selec t the value for C1, mak e the z er o at around 10 Hz.
1
2π
.
100
.
KC1
.
10
C1 1
2π
.
100
.
K10
.
C1 0.15 uF
The bl ockin g cap Cbl ock should also have the same frequenc y res ponse, but due to t he low im pedance,
its value will be much higher, usually requiring a polarized cap. A blocking cap may also be needed on
the modem s id e of the t r ansformer if the D C of fs et cu r r ent of the t r ansmit pins will exceed the cu r r ent
rating for a dry transformer circuit.
Cblock 1
2π
.
600
.
10
.
Cblock 27 uF
I f you are usi ng a W et trans former des i gn, as in th e followin g figur e:
The only di fferenc e is that t he bl ock i ng capac it or , Cblock, it i s removed. Al l ot her equations sti l l hold true.
Trans-H ybrid Loss (THL)
Trans-Hybrid Loss is by definition the loss of transmit signal from Tip/Ring to the receive inputs on the
m odem IC. This definition is only valid when dri ving a specific phone l ine impedance. In real it y, phone
line impedanc es are never perfect, s o this defini tion isn’ t of muc h help. Inst ead, as an alt er nate definiti on
t hat hel ps in anal ysis for this modem design, THL is the loss from t he transmit pi ns to t he r eceive pins .
73M19 03 Data She e t DS_1903_032
42 Rev. 2.1
Appendix B – Crystal Oscillator
The crystal osci llator is designed t o operate over wid e choice of crystal s (from 9 MHz t o 27 MHz). The
cr ystal oscill ator output is input t o an N CO based pre-scaler ( di vider) prior to bei ng passed onto an on-
chi p PL L. The intent of the pre-s caler i s to convert t he crystal oscillator frequency, F xtal, t o a convenient
frequen cy to be used as a r eference frequency, Fref, for the PLL. A s et of t hr ee numb er s– Pdvsr (5 bit),
Prst (3 bit) and Pseq (8 bi t) mu st be en tered through the s er ial port as fol lows:
Pdvsr = Integ er [Fref/Fxtal];
P r st = Denominator of the ratio (Fref/ Fxtal ) minus 1 wh en it i s expr ess ed as a ratio of two small est
integers = N nco1/Dnc o1;
P seq = D i vide Sequenc e
Fxtal
mux count ctrl
overflow
Counter
Pdvsr
Pdvsr +1
Sequence
Register Rst
Sequence
Counter
Fref
Pseq[7:0] Prst[2:0]
Figure 17: NCO Block Diagr am
Note that in al l cas es, pr e-scaler should be designed such that pre-scaler output frequency, Fref, is in the
range of 2 ~ 4 MHz.
I n the first exam pl e bel ow, the exact divide ratio required is Fxtal/Fref = 15.625 =125/8. If a divide
sequence of {÷16,÷16,÷15,÷16,÷16,÷15,÷16,÷15 } is r epeated, th e effective di vide rati o wou l d be exac tly
15.625. Consequently, Pdvsr of 15, the length of the repeating pattern, Prst = 8 –1 =7, and the pattern,
{1,1,0,1,1,0,1,0}, where 0 means Pdvsr, or ÷15, and 1 means Pdvsr + 1, o r ÷16 must be entered as bel ow.
Example 1:
F xtal = 27 MHz, Fr ef = 1.728 MHz.
Pdvsr = Integer [Fxtal/Fref] = 15 =0Fh
Prst[2:0] = 8 – 1 = 7 from Fxtal/Fref = 15.625 =125/8;
Pseq = ÷16,÷16,÷15,÷16,÷16,÷15,÷16,÷15 => {1,1,0,1,1,0,1,0} =DAh.
In the second example, Fxta l/Fref =4.0. Thi s is a constant divide by 4 . Thus Pdvsr is 4, Prst = 1 –1
=0 and Pseq = {x,x,x,x,x,x,x,x).
DS_1903_032 73M1903 Da ta She e t
Rev. 2.1 43
Example 2:
Fxtal = 18.432 MHz, Fref = 2.304 MHz.
Pdvsr = Integer [Fxtal/Fref] = 8 = 8h;
Prst[2:0] = 1- 1 = 0 from Fref/Fxtal = 18.432/ 2. 304 = 8/1;
Pse q = {x,x,x,x,x,x,x, x} = xxh
Example 3:
Fxtal = 24.576 MHz, fref = 2. 4576 M Hz.
Pdvsr = Integer [ Fxtal/Fref] = 10 = Ah;
Prst[2:0] = 1- 1 = 0 from Fref/Fxtal = 24.576/2.4576 = 10/1;
Pse q = {x,x,x,x,x,x,x, x} = xxh
I t is also impor tant to not e that when Fxtal/F r ef i s an integer the outp ut of t he pr e-scaler i s a s trai ght
frequency divider (example 2). As such there will be no jitt er gener ated at Fr ef. However if Fxt al/ Fref is
a fractional nu m ber , F r ef, at t he output of the pr e-scaler N CO wou ld be exact onl y in an average s ense
(example 1) and there will be a certain amount of fixed pattern (r epeati ng) jitt er ass ociated wi th F r ef which
can be filtered out by the PLL that follows b y appropri ately progr amming the PLL. It is impor tant to not e,
howev er , that t he fixed pat tern j it ter does not degr ade the performance of the sigma delta modul ators so
long as its frequency is >> 4 kHz.
PLL
VCO
Kvco
NCO
Prescaler
PFD Charge
Pump
NCO
Kd
Up
Dn
R1
C1 C2 Divide
by 2/1
Ichp Control 33
Fref
Kvco Control
Figure 18: PLL Bl ock Diagram
1903B has a buil t in PLL circuit to allow an operation ov er wide range of Fs. It is of a conven ti onal design
with the exception of an NCO based feedback divider. See Figure 18. The architec ture of the 73m1903
dic tates that t he PLL output frequency, Fvc o, be rel ated to t he sampl i ng r ate, fs, by fvco = 2 x 2 304 x fs.
The nco must func tion as a divider wh ose divide rati o equal s Fr ef/Fvco.
Just as in the NCO pre-sc aler, a set of t hr ee numbers– Ndvsr (7 bit s), Nrst (3 bit ) and Nseq (8 bi ts )
mus t be entered through a s er i al p or t to effect t his di vide:
Ndvsr = Integer [ Fref/Fxtal ] ;
Nrst = denomin ator of the ratio ( Fvco/Fref), D nco1, minus 1, when it is expressed as a ratio of two
smallest integers = N nco1/Dnco1;
Ns eq = Divide Sequence
Example 1:
Fs = 7.2 kHz or Fvco = 2 x 2304 x 7.2 kHz =33.1776 MHz, Fr ef = 1.728 MHz.
Nd vsr = I nteger [ F vco/F ref ] = 19
Nrst = 5 – 1 = 4 from Fvco/Fref = 19.2 = 96/5;
Nseq = ÷19, ÷19, ÷19, ÷19, ÷20 => {0,0,0,0,1} =xxx00001 = 01h.
73M19 03 Data She e t DS_1903_032
44 Rev. 2.1
Example 2:
Fs = 8.0 kHz or Fvco = 2 x 2304 x 8 kHz =36.864 MHz, Fref = 2.304 MHz.
Ndvsr = Integer [Fvco/F r ef] = 16 = 10h;
Nrst= 1 -1 = 0 from Fvco/ Fref = 16/1;
N seq = {x,x,x,x,x,x,x,x} = xxh.
Example 3:
Fs = 9.6 kHz or Fvco = 2 x 2304 x 9.6 kHz =44.2368 MHz, Fr ef = 2.4576 MHz.
Ndvsr = Integer [Fvco/F r ef] = 18 = 16h;
Nrst= 1 -1 = 0 from Fvco/ Fref = 18/1;
N seq = {x,x,x,x,x,x,x,x} = xxh.
It is important to note th at in gener al t he N C O based feed back di vider will generate a fixed j it ter pattern
whos e frequency components ar e at F r ef/Accreset 2 and i ts integ er m ult i ples. Th e overall jitter frequenc y
will be a nonlin ear combi nation of jit ters from both pre-scaler and PLL N C O. The fundamental frequency
compon ent of this jitt er is at Fref/Prst/Nrst. The PLL paramet er s should be sel ect ed to remove this ji tter.
Three separate controls are provided to fine tune the PLL as shown in the following sections.
To ensu r e quick settli ng of PLL, a featur e w as des i gned in to the 73m1903 wher e Ic hp is kept at a higher
value until l okdet bec omes act i ve or F r cvco bi t is s et to 1, whichever occurs first. Thus PLL is guaranteed
t o have t he sett l in g time of less than one frame synch period after a new set of NCO paramet er s had
been wr i tten to t he appropr i ate registers. The ser i al port regist er writes for a par ticular sampl e r ate s houl d
be don e in sequence starti ng from r egister 08h endi ng i n r egister 0dh. 0dh register s houl d be the last one
to be written t o. This will be followed by a write to the next regi ster in sequence ( 0eh) to force t he
t r ansition of Sysc lk from X tal to Pllclk.
Upon the system r eset, the system clock is reset to Fxtal/9 . The s ys tem clock will remain at F xtal/9 unt il
the hos t forc es th e transition, but no s ooner the second frame syn ch period after the writ e to 0dh. When
t hi s happens, the syst em cl ock will transition to pllclk without any glitches through a specially designed
deglitch mux.
Examples of NCO Settings
Exampl e 1:
Crystal Frequency = 24.576 MHz; Desi r ed Sam pl ing Rat e, F s = 13.714 kHz(=2.4 kHz x 10/7 x 4)
S tep 1. F irs t c om pute the requir ed VC O frequenc y, Fvco, c or respondi ng to
Fs = 2.4 kHz x 10/7 x 4 = 13.714 kHz, or
Fvco = 2 x 2304 x Fs = 2 x 2304 x 2.4 kHz x 10/7 x 4 = 63.19543 MHz.
Step 2. Express the requi r ed VCO frequenc y divided by the Crystal F r equency as a ratio of two in tegers .
This is initially given by:
MHz
FxtalFvco 576.24 4 10/7 2.4kHz 2304 2
/••••
=
.
A fter a few rou nds of simpli fication this r ati o r educes to:
18
1
7
1
Dnco2
Nnco2
Dnco1
Nnco1
)
1
18
()
7
1
(
7
18
/
==
•==FxtalFvco
DS_1903_032 73M1903 Da ta She e t
Rev. 2.1 45
where N nco1 and Nnco2 mus t be < or equal t o 8.
The ratio, N nco1/ Dnco1 = 1/7, is us ed to form a di vide r atio for the NCO i n pr esc al er and N nco2/Dnco2 =
1/18 for the NCO in the PLL.
P r esc al er NCO: From N nco1/Dnco1 = 1/7,
Pdvsr = Integer [ D nco1/ N nco1 ] = 7;
P r st[ 2:0] = Nnco1 – 1 = 0; this means NO frac tional divide. It alw ays does ÷7. Thus Pseq bec om es
“don’t c ar e” and i s ignor ed.
Pse q = {x,x,x,x,x,x,x, x} = xxh.
PLL NCO: From Nnco2/Dnco2 = 1/18,
Nd vsr = Integer [ Dnco2/Nnco2 ] = 18;
Nrst[2:0] = Nnco2 – 1 = 0; this means NO frac tional divid e. It always does ÷18. Thus Pseq becom es
“don’t c ar e” and i s ignor ed.
N seq = {x,x,x,x,x,x,x,x} = xxh.
Example 2:
Crystal Frequency = 24.576 MHz; Desi r ed Sam pl ing Rat e, F s = 10.971 kHz=2.4 kHz x 8/7 x4
S tep 1. F irs t c om pute the requir ed VC O frequenc y, Fvco, c or respondi ng to
Fs = 2.4 kHz x 8/7 x 4 =10.971 kHz.
Fvco = 2 x 2304 x Fs = 2 x 2304 x 2.4 kHz x 8/7 x 4 = 50.55634 MHz.
Ste p 2. Express the required VCO frequency divided by the Crystal Freq uency as a ratio of two in tegers.
This is initially given by:
MHz
FxtalFvco 576.24 4 8/7 2.4kHz 2304 2
/••••
=
.
A fter a few rou nds of simplifi cat ion t hi s ratio r educes to:
18
1
35
4
Dnco2
Nnco2
Dnco1
Nnco1
)
1
18
()
35
4
(/
==
•=FxtalFvco
, wh er e Nnco1 and Nn co2 must be < or equal to 8.
The ratio, N nco1/ Dnco1 = 4/35, is used to form a di vide r atio for the NCO i n pr e-s caler and N nco2/ Dnco2
=1/18 for the NCO in the PLL.
Pre-scaler NCO: From Nnco1/Dnco1 = 4/35,
Pdvsr = Integer [ Dnco1/Nnco1 ] = 8;
P r st[ 2:0] = Nnco1 – 1 = 3;
Dnco1/Nnco1 = 35/4 = 8.75 suggests a divide s equence of {÷9,÷9,÷9,÷8}, or
Pseq = {x,x,x,x,1,1,1,0} = xDh.
PLL NCO: From Nnco2/Dnco2 = 1/18,
Nd vsr = Integer [ Dnco2/Nnco2 ] = 18;
Nrst[2:0] = Nnco2 – 1 = 0; this means NO frac tional divid e. It always does ÷18. Thus Pseq becom es
“don’t c ar e” .
Ns eq = {x,x,x, x,x,x,x,x} = xxh.
73M19 03 Data She e t DS_1903_032
46 Rev. 2.1
Example 3:
Crystal Frequency = 27 MHz; Desired Sampling Rate, Fs = 7.2 kHz
S tep 1. F irs t c om pute the requir ed VC O frequenc y, Fvco, c or respondi ng to
Fs = 2.4 kHz x 3 = 7.2 kHz.
Fvco = 2 x 2304 x Fs = 2 x 2304 x 2.4 kHz x 3 = 33.1776 MHz.
Step 2. Express the requi r ed VCO frequenc y divided by the Crystal F r equency as a ratio of two in tegers .
This is initially given by:
MHz
FxtalFvco 27 3 2.4kHz 2304 2
/•••
=
.
A fter a few rou nds of simpli fication this r educes to:
96
5
125
8
Dnco2
Nnco2
Dnco1
Nnco1
)
5
96
()
125
8
(/
==
•=FxtalFvco
The two r atios are not uni que and many oth er poss ib iliti es exist. B ut for this particular applic ati on, they
are foun d to be the bes t set of c hoices withi n the c onstraints of Prst and N r st allowed. ( N nco1, Nnco2
mus t be less than or equal to 8.)
The ratio, N nco1/ Dnco1 = 8/125, is us ed to form a di vide r atio for the NCO i n pr escaler and Nnco2/ D nco2
=5/96 for the NCO in the PLL.
Pre-scaler NCO: From Nnco1/Dnco1 = 8/125,
P dvs r = Integer [ Dnco1/ Nn co1 ] = 15;
P r st[ 2:0] = Nnco1 – 1 = 7;
Dnco1/Nnco1 = 125/8 = 15.625 su ggests a di vide sequen ce of {÷16,÷16,÷15,÷16,÷16,÷15,÷16,÷15 } , or
Pseq = {1,1,0,1,1,0,1,0} = DAh.
PLL NCO: From Nnco2/Dnco2 = 5/96,
Ndvsr = Integer [ Dnco2/Nnco2 ] = 19;
Nrst[2:0] = Nnco2 – 1 = 4;
Dnco2/Nnco2 = 19.2 suggests a divide sequence of {÷19, ÷19, ÷19, ÷19, ÷20}, or
Nseq = {x,x,x,0,0,0,0,1} = x1h.
DS_1903_032 73M1903 Da ta She e t
Rev. 2.1 47
Rev isi on Histor y
Rev. #
Date
Comments
1.0 4/16/2004 First p ublication.
1.1 12/13/2004 Minor format modi fi cat ion.
1.2 7/15/2005 Company log o change and minor format modification.
1.4 9/14/2006 Correct ed QF N pin-o ut dr a wing.
1.5 5/23/2007 Added 20-VT pack age i nformat i on.
1.6 12/14/2007 C hanged 32-QFN from pu nched to SAWN.
Removed t he lead ed pack age option.
1.7 1/17/2008 Ch anged the bottom view package di mensi on for 32-QFN p ackage.
2.0 2/23/2009 Removed al l ref erences t o the 32-pin TQFP package.
Format ted to th e new cor por ate s tandard.
2.1 3/9/2010 Added the schemati c and bil l of materials in Section 10.
Format ted to th e new cor por ate s tandard.
© 20 10 Teridian Semic onduct or Corporation. All r i ghts res er ved.
Teridian Semiconduc tor C or por ation is a r egi stered t r ademark of Teridian Semic onduct or Corporation.
S impli fying System Int egr ation i s a trademark of Teridian Semiconductor C or por ation.
MicroDAA i s a registered t r ademark of T er i dian S emic onductor Cor porati on.
A ll other trademar ks ar e the proper ty of their r espec tive owners.
Teridian Semiconduc tor C or por ation makes no warran ty fo r the us e of its products, ot her than exp r essly
contained i n the C om pany’s warranty d etailed in the Teridian Semi conductor Corporation st andar d Terms
and Conditions. The company assumes no r esponsibility for any errors which may appear in this
documen t, reserves the right to change devices or specificati ons det ai led herein at any ti me without
not i ce and does not make any commitment to update the information cont ained herein. Accordin gl y, th e
reader i s cauti oned to verify that th is document is curr ent by com par i ng i t to the latest vers ion on
http://www.teridian.com or by chec king wit h your sales r epr esentat ive.
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