1
®
FN6406.0
ISL59910, ISL59913
Triple Differential Receiver/Equalizer
The ISL59910 and ISL59913 are triple chann el differential
receivers and equalizers. They each con tain three high speed
differentia l recei vers with five programmable poles. The
output s of these po le blocks are then summed into an output
buffer. The equalization length is set with the volt age on a
single pin. The ISL59 910 and ISL59913 output can also b e
put into a high impedance st ate, enab ling multiple devices to
be connected in pa ral lel and use d in multiplexing ap plication.
The gain can be adjusted up or down on each channel by 6dB
using its VGAIN control signal. In addition, a further 6dB of gain
can be switched in to provide a matched drive into a cable.
The ISL59910 and ISL59913 have a bandwidth of 150MHz
and consume just 108mA on ±5V supply. A si ngle input
voltage is used to set the compensation levels for the
required length of cable.
The ISL59910 is a special version of the ISL 59913 that
decodes syncs encoded onto the common modes of three
pairs of CAT-5 cable by the EL4543. (Refer to the EL4543
datasheet for details.)
The ISL59910 and ISL59913 are available in a 28 Ld QFN
package and are specified for operation over the full -40°C to
+85°C temperature range.
Features
150MHz -3dB bandwidth
CAT-5 compensation
- 100MHz @ 600 ft
- 135MHz @ 300 ft
108mA supply curren t
Differential input range 3.2V
Common mode input range -4V to +3.5V
±5V supply
Output to within 1.5V of supplies
Available in 28 Ld QFN package
Pb-free plus anneal available (RoHS compliant)
Applications
Twi sted-pair receiving/equalizer
KVM (Keyboard/Video/Mouse)
VGA over twisted-pair
Security video
Pinouts ISL59910
(28 LD QFN)
TOP VIEW
ISL59913
(28 LD QFN)
TOP VIEW
THERMAL
PAD
22
21
20
19
18
17
16
28
27
26
25
24
9
10
11
12
13
1
2
3
4
5
6
7
VSMO_B
VOUT_B
VSPO_B
VSPO_G
VOUT_G
VSMO_G
VSMO_R
VSP
VINM_B
VINP_B
VINM_G
VINP_G
VINM_R
VINP_R
0V
ENABLE
X2
SYNCREF
VOUT
VSPO_R
VCTRL
VREF
VGAIN_R
VGAIN_G
815
14 23
VSM
VGAIN_B
VOUT_R
HOUT
THERMAL
PAD
22
21
20
19
18
17
16
28
27
26
25
24
9
10
11
12
13
1
2
3
4
5
6
7
VSMO_B
VOUT_B
VSPO_B
VSPO_G
VOUT_G
VSMO_G
VSMO_R
VSP
VINM_B
VINP_B
VINM_G
VINP_G
VINM_R
VINP_R
0V
ENABLE
X2
VCM_B
VCM_G
VSPO_R
VCTRL
VREF
VGAIN_R
VGAIN_G
815
14 23
VSM
VGAIN_B
VOUT_R
VCM_R
Data Sheet
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
December 15, 2006
EXPOSED DIEPLATE SHOULD BE CONNECTED TO -5V
2FN6406.0
December 15, 2006
Ordering Information
PART
NUMBER PART
MARKING TAPE & REEL PACKAGE PKG.
DWG. #
ISL59910IRZ
(Note) 59910 CRZ - 28 Ld QFN
(Pb-free) MDP0046
ISL59910IRZ-T7
(Note) 59910 CRZ 7” 28 Ld QFN
(Pb-free) MDP0046
ISL59913IRZ
(Note) 59913 CRZ - 28 Ld QFN
(Pb-free) MDP0046
ISL59913IRZ-T7
(Note) 59913 CRZ 7” 28 Ld QFN
(Pb-free) MDP0046
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
ISL59910, ISL59913
3FN6406.0
December 15, 2006
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise not ed, all tests are
at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Absolute Maximum Ratings (TA = +25°C) Operating Conditions
Supply Voltage between VS+ and VS-. . . . . . . . . . . . . . . . . . . . .12V
Maximum Continuous Output Current per Channel. . . . . . . . . 30mA
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Pin Voltages. . . . . . . . . . . . . . . . . . . . . . . . . VS- -0.5V to VS+ +0.5V
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Die Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operat i onal sections of this specification is not implied.
Electrical Specifications VSA+ = VA+ = +5V, VSA- = VA- = -5V, TA = +25°C, exposed die plate = -5V, unless otherwise specified.
PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT
AC PERFORMANCE
BW Bandwidth (See Figure 1) 150 MHz
SR Slew Rate VIN = -1V to +1V, VG = 0.39, VC = 0,
RL = 75 + 75Ω
1.5 kV/µs
THD Total Harmonic Distortion 10MHz 2VP-P out, VG = 1V, X2 gain, VC = 0 -50 dBc
DC PERFORMANCE
V(VOUT)OS Offset Voltage X2 = high, no equalization -110 -15 +110 mV
ΔVOS Channel-to-Channel Offset Matching X2 = high, no equalization -140 0 +140 mV
INPUT CHARACTERISTICS
CMIR Common-Mode Input Range -4/+3.5 V
ONOISE Output Noise VG = 0V , VC = 0V, X2 = HIGH, RLOAD = 150Ω,
Input 50Ω to GND, 10MHz -110 dBm
CMRR Common-Mode Rejection Ratio Measured at 10kHz -80 dB
CMRR Common-Mode Rejection Ratio Measured at 10MHz -55 dB
CMBW CM Amplifier Bandwidth 10k || 10pF load 50 MHz
CMSLEW CM Slew Rate Measured @ +1V to -1V 100 V/µs
CINDIFF Differential Input Capacitance Capacitance VINP to VINM 600 fF
RINDIFF Differential Input Resistance Resistance VINP to VINM 1MΩ
CINCM CM Input Capacitance Capacitance VINP = VINM to GND 1.2 pF
RINCM CM Input Resistance Resistance VINP = VINM to GND 1 MΩ
+IIN Positive Input Current DC bias @ VINP = VINM = 0V 1 µA
-IIN Negative Input Current DC bias @ VINP = VINM = 0V 1 µA
VINDIFF Differential Input Range VINP - VINM when slope gain falls to 0.9 2.5 V
OUTPUT CHARACTERISTICS
V(VOUT) Output Voltage Swing RL = 150Ω±3.5 V
I(VOUT) Output Drive Current RL = 10Ω, VINP = 1V, VINM = 0V, X2 = high,
VG = 0.39 50 60 mA
R(VCM) CM Output Resistance of
VCM_R/G/B (ISL59913 only) at 100kHz 30 Ω
Gain Gain VC = 0, VG = 0.39, X2 = 5, RL = 150Ω0.85 1.0 1.1
ΔGain @ DC Channel-to-Channel Gain Matching VC = 0, VG = 0.39, X2 = 5, RL = 150Ω38%
ΔGain @
15MHz Channel-to-Channel Gain Matching VC = 0.6, VG = 0.39, X2 = 5, RL = 150Ω,
Frequency = 15MHz 311%
V(SYNC)HI High Level output on V/HOUT
(ISL59910 only) V(VSP)
- 0.1V V(VSP)
ISL59910, ISL59913
4FN6406.0
December 15, 2006
V(SYNC)LO Low Level output on V/HOUT
(ISL59910 only) V(SYNC
REF) V(SYNC
REF)
+ 0.1V
SUPPLY
ISON Supply Current per Channel VENBL = 5, VINM = 0 323639mA
ISOFF Supply Current per Channel VENBL = 0, VINM = 0 0.2 0.4 mA
PSRR Power Supply Rejection Ratio DC to 100kHz, ±5V supply 65 dB
LOGIC CONTROL PINS (ENABLE, X2)
VHI Logic High Level VIN - VLOGIC ref for guaranteed high level 1.4 V
VLOW Logic Low Level VIN - VLOGIC ref for guaranteed low level 0.8 V
ILOGICH Logic High Input Current VIN = 5V, VLOGIC = 0V 50 µA
ILOGICL Logic Low Input Current VIN = 0V, VLOGIC = 0V 15 µA
Electrical Specifications VSA+ = VA+ = +5V, VSA- = VA- = -5V, TA = +25°C, exposed die plate = -5V, unless otherwise specified.
PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT
Pin Descriptions
PIN
NUMBER
ISL59910 ISL59913
PIN NAME PIN FUNCTION PIN NAME PIN FUNCTION
1 VSMO_B -5V to blue output buffer VSMO_B -5V to blue output buffer
2 VOUT_B Blue output voltage referenced to 0V pin VOUT_B Blue output voltage referenced to 0V pin
3 VSPO_B +5V to blue output buffer VSPO_B +5V to blue output buffer
4 VSPO_G +5V to green output buffer VSPO_G +5V to green output buffer
5 VOUT_G Green output voltage referenced to 0V pin VOUT_G Green output voltage referenced to 0V pin
6 VSMO_G -5V to green output buffer VSMO_G -5V to green output buffer
7 VSMO_R -5V to red output buffer VSMO_R -5V to red output buffer
8 VOUT_R Red output voltage referenced to 0V pin VOUT_R Red output voltage referenced to 0V pin
9 VSPO_R +5V to red output buffer VSPO_R +5V to red output buffer
10 VCTRL Equalization control voltage (0V to 0.95V) VCTRL Equalization control voltage (0V to 0.95V)
11 VREF Reference voltage for logic signals, VCTRL and
VGAIN pins VREF Reference voltage for logic signals, VCTRL and
VGAIN pins
12 VGAIN_R Red channel gain voltage (0V to 1V) VGAIN_R Red channel gain voltage (0V to 1V)
13 VGAIN_G Green channel gain voltage (0V to 1V) VGAIN_G Green channel gain voltage (0V to 1V)
14 VGAIN_B Blue channel gain voltage (0V to 1V) VGAIN_B Blue channel gain voltage (0V to 1V)
15 VSM -5V to core of chip VSM -5V to core of chip
16 VINP_R Red positive differential input VINP_R Red positive differential input
17 VINM_R Red negative differential input VINM_R Red negative differential input
18 VINP_G Green positive differential input VINP_G Green positive differential input
19 VINM_G Green negative differential input VINM_G Green negative differential input
20 VINP_B Blue positive differential input VINP_B Blue positive differential input
21 VINM_B Blue negative differential input VINM_B Blue negative differential input
22 VSP +5V to core of chip VSP +5V to core of chip
23 HOUT Decoded Horizontal sync referenced to
SYNCREF VCM_R Red common-mode voltage at inputs
24 VOUT Decoded Vertical sync referenced to SYNCREF VCM_G Green common-mode voltage at inputs
25 SYNCREF Reference level for HOUT and VOUT logic outputs VCM_B Blue common-mode voltage at inputs
ISL59910, ISL59913
5FN6406.0
December 15, 2006
26 X2 Logic signal for x1/x2 output gain setting X2 Logic signal for x1/x2 output gain setting
27 ENABLE Chip enable logic signal ENABLE Chip enable logic signal
28 0V 0V reference for output voltage 0V 0V reference for output voltage
Thermal Pad Must be connected to -5V
Pin Descriptions (Continued)
PIN
NUMBER
ISL59910 ISL59913
PIN NAME PIN FUNCTION PIN NAME PIN FUNCTION
Typical Performance Curves
FIGURE 1. FREQUENCY RESPONSE OF ALL CHANNELS FIGURE 2. GAIN vs FREQUENCY ALL CHANNELS
FIGURE 3. GAIN vs FREQUENCY FOR VARIOUS VCTRL FIGURE 4. GAIN vs FREQUENCY FOR V ARIOUS VCTRL AND
VGAIN
1M 10M 100M 200M
5
3
1
-1
-3
-5
X2=LOW
VGAIN=0V
VCTRL=0V
RLOAD=150
FREQUENCY (Hz)
GAIN (dB)
X2=HIGH
VGAIN=0.35V
VCTRL=0V
RLOAD=150Ω
X2=LOW
VS=±5V
RL=150Ω
VGAIN=0V
VCTRL=0.1V STEP S
Source=-20dBm
VCTRL=0V
VCTRL=1V X2=LOW
VS=±5V
RL=150Ω
Source=-20dBm
VCTRL=0V
VGAIN=0V
VCTRL=0.25V
VGAIN=0.25V
VCTRL=0V
VGAIN=0.25V
ISL59910, ISL59913
6FN6406.0
December 15, 2006
FIGURE 5. GAIN vs FREQUENCY FOR V ARIOUS VCTRL AND
CABLE LENGTHS FIGURE 6. CHANNEL MISMATCH
FIGURE 7. OFFSET vs VCTRL FIGURE 8. DC GAIN vs VGAIN
FIGURE 9. HARMONIC DISTORTION vs FREQUENCY FIGURE 10. OUTPUT NOISE
Typical Performance Curves (Continued)
X2=LOW
VS=±5V
RL=150Ω
VGAIN=1V
SOURCE=-20dBm
VCTRL=1V
CABLE=3FT
VCTRL=0V
CABLE=600FT
VCTRL=0V
CABLE=3FT
VCTRL=1V
CABLE=600FT
X2=LOW
VGAIN=0.5V
VCTRL=0.5V
RLOAD=150Ω
VS=±5V, RL=150Ω
INPUT 50Ω TO GROUND
X2=LOW
X2=HIGH
X2=LOW
VCTRL=0V
X2=HiGH
VCTRL=0V
VGAIN=1V
VCTRL=0V
RLOAD=150Ω
INPUT=50Ω TO GND
X2=HIGH
VS=±5V
RL=150Ω
VCTRL=0V
VGAIN=1V
2nd
HAMONIC
3rd
HARMONIC
TOT AL
HARMONIC
X2=HIGH
VS=±5V
RL=150Ω
INPUT=50Ω TO GROUND
VCTRL=0V
VGAIN=0V
VCTRL=1V
VGAIN=0V
VCTRL=0V
VGAIN=1V
VCTRL=1V
VGAIN=1V
ISL59910, ISL59913
7FN6406.0
December 15, 2006
FIGURE 11. COMMON-MODE REJECTION FIGURE 12. CM AMPLIFIER BANDWIDTH
FIGURE 13. (+)PSRR vs FREQUENCY FIGURE 14. (-)PSRR vs FREQUENCY
FIGURE 15. BLUE CROSSTALK (CABLE LENGTH = 3ft.) FIGURE 16. BLUE CROSSTALK (CABLE LENGTH = 600ft.)
Typical Performance Curves (Continued)
100k 1M 10M 100M
-10
-20
-40
-60
-80
-100
VGAIN=0.35V
(ALL CHANNELS)
VCTRL=0V
X2=HIGH
FREQUENCY (Hz)
CMRR (dB)
100k 1M 10M 100M
4
2
0
-2
-4
-6
VGAIN=0.35V
(ALL CHANNELS)
VCTRL=0V
RLOAD=150Ω
X2=HIGH
FREQUENCY (Hz)
GAIN (dB)
10 1k 100k 100M
0
-20
-40
-60
-80
-100
VCC=5V
VCTRL=0V
VGAIN=0V
(ALL CHANNELS)
INPUTS ON GND
FREQUENCY (Hz)
+PSRR (dB)
100 10k 1M 10M 10 1k 100k 100M
-20
-40
-60
-80
-100
-120
VEE=-5V
VCTRL=0V
VGAIN=0V
(ALL CHANNELS)
INPUTS ON GND
FREQUENCY (Hz)
-PSRR (dB)
100 10k 1M 10M
X2=LOW
VS=±5V
RL=150Ω
VCTRL=1V
VGAIN=1V
BLUE
RED
GREEN
ISL59910, ISL59913
8FN6406.0
December 15, 2006
FIGURE 17. GREEN CROSSTALK (CABLE LENGTH = 3ft.) FIGURE 18. GREEN CROSSTALK (CABLE LENGTH = 600ft.)
FIGURE 19. RED CROSSTALK (CABLE LENGTH = 3ft.) FIGURE 20. RED CROSSTALK (CABLE LENGTH =600ft.)
FIGURE 21. RISE TIME AND FALL TIME FIGURE 22. PULSE RESPONSE FOR VARIOUS CABLE
LENGTHS
Typical Performance Curves (Continued)
X2=LOW
VS=±5V
RL=150Ω
VCTRL=1V
VGAIN=1V
BLUE
RED
GREEN
X2=LOW
VS=±5V
RL=150Ω
VCTRL=1V
VGAIN=1V
BLUE
RED
GREEN
X2=HIGH
VS=±5V
RL=150Ω
VGAIN=0V
INPUT=10MHz
VCTRL=0V
CABLE=3FT VCTRL=0.2V
CABLE=600FT
ISL59910, ISL59913
9FN6406.0
December 15, 2006
Applications Information
Logic Control
The ISL59913 has two logical input pins, Chip Enable
(ENABLE) and Switch Gain (X2). The logic circuits all have a
nominal threshold of 1.1V above the potential of the logic
reference pin (VREF). In most applications it is expected that
this chip will run from a +5V, 0V, -5V supply system with logic
being run between 0V and +5V. In this case the logic
reference voltage should be tied to the 0V supply. If the logic
is referenced to the -5V rail, then the logic reference should
be connected to -5V. The logic reference pin sources about
60µA and this will rise to about 200µA if all inputs are true
(positive).
The logic inputs all source up to 10µA when they are held at
the logic reference level. When taken positive, the inputs
sink a current dependent on the high level, up to 50µA for a
high level 5V above the refe rence level.
The logic inputs, if not used, should be tied to the
appropriate voltage in order to define their state.
Control Reference an d Signal Reference
Analog control voltages are required to set the equalizer and
contrast levels. These signals are voltages in the range
0V to 1V , which are referenced to the control reference pin. It
is expected that the control reference pin will be tied to 0V
and the control voltage will vary from 0V to 1V. It is; however ,
acceptable to connect the control reference to any potential
between -5V and 0V to which the control voltages are
referenced.
The control voltage pins themse lves are high impedance.
The control reference pin will source between 0µA and
200µA depending on the control voltages being applied.
The control reference and logic reference ef fectively remove
the necessity for the 0V rail and operation from ±5V (or 0V
and 10V) only is possible. However we sti ll need a furthe r
reference to define the 0V level of the sin gle en ded outp ut
signal. The reference for the outp ut signal is provided by the
0V pin. The output st age cannot pul l fully up or down to e ither
supply so it is import ant that the reference is position ed to
allow full output swing. The 0V reference should be tied to a
'quiet ground' as any noise on this pin is transferred directly to
the output. The 0V pin is a high impedance pin and draws DC
bias currents of a few µ A and similar level s of AC current.
Equalizing
When transmitting a signal across a twisted pair cable, it is
found that the high frequency (above 1MHz) information is
attenuated more significantly than the information at low
frequencies. The attenuation is predominantly due to resistive
skin effect losses and has a loss curve which depends on the
resistivity of the conductor , surface condition of the wire and the
wire diameter . For the range of high performance twisted pair
cables based on 24awg copper wire (CAT -5 etc). These
parameters vary only a little between cable types and in general
cables exhibit the same frequency dependence of loss. (The
lower loss cables can be compared with somewhat longer
lengths of their more lossy brothers.) This enables a single
equalizing law equation to be built into the ISL59913.
With a control voltage applied between pins VCTRL and
VREF, the frequency dependence of the equali z ation is
shown in Figure 8. The equalization matches the cable loss
up to about 100MHz. Above this, system gain is rolled off
rapidly to reduce noise bandwidth. The roll-off occurs more
rapidly for higher control voltages, thus the system (cable +
equalizer) bandwidth reduces as the cable length increases.
This is desirable, as noise becomes an increasing issue as
the equalization increases.
Typical Performance Curves (Continued)
FIGURE 23. P ACKAGE POWER DISSIPA TION vs AMBIENT
TEMPERATURE FIGURE 24. P ACKAGE POWER DISSIP ATION vs AMBIENT
TEMPERATURE
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD - QFN EXPOSED
DIEPAD SOLDERED TO PCB PER JESD51-5
θ
JA
=37°C/W
QFN28
3.378W
0 50 85 150
4.5
3.5
2.5
1.5
0.5
0
AMBIENT TEMPERATURE (°C)
POWER DISSIPATION (W)
25 75 100 125
4
2
1
3
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
893mW
θ
JA
=140°C/W
QFN28
0 50 85 150
1.2
0.8
0.6
0.4
0.2
0
AMBIENT TEMPERATURE (°C)
POWER DISSIPATION (W)
25 75 100 125
1
ISL59910, ISL59913
10 FN6406.0
December 15, 2006
Contrast
By varying the voltage betwee n pins VGAIN and VREF, the
gain of the signal path can be chang ed in the ratio 4:1. The
gain change varies almost linearly with control volt age. For
normal operation it is antici pated the X2 mode wil l be selected
and the output load will be ba ck ma tched. A unity gai n to the
output load will then be achieved with a gain control voltage of
about 0.35V. This allows the gain to be trimmed up or down by
6dB to compensate for any gain/loss errors that af fect the
contrast of the video signal. Figure 26 shows an e xample plot
of the gain to the load with gain control voltage.
Common Mode Sync Decoding
The ISL59910 features common mode decoding to allow
horizont al and vertical synchronization informa tion, which has
been encoded on the three dif ferential input s by th e EL4543,
to be decoded. The entire RG B video sig nal can therefore be
transmitted, along with the associated synchronization
information, by using just three twisted pairs.
Decoding is based on the EL4543 encoding scheme, as
described in Figure 26 and Table 1. The scheme is a three-level
system, which has been designed such that the sum of the
common mode voltages results in a fixed average DC level with
no AC content. This eliminates the effect of EMI radiation into
the common mode signals along the twisted pairs of the cable
The common mode voltages are initially extracted by the
ISL59910 from the three input pairs. These are then passed to
an internal logic decoding block to provide Horizontal and
Vertical sync output signals (HOUT and VOUT).
Power Dissipation
The ISL59910 and ISL59913 are designed to operate with
±5V supply voltages. The supply currents are tested in
production and guaranteed to be less th an 39mA per
channel. Operating at ±5V power supply, the total power
dissipation is:
where:
•PD
MAX = Maximum power dissipation
•V
S = Supply voltage = 5V
•I
MAX = Maximum quiescent supply current per
channel = 39mA
•V
OUTMAX = Maximum output voltage swing of the
application = 2V
RL = Load resistance = 150Ω Ω
θJA required for long term reliable operation can be
calculated. This is done using Equation 3:
00.8
VGAIN
0.4 1
2
1.8
1.4
1
0.6
0.4
GAIN (V)
0.60.2
1.6
1.2
0.8
FIGURE 25. V ARIATION OF GAIN WITH GAIN CONTROL
VOLTAGE
TABLE 1. H AND V SYNC DECODING
RED CM GREEN CM BLUE CM HSYNC VSYNC
Mid High Low Low Low
High Low Mid Low High
Low High Mid High Low
Mid Low High High High
NOTE: Level ‘Mid’ is halfway between ‘High’ and ‘Low’
TIME (0.5ms/DIV)
VOLTAGE
(0.5V/DIV)
BLUE CM
OUT (CH A)
GREEN CM
OUT (CH B)
RED CM
OUT (CH C)
VSYNC
HSYNC
VOLTAGE
(2.5V/DIV)
FIGURE 26. H AND V SYNCS ENCODED
PDMAX 32V
S
×ISMAX VS
( - VOUTMAX)VOUTMAX
RL
----------------------------
×+××=
(EQ. 1)
PDMAX 1.29W=(EQ. 2)
ISL59910, ISL59913
11
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No lice nse is gran t ed by i mpli catio n or other wise u nder an y p a tent or patent rights of I nter sil or it s sub sidi aries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6406.0
December 15, 2006
Where
Tj is the maximum junction temperature (+150°C)
Ta is the maximum ambient temperature (+85°C)
For a QFN 28 package in a properly layout PCB heatsinking
copper area, +37°C/W θJA thermal resistance can be
achieved. To disperse the heat, the bottom heatspreader
must be soldered to the PCB. Heat flows through the
heatspreader to the circuit board copper then spreads and
converts to air. Thus the PCB copper plane becomes the
heatsink. This has proven to be a very effective technique. A
separate application note details the 28 Ld QFN. PCB
design considerations are available.
θJA Tj Ta()
PD
-----------------------
=50.4CW=(EQ. 3)
ISL59910, ISL59913
12 FN6406.0
December 15, 2006
ISL59910, ISL59913
QFN (Quad Flat No-Lead) Package Family
PIN #1
I.D. MARK
2
1
3
(N-2)
(N-1)
N
(N/2)
2X
0.075
TOP VI EW
(N/2)
NE
2
3
1
PIN #1 I.D.
(N-2)
(N-1)
N
b
L
N LEADS
BOTTOM VIEW
DETAIL X
PLANE
SEATING
N LEADS
C
SEE DETAIL "X"
A1 (L)
N LEADS
& EXPOSED PAD
0.10
SIDE VIEW
0.10 BA
MC
C
B
A
E
2X
0.075 C
D
3
5
7
(E2)
(D2)
e
0.08 C
C
(c)
A2
C
MDP0046
QFN (QUAD FLAT NO-LEAD) PACKAGE FAMILY
(COMPLIANT TO JEDEC MO-220)
SYMBOL QFN44 QFN38 QFN32 TOLERANCE NOTES
A 0.90 0.90 0.90 0.90 ±0.10 -
A1 0.02 0.02 0.02 0.02 +0.03/-0.02 -
b 0.25 0.25 0.23 0.22 ±0.02 -
c 0.20 0.20 0.20 0.20 Reference -
D 7.00 5.00 8.00 5.00 Basic -
D2 5.10 3.80 5.80 3.60/2.48 Reference 8
E 7.00 7.00 8.00 6.00 Basic -
E2 5.10 5.80 5.80 4.60/3.40 Reference 8
e 0.50 0.50 0.80 0.50 Basic -
L 0.55 0.40 0.53 0.50 ±0.05 -
N 44 38 32 32 Reference 4
ND 11 7 8 7 Reference 6
NE 11 12 8 9 Reference 5
SYMBOL QFN28 QFN24 QFN20 QFN16 TOLER-
ANCE NOTES
A 0.90 0.90 0.90 0.90 0.90 ±0.10 -
A1 0.02 0.02 0.02 0.02 0.02 +0.03/
-0.02 -
b 0.25 0.25 0.30 0.25 0.33 ±0.02 -
c 0.20 0.20 0.20 0.20 0.20 Reference -
D 4.00 4.00 5.00 4.00 4.00 Basic -
D2 2.65 2.80 3.70 2.70 2.40 Reference -
E 5.00 5.00 5.00 4.00 4.00 Basic -
E2 3.65 3.80 3.70 2.70 2.40 Reference -
e 0.50 0.50 0.65 0.50 0.65 Basic -
L 0.40 0.40 0.40 0.40 0.60 ±0.05 -
N 28 24 20 20 16 Reference 4
ND 6 5 5 5 4 Reference 6
NE 8 7 5 5 4 Reference 5
Rev 10 12/04
NOTES:
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Tiebar view show n is a non-functional feature.
3. Bottom-side pin #1 I.D. is a diepad chamfer as shown.
4. N is the total number of terminals on the device.
5. NE is the number of terminals on the “E” side of the package
(or Y-direction).
6. ND is the number of terminals on the “D” side of the package
(or X-direction). ND = (N/2)-NE.
7. Inward end of terminal may be square or circular in shape with radius
(b/2) as shown.
8. If two values are listed, multiple exposed pad options are available.
Refer to device-specific datasheet.