TLC2654, TLC2654A
Advanced LinCMOS LOW-NOISE CHOPPER-STABILIZED
OPERATIONAL AMPLIFIERS
SLOS020G – NOVEMBER 1988 – REVISED APRIL 2001
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Input Noise Voltage
0.5 µV (Peak-to-Peak) Typ, f = 0 to 1 Hz
1.5 µV (Peak-to-Peak) Typ, f = 0 to 10 Hz
47 nV/√Hz Typ, f = 10 Hz
13 nV/√Hz Typ, f = 1 kHz
D
High Chopping Frequency . . . 10 kHz Typ
D
No Clock Noise Below 10 kHz
D
No Intermodulation Error Below 5 kHz
D
Low Input Offset Voltage
10 µV Max (TLC2654A)
D
Excellent Offset Voltage Stability
With Temperature . . . 0.05 µV/°C Max
D
AVD . . . 135 dB Min (TLC2654A)
D
CMRR...110 dB Min (TLC2654A)
D
kSVR ...110 dB Min
D
Single-Supply Operation
D
Common-Mode Input Voltage Range
Includes the Negative Rail
D
No Noise Degradation With External
Capacitors Connected to VDD–
D
Available in Q-Temp Automotive
HighRel Automotive Applications
Configuration Control/Print Support
Qualification to Automotive Standards
description
The TLC2654 and TLC2654A are low-noise
chopper-stabilized operational amplifiers using
the Advanced LinCMOS process. Combining
this process with chopper-stabilization circuitry
makes excellent dc precision possible. In addition,
circuit techniques are added that give the
TLC2654 and TLC2654A superior noise perfor-
mance.
Chopper-stabilization techniques provide for extremely high dc precision by continuously nulling input offset
voltage even during variations in temperature, time, common-mode voltage, and power-supply voltage. The
high chopping frequency of the TLC2654 and TLC2654A (see Figure 1) provides excellent noise performance
in a frequency spectrum from near dc to 10 kHz. In addition, intermodulation or aliasing error is eliminated from
frequencies up to 5 kHz.
This high dc precision and low noise, coupled with the extremely high input impedance of the CMOS input stage,
makes the TLC2654 and TLC2654A ideal choices for a broad range of applications such as low-level,
low-frequency thermocouple amplifiers and strain gauges and wide-bandwidth and subsonic circuits. For
applications requiring even greater dc precision, use the TLC2652 or TLC2652A devices, which have a
chopping frequency of 450 Hz.
Copyright 2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
Advanced LinCMOS is a trademark of Texas Instruments.
1
2
3
4
8
7
6
5
CXA
IN–
IN+
VDD–
CXB
VDD+
OUT
CLAMP
D, JG, OR P PACKAGE
1
2
3
4
5
6
7
14
13
12
11
10
9
8
CXB
CXA
NC
IN–
IN+
NC
VDD–
INT/EXT
CLK IN
CLK OUT
VDD+
OUT
CLAMP
C RETURN
D, J, OR N PACKAGE
(TOP VIEW)
NC – No internal connection
3 2 1 20 19
910111213
4
5
6
7
8
18
17
16
15
14
CLK OUT
NC
VDD+
NC
OUT
NC
NC
IN–
NC
IN+
FK PACKAGE
(TOP VIEW)
C
C
NC
C RETURN
CLAMP INT/EXT
CLK IN
NC
V
NC
XA
XB
DD –
(TOP VIEW)
TLC2654, TLC2654A
Advanced LinCMOS LOW-NOISE CHOPPER-STABILIZED
OPERATIONAL AMPLIFIERS
SLOS020G – NOVEMBER 1988 – REVISED APRIL 2001
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
The TLC2654 and TLC2654A common-mode
input voltage range includes the negative rail,
thereby providing superior performance in either
single-supply or split-supply applications, even at
power supply voltage levels as low as ±2.3 V.
Two external capacitors are required to operate
the device; however, the on-chip chopper-control
circuitry is transparent to the user. On devices in
the 14-pin and 20-pin packages, the control
circuitry is accessible, allowing the user the option
of controlling the clock frequency with an external
frequency source. In addition, the clock threshold
of the TLC2554 and TLC2654A requires no level
shifting when used in the single-supply configura-
tion with a normal CMOS or TTL clock input.
Innovative circuit techniques used on the
TLC2654 and TLC2654A allow exceptionally fast
overload recovery time. An output clamp pin is
available to reduce the recovery time even further.
The device inputs and outputs are designed to
withstand –100-mA surge currents without
sustaining latch-up. In addition, the TLC2654 and TLC2654A incorporate internal ESD-protection circuits that
prevent functional failures at voltages up to 2000 V as tested under MIL-STD-883C, Method 3015; however,
exercise care in handling these devices, as exposure to ESD may result in degradation of the device parametric
performance.
The C-suffix devices are characterized for operation from 0°C to 70°C. The I-suffix devices are characterized
for operation from –40°C to 85°C. The Q-suffix devices are characterized for operation from –40°C to 125°C.
The M-suffix devices are characterized for operation over the full military temperature range of –55°C to125°C.
AVAILABLE OPTIONS
PACKAGED DEVICES
T
V
IO
max 8 PIN 14 PIN 20 PIN
TA
VIOmax
AT 25°CSMALL
OUTLINE
(D)
CERAMIC
DIP
(JG)
PLASTIC
DIP
(P)
SMALL
OUTLINE
(D)
CERAMIC
DIP
(J)
PLASTIC
DIP
(N)
CERAMIC
DIP
(FK)
10 µV
TLC2654AC
-
8D
—
TLC2654ACP
TLC2654AC
-
14D
—
TLC2654ACN
—
0°C to 70°C
10
µV
20 mV
TLC2654AC
-
8D
TLC2654C 8D
—
TLC2654ACP
TLC2654CP
TLC2654AC
-
14D
TLC2654C 14D
—
TLC2654ACN
TLC2654CN
—
20
mV
TLC2654C
-
8D
—
TLC2654CP
TLC2654C
-
14D
—
TLC2654CN
—
10 µV
TLC2654AI
-
8D
—
TLC2654AIP
TLC2654AI
-
14D
—
TLC2654AIN
—
–40°C to 85°C
10
µV
20 µV
TLC2654AI
-
8D
TLC2654I 8D
—
TLC2654AIP
TLC2654IP
TLC2654AI
-
14D
TLC2654I 14D
—
TLC2654AIN
TLC2654IN
—
20
µ
V
TLC2654I
-
8D
—
TLC2654IP
TLC2654I
-
14D
—
TLC2654IN
—
10 µV
TLC2654AQ
-
8D
— — — — — —
–40°C to 125°C
10
µV
20 µV
TLC2654AQ
-
8D
TLC2654Q 8D
— — — — — —
20
µ
V
TLC2654Q
-
8D
— — — — — —
10 µV
TLC2654AM
-
8D
TLC2654AMJG
TLC2654AMP
TLC2654AM
-
14D
TLC2654AMJ
TLC2654AMN
TLC2654AMFK
–55°C to 125°C
10
µV
20 µV
TLC2654AM
-
8D
TLC2654M 8D
TLC2654AMJG
TLC2654MJG
TLC2654AMP
TLC2654MP
TLC2654AM
-
14D
TLC2654M 14D
TLC2654AMJ
TLC2654MJ
TLC2654AMN
TLC2654MN
TLC2654AMFK
TLC2654MFK
20
µ
V
TLC2654M
-
8D
TLC2654MJG
TLC2654MP
TLC2654M
-
14D
TLC2654MJ
TLC2654MN
TLC2654MFK
The 8-pin and 14-pin D packages are available taped and reeled. Add R suffix to device type (e.g., TLC2654AC-8DR).
Vn – Equivalent Input Noise Voltage – nV/XXVZ
EQUIVALENT INPUT NOISE VOLTAGE
vs
FREQUENCY
1 k
100
10 1 10 100
f – Frequency – Hz 1 k
10 k
VnnV/ Hz
Typical 250-Hz
Chopper-Stabilized
Operational Amplifier
TLC2654
Figure 1
TLC2654, TLC2654A
Advanced LinCMOS LOW-NOISE CHOPPER-STABILIZED
OPERATIONAL AMPLIFIERS
SLOS020G – NOVEMBER 1988 – REVISED APRIL 2001
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
External Components
C RETURN
VDD–
Null
IN+
IN–
VDD+
Main CIC
CLAMP
OUT
CXB CXA
Clamp
Circuit
Compensation-
Biasing
Circuit
A
A
A
B
B
B
5
4
11
12
78
9
10
+
–
+
–
Pin numbers shown are for the D (14 pin), J, and N packages.
TLC2654, TLC2654A
Advanced LinCMOS LOW-NOISE CHOPPER-STABILIZED
OPERATIONAL AMPLIFIERS
SLOS020G – NOVEMBER 1988 – REVISED APRIL 2001
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VDD+ (see Note 1) 8 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply voltage, VDD– (see Note 1) –8 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential input voltage, VID (see Note 2) ±16 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, VI (any input, see Note 1) ±8 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range on CLK IN and INT/EXT V
DD– to VDD– + 5.2 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input current, II (each input) ±5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output current, IO ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Duration of short-circuit current at (or below) 25°C (see Note 3) unlimited. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into CLK IN and INT/EXT ±5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA: C suffix 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I suffix –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Q suffix –40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M suffix –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Case temperature for 60 seconds: FK package 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D, N, or P package 260°C. . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J or JG package 300°C. . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to the midpoint between VDD+ and VDD–.
2. Dif ferential voltages are at IN+ with respect to IN–.
3. The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum
dissipation rating is not exceeded.
DISSIPATION RATING TABLE
PACKAGE
T
A
≤ 25°CDERATING FACTOR T
A
= 70°C T
A
= 85°C T
A
= 125°C
PACKAGE
A
POWER RATING ABOVE TA = 25°C
A
POWER RATING
A
POWER RATING
A
POWER RATING
D
(
8 pin
)
725 mW 5.8 mW/°C464 mW 377 mW 145 mW
D
(8
in)
D
(
14 pin
)
725
mW
950 mW
5.8
mW/ C
7.6 mW/°C
464
mW
608 mW
377
mW
494 mW
145
mW
190 mW
()
FK 1375 mW 11.0 mW/°C880 mW 715 mW 275 mW
J1375 mW 11.0 mW/°C880 mW 715 mW 275 mW
JG 1050 mW 8.4 mW/°C672 mW 546 mW 210 mW
N1150 mW 9.2 mW/°C736 mW 598 mW 230 mW
P1000 mW 8.0 mW/°C640 mW 520 mW 200 mW
recommended operating conditions
C SUFFIX I SUFFIX Q SUFFIX M SUFFIX
UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
UNIT
Supply voltage, VDD±±2.3 ±8±2.3 ±8±2.3 ±8±2.3 ±8 V
Common-mode input voltage, VIC VDD–VDD+ –2.3 VDD–VDD+ –2.3 VDD–VDD+ –2.3 VDD–VDD+ –2.3 V
Clock input voltage VDD–VDD– +5 VDD–VDD– +5 VDD–VDD– +5 VDD–VDD– +5 V
Operating free-air temperature, TA0 70 –40 85 –40 125 –55 125 °C
TLC2654, TLC2654A
Advanced LinCMOS LOW-NOISE CHOPPER-STABILIZED
OPERATIONAL AMPLIFIERS
SLOS020G – NOVEMBER 1988 – REVISED APRIL 2001
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at specified free-air temperature, VDD±= ±5 V (unless otherwise noted)
TEST CONDITIONS
TA†
TLC2654C TLC2654AC
UNIT
TEST
CONDITIONS
T
A
†
MIN TYP MAX MIN TYP MAX
UNIT
VIO
Input offset volta
g
e25°C 5 20 4 10
µV
V
IO
g
(see Note 4) Full range 34 24 µ
V
αVIO
Temperature coefficient of
Full range
001
005
001
005
µV/°C
αVIO input offset voltage
Full
range
0
.
01
0
.
05
0
.
01
0
.
05
µ
V/°C
Input offset voltage
long-term drift (see Note 5) VIC = 0, RS = 50 Ω25°C0.003 0.06 0.003 0.02 µV/mo
IIO
In
p
ut offset current
25°C 30 60 30 60 p
A
I
IO
Input
offset
current
Full range 150 150
pA
IIB
In
p
ut bias current
25°C 50 60 50 60 p
A
I
IB
Input
bias
current
Full range 150 150
pA
VICR
Common-mode input
RS=50Ω
Full range
–5
to
–5
to
V
V
ICR voltage range
R
S =
50
Ω
Full
range
t
o
2.7
t
o
2.7
V
VOM
Maximum positive peak
RL=10kΩ
See Note 6
25°C 4.7 4.8 4.7 4.8
V
V
OM+ output voltage swing
R
L =
10
kΩ
,
See
Note
6
Full range 4.7 4.7
V
VOM
Maximum ne
g
ative peak
RL=10kΩ
See Note 6
25°C–4.7 –4.9 –4.7 –4.9
V
V
OM–
g
output voltage swing
R
L =
10
kΩ
,
See
Note
6
Full range –4.7 –4.7
V
AVD
Lar
g
e-si
g
nal differential
VO=±4V
RL=10kΩ
25°C 120 155 135 155
dB
A
VD
gg
voltage amplification
V
O =
±4
V
,
R
L =
10
kΩ
Full range 120 130
dB
Internal chopping
frequency 25°C 10 10 kHz
Clam
p
on state current
RL= 100 kΩ
25°C 25 25
µA
Clamp
on
-
state
current
R
L =
100
kΩ
Full range 25 25 µ
A
Clam
p
off state current
VO=4Vto4V
25°C 100 100 p
A
Clamp
off
-
state
current
V
O = –
4
V
to
4
V
Full range 100 100
pA
CMRR
Common-mode rejection VO = 0,
VIC VICRmin
25°C 105 125 110 125
dB
CMRR
j
ratio
V
IC =
V
ICRm
i
n,
RS = 50 ΩFull range 105 110
dB
kSVR
Suppl
y
volta
g
e rejection V
DD±
= ±2.3 V to ±8 V, 25°C110 125 110 125
dB
k
SVR
ygj
ratio (∆VDD±/∆VIO)
DD±,
VO = 0, RS = 50 ΩFull range 110 110
dB
IDD
Su
pp
ly current
VO=0
No load
25°C 1.5 2.4 1.5 2.4
mA
I
DD
Supply
current
V
O =
0
,
No
load
Full range 2.5 2.5
mA
†Full range is 0°C to 70°C.
NOTES: 4. This parameter is not production tested full range. Thermocouple effects preclude measurement of the actual VIO of these devices
in high-speed automated testing. VIO is measured to a limit determined by the test equipment capability at the temperature extremes.
The test ensures that the stabilization circuitry is performing properly.
5. Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at T A = 150°C extrapolated
to TA = 25° using the Arrhenius equation and assuming an activation energy of 0.96 eV.
6. Output clamp is not connected.
TLC2654, TLC2654A
Advanced LinCMOS LOW-NOISE CHOPPER-STABILIZED
OPERATIONAL AMPLIFIERS
SLOS020G – NOVEMBER 1988 – REVISED APRIL 2001
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
operating characteristics at specified free-air temperature, VDD± = ±5 V
PARAMETER
TEST
TA†
TLC2654C TLC2654AC
UNIT
PARAMETER
TEST
CONDITIONS
T
A
†
MIN TYP MAX MIN TYP MAX
UNIT
SR+
Positive slew rate at unity gain
25°C 1.5 2 1.5 2
V/µs
SR
+
Positive
slew
rate
at
unity
gain
VO = ±2.3 V,
RL10 kΩ
Full range 1.3 1.3
V/
µ
s
SR
Negative slew rate at unity gain
R
L =
10
kΩ
,
CL
= 1
00
pF 25°C 2.3 3.7 2.3 3.7
V/µs
SR
–
Negative
slew
rate
at
unity
gain
CL
=
100
F
Full range 1.7 1.7
V/
µ
s
V
Equivalent input noise volta
g
e f = 10 Hz
25°C
47 47 75
nV/√Hz
V
n
qg
(see Note 7) f = 1 kHz
25°C
13 13 20 n
V/√H
z
VN(PP)
Peak-to-peak equivalent input f = 0 to 1 Hz
25°C
0.5 0.5
µV
V
N(PP)
q
noise voltage f = 0 to 10 Hz
25°C
1.5 1.5 µ
V
InEquivalent input noise current f = 10 kHz 25°C 0.004 0.004 pA/√Hz
f = 10 kHz,
Gain-bandwidth product
,
RL = 10 kΩ,25°C 1.9 1.9 MHz
L
CL = 100 pF
φmPhase margin at unity gain RL = 10 kΩ,
CL = 100 pF 25°C 48°48°
†Full range is 0°C to 70°C.
NOTE 7: This parameter is tested on a sample basis for the TLC2654A. For other test requirements, please contact the factory . This statement
has no bearing on testing or nontesting of other parameters.
TLC2654, TLC2654A
Advanced LinCMOS LOW-NOISE CHOPPER-STABILIZED
OPERATIONAL AMPLIFIERS
SLOS020G – NOVEMBER 1988 – REVISED APRIL 2001
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at specified free-air temperature, VDD ± = ±5 V (unless otherwise noted)
TEST CONDITIONS
TA†
TLC2654I TLC2654AI
UNIT
TEST
CONDITIONS
T
A
†
MIN TYP MAX MIN TYP MAX
UNIT
VIO
Input offset volta
g
e25°C 5 20 4 10
µV
V
IO
g
(see Note 4) Full range 40 30 µ
V
αVIO
Temperature coefficient of
Full range
001
005
001
005
µV/°C
αVIO input offset voltage
Full
range
0
.
01
0
.
05
0
.
01
0
.
05
µ
V/°C
Input offset voltage
long-term drift (see Note 5) VIC = 0, RS = 50 Ω25°C0.003 0.06 0.003 0.02 µV/mo
IIO
In
p
ut offset current
25°C 30 60 30 60 p
A
I
IO
Input
offset
current
Full range 200 200
pA
IIB
In
p
ut bias current
25°C 50 60 50 60 p
A
I
IB
Input
bias
current
Full range 200 200
pA
VICR
Common-mode input
RS=50Ω
Full range
–5
to
–5
to
V
V
ICR voltage range
R
S =
50
Ω
Full
range
t
o
2.7
t
o
2.7
V
VOM
Maximum positive peak
RL=10kΩ
See Note 6
25°C 4.7 4.8 4.7 4.8
V
V
OM+ output voltage swing
R
L =
10
kΩ
,
See
Note
6
Full range 4.7 4.7
V
VOM
Maximum ne
g
ative peak
RL=10kΩ
See Note 6
25°C–4.7 –4.9 –4.7 –4.9
V
V
OM–
g
output voltage swing
R
L =
10
kΩ
,
See
Note
6
Full range –4.7 –4.7
V
AVD
Lar
g
e-si
g
nal differential
VO=±4V
RL=10kΩ
25°C 120 155 135 155
dB
A
VD
gg
voltage amplification
V
O =
±4
V
,
R
L =
10
kΩ
Full range 120 125
dB
Internal chopping
frequency 25°C 10 10 kHz
Clam
p
on state current
RL= 100 kΩ
25°C 25 25
µA
Clamp
on
-
state
current
R
L =
100
kΩ
Full range 25 25 µ
A
Clam
p
off state current
VO=4Vto4V
25°C 100 100 p
A
Clamp
off
-
state
current
V
O = –
4
V
to
4
V
Full range 100 100
pA
CMRR
Common-mode re
j
ection VO = 0,
VIC VICRmin
25°C 105 125 110 125
dB
CMRR
j
ratio
V
IC =
V
ICRm
i
n,
RS = 50 ΩFull range 105 110
dB
kSVR
Supply volta
g
e rejection V
DD±
= ±2.3 V to ±8 V, 25°C110 125 110 125
dB
k
SVR
ygj
ratio (∆VDD±/∆VIO)
DD±,
VO = 0, RS = 50 ΩFull range 110 110
dB
IDD
Su
pp
ly current
VO=0
No load
25°C 1.5 2.4 1.5 2.4
mA
I
DD
Supply
current
V
O =
0
,
No
load
Full range 2.5 2.5
mA
†Full range is –40°C to 85°C
NOTES: 4. This parameter is not production tested full range. Thermocouple effects preclude measurement of the actual VIO of these devices
in high-speed automated testing. VIO is measured to a limit determined by the test equipment capability at the temperature extremes.
The test ensures that the stabilization circuitry is performing properly.
5. Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at T A = 150°C extrapolated
to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
6. Output clamp is not connected.
TLC2654, TLC2654A
Advanced LinCMOS LOW-NOISE CHOPPER-STABILIZED
OPERATIONAL AMPLIFIERS
SLOS020G – NOVEMBER 1988 – REVISED APRIL 2001
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
operating characteristics at specified free-air temperature, VDD± = ±5 V
PARAMETER
TEST
TA†
TLC2654I TLC2654AI
UNIT
PARAMETER
CONDITIONS
T
A
†
MIN TYP MAX MIN TYP MAX
UNIT
SR+
Positive slew rate at unity gain
25°C 1.5 2 1.5 2
V/µs
SR
+
Positive
slew
rate
at
unity
gain
VO = ±2.3 V,
RL10 kΩ
Full range 1.2 1.2
V/
µ
s
SR
Negative slew rate at unity gain
R
L =
10
kΩ
,
CL
= 1
00
pF 25°C 2.3 3.7 2.3 3.7
V/µs
SR
–
Negative
slew
rate
at
unity
gain
CL
=
100
F
Full range 1.5 1.5
V/
µ
s
V
Equivalent input noise volta
g
ef = 10 Hz
25°C
47 47 75
nV/√Hz
V
n
qg
(see Note 7) f = 1 kHz
25°C
13 13 20 n
V/√H
z
VN(PP)
Peak-to-peak equivalent input f = 0 to 1 Hz
25°C
0.5 0.5
µV
V
N(PP)
q
noise voltage f = 0 to 10 Hz
25°C
1.5 1.5 µ
V
InEquivalent input noise current f = 10 kHz 25°C 0.004 0.004 pA/√Hz
f = 10 kHz
,
Gain-bandwidth product
f
10
kHz,
RL = 10 kΩ,25°C 1.9 1.9 MHz
L
CL = 100 pF
φmPhase margin at unity gain RL = 10 kΩ,
CL = 100 pF 25°C 48°48°
†Full range is –40°C to 85°C.
NOTE 7: This parameter is tested on a sample basis for the TLC2654A. For other test requirements, please contact the factory . This statement
has no bearing on testing or nontesting of other parameters.
TLC2654, TLC2654A
Advanced LinCMOS LOW-NOISE CHOPPER-STABILIZED
OPERATIONAL AMPLIFIERS
SLOS020G – NOVEMBER 1988 – REVISED APRIL 2001
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at specified free-air temperature, VDD ± = ±5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS T
A†
TLC2654Q
TLC2654M TLC2654AQ
TLC2654AM UNIT
TA
MIN TYP MAX MIN TYP MAX
VIO
Input offset volta
g
e 25°C 5 20 4 10
µV
V
IO
g
(see Note 4) Full range 50 40 µ
V
αVIO
Temperature coefficient of
Full range
001
005
∗
001
005
∗
µV/°C
αVIO input offset voltage
Full
range
0
.
01
0
.
05∗
0
.
01
0
.
05∗
µ
V/°C
Input offset voltage
long-term drift (see Note 5) VIC = 0, RS = 50 Ω25°C0.003 0.06∗0.003 0.02∗µV/mo
IIO
In
p
ut offset current
25°C 30 60 30 60 p
A
I
IO
Input
offset
current
Full range 500 500
pA
IIB
In
p
ut bias current
25°C 50 60 50 60 p
A
I
IB
Input
bias
current
Full range 500 500
pA
Common mode input
–5–5
VICR
C
ommon-mo
d
e
i
npu
t
voltage range
RS = 50 ΩFull range
5
to
5
to V
ICR
voltage
range
S
g
2.7 2.7
VOM
Maximum positive peak
RL=10kΩ
See Note 6
25°C 4.7 4.8 4.7 4.8
V
V
OM+ output voltage swing
R
L =
10
kΩ
,
See
Note
6
Full range 4.7 4.7
V
VOM
Maximum ne
g
ative peak
RL=10kΩ
See Note 6
25°C–4.7 –4.9 –4.7 –4.9
V
V
OM–
g
output voltage swing
R
L =
10
kΩ
,
See
Note
6
Full range –4.7 –4.7
V
AVD
Lar
g
e-si
g
nal differential
VO=±4V
RL=10kΩ
25°C 120 155 135 155
dB
A
VD
gg
voltage amplification
V
O =
±4
V
,
R
L =
10
kΩ
Full range 120 120
dB
Internal chopping
frequency 25°C 10 10 kHz
Clam
p
on state current
RL= 100 kΩ
25°C 25 25
µA
Clamp
on
-
state
current
R
L =
100
kΩ
Full range 25 25 µ
A
Clam
p
off state current
VO=4Vto4V
25°C 100 100 p
A
Clamp
off
-
state
current
V
O = –
4
V
to
4
V
Full range 500 500
pA
CMRR
Common-mode rejection VO = 0,
VIC VICRmin
25°C 105 125 110 125
dB
CMRR
j
ratio
V
IC =
V
ICRm
i
n,
RS = 50 ΩFull range 105 110
dB
kSVR
Suppl
y
volta
g
e rejection V
DD±
= ±2.3 V to ±8 V, 25°C110 125 110 125
dB
k
SVR
ygj
ratio (∆VDD±/∆VIO)
DD±,
VO = 0, RS = 50 ΩFull range 105 110
dB
IDD
Su
pp
ly current
VO=0
No load
25°C 1.5 2.4 1.5 2.4
mA
I
DD
Supply
current
V
O =
0
,
No
load
Full range 2.5 2.5
mA
∗ On products complaint to MIL-STD-883, Class B, this parameter is not production tested.
†Full range is –40° to 125°C for Q suf fix, –55° to 125°C for M suffix.
NOTES: 4. This parameter is not production tested full range. Thermocouple effects preclude measurement of the actual VIO of these devices
in high-speed automated testing. VIO is measured to a limit determined by the test equipment capability at the temperature extremes.
The test ensures that the stabilization circuitry is performing properly.
5. Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at T A = 150°C extrapolated
to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
6. Output clamp is not connected.
TLC2654, TLC2654A
Advanced LinCMOS LOW-NOISE CHOPPER-STABILIZED
OPERATIONAL AMPLIFIERS
SLOS020G – NOVEMBER 1988 – REVISED APRIL 2001
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
operating characteristics at specified free-air temperature, VDD± = ±5 V
PARAMETER TEST CONDITIONS TA
†
TLC2654Q
TLC2654M
TLC2654AQ
TLC2654AM UNIT
MIN TYP MAX
SR+
Positive slew rate at unity gain
25°C 1.5 2
V/µs
SR
+
Positive
slew
rate
at
unity
gain
VO=±23V
RL=10kΩ
CL= 100
p
F
Full range 1.1
V/
µ
s
SR
Negative slew rate at unity gain
V
O =
±2
.
3
V
,
R
L =
10
kΩ
,
C
L =
100
pF
25°C 2.3 3.7
V/µs
SR
–
Negative
slew
rate
at
unity
gain
Full range 1.3
V/
µ
s
V
Equivalent in
p
ut noise voltage
f = 10 Hz 25°C 47
nV/√Hz
V
n
Equivalent
input
noise
voltage
f = 1 kHz 25°C 13 n
V/√H
z
VN(PP)
Peak-to-peak equivalent input f = 0 to 1 Hz 25°C 0.5
µV
V
N(PP)
q
noise voltage f = 0 to 10 Hz 25°C 1.5 µ
V
InEquivalent input noise current f = 1 kHz 25°C 0.004 pA/√Hz
Gain-bandwidth product f = 10 kHz, RL = 10 kΩ, CL = 100 pF 25°C 1.9 MHz
φmPhase margin at unity gain RL = 10 kΩ, CL = 100 pF 25°C 48°
†Full range is –40° to 125°C for Q suf fix, –55° to 125°C for M suffix.
TLC2654, TLC2654A
Advanced LinCMOS LOW-NOISE CHOPPER-STABILIZED
OPERATIONAL AMPLIFIERS
SLOS020G – NOVEMBER 1988 – REVISED APRIL 2001
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
VIO Input of fset voltage Distribution 2
Normalized input offset voltage vs Chopping frequency 3
IIO
In
p
ut offset current
vs Choppin
g
frequenc
y
4
I
IO
Input
offset
current
gq y
vs Free-air temperature 5
vs Common-mode input volta
g
e 6
IIB Input bias current
vs
Common mode
in ut
voltage
vs Chopping frequency
6
7
IB
gq y
vs Free-air temperature 8
Clamp current vs Output voltage 9
VOM
Maximum
p
eak out
p
ut voltage swing
vs Output current 10
V
OM
Maximum
peak
output
voltage
swing
vs Free-air temperature 11
VO(PP) Maximum peak-to-peak output voltage swing vs Frequency 12
CMRR Common-mode rejection ratio vs Frequency 13
AVD
Large signal differential voltage am
p
lification
vs Frequenc
y
14
A
VD
Large
-
signal
differential
voltage
amplification
qy
vs Free-air temperature 15
Cho
pp
ing frequency
vs Supply volta
g
e 16
Chopping
frequency
yg
vs Free-air temperature 17
IDD
Su
pp
ly current
vs Suppl
y
volta
g
e 18
I
DD
Supply
current
yg
vs Free-air temperature 19
IOS
Short circuit out
p
ut current
vs Supply volta
g
e 20
I
OS
Short
-
circuit
output
current
yg
vs Free-air temperature 21
SR
Slew rate
vs Suppl
y
volta
g
e 22
SR
Slew
rate
yg
vs Free-air temperature 23
Voltage follower
p
ulse res
p
onse
Small si
g
nal 24
Voltage
-
follower
pulse
response
g
Large signal 25
VN(PP) Peak-to-peak input noise voltage vs Chopping frequency 26, 27
VnEquivalent input noise voltage vs Frequency 28
kSVR Supply voltage rejection ratio vs Frequency 29
Gain bandwidth
p
roduct
vs Supply volta
g
e 30
Gain
-
bandwidth
product
yg
vs Free-air temperature 31
φ
Phase margin
vs Suppl
y
volta
g
e 32
φ
m
Phase
margin
yg
vs Load capacitance 33
Phase shift vs Frequency 14
TLC2654, TLC2654A
Advanced LinCMOS LOW-NOISE CHOPPER-STABILIZED
OPERATIONAL AMPLIFIERS
SLOS020G – NOVEMBER 1988 – REVISED APRIL 2001
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS†
Figure 2
8
4
0
Percentage of Units – %
12
16
DISTRIBUTION OF TLC2654
INPUT OFFSET VOLTAGE
20
–20 –16 –12 – 8 – 4 0 4 8 12 16 20
456 Units Tested From 4 Wafer Lots
VIO – Input Offset Voltage – µV
VDD± = ±5 V
TA = 25°C
N Package
Figure 3
10
0
–10
VIO – Normalized Input Offset Voltage – uV
20
30
NORMALIZED INPUT OFFSET VOLTAGE
vs
CHOPPING FREQUENCY
40
100 1K 10K 100K
VIO µV
VDD± = ±5 V
VIC = 0
TA = 25°C
Chopping Frequency – Hz
Figure 4
60
40
20
0
100 1 k 10 k
IIO – Input Offset Current – pA
80
INPUT OFFSET CURRENT
vs
CHOPPING FREQUENCY
100
100 k
IIO
120
140 VDD± = ±5 V
VIC = 0
TA = 25°C
Chopping Frequency – Hz
Figure 5
IIO – Input Offset Current – pA
IIO
60
40
20
025 45 65 85
80
INPUT OFFSET CURRENT
vs
FREE-AIR TEMPERATURE
100
105 125
TA – Free-Air Temperature – °C
VDD± = ±5 V
VIC = 0
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
TLC2654, TLC2654A
Advanced LinCMOS LOW-NOISE CHOPPER-STABILIZED
OPERATIONAL AMPLIFIERS
SLOS020G – NOVEMBER 1988 – REVISED APRIL 2001
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS†
Figure 6
VIC – Common-Mode Input Voltage – V
INPUT BIAS CURRENT
vs
COMMON-MODE INPUT VOLTAGE
10
IIB – Input Bias Current – pA
100
1000
– 5 – 3 –11 35
IIB
VDD± = ±5 V
TA = 25°C
– 4 – 20 2 4
Figure 7
INPUT BIAS CURRENT
vs
CHOPPING FREQUENCY
60
40
20
0
100 1 k 10 k 100 k
IIB – Input Bias Current – pA
80
100
IIB
VDD± = ±5 V
VIC = 0
TA = 25°C
Chopping Frequency – Hz
Figure 8
TA – Free-Air Temperature – °C
60
40
20
025 45 65 85
IIB – Input Bias Current – pA
80
INPUT BIAS CURRENT
vs
FREE-AIR TEMPERATURE
100
105 125
IIB
VDD± = ±5 V
VIC = 0
Figure 9
1 nA
100 pA
10 pA
1 pA 4 4.2 4.4 4.6
|Clamp Current|
10
CLAMP CURRENT
vs
OUTPUT VOLTAGE
4.8 5
|VO| – Output Voltage – V
1
100 nA
10 nA
VDD± = ±5 V
TA = 25°C
100 Aµ
Aµ
Aµ
Positive Clamp Current
Negative Clamp Current
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
TLC2654, TLC2654A
Advanced LinCMOS LOW-NOISE CHOPPER-STABILIZED
OPERATIONAL AMPLIFIERS
SLOS020G – NOVEMBER 1988 – REVISED APRIL 2001
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS†
Figure 10
4.6
4.4
4.2
4
– Maximum Peak Output Voltage – V
4.8
MAXIMUM PEAK OUTPUT VOLTAGE
vs
OUTPUT CURRENT
5
OM
|IO| – Output Current – mA
VDD± = ±5 V
TA = 25°C
VOM+ VOM–
0 0.4 0.8 1.2 1.6 2
V
Figure 11
TA – Free-Air Temperature – °C
5
0
– 2.5
– 5
–75 – 50 – 25 0 25 50
MAXIMUM PEAK OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
75 100 125
2.5
VDD± = ±5 V
RL = 10 kΩ
– Maximum Peak Output Voltage – V
OM
V
VOM+
VOM–
Figure 12
6
4
2
0
VO(PP) – Maximum Peak-to-Peak Output Voltage – V
8
10
100 1 k 10 k
f – Frequency – Hz
MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE
vs
FREQUENCY
100 k 1 M
VO(PP)
TA = –55°C
TA = 125°C
VDD± = ±5 V
RL = 10 kΩ
Figure 13
100
80
40
20
0
140
60
10 100 1 k 10 k
CMRR – Common-Mode Rejection Ratio – dB
120
f – Frequency – Hz
COMMOM-MODE REJECTION RATIO
vs
FREQUENCY
VDD± = ±5 V
TA = 25°C
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
TLC2654, TLC2654A
Advanced LinCMOS LOW-NOISE CHOPPER-STABILIZED
OPERATIONAL AMPLIFIERS
SLOS020G – NOVEMBER 1988 – REVISED APRIL 2001
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS†
Figure 14
20
0
–20
–40
AVD – Large-Signal Differential Voltage Amplification – dB
40
60
80
10 100 1 k 10 k 100 k
f – Frequency – Hz
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE SHIFT
vs
FREQUENCY
1 M 10 M
100
120
220°
200°
180°
160°
140°
120°
100°
80°
60°
AVD
VDD± = ±5 V
RL = 10 kΩ
CL = 100 pF
TA = 25°C
Phase Shift
AVD
Phase Shift
Figure 15
TA – Free-Air Temperature – °C
156
154
152
– 25 0 50
158
LARGE-SIGNAL DIFFERENTIAL
VOLTAGE AMPLIFICATION
vs
FREE-AIR TEMPERATURE
160
100 125
– 50 25 75
VDD± = ±5 V
RL = 10 kΩ
VO = ±4 V
AVD – Large-Signal Differential Voltage Amplification – dB
AVD
– 75
150
Figure 16
|VDD±| – Supply Voltage – V
10.6
10.2
9.8
9.4012345
Chopping Frequency – kHz
11
11.4
CHOPPING FREQUENCY
vs
SUPPLY VOLTAGE
678
TA = 25°C
Figure 17
10.5
9.5
9
8.5
–75 – 50 – 25 0 25 50
CHOPPING FREQUENCY
vs
FREE-AIR TEMPERATURE
75 100 125
10
VDD± = ±5 V
TA – Free-Air Temperature – °C
Chopping Frequency – kHz
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
TLC2654, TLC2654A
Advanced LinCMOS LOW-NOISE CHOPPER-STABILIZED
OPERATIONAL AMPLIFIERS
SLOS020G – NOVEMBER 1988 – REVISED APRIL 2001
16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS†
Figure 18
IDD – Supply Current – mA
IDD
1.2
0.8
0.4
00235
1.6
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
2
78146
TA = 25°C
TA = –55°C
TA = 125°C
VO = 0
No Load
|VDD ±| – Supply Voltage – V
Figure 19
1.2
0.8
0.4
0
–75 – 25 0 50
IDD – Supply Current – mA
1.6
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
2
100 125– 50 25 75
IDD
VDD± = ±5 V
VDD± = ±7.5 V
VDD± = ±2.5 V
VO = 0
No Load
TA – Free-Air Temperature – °C
Figure 20
0
– 4
– 8
–12012345
IOS – Short-Circuit Output Current – mA
4
8
SHORT-CIRCUIT OUTPUT CURRENT
vs
SUPPLY VOLTAGE
12
678
|VDD ±| – Supply Voltage – V
IOS
VO = 0
TA = 25°C
VID = –100 mV
VID = 100 mV
Figure 21
0
– 5
–10
–15
–75 – 50 – 25 0 25 50
IOS – Short-Circuit Output Current – mA
5
10
SHORT-CIRCUIT OUTPUT CURRENT
vs
FREE-AIR TEMPERATURE
15
75 100 125
TA – Free-Air Temperature – °C
IOS
VID = 100 mV
VID = –100 mV
VDD± = ±5 V
VO = 0
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
TLC2654, TLC2654A
Advanced LinCMOS LOW-NOISE CHOPPER-STABILIZED
OPERATIONAL AMPLIFIERS
SLOS020G – NOVEMBER 1988 – REVISED APRIL 2001
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS†
Figure 22
5
4
1
01234567
SR – Slew Rate – V/us
SLEW RATE
vs
SUPPLY VOLTAGE
8
3
2
µsV/
RL = 10 kΩ
CL = 100 pF
TA = 25°C
SR–
0
|VDD ±| – Supply Voltage – V
SR+
Figure 23
1
02550
SR – Slew Rate – V/us
3
SLEW RATE
vs
FREE-AIR TEMPERATURE
4
75 100 125
2
0
µsV/
VDD± = ±5 V
RL = 10 kΩ
CL = 100 pF
SR–
SR+
–75 –50 –25
TA – Free-Air Temperature – °C
Figure 24
t – Time – µs
25
– 50
–75
–100 0123
VO – Output Voltage – mV
75
VOLTAGE-FOLLOWER
SMALL-SIGNAL
PULSE RESPONSE
46
0
100
50
– 25
VO
VDD± = ±5 V
RL = 10 kΩ
CL = 100 pF
TA = 25°C
57
Figure 25
t – Time – µs
51015202530
VO – Output Voltage – V
VOLTAGE-FOLLOWER
LARGE-SIGNAL
PULSE RESPONSE
35 40
VO
VDD± = ±5 V
RL = 10 kΩ
CL = 100 pF
TA = 25°C
1
– 2
– 3
– 4
3
0
4
2
–1
0
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
TLC2654, TLC2654A
Advanced LinCMOS LOW-NOISE CHOPPER-STABILIZED
OPERATIONAL AMPLIFIERS
SLOS020G – NOVEMBER 1988 – REVISED APRIL 2001
18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 26
Chopping Frequency – kHz
VN(PP) – Peak-to-Peak Input Noise Voltage – uV
N(PP)
V
PEAK-TO-PEAK INPUT NOISE VOLTAGE
vs
CHOPPING FREQUENCY
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
0246810
VDD± = ±5 V
RS = 20 Ω
f = 0 to 1 Hz
TA = 25°C
µV
Figure 27
VN(PP) – Peak-to-Peak Input Noise Voltage – uV
N(PP)
V µV
3
2
1
00246
4
PEAK-TO-PEAK INPUT NOISE VOLTAGE
vs
CHOPPING FREQUENCY
5
810
VDD± = ±5 V
RS = 20 Ω
f = 0 to 10 Hz
TA = 25°C
Chopping Frequency – kHz
Figure 28
30
20
10
01 10 100
VN – Equivalent Input Noise Voltage – xxxxxx
40
f – Frequency – Hz
EQUIVALENT INPUT NOISE VOLTAGE
vs
FREQUENCY
50
1 k 10 k
nV/ Hz
Vn
VDD± = ±5 V
RS = 20 Ω
TA = 25°C
Figure 29
100
80
40
20
140
60
100 1 k 10 k
kSVR – Supply Voltage Rejection Ratio – dB
120
f – Frequency – Hz
SUPPLY VOLTAGE REJECTION RATIO
vs
FREQUENCY
k SVR
VDD± = ±2.3 V to ±8 V
TA = 25°C
kSVR+
kSVR–
010
TLC2654, TLC2654A
Advanced LinCMOS LOW-NOISE CHOPPER-STABILIZED
OPERATIONAL AMPLIFIERS
SLOS020G – NOVEMBER 1988 – REVISED APRIL 2001
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS†
Figure 30
|VDD±| – Supply Voltage – V
1.9
1.8012345
Gain-Bandwidth Product – MHz
2
GAIN-BANDWIDTH PRODUCT
vs
SUPPLY VOLTAGE
2.1
678
RL = 10 kΩ
CL = 100 pF
TA = 25°C
Figure 31
2
1.8
1.6
1.2
–75 – 50 – 25 0 25 50
Gain-Bandwidth Product – MHz
2.2
2.4
GAIN-BANDWIDTH PRODUCT
vs
FREE-AIR TEMPERATURE
2.6
75 100 125
VDD± = ±5 V
RL = 10 kΩ
CL = 100 pF
1.4
TA – Free-Air Temperature – °C
Figure 32
0235
– Phase Margin
PHASE MARGIN
vs
SUPPLY VOLTAGE
78146
φm
|VDD±| – Supply Voltage – V
60°
50°
40°
30°
20°
10°
0°
RL = 10 kΩ
CL = 100 pF
TA = 25°C
Figure 33
60°
50°
40°
30°
20°
10°
0°
CL – Load Capacitance – pF
0 200 400 600
PHASE MARGIN
vs
LOAD CAPACITANCE
800 1000
VDD± = ±5 V
RL = 10 kΩ
TA = 25°C
– Phase Marginφm
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
0
– 50 0 10203040
VI – Input Voltage – mV VO – Output Voltage – V
– 5
t – Time – ms
0
50 60 70 80
VIVO
VDD± = ±5 V
TA = 25°C
Figure 34. Overload Recovery
TLC2654, TLC2654A
Advanced LinCMOS LOW-NOISE CHOPPER-STABILIZED
OPERATIONAL AMPLIFIERS
SLOS020G – NOVEMBER 1988 – REVISED APRIL 2001
20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
capacitor selection and placement
Leakage and dielectric absorption are the two important factors to consider when selecting external capacitors
CXA and CXB. Both factors can cause system degradation, negating the performance advantages realized by
using the TLC2654.
Degradation from capacitor leakage becomes more apparent with increasing temperatures. Low-leakage
capacitors and standoffs are recommended for operation at TA = 125°C. In addition, guard bands are
recommended around the capacitor connections on both sides of the printed-circuit board to alleviate problems
caused by surface leakage on circuit boards.
Capacitors with high dielectric absorption tend to take several seconds to settle upon application of power, which
directly affects input offset voltage. In applications needing fast settling of input voltage, high-quality film
capacitors such as mylar, polystyrene, or polypropylene should be used. In other applications, a ceramic or
other low-grade capacitor can suffice.
Unlike many choppers available today, the TLC2654 is designed to function with values of CXA and CXB in the
range of 0.1 µF to 1 µF without degradation to input offset voltage or input noise voltage. These capacitors
should be located as close as possible to CXA and CXB and return to either VDD– or C RETURN. On many
choppers, connecting these capacitors to VDD– causes degradation in noise performance; this problem is
eliminated on the TLC2654.
internal/external clock
The TLC2654 has an internal clock that sets the chopping frequency to a nominal value of 10 kHz. On 8-pin
packages, the chopping frequency can only be controlled by the internal clock; however , on all 14-pin packages
and the 20-pin FK package the device chopping frequency can be set by the internal clock or controlled
externally by use of the INT/EXT and CLK IN. To use the internal 10-kHz clock, no connection is necessary. If
external clocking is desired, connect INT/EXT to VDD– and the external clock to CLK IN. The external clock trip
point is 2.5 V above the negative rail; however, CLK IN can be driven from the negative rail to 5 V above the
negative rail. This allows the TLC2654 to be driven directly by 5-V TTL and CMOS logic when operating in the
single-supply configuration. If this 5-V level is exceeded, damage could occur to the device unless the current
into CLK IN is limited to ±5 mA. A divide-by-two
frequency divider interfaces with CLK IN and sets
the chopping frequency. The chopping frequency
appears on CLK OUT.
overload recovery/output clamp
When large differential-input-voltage conditions
are applied to the TLC2654, the nulling loop
attempts to prevent the output from saturating by
driving CXA and CXB to internally-clamped voltage
levels. Once the overdrive condition is removed,
a period of time is required to allow the built-up
charge to dissipate. This time period is defined as
overload recovery time (see Figure 34). Typical
overload recovery time for the TLC2654 is
significantly faster than competitive products;
however, this time can be reduced further by use
of internal clamp circuitry accessible through
CLAMP if required.
TLC2654, TLC2654A
Advanced LinCMOS LOW-NOISE CHOPPER-STABILIZED
OPERATIONAL AMPLIFIERS
SLOS020G – NOVEMBER 1988 – REVISED APRIL 2001
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
overload recovery/output clamp (continued)
The clamp is a switch that is automatically activated when the output is approximately 1 V from either supply
rail. When connected to the inverting input (in parallel with the closed-loop feedback resistor), the closed-loop
gain is reduced and the TLC2654 output is prevented from going into saturation. Since the output must source
or sink current through the switch (see Figure 9), the maximum output voltage swing is slightly reduced.
thermoelectric effects
To take advantage of the extremely low offset voltage temperature coefficient of the TLC2654, care must be
taken to compensate for the thermoelectric effects present when two dissimilar metals are brought into contact
with each other (such as device leads being soldered to a printed-circuit board). It is not uncommon for dissimilar
metal junctions to produce thermoelectric voltages in the range of several microvolts per degree Celsius (orders
of magnitude greater than the 0.01 µV/°C typical of the TLC2654).
To help minimize thermoelectric effects, pay careful attention to component selection and circuit-board layout.
Avoid the use of nonsoldered connections (such as sockets, relays, switches, etc.) in the input signal path.
Cancel thermoelectric effects by duplicating the number of components and junctions in each device input. The
use of low-thermoelectric-coefficient components, such as wire-wound resistors, is also beneficial.
latch-up avoidance
Because CMOS devices are susceptible to latch-up due to their inherent parasitic thyristors, the TLC2654 inputs
and outputs are designed to withstand –100-mA surge currents without sustaining latch-up; however,
techniques to reduce the chance of latch-up should be used whenever possible. Internal protection diodes
should not, by design, be forward biased. Applied input and output voltages should not exceed the supply
voltage by more than 300 mV. Care should be exercised when using capacitive coupling on pulse generators.
Supply transients should be stunted by the use of decoupling capacitors (0.1 µF typical) located across the
supply rails as close to the device as possible.
The current path established if latch-up occurs is usually between the supply rails and is limited only by the
impedance of the power supply and the forward resistance of the parasitic thyristor. The chance of latch-up
occurring increases with increasing temperature and supply voltage.
electrostatic-discharge protection
The TLC2654 incorporates internal ESD-protection circuits that prevent functional failures at voltages at or
below 2000 V. Care should be exercised in handling these devices, as exposure to ESD may result in
degradation of the device parametric performance.
theory of operation
Chopper-stabilized operational amplifiers offer the best dc performance of any monolithic operational amplifier .
This superior performance is the result of using two operational amplifiers — a main amplifier and a nulling
amplifier – plus oscillator-controlled logic and two external capacitors to create a system that behaves as a
single amplifier. With this approach, the TLC2654 achieves submicrovolt input offset voltage, submicrovolt
noise voltage, and offset voltage variations with temperature in the nV/°C range.
The TLC2654 on-chip control logic produces two dominant clock phases: a nulling phase and an amplifying
phase. The term chopper-stabilized derives from the process of switching between these two clock phases.
Figure 35 shows a simplified block diagram of the TLC2654. Switches A and B are make-before-break types.
TLC2654, TLC2654A
Advanced LinCMOS LOW-NOISE CHOPPER-STABILIZED
OPERATIONAL AMPLIFIERS
SLOS020G – NOVEMBER 1988 – REVISED APRIL 2001
22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
theory of operation (continued)
During the nulling phase, switch A is closed, shorting the nulling amplifier inputs together and allowing the nulling
amplifier to reduce its own input offset voltage by feeding its output signal back to an inverting input node.
Simultaneously , external capacitor CXA stores the nulling potential to allow the offset voltage of the amplifier to
remain nulled during the amplifying phase.
Null
IN+
IN–
Main
VDD–
CXA
CXB
B
A
B
A+
+
–
–
5
410 OUT
7
Pin numbers shown are for the D (14 pin), J, and N packages.
Figure 35. TLC2654 Simplified Block Diagram
During the amplifying phase, switch B is closed, connecting the output of the nulling amplifier to a noninverting
input of the main amplifier. In this configuration, the input offset voltage of the main amplifier is nulled. Also,
external capacitor CXB stores the nulling potential to allow the offset voltage of the main amplifier to remain
nulled during the next nulling phase.
This continuous chopping process allows offset voltage nulling during variations in time and temperature and
over the common-mode input voltage range and power supply range. In addition, because the low-frequency
signal path is through both the null and main amplifiers, extremely high gain is achieved.
The low-frequency noise of a chopper amplifier depends on the magnitude of the component noise prior to
chopping and the capability of the circuit to reduce this noise while chopping. The use of the Advanced LinCMOS
process, with its low-noise analog MOS transistors and patent-pending input stage design, significantly reduces
the input noise voltage.
The primary source of nonideal operation in chopper-stabilized amplifiers is error charge from the switches. As
charge imbalance accumulates on critical nodes, input offset voltage can increase especially with increasing
chopping frequency. This problem has been significantly reduced in the TLC2654 by use of a patent-pending
compensation circuit and the Advanced LinCMOS process.
The TLC2654 incorporates a feed-forward design that ensures continuous frequency response. Essentially, the
gain magnitude of the nulling amplifier and compensation network crosses unity at the break frequency of the
main amplifier . As a result, the high-frequency response of the system is the same as the frequency response
of the main amplifier . This approach also ensures that the slewing characteristics remain the same during both
the nulling and amplifying phases.
The primary limitation on ac performance is the chopping frequency . As the input signal frequency approaches
the chopper’s clock frequency, intermodulation (or aliasing) errors result from the mixing of these frequencies.
To avoid these error signals, the input frequency must be less than half the clock frequency. Most choppers
available today limit the internal chopping frequency to less than 500 Hz in order to eliminate errors due to the
charge imbalancing phenomenon mentioned previously . However , to avoid intermodulation errors on a 500-Hz
chopper, the input signal frequency must be limited to less than 250 Hz.
TLC2654, TLC2654A
Advanced LinCMOS LOW-NOISE CHOPPER-STABILIZED
OPERATIONAL AMPLIFIERS
SLOS020G – NOVEMBER 1988 – REVISED APRIL 2001
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
theory of operation (continued)
The TLC2654 removes this restriction on ac performance by using a 10-kHz internal clock frequency . This high
chopping frequency allows amplification of input signals up to 5 kHz without errors due to intermodulation and
greatly reduces low-frequency noise.
THERMAL INFORMATION
temperature coefficient of input offset voltage
Figure 36 shows the effects of package-included thermal EMF. The TLC2654 can null only the offset voltage
within its nulling loop. There are metal-to-metal junctions outside the nulling loop (bonding wires, solder joints,
etc.) that produce EMF. In Figure 36, a TLC2654 packaged in a 14-pin plastic package (N package) was placed
in an oven at 25°C at t = 0, biased up, and allowed to stabilize. At t = 3 min, the oven was turned on and allowed
to rise in temperature to 125°C. As evidenced by the curve, the overall change in input offset voltage with
temperature is less than the specified maximum limit of 0.05 µV/°C.
– Input Offset Voltage –
– 12
– 15
4
– 18 0 3 6 9 12 15 18
– 4
– 8
0
t – Time – min
8
21 24 27 30
0.1 µF
0.1 µF
50 kΩ
5 V
–5 V
50 kΩ
100 Ω
VO
VIO = VO/1000
0
– 0.04
0.04
+
–
VIO Vµ
aVIO – Temperature Coefficient of
Input Offset Voltage – uV/C
αVIO V/µC
°
IN–
IN+
4
5OUT
10– 0.08
– 0.12
– 0.16
– 0.2
0.08
Pin numbers shown are for the D (14-pin), J, and N
packages.
Figure 36. Effects of Package-Induced Thermal EMF
TLC2654, TLC2654A
Advanced LinCMOS LOW-NOISE CHOPPER-STABILIZED
OPERATIONAL AMPLIFIERS
SLOS020G – NOVEMBER 1988 – REVISED APRIL 2001
24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
4040047/D 10/96
0.228 (5,80)
0.244 (6,20)
0.069 (1,75) MAX 0.010 (0,25)
0.004 (0,10)
1
14
0.014 (0,35)
0.020 (0,51)
A
0.157 (4,00)
0.150 (3,81)
7
8
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.010 (0,25)
PINS **
0.008 (0,20) NOM
A MIN
A MAX
DIM
Gage Plane
0.189
(4,80)
(5,00)
0.197
8
(8,55)
(8,75)
0.337
14
0.344
(9,80)
16
0.394
(10,00)
0.386
0.004 (0,10)
M
0.010 (0,25)
0.050 (1,27)
0°–8°
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
TLC2654, TLC2654A
Advanced LinCMOS LOW-NOISE CHOPPER-STABILIZED
OPERATIONAL AMPLIFIERS
SLOS020G – NOVEMBER 1988 – REVISED APRIL 2001
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER
4040140/D 10/96
28 TERMINAL SHOWN
B
0.358
(9,09)
MAX
(11,63)
0.560
(14,22)
0.560
0.458
0.858
(21,8)
1.063
(27,0)
(14,22)
A
NO. OF
MINMAX
0.358
0.660
0.761
0.458
0.342
(8,69)
MIN
(11,23)
(16,26)
0.640
0.739
0.442
(9,09)
(11,63)
(16,76)
0.962
1.165
(23,83)
0.938
(28,99)
1.141
(24,43)
(29,59)
(19,32)(18,78)
**
20
28
52
44
68
84
0.020 (0,51)
TERMINALS
0.080 (2,03)
0.064 (1,63)
(7,80)
0.307
(10,31)
0.406
(12,58)
0.495
(12,58)
0.495
(21,6)
0.850
(26,6)
1.047
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.035 (0,89)
0.010 (0,25)
121314151618 17
11
10
8
9
7
5
432
0.020 (0,51)
0.010 (0,25)
6
12826 27
19
21
B SQ
A SQ 22
23
24
25
20
0.055 (1,40)
0.045 (1,14)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
TLC2654, TLC2654A
Advanced LinCMOS LOW-NOISE CHOPPER-STABILIZED
OPERATIONAL AMPLIFIERS
SLOS020G – NOVEMBER 1988 – REVISED APRIL 2001
26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
J (R-GDIP-T**) CERAMIC DUAL-IN-LINE PACKAGE
1
20
0.290
(7,87)
0.310
0.975
(24,77)
(23,62)
0.930
(7,37)
0.245
(6,22)
(7,62)
0.300
181614
PINS **
0.290
(7,87)
0.310
0.785
(19,94)
(19,18)
0.755
(7,37)
0.310
(7,87)
(7,37)
0.290
0.755
(19,18)
(19,94)
0.785
0.245
(6,22)
(7,62)
0.300
A
0.300
(7,62)
(6,22)
0.245
A MIN
A MAX
B MAX
B MIN
C MIN
C MAX
DIM
0.310
(7,87)
(7,37)
0.290
(23,10)
0.910
0.300
(7,62)
(6,22)
0.245
0°–15°
Seating Plane
0.014 (0,36)
0.008 (0,20)
4040083/D 08/98
C
8
7
0.020 (0,51) MIN
B
0.070 (1,78)
0.100 (2,54)
0.065 (1,65)
0.045 (1,14)
14 PIN SHOWN
14
0.015 (0,38)
0.023 (0,58)
0.100 (2,54)
0.200 (5,08) MAX
0.130 (3,30) MIN
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification on press ceramic glass frit seal only.
E. Falls within MIL STD 1835 GDIP1-T14, GDIP1-T16, GDIP1-T18, GDIP1-T20, and GDIP1-T22.
TLC2654, TLC2654A
Advanced LinCMOS LOW-NOISE CHOPPER-STABILIZED
OPERATIONAL AMPLIFIERS
SLOS020G – NOVEMBER 1988 – REVISED APRIL 2001
27
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE PACKAGE
0.310 (7,87)
0.290 (7,37)
0.014 (0,36)
0.008 (0,20)
Seating Plane
4040107/C 08/96
5
4
0.065 (1,65)
0.045 (1,14)
8
1
0.020 (0,51) MIN
0.400 (10,20)
0.355 (9,00)
0.015 (0,38)
0.023 (0,58)
0.063 (1,60)
0.015 (0,38)
0.200 (5,08) MAX
0.130 (3,30) MIN
0.245 (6,22)
0.280 (7,11)
0.100 (2,54)
0°–15°
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification on press ceramic glass frit seal only.
E. Falls within MIL-STD-1835 GDIP1-T8
TLC2654, TLC2654A
Advanced LinCMOS LOW-NOISE CHOPPER-STABILIZED
OPERATIONAL AMPLIFIERS
SLOS020G – NOVEMBER 1988 – REVISED APRIL 2001
28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
N (R-PDIP-T**) PLASTIC DUAL-IN-LINE PACKAGE
20
0.975
(24,77)
0.940
(23,88)
18
0.920
0.850
14
0.775
0.745
(19,69)
(18,92)
16
0.775
(19,69)
(18,92)
0.745
A MIN
DIM
A MAX
PINS **
0.310 (7,87)
0.290 (7,37)
(23.37)
(21.59)
Seating Plane
0.010 (0,25) NOM
14/18 PIN ONLY
4040049/C 08/95
9
8
0.070 (1,78) MAX
A
0.035 (0,89) MAX 0.020 (0,51) MIN
16
1
0.015 (0,38)
0.021 (0,53)
0.200 (5,08) MAX
0.125 (3,18) MIN
0.240 (6,10)
0.260 (6,60)
M
0.010 (0,25)
0.100 (2,54) 0°–15°
16 PIN SHOWN
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001 (20 pin package is shorter then MS-001.)
TLC2654, TLC2654A
Advanced LinCMOS LOW-NOISE CHOPPER-STABILIZED
OPERATIONAL AMPLIFIERS
SLOS020G – NOVEMBER 1988 – REVISED APRIL 2001
29
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
P (R-PDIP-T8) PLASTIC DUAL-IN-LINE PACKAGE
4040082/B 03/95
0.310 (7,87)
0.290 (7,37)
0.010 (0,25) NOM
0.400 (10,60)
0.355 (9,02)
58
41
0.020 (0,51) MIN
0.070 (1,78) MAX
0.240 (6,10)
0.260 (6,60)
0.200 (5,08) MAX
0.125 (3,18) MIN
0.015 (0,38)
0.021 (0,53)
Seating Plane
M
0.010 (0,25)
0.100 (2,54) 0°–15°
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
5962-9089502M2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
5962-9089502MCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type
5962-9089502MPA ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type
5962-9089504QCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type
5962-9089504QPA ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type
TLC2654AC-8D ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC2654AC-8DG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC2654AC-8DR OBSOLETE SOIC D 8 TBD Call TI Call TI
TLC2654ACP ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TLC2654ACPE4 ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TLC2654AI-8D ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC2654AI-8DG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC2654AIP ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TLC2654AIPE4 ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TLC2654AMJB ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type
TLC2654AMJGB ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type
TLC2654AQ-8D ACTIVE SOIC D 8 75 TBD CU NIPDAU Level-1-220C-UNLIM
TLC2654AQ-8DG4 ACTIVE SOIC D 8 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC2654C-14D OBSOLETE SOIC D 14 TBD Call TI Call TI
TLC2654C-14DR ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC2654C-14DRG4 ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC2654C-8D ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC2654C-8DG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC2654C-8DR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC2654C-8DRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC2654CN ACTIVE PDIP N 14 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TLC2654CNE4 ACTIVE PDIP N 14 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TLC2654CP ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TLC2654CPE4 ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
PACKAGE OPTION ADDENDUM
www.ti.com 15-Oct-2009
Addendum-Page 1
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TLC2654I-8D ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC2654I-8DG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC2654I-8DR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC2654I-8DRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC2654IP ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TLC2654IPE4 ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TLC2654MFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
TLC2654MJB OBSOLETE CDIP J 14 TBD Call TI Call TI
TLC2654MJGB ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type
TLC2654Q-8D ACTIVE SOIC D 8 75 TBD CU NIPDAU Level-1-220C-UNLIM
TLC2654Q-8DG4 ACTIVE SOIC D 8 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 15-Oct-2009
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm) W
(mm) Pin1
Quadrant
TLC2654C-14DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
TLC2654C-8DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLC2654I-8DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Mar-2008
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLC2654C-14DR SOIC D 14 2500 346.0 346.0 33.0
TLC2654C-8DR SOIC D 8 2500 346.0 346.0 29.0
TLC2654I-8DR SOIC D 8 2500 346.0 346.0 29.0
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Mar-2008
Pack Materials-Page 2
MECHANICAL DATA
MLCC006B – OCTOBER 1996
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER
4040140/D 10/96
28 TERMINAL SHOWN
B
0.358
(9,09)
MAX
(11,63)
0.560
(14,22)
0.560
0.458
0.858
(21,8)
1.063
(27,0)
(14,22)
A
NO. OF
MINMAX
0.358
0.660
0.761
0.458
0.342
(8,69)
MIN
(11,23)
(16,26)
0.640
0.739
0.442
(9,09)
(11,63)
(16,76)
0.962
1.165
(23,83)
0.938
(28,99)
1.141
(24,43)
(29,59)
(19,32)(18,78)
**
20
28
52
44
68
84
0.020 (0,51)
TERMINALS
0.080 (2,03)
0.064 (1,63)
(7,80)
0.307
(10,31)
0.406
(12,58)
0.495
(12,58)
0.495
(21,6)
0.850
(26,6)
1.047
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.035 (0,89)
0.010 (0,25)
12
1314151618 17
11
10
8
9
7
5
432
0.020 (0,51)
0.010 (0,25)
6
12826 27
19
21
B SQ
A SQ 22
23
24
25
20
0.055 (1,40)
0.045 (1,14)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
MECHANICAL DATA
MCER001A – JANUARY 1995 – REVISED JANUAR Y 1997
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE
0.310 (7,87)
0.290 (7,37)
0.014 (0,36)
0.008 (0,20)
Seating Plane
4040107/C 08/96
5
4
0.065 (1,65)
0.045 (1,14)
8
1
0.020 (0,51) MIN
0.400 (10,16)
0.355 (9,00)
0.015 (0,38)
0.023 (0,58)
0.063 (1,60)
0.015 (0,38)
0.200 (5,08) MAX
0.130 (3,30) MIN
0.245 (6,22)
0.280 (7,11)
0.100 (2,54)
0°–15°
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP1-T8
MECHANICAL DATA
MPDI001A – JANUARY 1995 – REVISED JUNE 1999
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
P (R-PDIP-T8) PLASTIC DUAL-IN-LINE
8
4
0.015 (0,38)
Gage Plane
0.325 (8,26)
0.300 (7,62)
0.010 (0,25) NOM
MAX
0.430 (10,92)
4040082/D 05/98
0.200 (5,08) MAX
0.125 (3,18) MIN
5
0.355 (9,02)
0.020 (0,51) MIN
0.070 (1,78) MAX
0.240 (6,10)
0.260 (6,60)
0.400 (10,60)
1
0.015 (0,38)
0.021 (0,53)
Seating Plane
M
0.010 (0,25)
0.100 (2,54)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
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