74HCT273N,652 - NXP - Datasheet.Directory

1. General description

The 74HC273; 74HCT273 is an octal positive-edge triggered D-type flip-flop. The device

features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the st ate of

their corresponding Dn inputs that meet the set-up and hold time requirements on the

LOW-to- HIGH clock (CP) transition. A LOW on MR forces the outpu ts LOW indepen dently

of clock and data inputs. Inputs include clamp diodes. This enables the use of current

limiting resistors to interface inputs to voltages in excess of VCC.

2. Features and benefits

Input levels:

For 74HC273: CMOS level

For 74HCT273: TTL level

Common clock and master reset

Eight positive edge-triggered D-type flip-flops

Complies with JEDEC standard no. 7A

ESD protection:

HBM JESD22-A114F exceeds 2000 V

MM JESD22-A115 -A ex ce ed s 20 0 V.

Multiple package options

Specified from 40 Cto+85C and from 40 Cto+125C

3. Ordering information

74HC273; 74HCT273

Octal D-type flip-flop with reset; positive-edge trigger

Rev. 4 — 10 June 2013 Product data sheet

Table 1. Ordering information

Type number Package

Temperatu re range Name Description Version

74HC273N 40 C to +125 C DIP20 plastic dual in-line package; 20 leads (300 mil) SOT146-1

74HCT273N

74HC273D 40 C to +125 C SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1

74HCT273D

74HC273DB 40 C to +125 C SSOP20 plastic shrink small outline package; 20 leads; body width

5.3 mm SOT339-1

74HCT273DB

Product data sheet Rev. 4 — 10 June 2013 2 of 21

NXP Semiconductors 74HC273; 74HCT273

Octal D-type flip-flop with reset; positive-edge trigger

4. Functional diagram

74HC273PW 40 C to +125 C TSSOP20 plastic thin shrink small outline package; 20 leads; body

width 4.4 mm SOT360-1

74HCT273PW

74HC273BQ 40 C to +125 C DHVQFN20 plastic dual in-line compatible thermal enhanced very thin

quad flat package; no leads; 20 terminals;

body 2.5 4.5 0.85 mm

SOT764-1

74HCT273BQ

Table 1. Ordering information …continued

Type number Package

Temperatu re range Name Description Version

Fig 1. Functional diagram Fig 2. Logic symbol Fig 3. IEC logic symbol

001aae055

FF1

FF8

mna763

D7 MR

CP Q0

mna764

11 C1

1D 2

Product data sheet Rev. 4 — 10 June 2013 3 of 21

NXP Semiconductors 74HC273; 74HCT273

Octal D-type flip-flop with reset; positive-edge trigger

Fig 4. Logic diagra m

001aae056

FF8

FF7

FF6

FF5

FF4

FF3

FF2

CPCPCPCP

FF1

Product data sheet Rev. 4 — 10 June 2013 4 of 21

NXP Semiconductors 74HC273; 74HCT273

Octal D-type flip-flop with reset; positive-edge trigger

5. Pinning information

5.1 Pinning

5.2 Pin description

(1) This is not a supply pin. The substrate is attached to this

pad using conductive die attach material. There is no

electrical or mechanical requirement to solder this pad.

However, if it is soldered, the solder land should remain

floating or be connected to GND.

Fig 5. Pin configuration DIP20, SO20, SSOP20 and

TSSOP20 Fig 6. Pin configuration DHVQFN20

74HC273

74HCT273

MR V

Q0 Q7

D0 D7

D1 D6

Q1 Q6

Q2 Q5

D2 D5

D3 D4

Q3 Q4

GND CP

001aae053

001aae054

74HC273

74HCT273

Transparent top view

D2 D5

Q2 Q5

Q1 Q6

D1 D6

D0 D7

Q0 Q7

GND

912

8 13

7 14

6 15

5 16

4 17

3 18

2 19

terminal 1

index area

GND

(1)

Table 2. Pin de scription

Symbol Pin Description

MR 1 master reset input (active LOW)

Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7 2, 5, 6, 9, 12, 15, 16, 19 flip-flop output

D0, D1, D2, D3, D4, D5, D6, D7 3, 4, 7, 8, 13, 14, 17, 18 data input

GND 10 ground (0 V)

CP 11 clock input (LOW-to-HIGH, edge-triggered)

VCC 20 supply voltage

Product data sheet Rev. 4 — 10 June 2013 5 of 21

NXP Semiconductors 74HC273; 74HCT273

Octal D-type flip-flop with reset; positive-edge trigger

6. Functional description

[1] H = HIGH voltage level;

h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;

L = LOW voltage level;

l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;

X = don’t care;

 = LOW-to-HIGH clock transition.

7. Limiting values

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

[2] For DIP20 package: above 70 C the value of Ptot derates linearly with 12 mW/K.

[3] For SO20 package: above 70 C the value of Ptot derates linearly with 8 mW/K.

For SSOP20 and TSSOP20 packages: above 60 C the value of Ptot derates linearly with 5.5 mW/K.

For DHVQFN20 packages: Ptot derates linearly with 4.5 mW/K above 60 C.

Table 3. Function table[1]

Operating modes Inputs Outputs

MR CP Dn Qn

reset (clear) L X X L

load “1” H hH

load “0” H lL

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V)

Symbol Parameter Conditions Min Max Unit

VCC supply voltage 0.5 +7 V

IIK input clamping current VI < 0.5 V or VI>V

CC +0.5V [1] -20 mA

IOK output clamping current VO < 0.5 V or VO>V

CC +0.5V [1] -20 mA

IOoutput current 0.5 V < VO< VCC +0.5V - 25 mA

ICC supply current - 50 mA

IGND ground current 50 - mA

Tstg storage temperature 65 +150 C

Ptot total power dissipation Tamb = 40 C to +125 C

DIP20 package [2] - 750 mW

SO20, SSOP20, TSSOP20 and

DHVQFN20 package [3] - 500 mW

Product data sheet Rev. 4 — 10 June 2013 6 of 21

NXP Semiconductors 74HC273; 74HCT273

Octal D-type flip-flop with reset; positive-edge trigger

8. Recommended operating conditions

9. Static characteristics

Table 5. Re commended operating conditions

Voltages are referenced to GND (ground = 0 V)

Symbol Parameter Conditions 74HC273 74HCT273 Unit

Min Typ Max Min Typ Max

VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V

VIinput voltage 0 - VCC 0-V

CC V

VOoutput voltage 0 - VCC 0-V

CC V

Tamb ambient temperature 40 - +125 40 - +125 C

t/V input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V

VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V

VCC = 6.0 V - - 83 - - - ns/V

Table 6. Static characteristics

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit

Min Typ Max Min Max Min Max

74HC273

VIH HIGH-level

input voltage VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V

VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V

VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V

VIL LOW-level

input voltage VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V

VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V

VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V

VOH HIGH-level

output voltage VI = VIH or VIL

IO = 20 A; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V

IO = 20 A; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V

IO = 20 A; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V

IO = 4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V

IO = 5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V

VOL LOW-level

output voltage VI = VIH or VIL

IO = 20 A; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V

IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V

IO = 20 A; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V

IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V

IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V

IIinput leakage

current VI = VCC or GND;

VCC =6.0V --0.1 - 1-1A

ICC supply current VI = VCC or GND; IO=0A;

VCC =6.0V - - 8.0 - 80 - 160 A

Product data sheet Rev. 4 — 10 June 2013 7 of 21

NXP Semiconductors 74HC273; 74HCT273

Octal D-type flip-flop with reset; positive-edge trigger

10. Dynamic characteristics

CIinput

capacitance -3.5- - - - -pF

74HCT273

VIH HIGH-level

input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V

VIL LOW-level

input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V

VOH HIGH-level

output voltage VI = VIH or VIL; VCC = 4.5 V

IO = 20 A 4.4 4.5 - 4.4 - 4.4 - V

IO = 4.0 mA 3.98 4.32 - 3.84 - 3.7 - V

VOL LOW-level

output voltage VI = VIH or VIL; VCC = 4.5 V

IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V

IO = 5.2 mA; VCC = 5.5 V - 0.15 0.26 - 0.33 - 0.4 V

IIinput leakage

current VI = VCC or GND;

VCC =5.5V --0.1 - 1-1A

ICC supply current VI = VCC or GND; IO=0A;

VCC =5.5V - - 8.0 - 80 - 160 A

ICC additional

supply current per input pin;

VI=V

CC 2.1 V;

other inputs at VCC or GND;

VCC = 4.5 V to 5.5 V

MR input - 100 360 - 450 - 490 A

CP input - 175 630 - 787.5 - 857.5 A

Dn input - 15 54 - 67.5 - 73.5 A

CIinput

capacitance -3.5- - - - -pF

Table 6. Static characteristics …continued

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit

Min Typ Max Min Max Min Max

Table 7. Dynamic characteristics

GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 10

Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit

Min Typ Max Min Max Min Max

74HC273

tpd propagation

delay CP to Qn; see Figure 7 [1]

VCC = 2.0 V - 41 150 - 185 - 225 ns

VCC = 4.5 V - 15 30 - 37 - 45 ns

VCC = 5.0 V; CL=15pF - 15 - - - - - ns

VCC = 6.0 V - 13 2 6 - 31 - 38 ns

Product data sheet Rev. 4 — 10 June 2013 8 of 21

NXP Semiconductors 74HC273; 74HCT273

Octal D-type flip-flop with reset; positive-edge trigger

tPHL HIGH to LOW

propagation

delay

MR to Qn; see Figure 8

VCC = 2.0 V - 44 150 - 185 - 225 ns

VCC = 4.5 V - 16 30 - 37 - 45 ns

VCC = 5.0 V; CL=15pF - 15 - - - - - ns

VCC = 6.0 V - 14 2 6 - 31 - 38 ns

tttransition time Qn output; see Figure 7 [2]

VCC = 2.0 V - 19 75 - 95 - 110 ns

VCC = 4.5 V - 7 15 - 19 - 22 ns

VCC = 6.0 V - 6 13 - 15 - 19 ns

tWpulse width CP input HIGH or LOW;

see Figure 7

VCC = 2.0 V 80 14 - 100 - 120 - ns

VCC = 4.5 V 16 5 - 20 - 24 - ns

VCC = 6.0 V 14 4 - 17 - 20 - ns

MR input LOW;

see Figure 8

VCC = 2.0 V 60 17 - 75 - 90 - ns

VCC = 4.5 V 12 6 - 15 - 18 - ns

VCC = 6.0 V 10 5 - 13 - 15 - ns

trec recovery time MR to CP; see Figure 8

VCC = 2.0 V 50 6 - 65 - 75 - ns

VCC = 4.5 V 10 2 - 13 - 15 - ns

VCC = 6.0 V 9 2- 11 - 13 - ns

tsu set-up time Dn to CP; see Figure 9

VCC = 2.0 V 60 11 - 75 - 90 - ns

VCC = 4.5 V 12 4 - 15 - 18 - ns

VCC = 6.0 V 10 3 - 13 - 15 - ns

thhold time Dn to CP; see Figure 9

VCC = 2.0 V 3 6- 3 - 3 - ns

VCC = 4.5 V 3 2- 3 - 3 - ns

VCC = 6.0 V 3 2- 3 - 3 - ns

fmax maximum

frequency CP input; see Figure 7

VCC = 2.0 V 6 20.6 - 4.8 - 4 - MHz

VCC = 4.5 V 30 103 - 24 - 20 - MHz

VCC = 5.0 V; CL=15pF - 66 - - - - - MHz

VCC = 6.0 V 35 122 - 28 - 24 - MHz

CPD power

dissipation

capacitance

per package;

VI=GNDtoV

[3] -20- - - - - pF

Table 7. Dynamic characteristics …continued

GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 10

Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit

Min Typ Max Min Max Min Max

Product data sheet Rev. 4 — 10 June 2013 9 of 21

NXP Semiconductors 74HC273; 74HCT273

Octal D-type flip-flop with reset; positive-edge trigger

[1] tpd is the same as tPHL and tPLH.

[2] tt is the same as tTHL and tTLH.

[3] CPD is used to determine the dynamic power dissipation (PD in W).

PD = CPD  VCC2  fi + (CL  VCC2  fo) where:

fi = input frequency in MHz;

fo = output frequency in MHz;

 (CL  VCC2  fo) = sum of outputs;

CL = output load capacitance in pF;

VCC = supply voltage in V.

74HCT273

tpd propagation

delay CP to Qn; see Figure 7 [1]

VCC = 4.5 V - 16 30 - 38 - 45 ns

VCC = 5.0 V; CL=15pF - 15 - - - - - ns

tPHL HIGH to LOW

propagation

delay

MR to Qn; see Figure 8

VCC = 4.5 V - 23 34 - 43 - 51 ns

VCC = 5.0 V; CL=15pF - 20 - - - - - ns

tttransition time Qn output; see Figure 7 [2]

VCC = 4.5 V - 7 15 - 19 - 22 ns

tWpulse width CP input; see Figure 7

VCC = 4.5 V 16 9 - 20 - 24 - ns

MR input LOW;

see Figure 8

VCC = 4.5 V 16 8 - 20 - 24 - ns

trec recovery time MR to CP; see Figure 8

VCC = 4.5 V 10 2 - 13 - 15 - ns

tsu set-up time Dn to CP; see Figure 9

VCC = 4.5 V 12 5 - 15 - 18 - ns

thhold time Dn to CP; see Figure 9

VCC = 4.5 V 3 4- 3 - 3 - ns

fmax maximum

frequency CP input; see Figure 7

VCC = 4.5 V 30 56 - 24 - 20 - MHz

VCC = 5.0 V; CL=15pF - 36 - - - - - MHz

CPD power

dissipation

capacitance

per package;

VI=GNDtoV

CC  1.5 V [3] -23- - - - - pF

Table 7. Dynamic characteristics …continued

GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 10

Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit

Min Typ Max Min Max Min Max

Product data sheet Rev. 4 — 10 June 2013 10 of 21

NXP Semiconductors 74HC273; 74HCT273

Octal D-type flip-flop with reset; positive-edge trigger

11. Waveforms

Measurement points are given in Table 8.

VOL and VOH are typical voltage output levels that occur with the output load.

Fig 7. Propagation delay clock input (CP) to output (Qn), clock (CP) pulse width, output transition time and the

maximum clock pulse freq uency

001aae062

CP input

Qn output

PHL

PLH

10%

90%

GND

1/f

max

THL

TLH

Measurement points are given in Table 8.

VOL and VOH are typical voltage output levels that occur with the output load.

Fig 8. Pro pagation delay master reset (MR) to output (Qn ), pulse width master reset (MR) and recovery time

master reset (MR) to clock (CP)

mna464

MR input

CP input

Qn output

tPHL

tWtrec

GND

VOL

GND

VOH

Product data sheet Rev. 4 — 10 June 2013 11 of 21

NXP Semiconductors 74HC273; 74HCT273

Octal D-type flip-flop with reset; positive-edge trigger

Measurement points are given in Table 8.

The shaded areas indicate when the input is permitted to change for predictable output performance.

VOL and VOH are typical voltage output levels that occur with the output load.

Fig 9. Dat a set-u p an d hold times data input (Dn)

mna767

GND

Qn output

CP input

Dn input

Table 8. Measur ement points

Type Input Output

VIVMVM

74HC273 VCC 0.5VCC 0.5VCC

74HCT273 3 V 1.3 V 1.3 V

Product data sheet Rev. 4 — 10 June 2013 12 of 21

NXP Semiconductors 74HC273; 74HCT273

Octal D-type flip-flop with reset; positive-edge trigger

Test data is given in Table 9.

Definitions for test circuit:

RT = Termination resistance should be equal to output impedance Zo of the pulse generator.

CL = Load capacitance including jig and probe capacitance.

RL = Load resistance.

S1 = Test selection switch

Fig 10. Test circuit for measuring switching times

10 %

90 %

0 V

negative

pulse

positive

pulse

0 V

90 %

10 %

001aad983

DUT

VIVO

RLS1

open

Table 9. Test data

Type Input Load S1 position

VItr, tfCLRLtPHL, tPLH

74HC273 VCC 6ns 15pF, 50 pF 1kopen

74HCT273 3V 6ns 15pF, 50 pF 1kopen

Product data sheet Rev. 4 — 10 June 2013 13 of 21

NXP Semiconductors 74HC273; 74HCT273

Octal D-type flip-flop with reset; positive-edge trigger

12. Package outline

Fig 11. Package outline SOT146-1 (DIP20)

UNIT A

max. 1 2 b1cD E e M

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

SOT146-1 99-12-27

03-02-13

min. A

max. bZ

max.

1.73

1.30 0.53

0.38 0.36

0.23 26.92

26.54 6.40

6.22 3.60

3.05 0.2542.54 7.62 8.25

7.80 10.0

8.3 24.2 0.51 3.2

0.068

0.051 0.021

0.015 0.014

0.009 1.060

1.045 0.25

0.24 0.14

0.12 0.010.1 0.3 0.32

0.31 0.39

0.33 0.0780.17 0.02 0.13

SC-603MS-001

(e )

seating plane

pin 1 index

0 5 10 mm

scale

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

(1)

(1) (1)

DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1

Product data sheet Rev. 4 — 10 June 2013 14 of 21

NXP Semiconductors 74HC273; 74HCT273

Octal D-type flip-flop with reset; positive-edge trigger

Fig 12. Package outline SOT163-1 (SO20)

UNIT A

max. A1A2A3bpcD

(1) E(1) (1)

ELL

pQZ

ywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

2.65 0.3

0.1 2.45

2.25 0.49

0.36 0.32

0.23 13.0

12.6 7.6

7.4 1.27 10.65

10.00 1.1

1.0 0.9

0.4 8

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.1

0.4

SOT163-1

detail X

0.25

075E04 MS-013

pin 1 index

0.1 0.012

0.004 0.096

0.089 0.019

0.014 0.013

0.009 0.51

0.49 0.30

0.29 0.05

1.4

0.055

0.419

0.394 0.043

0.039 0.035

0.016

0.01

0.25

0.01 0.004

0.043

0.016

0.01

0 5 10 mm

scale

vMA

(A )

SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1

99-12-27

03-02-19

Product data sheet Rev. 4 — 10 June 2013 15 of 21

NXP Semiconductors 74HC273; 74HCT273

Octal D-type flip-flop with reset; positive-edge trigger

Fig 13. Package outline SOT339-1 (SSOP20)

UNIT A1A2A3bpcD

(1) E(1) eH

ELL

pQ(1)

Zywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.21

0.05 1.80

1.65 0.38

0.25 0.20

0.09 7.4

7.0 5.4

5.2 0.65 7.9

7.6 0.9

0.7 0.9

0.5 8

0.131.25 0.2 0.1

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.

1.03

0.63

SOT339-1 MO-150 99-12-27

03-02-19

detail X

vMA

(A )

110

20 11

0.25

pin 1 index

0 2.5 5 mm

scale

SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1

max.

Product data sheet Rev. 4 — 10 June 2013 16 of 21

NXP Semiconductors 74HC273; 74HCT273

Octal D-type flip-flop with reset; positive-edge trigger

Fig 14. Package outline SOT360-1 (TSSOP20)

UNIT A1A2A3bpcD

(1) E(2) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05 0.95

0.80 0.30

0.19 0.2

0.1 6.6

6.4 4.5

4.3 0.65 6.6

6.2 0.4

0.3 0.5

0.2 8

0.13 0.10.21

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

0.75

0.50

SOT360-1 MO-153 99-12-27

03-02-19

0.25

110

20 11

pin 1 index

detail X

(A )

vMA

0 2.5 5 mm

scale

TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1

max.

1.1

Product data sheet Rev. 4 — 10 June 2013 17 of 21

NXP Semiconductors 74HC273; 74HCT273

Octal D-type flip-flop with reset; positive-edge trigger

Fig 15. Package outline SOT764-1 (DHVQFN20)

terminal 1

index area

0.51

A1Eh

UNIT ye

0.2

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 4.6

4.4

3.15

2.85

2.6

2.4 1.15

0.85

3.5

0.30

0.18

0.05

0.00 0.05 0.1

DIMENSIONS (mm are the original dimensions)

SOT764-1 MO-241 - - -- - -

0.5

0.3

0.1

0.05

0 2.5 5 mm

scale

SOT764-1

DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;

20 terminals; body 2.5 x 4.5 x 0.85 mm

A(1)

max.

AA1c

detail X

y1C

19 12

terminal 1

index area

E(1)

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

D(1)

02-10-17

03-01-27

Product data sheet Rev. 4 — 10 June 2013 18 of 21

NXP Semiconductors 74HC273; 74HCT273

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13. Abbreviations

14. Revision history

Table 10. Abbreviations

Acronym Description

CMOS Complementary Metal-Oxide Semiconductor

DUT Device Under Test

ESD ElectroSt atic Discharge

HBM Human Body Model

MM Machine Model

TTL Transistor-Transistor Logic

Table 11. Revision history

Document ID Release date Data sheet status Change notice Supersedes

74HC_HCT273 v.4 20130610 Product data sheet - 74HC_HCT273 v.3

Modifications: •The format of this data sheet has been redesigned to comply with the new iden tity

guidelines of NXP Semiconductors.

•Legal texts have been adapted to the new company name where appropriate.

74HC_HCT273 v.3 20060124 Product data sheet - 74HC_HCT273_CNV v.2

74HC_HCT273_CNV v.2 19970827 Product specification - -

Product data sheet Rev. 4 — 10 June 2013 19 of 21

NXP Semiconductors 74HC273; 74HCT273

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15. Legal information

15.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

15.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and

full information. For detailed and full information se e the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall pre vail.

Product specificat ion — The information and data provided in a Product

data sheet shall define the specification of the product as agreed be tween

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to off er functions and qualities beyond those described in the

Product data sheet.

15.3 Disclaimers

Limited warr a nty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Se miconductors takes no

responsibility for the content in this document if provided by an inf ormation

source outside of NXP Semiconductors.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequ ential damages (including - wit hout limitatio n - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ ag gregate and cumulative l iability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in life support, life-crit ical or

safety-critical systems or equipment, nor in app lications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in perso nal injury, death or severe property or environme ntal

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconducto rs products in such equipment or

applications and ther efore such inclu sion and/or use is at the cu stomer’s own

risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty tha t such application s will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and ope ration of their applications

and products using NXP Semiconductors product s, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suit able and fit for the custome r’s applications and

products planned, as well as fo r the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for th e customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings onl y and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanent ly and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individua l agreement. In case an individual

agreement is concluded only the ter ms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing i n this document may be interpreted or

construed as an of fer t o sell product s that is open for accept ance or t he grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the obj ective specification for product development .

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.

Product [short] dat a sheet Production This document contains the prod uct specification.

Product data sheet Rev. 4 — 10 June 2013 20 of 21

NXP Semiconductors 74HC273; 74HCT273

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Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product i s automotive qualified,

the product is not suitable for automo tive use. It i s neit her qualif ied nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

non-automotive qualified products in automo tive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automot ive specifications and standard s, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from custome r design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

15.4 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respect i ve ow ners.

16. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

NXP Semiconductors 74HC273; 74HCT273

Octal D-type flip-flop with reset; positive-edge trigger

For more information, please visit: http://www.nxp.co m

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 10 June 2013

Document identifier: 74HC_HCT273

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

17. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 1

4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

6 Functional description . . . . . . . . . . . . . . . . . . . 5

7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5

8 Recommended operating conditions. . . . . . . . 6

9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6

10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7

11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13

13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 18

14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 18

15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 19

15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 19

15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 19

15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 20

16 Contact information. . . . . . . . . . . . . . . . . . . . . 20

17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21