PF1061-04 SRM2AV413LLBT8 4M-bit Static RAM ge olta V ow er L n Sup eratio ts Op oduc Pr Super Low Voltage Operation and Low Current Consumption Access Time 85ns (2.4V) 262,144 Words x 16-bit Asynchronous Wide Temperature Range DESCRIPTION The SRM2AV413LLBT8 is a 262,144words x 16-bit asynchronous, random access memory on a monolithic CMOS chip. Its very low standby power requirement makes it ideal for applications requiring non-volatile storage with back-up batteries. The asynchronous and static nature of the memory requires no external clock and no refreshing circuit. It is possible to control the data width by the data byte control. 3-state output allows easy expansion of memory capacity. The temperature range of the SRM2AV413LLBT8 is from -40 to 85C, and it is suitable for the industrial products. FEATURES Fast Access time ........................ 85ns (2.4V) Low supply current ..................... LL Version Completely static ........................ No clock required Supply voltage ............................ 2.4V to 3.3V 3-state output with wired-OR capability Non-volatile storage with back-up batteries Package ..................................... SRM2AV413LLBT TFBGA-48 pin (Tape CSP) CS2 LB UB OE WE X Decoder Memory Cell Array 1024 x 256 x 16 8 Y Decoder 256x16 256 Column Gate 16 I/O Buffer I/O1 Rev.1.2 1024 CS1,CS2 Control Logic CS1 K 10 LB , UB OE , WE Control Logic A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 Address Buffer BLOCK DIAGRAM I/O16 1 SRM2AV413LLBT8 PIN CONFIGURATION TFBGA-48 pin SRM2AV413LLBT 1 2 3 4 5 6 A LB OE A0 A1 A2 CS2 B I/O9 UB A3 A4 CS1 I/O1 C I/O10 I/O11 A5 A6 I/O2 I/O3 D VSS I/O12 A17 A7 I/O4 VDD E VDD I/O13 NC A16 I/O5 VSS F I/O15 I/O14 A14 A15 I/O6 I/O7 G I/O16 NC H NC A8 A12 A13 A9 WE I/O8 A10 A11 NC Top view (Looking through part) PIN DESCRIPTION A0 to A17 WE OE CS1 CS2 LB UB I/O1 to 16 VDD VSS NC 2 Address Input Write Enable Output Enable Chip Select1 Chip Select2 LOWER Byte Enable UPPER Byte Enable Data I/O Power Supply (2.4V to 3.3V) Power Supply (0V) No connection Rev.1.2 SRM2AV413LLBT8 ABSOLUTE MAXIMUM RATINGS Parameter Supply voltage Input voltage Input/Output voltage Power dissipation Operating temperature Storage temperature Soldering temperature and time * VI,VI/O Symbol VDD VI VI/O PD Topr Tstg Tsol (Min.) = -2.0V (when pulse width is less than 50ns) DC RECOMMENDED OPERATING CONDITIONS Parameter Symbol VDD VSS VIH VIL Supply voltage Input voltege * if (VSS=0V) Unit V V V W C C - Ratings - 0.5 to 4.0 - 0.5 * to VDD + 0.3 - 0.5 * to VDD + 0.3 0.5 - 40 to 85 - 65 to 150 260C, 10s (at lead) (Ta = -40 to 85 C) VDD = 2.7 to 3.3V Unit Max. Min. Typ. 3.3 2.7 3.0 V 0.0 0.0 0.0 V VDD+0.3 2.0 - V - 0.3 * - 0.6 V VDD = 2.4 to 3.3V Max. Min. Typ. 3.3 2.4 3.0 0.0 0.0 0.0 VDD+0.3 0.75VDD - - 0.3 - 0.3* pulse width is less than 50ns it is - 2.0V ELECTRICAL CHARACTERISTICS DC Electrical Characteristics Parameter Symbol ILI Input leakage current Conditions (VSS =0V, Ta = -40 to 85 C) VDD = 2.4 to 3.3V Unit Max. Min. Typ. *1 VI = 0 to VDD -1.0 - 1.0 A -1.0 - 1.0 A 2.0 VDD-0.2 - - - - - - - - 0.4 0.2 V - - 1.0 mA Output leakage current ILO LB and UB = VIH or CS1 = VIH or CS2 = VIL or WE=VIL or OE = VIH, VI/O = 0 to VDD High level output voltage VOH IOH Low level output voltage VOL IOL IDDS Standby supply current IDDS1 -0.5mA -100A 1.0mA 100A CS1 = VIH or CS2= VIL CS1 = CS2 VDD - 0.2V or CS2 0.2V Ta 25C, VDD 3.0V IDDA VI = VIL or VIH II/O = 0mA, tcyc = Min. IDDA1 VI = VIL or VIH II/O = 0mA, tcyc = 1s Average operating current IDDO - - 15 - 0.5 1.0 A - 25 35 mA 4.0 6.0 4.0 6.0 - VI = VIL or VIH II/O = 0mA Operating Supply Current V - K mA mA *1 : Typical values are measured at Ta = 25C and VDD = 3.0V Terminal Capacitance Parameter Address Capacitance Input Capacitance I/O Capacitance (Ta = 25C, f = 1MHz) Symbol Conditions Min. CADD CI CI/O VADD = 0V VI = 0V VI/O = 0V - - - Typ. - - - Max. Unit 8 8 10 pF pF pF Note : This parameter is made by the inspection data of sample, not of all products Rev.1.2 3 SRM2AV413LLBT8 AC Electrical Characteristics Read Cycle Parameter (VSS = 0V, Ta = -40 to 85C) Symbol SRM2AV413LLBT8 2.4 to 3.3V Test Conditions Unit Max. Min. Read cycle time tRC 1 85 - ns Address access time tACC 1 - 85 ns CS1 access time tACS1 1 - 85 ns CS2 access time tACS2 1 - 85 ns OE access time tOE 1 - 45 ns LB, UB access time tAB 1 - 45 ns CS1 output set time tCLZ1 2 - ns CS2 output set time tCLZ2 2 5 5 - ns CS1 output floating tCHZ1 2 - 30 ns CS2 output floating tCHZ2 2 - 30 ns LB, UB output set time tBLZ 2 0 - ns LB, UB output floating tBHZ 2 - 30 OE output set time tOLZ 2 0 - ns ns OE output floating tOHZ 2 - Output hold time tOH 1 5 30 - Write Cycle ns ns (VSS = 0V, Ta = -40 to 85C) Parameter Symbol SRM2AV413LLBT8 2.4 to 3.3V Test Conditions Unit Write cycle time tWC 1 Min. 85 Chip select time (CS1) tCW1 1 70 - ns Chip select time (CS2) tCW2 1 70 - ns Address enable time tAW 1 70 - ns Address setup time tAS 1 0 - ns Write pulse width tWP 1 60 - ns LB, UB select time tBW 1 70 - ns Address hold time tWR 1 0 - ns Data setup time tDW 1 35 ns Data hold time tDH 1 0 - - WE output floating tWHZ 2 - WE output set time tOW 2 5 35 - ns ns *1 Test Conditions Max. - ns ns *2 Test Conditions 1. Input pulse level : 0.3V to 0.8VDD (2.4Vto 3.3V) 1. Input pulse level : 2. tr = tf = 5ns 2. tr = tf = 5ns 0.3V to 0.8VDD(2.4V to 3.3V) 3. Input and output timing reference levels :1/2VDD(2.4V to 3.3V) 3. Input timing reference levels :1/2VDD (2.4V to 3.3V) 4. Output load : CL =50pF (Includes Jig Capacitance) 4. Output timing reference levels : 200mV (The level changed from stable output voltage level) 5. Output load :CL = 5pF (Includes Jig Capacitance) 1TTL I/O I/O CL 4 1TTL CL Rev.1.2 SRM2AV413LLBT8 Timing Chart Read Cycle*1 Write Cycle 1 (CS1 Control) *2, *3 tWC tRC A0 to 17 A0 to 17 CS1 CS2 LB, UB tACC tACS1 tCLZ1 tACS2 tCLZ2 tAB tBLZ OE tOH tCHZ1 tCHZ2 tOE tOLZ I/O1 to 16 (Dout) CS1 tAS tAW tWR tCW1 tCW2 CS2 tBW LB, UB tBHZ WE tOHZ I/O1 to 16 (Dout) tWP High-Z tDW tDH (Din) Write Cycle 2 (CS2 Control) *2, *3 Write Cycle 3 (WE Control)*3 tWC tWC A0 to 17 A0 to 17 tAW CS1 tWR tCW1 tCW1 CS1 tCW2 tCW2 tAS CS2 CS2 tBW LB, UB tAS tWP WE tWP tWR WE High-Z I/O1 to 16 (Dout) tBW LB, UB tDW tDH (Din) I/O1 to 16 (Dout) tWHZ tOW tDW tDH (Din) Write Cycle 4 (UB, LB Control) *3 tWC A0 to 17 tCW1 CS1 tWR tCW2 CS2 tAS tBW LB, UB WE tWP I/O1 to 16 (Dout) High-Z K tDW tDH (Din) Note : *1 During read cycle time, WE is to be "High" level. In write cycle time that is controlled by CS1 or CS2, output buffer is to be "Hi-Z" state even if OE is "Low" level. *3 When output buffer is in output state, be careful that do not input the opposite signals to the output data. *2 DATA RETENTION CHARACTERISTIC WITH LOW VOLTAGE POWER SUPPLY Parameter Symbol Data retention supply voltage VDDR Conditions VDDR = 2.5V Data retention curren IDDR Data hold time Operation recovery time tCDR tR CS1 = CS2 VDD - 0.2V or CS2 0.2V (VSS = 0V, Ta = -40 to 85C) Unit Min. Typ.* Max. 3.3 - 1.2 V - 0.4 13 0 5 - - - - A ns ms * : Reference data at Ta=25C Rev.1.2 5 SRM2AV413LLBT8 Data retention timing (CS2 Control) Data retention timing (CS1 Control) VDD VDD VDDR 1.2V 2.4V tCDR 2.4V 2.4V tCDR tR Data hold time VDDR 1.2V Data hold time 2.4V tR VIH CS1 VDD - 0.2V CS1 0.8xVDD CS2 0.8xVDD VIH 0.3 0.3 VIL VIL CS2 0.2V FUNCTIONS Truth Table CS1 H X L L L L L L L L CS2 X L H H H H H H H H LB X X X H L H L L H L UB X X X H H L L H L L OE X X H X X X X L L L WE X X H X L L L H H H I/O1 to 8 High-Z High-Z High-Z High-Z Data In High-Z Data In DataOut High-Z Data Out I/O9 to 16 High-Z High-Z High-Z High-Z High-Z Data In Data In High-Z DataOut Data Out MODE Not Selected Not Selected Output disable Output disable Lower Byte Write Upper Byte Write All Byte Write Lower Byte Read Upper Byte Read All Byte Read IDD IDDS, IDDS1 IDDS, IDDS1 IDDA, IDDA1 IDDA, IDDA1 IDDA, IDDA1 IDDA, IDDA1 IDDA, IDDA1 IDDA, IDDA1 IDDA, IDDA1 IDDA, IDDA1 X : High or Low Reading data It is possible to control the data width by LB and UB pins. (1) Reading data from lower byte Data is able to be read when the address is set while holding CS1 ="Low",CS2 = "High", OE= "Low", LB ="Low", and WE = "High". (2) Reading data from upper byte Data is able to be read when the address is set while holding CS1= "Low",CS2 = "High", OE = "Low", UB = "Low", and WE ="High". (3) Reading data from both bytes Data is able to be read when the address is set while holding CS1 = "Low",CS2= "High", OE ="Low", UB ="Low", LB = "Low", and WE = "High". Since I/O pins are in "Hi-Z" state when OE = "High", the data bus line can be used for any other objective, then access time apparently is able to be cut down. 6 Rev.1.2 SRM2AV413LLBT8 Writing data (1) Writing data into lower byte There are the following four ways of writing data into memory. i) Hold CS2 = "High",WE = "Low",UB ="High", and LB = "Low",set address and give "Low" pulse to CS1. ii) Hold CS1 = "Low",WE = "Low",UB ="High", and LB = "Low",set address and give "High" pulse to CS2. iii) Hold CS1 = "Low",CS2 = "High",UB ="High", and LB = "Low",set address and give "Low" pulse to WE ix) Hold CS1 = "Low",CS2 = "High",WE ="Low",and UB= "High",set address and give "Low" pulse to LB. Anyway, data on I/O pins are latched up into the memory cell during CS1 ="Low",CS2 = "High",WE and LB ="Low". (2) Writing data into upper byte There are the following four ways of writing data into the memory. i) Hold CS2 ="High",WE ="Low",LB ="High",and UB ="Low",set address and give "Low" pulse to CS1. ii) Hold CS1 ="Low",WE ="Low",LB ="High",and UB ="Low",set address and give "High" pulse to CS2. iii) Hold CS1 ="Low",CS2 ="High",LB ="High",and UB ="Low",set address and give "Low" pulse to WE. ix) Hold CS1="Low",CS2 ="High",WE="Low",and LB="High",set address and give "Low" pulse to UB. Anyway, data on I/O pins are latched up into the memory cell during CS1 ="Low",CS2 = "High",WE and UB ="Low". (3)Writing data into both bytes There are the following four ways of writing data into the memory. i) Hold CS2 = "High", WE = "Low", LB and UB = "Low", set address and give "Low" pulse to CS1. ii) Hold CS1 = "Low", WE = "Low", LB and UB = "Low", set address and give "High" pulse to CS2. iii) Hold CS1 = "Low", CS2 = "High", LB and UB = "Low", set address and give "Low" pulse to WE. ix) Hold CS1 = "Low", CS2 = "High", WE = "Low", set address and give "Low" pulse to LB and UB. Anyway, data on I/Opins are latched up into the memory cell during CS1 = "Low" , CS2 ="High" , WE = "Low", UB and LB = "Low". As DATA I/O pins are in "Hi-Z" when CS1= "High", CS2 = "Low", OE= "High", or LB and UB ="High", the contention on the data bus can be avoided. But while I/O pins are in the output state, the data that is opposite to the output data should not be given. Standby mode When CS1 is "High" or CS2 is "Low" the chip is in the standby mode (only retaining data operation). In this case data I/O pins are Hi-Z, and all inputs of addresses, WE, OE, UB, LB, and data are inhibited. When CS1 = CS2 VDD - 0.2V or CS2 0.2V, there is almost no current flow except through the high resistance parts of the memory. Data retention at low voltage In case of the data retention in the stadby mode, the power supply can be gone down till the specified voltage. But it is impossible to write or read in this mode. Rev.1.2 7 K SRM2AV413LLBT8 PACKAGE DIMENSIONS TFBGA-48 pin BOTTOM VIEW 1 2 3 4 5 6 H 0.75 Typ. F E D C 8.0 0.2 G B A 0.350.05 0.75 Typ. 1.0 Max. 10.0 0.2 0.2 +0.1 -0.05 SIDE VIEW TOP VIEW 1 2 3 4 5 6 A B INDEX C D E F G H SRAM Die Base Tape Unit : mm 8 Rev.1.2 SRM2AV413LLBT8 CHARACTERISTICS CURVES Normalized I DDA -Ta Normalized IDDA -Frequency Normalized I DDA -VDD 1.6 1.6 1.7 VDD =3.0V READ,WRITE 1.6 Ta=25 C READ,WRITE 1.4 1.4 1.5 1.2 1.4 1.3 1.2 Ta=25 C VDD =3.0V 1 WRITE 1.2 READ 1 0.8 1.1 WRITE READ 0.6 1 0.8 WRITE READ 0.9 0.4 0.6 0.8 0.2 0.7 0.6 -60 0.4 0 -40 -20 0 20 Ta (C) 40 60 80 0 2 4 Normalized I DDS1 -Ta 1.6 6 8 10 12 14 16 18 20 Frequency (MHz) 2 2.8 3.2 3.6 4 VDD (V) Normlized I DDS1 -VDD 100 2.4 Normalized IOH -V OH 100 2 Ta=25 C VDD =3.0V Ta=25 C VDD=3.0V 1.8 1.6 10 1.4 10 1.2 1 1 0.8 1 0.6 0.1 0.4 K 0.2 0.1 -60 -40 -20 Rev.1.2 0.01 0 20 40 Ta (C) 60 80 100 0 1.6 2 2.4 2.8 3.2 VDD (V) 3.6 4 0.5 1 1.5 2 2.5 VOH (V) 3 3.5 9 SRM2AV413LLBT8 Normalized tACC tACS1-Ta tACS2 Normalized 1.2 VDD=3.0V Normalized I OL -VOL t ACC t ACS1-VDD t ACS2 2.4 2.5 1.1 Ta=25C VDD =3.0V 2.2 Ta=25C 2 2.0 1.8 1.6 1 1.4 1.5 1.2 1 0.9 1.0 0.8 0.6 0.8 0.5 0.4 0.2 0.7 -60 -40 -20 0.0 0 20 40 Ta (C) 60 80 100 2.2 2.1 2 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 2.5 3 VDD (V) 3.5 4 0 0.2 0.4 0.6 VOL (V) 0.8 1 t ACS1-C L t ACS2 100 10 Ta=25C VDD =3.0V 1 0 100 200 CL (pF) 10 2 Normalized I DDR -Ta t ACC Normalized 0 1.5 300 400 0.1 -60 -40 -20 0 20 40 Ta= (C) 60 80 100 Rev.1.2 SRM2AV413LLBT8 K NOTICE: No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from another government agency. (c) Seiko Epson Corporation 2000 All right reserved. Revised January, 2000 Printed in Japan T Rev.1.2