1Rev.1.2
K
■ DESCRIPTION
The SRM2AV413LLBT8 is a 262,144words x 16-bit asynchronous, random access memory on a monolithic
CMOS chip. Its very low standby power requirement makes it ideal for applications requiring non-volatile storage
with back-up batteries. The asynchronous and static nature of the memory requires no external clock and no
refreshing circuit. It is possible to control the data width by the data byte control. 3-state output allows easy
expansion of memory capacity. The temperature range of the SRM2AV413LLBT8 is from –40 to 85°C, and it is
suitable for the industrial products.
■ FEATURES
● Fast Access time........................ 85ns (2.4V)
● Low supply current ..................... LL Version
● Completely static........................ No clock required
● Supply voltage............................ 2.4V to 3.3V
● 3-state output with wired-OR capability
● Non-volatile storage with back-up batteries
● Package ..................................... SRM2AV413LLBT TFBGA-48 pin (Tape CSP)
4M-bit Static RAM
PF1061-04
SRM2AV413LLBT
8
■ BLOCK DIAGRAM
●Super Low Voltage Operation and Low Current Consumption
●Access Time 85ns (2.4V)
●262,144 Words x 16-bit Asynchronous
●Wide Temperature Range
I/O Buffer
16
I/O1 I/O16
CS1
OE
WE
LB
UB
LB , UB
OE , WE
Control
Logic
CS1,CS2
Control
Logic
10
8
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
Address Buffer
Memory Cell Array
1024 x 256 x 16
Column Gate
1024
256
256x16
X DecoderY Decoder
CS2
Super Low Voltage
Operation
Products
Rev.1.22
SRM2AV413LLBT
8
■ PIN CONFIGURATION
■ PIN DESCRIPTION
A0 to A17
WE
OE
CS1
LB
UB
I/O1 to 16
V
DD
V
SS
NC
Address Input
Write Enable
Output Enable
Chip Select1
Chip Select2
LOWER Byte Enable
UPPER Byte Enable
Data I/O
Power Supply (2.4V to 3.3V)
Power Supply (0V)
No connection
A
B
C
D
E
F
G
H
213456
LB OE A0
A3
A5
A17
NC
A14
A12
A9
A1
A4
A6
A7
A16
A15
A13
A10
A2
CS1
I/O2
I/O4
I/O5
I/O6
WE
A11
CS2
NCNC
I/O1
I/O3
V
DD
V
SS
I/O7
I/O8
UB
I/O9
I/O10 I/O11
I/O12I/O12
I/O13
I/O14
NC
A8
I/O15
I/O16
V
SS
V
DD
TFBGA-48 pin
Top view (Looking through part)
SRM2AV413LLBT
CS2
SRM2AV413LLBT
8
Rev.1.2 3
K
■ ABSOLUTE MAXIMUM RATINGS
■ DC RECOMMENDED OPERATING CONDITIONS
● Terminal Capacitance
■ ELECTRICAL CHARACTERISTICS
● DC Electrical Characteristics
Supply voltage
Input voltage
Input/Output voltage
Power dissipation
Operating temperature
Storage temperature
Soldering temperature and time
Parameter VDD
VI
VI/O
PD
T
opr
T
stg
T
sol
Symbol Ratings Unit
– 0.5 to 4.0
– 0.5
*
to VDD + 0.3
– 0.5
*
to VDD + 0.3
0.5
– 40 to 85
– 65 to 150
260°C, 10s (at lead)
(VSS=0V)
*
VI,VI/O (Min.) = –2.0V (when pulse width is less than 50ns)
V
V
V
W
°C
°C
–
(Ta = –40 to 85 °C)
Parameter
Supply voltage
Input voltege
Symbol
VDD
VSS
VIH
VIL
V
V
V
V
*
if pulse width is less than 50ns it is – 2.0V
Min.
2.4
0.0
0.75VDD
– 0.3
*
Typ.
3.0
0.0
–
–
Max.
3.3
0.0
VDD+0.3
0.3
Min.
2.7
0.0
2.0
– 0.3
*
Typ.
3.0
0.0
–
–
Max.
3.3
0.0
VDD+0.3
0.6
Unit
Parameter Symbol Conditions Unit
Input leakage current
Standby supply current
Average operating current
Operating Supply Current
High level output voltage
ILI
ILO
VOH IOH
Low level output voltage VOL
IDDS
IDDS1
IDDA
IDDA1
IDDO
IOL
µA
(V
SS
=0V, Ta = –40 to 85 °C)
V
DD
= 2.4 to 3.3V
V
DD
= 2.4 to 3.3V V
DD
= 2.7 to 3.3V
V
I
= 0 to V
DD
LB and UB = V
IH
or
CS1 = V
IH
or CS2 = V
IL or
WE=V
IL
or OE = V
IH
, V
I/O
= 0 to V
DD
CS1 = V
IH or
CS2= V
IL
Output leakage current
–1.0
Min. Typ.
*1
Max.
– 1.0
µA–1.0 – 1.0
mA
–
µA
mA
–25 35
mA
–4.0 6.0
mA
– 4.0 6.0
V
V
2.0
V
DD
–0.2
–
–
–
–
–
–
–
–
0.4
0.2
*1 : Typical values are measured at Ta = 25°C and V
DD
= 3.0V
(Ta = 25°C, f = 1MHz)
Parameter Symbol Unit
Conditions
Address Capacitance
Input Capacitance
I/O Capacitance
CADD
CI
CI/O
VADD = 0V
VI = 0V
VI/O = 0V
Max.Min. Typ.
Note : This parameter is made by the inspection data of sample, not of all products
V
I
= V
IL
or V
IH
I
I/O
= 0mA, t
cyc
= Min.
V
I
= V
IL
or V
IH
I
I/O
= 0mA, t
cyc
= 1µs
V
I
= V
IL
or V
IH
I
I/O
= 0mA
–
–
–
–
–
–
8
8
10
pF
pF
pF
–0.5mA
–100µA
1.0mA
100µA
–
–
0.5
–
–
Ta ≤ 25°C, VDD ≤ 3.0V
CS1 = CS2 ≥ VDD – 0.2V
or CS2 ≤ 0.2V
1.0
15
1.0
Rev.1.24
SRM2AV413LLBT
8
1TTL
I/O C
L
*1 Test Conditions
1. Input pulse level : 0.3V to 0.8VDD (2.4Vto 3.3V)
2. tr = tf = 5ns
3. Input and output timing reference levels :1/2VDD (2.4V to 3.3V)
4. Output load : CL =50pF (Includes Jig Capacitance)
*2 Test Conditions
1. Input pulse level : 0.3V to 0.8VDD (2.4V to 3.3V)
2. tr = tf = 5ns
3. Input timing reference levels :1/2VDD (2.4V to 3.3V)
4. Output timing reference levels : ±200mV (The level changed from stable
output voltage level)
5. Output load :CL = 5pF (Includes Jig Capacitance)
❍ Write Cycle
● AC Electrical Characteristics
❍ Read Cycle
1TTL
I/O C
L
Unit
SRM2AV413LLBT
8
2.4 to 3.3V
Min.
85
–
–
–
–
–
5
–
–
0
–
0
–
5
Max.
–
85
85
85
45
45
–
–
30
30
–
30
–
30
Parameter Symbol Test
Conditions
(V
SS
= 0V, Ta = –40 to 85°C)
Read cycle time
Address access time
CS1 access time
CS2 access time
OE access time
LB, UB access time
CS1 output set time
CS2 output set time
CS1 output floating
CS2 output floating
LB, UB output set time
LB, UB output floating
OE output set time
OE output floating
Output hold time
t
RC
t
ACC
t
ACS1
t
ACS2
t
OE
t
AB
t
CLZ1
t
CLZ2
t
CHZ1
t
CHZ2
t
BLZ
t
BHZ
t
OLZ
t
OHZ
t
OH
1
1
1
1
1
1
2
2
2
2
2
2
2
2
1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
–
ns
ns
ns
Unit
SRM2AV413LLBT8
2.4 to 3.3V
85
70
70
70
0
60
70
0
35
0
–
5
–
–
–
–
–
–
–
–
–
–
Parameter Symbol Test
Conditions
(VSS = 0V, Ta = –40 to 85°C)
Write cycle time
Chip select time (CS1)
Chip select time (CS2)
Address enable time
Address setup time
Write pulse width
LB, UB select time
Address hold time
Data setup time
Data hold time
WE output floating
WE output set time
t
WC
t
CW1
t
CW2
t
AW
t
AS
t
WP
t
BW
t
WR
t
DW
t
DH
t
WHZ
t
OW
1
1
1
1
1
1
1
1
1
1
2
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Min. Max.
–
35 ns
SRM2AV413LLBT
8
Rev.1.2 5
K
Note : *1 During read cycle time, WE is to be "High" level.
*2 In write cycle time that is controlled by CS1 or CS2, output buffer is to be "Hi-Z" state even if OE is "Low" level.
*3 When output buffer is in output state, be careful that do not input the opposite signals to the output data.
● DATA RETENTION CHARACTERISTIC WITH LOW VOLTAGE POWER SUPPLY
● Timing Chart
tCHZ2
CS1
Read Cycle*1
A0 to 17
LB, UB
OE
I/O1 to 16
(Dout)
tRC
tACC
tBLZ tOE
tOHZ
tOLZ
Write Cycle 1 (CS1 Control) *2, *3
tAW
tDW
tWR
tAS
tDH
Write Cycle 3 (WE Control)*3
Write Cycle 4 (UB, LB Control)
A0 to 17
CS1
LB, UB
WE
I/O1 to 16
(Dout)
(Din)
tOH
High-Z
tBW
tCHZ1
tCLZ1
CS2 CS2
tWC
tCW1
tWP
tDW
tWR
tAS
tDH
A0 to 17
CS1
LB, UB
WE
I/O1 to 16
(Dout)
(Din)
High-Z
CS2
tWC
tCW1
tWP
tDW
tBW
tWR
tAS
tWHZ tOW
tDH
A0 to 17
CS1
LB, UB
WE
I/O1 to 16
(Dout)
(Din)
tCW2
Write Cycle 2 (CS2 Control) *2, *3
tAW
tDW
tWR
tAS
tDH
A0 to 17
CS1
LB, UB
WE
I/O1 to 16
(Dout)
(Din)
High-Z
tBW
CS2
*3
CS2
tCW2
tWP
tCW2
tBW
tCW1
tWC
tACS1
tWP
tAB
tACS2
tCLZ2
tCW2
tWC
tCW1
tBHZ
Parameter Symbol Conditions Min. Typ.* Max. Unit
Data retention supply voltage
Data retention curren
Data hold time
Operation recovery time
V
DDR
I
DDR
t
CDR
t
R
V
µA
ns
ms
(V
SS
= 0V, Ta = –40 to 85°C)
V
DDR
= 2.5V
CS1 = CS2≥ V
DD
– 0.2V or CS2 ≤0.2V
* : Reference data at Ta=25°C
1.2
–
0
5
–
0.4
––
–
–
3.3
13
Rev.1.26
SRM2AV413LLBT
8
● Reading data
It is possible to control the data width by LB and UB pins.
(1) Reading data from lower byte
Data is able to be read when the address is set while holding CS1 ="Low",CS2 = "High", OE= "Low",
LB ="Low", and WE = "High".
(2) Reading data from upper byte
Data is able to be read when the address is set while holding CS1= "Low",CS2 = "High", OE = "Low",
UB = "Low", and WE ="High".
(3) Reading data from both bytes
Data is able to be read when the address is set while holding CS1 = "Low",CS2= "High", OE ="Low",
UB ="Low", LB = "Low", and WE = "High".
Since I/O pins are in "Hi-Z" state when OE = "High", the data bus line can be used for any other objective, then
access time apparently is able to be cut down.
■ FUNCTIONS
● Truth Table
Data retention timing (CS1 Control)
V
DD
CS1
t
CDR
t
R
V
DDR
≥ 1.2V
CS1 ≥V
DD
– 0.2V
2.4V2.4V
Data hold time
V
IL
V
IL
0.8xV
DD
0.8xV
DD
Data retention timing (CS2 Control)
V
DD
CS2
t
CDR
t
R
V
DDR
≥ 1.2V
CS2 ≤ 0.2V
2.4V2.4V
Data hold time
0.3 0.3
V
IH
V
IH
CS1
X
L
L
L
L
L
L
L
L
X
X
H
L
H
L
L
H
L
LB
X
X
H
H
L
L
H
L
L
UB
X
H
X
X
X
X
L
L
L
OE X
X
H
X
L
L
L
H
H
H
WE I/O1 to 8 IDD
MODE
IDDS, IDDS1
IDDA, IDDA1
IDDA, IDDA1
IDDA, IDDA1
IDDA, IDDA1
IDDA, IDDA1
IDDA, IDDA1
IDDA, IDDA1
IDDA, IDDA1
High-Z
High-Z
Data In
High-Z
Data In
DataOut
High-Z
Data Out
I/O9 to 16
High-Z
High-Z
High-Z
Data In
Data In
High-Z
DataOut
Data Out
Not Selected
Output disable
Lower Byte Write
Upper Byte Write
All Byte Write
Lower Byte Read
Upper Byte Read
All Byte Read
X : High or Low
CS2
X
L
H
H
H
H
H
H
H
H
HXXX
High-Z
High-Z High-Z
High-Z
Not Selected
Output disable
IDDS, IDDS1
SRM2AV413LLBT
8
Rev.1.2 7
K
(3)Writing data into both bytes
There are the following four ways of writing data into the memory.
i) Hold CS2 = "High", WE = "Low", LB and UB = "Low", set address and give "Low" pulse to CS1.
ii) Hold CS1 = "Low", WE = "Low", LB and UB = "Low", set address and give "High" pulse to CS2.
iii) Hold CS1 = "Low", CS2 = "High", LB and UB = "Low", set address and give "Low" pulse to WE.
ix) Hold CS1 = "Low", CS2 = "High", WE = "Low", set address and give "Low" pulse to LB and UB.
● Standby mode
Anyway, data on I/Opins are latched up into the memory cell during CS1 = "Low" , CS2 ="High" , WE = "Low",
UB and LB = "Low".
As DATA I/O pins are in "Hi-Z" when CS1= "High", CS2 = "Low", OE= "High", or LB and
UB ="High", the contention on the data bus can be avoided. But while I/O pins are in the output state, the
data that is opposite to the output data should not be given.
● Writing data
(1) Writing data into lower byte
There are the following four ways of writing data into memory.
i) Hold CS2 = "High",WE = "Low",UB ="High", and LB = "Low",set address and give "Low" pulse to CS1.
ii) Hold CS1 = "Low",WE = "Low",UB ="High", and LB = "Low",set address and give "High" pulse to CS2.
iii) Hold CS1 = "Low",CS2 = "High",UB ="High", and LB = "Low",set address and give "Low" pulse to WE
ix) Hold CS1 = "Low",CS2 = "High",WE ="Low",and UB= "High",set address and give "Low" pulse to LB.
Anyway, data on I/O pins are latched up into the memory cell during CS1 ="Low",CS2 = "High",WE and LB ="Low".
(2) Writing data into upper byte
There are the following four ways of writing data into the memory.
i) Hold CS2 ="High",WE ="Low",LB ="High",and UB ="Low",set address and give "Low" pulse to CS1.
ii) Hold CS1 ="Low",WE ="Low",LB ="High",and UB ="Low",set address and give "High" pulse to CS2.
iii) Hold CS1 ="Low",CS2 ="High",LB ="High",and UB ="Low",set address and give "Low" pulse to WE.
ix) Hold CS1="Low",CS2 ="High",WE="Low",and LB="High",set address and give "Low" pulse to UB.
Anyway, data on I/O pins are latched up into the memory cell during CS1 ="Low",CS2 = "High",WE and UB ="Low".
When CS1 is "High" or CS2 is "Low" the chip is in the standby mode (only retaining data operation). In this case
data I/O pins are Hi-Z, and all inputs of addresses, WE, OE, UB, LB, and data are inhibited. When
CS1 = CS2 ≥ VDD - 0.2V or CS2 ≤ 0.2V, there is almost no current flow except through the high resistance parts
of the memory.
● Data retention at low voltage
In case of the data retention in the stadby mode, the power supply can be gone down till the specified voltage.
But it is impossible to write or read in this mode.
Rev.1.28
SRM2AV413LLBT
8
TFBGA-48 pin
Unit : mm
■ PACKAGE DIMENSIONS
123 456
H
G
F
E
D
C
B
A
654321
A
B
C
D
E
F
G
H
BO TT OM VIEW
SIDE VIEW
T OP VIEW
SRAM Die
Base Tape
INDEX
0.75 Typ.
1.0 Max.
0.75 Typ.
8.0 ± 0.2
0.2
10.0 ± 0.2
φ0.35±0.05
+0.1
–0.05
SRM2AV413LLBT
8
Rev.1.2 9
K
■ CHARACTERISTICS CURVES
Normalized I
DDA
-Ta
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
-60 -40 -20 0 20 40 60 80
READ
WRITE
V
DD
=3.0V
READ,WRITE
Normalized I
DDS1
-Ta
0.1
1
10
100
-60 -40 -20 0 20 40 60 80 100
V
DD
=3.0V
Normlized I
DDS1
-V
DD
0.01
0.1
1
10
100
1.6 2 2.4 2.8 3.2 3.6 4
V
DD
(V)
Ta=25
Normalized I
OH
-V
OH
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
0.5 1 1.5 2 2.5 3 3.5
V
OH
(V)
Ta=25
V
DD
=3.0V
Normalized I
DDA
-Frequency
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
0 2 4 6 8 10 12 14 16 18 20
Frequency (MHz)
Ta=25
V
DD
=3.0V
READ
WRITE
Normalized I
DDA
-V
DD
0.4
0.6
0.8
1
1.2
1.4
1.6
1.6 2 2.4 2.8 3.2 3.6 4
V
DD
(V)
READ
WRITE
Ta=25
READ,WRITE
°C°C
°C
°C
Ta (°C)
Ta (°C)
Rev.1.210
SRM2AV413LLBT
8
ACC
Normalized
ACS1
-V
DD
ACS2
0.0
0.5
1.0
1.5
2.0
2.5
1.5 2 2.5 3 3.5 4
V
DD
(V)
Normalized I
DDR
-Ta
0.1
1
10
100
-60 -40 -20 0 20 40 60 80 100
ACC
Normalized
ACS1
-Ta
ACS2
0.7
0.8
0.9
1
1.1
1.2
-60 -40 -20 0 20 40 60 80 100
V
DD
=3.0V
Normalized I
OL
-V
OL
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
2.2
2.4
0 0.2 0.4 0.6 0.8 1
V
OL
(V)
V
DD
=3.0V
ACC
Normalized
ACS1
-C
L
ACS2
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2
2.1
2.2
0 100 200 300 400
C
L
(pF)
V
DD
=3.0V
t
t
tt
tt
t
t
t
Ta (°C)
Ta=25°C
Ta=25°C
Ta= (°C)
Ta=25°C
NOTICE:
No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko
Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of
any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that
this material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any intellectual
property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this
material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the
subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export
license from the Ministry of International Trade and Industry or other approval from another government agency.
© Seiko Epson Corporation 2000 All right reserved.
Revised January, 2000
Printed in Japan T
Rev.1.2
K
SRM2AV413LLBT
8
