DS07-13602-5E
FUJITSU SEMICONDUCTOR
DATA SHEET
16-bit Proprietary Microcontroller
CMOS
F2MC-16L MB90670/675 Series
MB90671/672/673/T673/P673 (MB90670 Series)
MB90676/677/678/T678/P678 (MB90675 Series)
■DESCRIPTION
The MB90670/675 series is a member of 16-bit proprietary single-chip microcontroller F2MC*1-16L family designed
to be combined with an ASIC (Application Specific IC) core. The MB90670/675 series is a high-performance
general-purpose 16-bit microcontroller for high-speed real-time processing in var ious industrial equipment, OA
equipment, and process control.
The instruction set of F2MC-16L CPU core inherits AT architecture of F2MC-8 family with additional instr uction
sets for high-level languages, extended addressing mode, enhanced multiplication/division instructions, and en-
hanced bit manipulation instructions. The microcontroller has a 32-bit accumulator f or processing long word data
(32-bit).
The MB90670/675 series has peripheral resources of UART0, UART1(SCI), an 8/10-bit A/D converter, an
8/16-bit PPG timer , a 16-bit reload timer , a 24-bit free run timer , an output compare (OCU), an input capture (ICU),
DTP/external interrupt circuit, an I2C*2 interface (in MB90675 series only). Embedded peripheral resources
performs data transmission with an intelligent I/O service function without the intervention of the CPU, enabling
real-time control in various applications.
*1:F2MC stands for FUJITSU Flexible Microcontroller.
*2:Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use these
components in an I2C system, provided that the system conforms to the I2C Standard Specification as
defined by Philips.
■PACKAGES
80-pin Plastic LQFP
(FPT-80P-M05)
80-pin Plastic QFP
(FPT-80P-M06)
100-pin Plastic LQFP
(FPT-100P-M05)
100-pin Plastic QFP
(FPT-100P-M06)
MB90670/675 Series
2
■FEATURES
•Clock
Embedded PLL clock multiplication circuit
Operating cloc k (PLL clock) can be selected from divided-b y-2 of oscillation or one to f our times the oscillation
(at oscillation of 4 MHz, 4 MHz to 16 MHz).
Minimum instruction execution time of 62.5 ns (at oscillation of 4 MHz, four times the PLL clock, operation at
Vcc of 5.0 V)
• CPU addressing space of 16 Mbytes
Internal addressing of 24-bit
External accessing can be performed by selecting 8/16-bit bus width (external bus mode)
• Instruction set optimized for controller applications
Rich data types (bit, byte, word, long word)
Rich addressing mode (23 types)
High code efficiency
Enhanced precision calculation realized by the 32-bit accumulator
• Instruction set designed for high level language (C) and multi-task operations
Adoption of system stack pointer
Enhanced pointer indirect instructions
Barrel shift instructions
• Enhanced execution speed
4-byte instruction queue
• Enhanced interrupt function
8 levels, 32 factors
• Automatic data transmission function independent of CPU operation
Extended intelligent I/O service function (EI2OS)
• Low-power consumption (standby) mode
Sleep mode (mode in which CPU operating clock is stopped)
Timebase timer mode (mode in which other than oscillation and timebase timer are stopped)
Stop mode (mode in which oscillation is stopped)
CPU intermittent operation mode
Hardware standby mode
•Process
CMOS technology
• I/O port
MB90670 series: Maximum of 65 ports
MB90675 series: Maximum of 84 ports
•Timer
Timebase timer/watchdog timer: 1 channel
8/16-bit PPG timer: 8-bit × 2 channels or 16-bit × 1 channel
16-bit reload timer: 2 channels
24-bit free run timer: 1 channel
• Input capture (ICU)
Generates an interrupt request by latching a 24-bit free run timer counter value upon detection of an edge
input to the pin.
• Output compare (OCU)
Generates an interrupt request and re verse the output le v el upon detection of a match between the 24-bit free
run timer counter value and the compare setting value.
•I
2C interface (in MB90675 series only)
• Serial I/O port for supporting Inter IC BUS
(Continued)
MB90670/675 Series
3
(Continued)
•UART0
With full-duplex double buffer (8-bit length)
Clock asynchronized or clock synchronized transmission (with start and stop bits) can be selectively used.
•UART1 (SCI)
With full-duplex double buffer (8-bit length)
Clock asynchronized or clock synchronized serial transmission (I/O extended serial) can be selectively used.
• DTP/external interrupt circuit (4 channels)
A module for starting extended intelligent I/O service (EI2OS) and generating an exter nal interr upt tr iggered
by an external input.
• Wake-up interrupt
Receives external interrupt requests and generates an interrupt request upon an “L” level input.
• Delayed interrupt generation module
Generates an interrupt request for switching tasks.
• 8/10-bit A/D converter (8 channels)
8-bit or 10-bit resolution can be selectively used.
Starting by an external trigger input.
MB90670/675 Series
4
■PRODUCT LINEUP
• MB90670 series
(Continued)
Part number
Item
MB90671 MB90672 MB90673 MB90T673 MB90P673
Classification Mask ROM products External ROM
product
One-time
PROM
product
ROM size 16 Kbytes 32 Kbytes 48 Kbytes External ROM 48 Kbytes
RAM size 640 bytes 1.64 Kbytes 2 Kbytes
CPU functions
Number of instructions:
Instruction bit length:
Instruction length:
Data bit length:
Minimum execution time:
Interrupt processing time:
340
8 bits, 16 bits
1 byte to 7 bytes
1 bit, 8 bits, 16 bits
62.5 ns (at machine clock of 16 MHz)
1.5 µs (at machine clock of 16 MHz, minimum value)
Ports General-purpose I/O ports (CMOS output): 57
General-purpose I/O ports (N-ch open-drain output): 8
Total: 65
UART0
Clock synchronized transmission (500 Kbps to 2 Mbps)
Clock asynchronized transmission (4800 Kbps to 500 Kbps)
Transmission can be performed by bi-directional serial transmission or by master/slave
connection.
UART1 (SCI)
Clock synchronized transmission (500 Kbps to 2 Mbps)
Clock asynchronized transmission (2400 Kbps to 62500 bps)
Transmission can be performed by bi-directional serial transmission or by master/slave
connection.
8/10-bit A/D converter
Conversion precision: 10-bit or 8-bit selectable
Number of inputs: 8
One-shot conversion mode (converts selected channel only once)
Continuous conversion mode (converts selected channel continuously)
Stop conversion mode (converts selected channel and stop operation repeatedly)
8/16-bit PPG timer
Number of channels: 2
8-bit or 16-bit PPG operation
A Pulse wave of given intervals and given duty ratios can be output.
Pulse cycle: 125 ns to 16.78 s (at oscillation of 4 MHz, machine clock of 16 MHz)
16-bit reload timer
Number of channels: 2
16-bit reload timer operation
Interval: 125 ns to 131 ms (at machine clock of 16 MHz)
External event count can be performed.
24-bit free run timer Number of channel :1
Overflow interrupts or intermediate bit interrupts may be generated.
Output compare unit
(OCU) Number of channels: 8
Pin input factor: A match signal of compare register
MB90670/675 Series
5
(Continued)
*: Varies with conditions such as the operating frequency. (See section “■ Electrical Characteristics.”)
Part number
Item
MB90671 MB90672 MB90673 MB90T673 MB90P673
Input capture unit (ICU) Number of channels: 4
Rewriting a register value upon a pin input (rising, falling, or both edges)
DTP/external interrupt circuit Number of inputs: 4
Started by a rising edge, a falling edge, an “H” level input, or an “L” level input.
External interrupt circuit or extended intelligent I/O service (EI2OS) can be used.
Wake-up interrupt Number of inputs: 8
Started by an “L” level input.
Delayed interrupt generation
module An interrupt generation module for switching tasks used in real-time operating sys-
tems.
I2C interface None
Timebase timer 18-bit counter
Interrupt interval: 1.024 ms, 4.096 ms, 16.384 ms, 131.072 ms
(at oscillation of 4 MHz)
Watchdog timer Reset generation interval: 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms
(at oscillation of 4 MHz, minimum value)
Low-power consumption
(standby) mode Sleep/stop/CPU intermittent operation/timebase timer/hardware stand-by
Process CMOS
Operating voltage* 2.7 V to 5.5 V
MB90670/675 Series
6
• MB90675 series
(Continued)
Part number
Item
MB90676 MB90677 MB90678 MB90T678 MB90P678 MB90V670
Classification Mask ROM products External ROM
product
One-time
PROM
product
Evaluation
product
ROM size 32 Kbytes 48 Kbytes 64 Kbytes None 64 Kbytes —
RAM size 1.64 Kbytes 2 Kbytes 3 Kbytes 4 Kbytes
CPU functions
The number of instructions:
Instruction bit length:
Instruction length:
Data bit length:
Minimum execution time:
Interrupt processing time:
340
8 bits, 16 bits
1 byte to 7 bytes
1 bit, 8 bits, 16 bits
62.5 ns (at machine clock of 16 MHz)
1.5 µs (at machine clock of 16 MHz, minimum value)
Ports General-purpose I/O ports (CMOS output): 74
General-purpose I/O ports (N-ch open-drain output): 10
Total: 84
UART0
Clock synchronized transmission (500 Kbps to 2 Mbps)
Clock asynchronized transmission (4800 Kbps to 500 Kbps)
Transmission can be performed by bi-directional serial transmission or by master/slave
connection.
UART1 (SCI)
Clock synchronized transmission (500 Kbps to 2 Mbps)
Clock asynchronized transmission (2400 Kbps to 62500 bps)
Transmission can be performed by bi-directional serial transmission or by master/slave
connection.
8/10-bit A/D con-
verter
Conversion precision: 10-bit or 8-bit can be selectively used.
Number of inputs: 8
One-shot conversion mode (converts selected channel only once)
Continuous conversion mode (converts selected channel continuously)
Stop conversion mode (converts selected channel and stop operation repeatedly)
8/16-bit PPG timer
Number of channels: 2
PPG operation of 8-bit or 16-bit
Pulse of given intervals and given duty ratios can be output
Pulse interval 125 ns to 16.78 s (at oscillation of 4 MHz, machine clock of 16 MHz)
16-bit reload timer
Number of channels: 2
16-bit reload timer operation
Interval: 125 ns to 131 ms (at machine clock of 16 MHz)
External event count can be performed.
24-bit free run timer Number of channel :1
Overflow interrupts or intermediate bit interrupts may be generated.
Output compare
(OCU) Number of channels: 8
Pin input factor: a match signal of compare register
MB90670/675 Series
7
(Continued)
*: Varies with conditions such as the operating frequency. (See section “■ ELECTRICAL CHARACTERISTICS.”)
Assurance for the MB90V670 is given only for operation with a tool at a power voltage of 2.7 V to 5.5 V, an
operating temperature of 0°C to 70°C, and an operating frequency of 1.5 MHz to 16 MHz.
■PACKAGE AND CORRESPONDING PRODUCTS
: Available × : Not available
Note: For more information about each package, see section “■ PACKAGE DIMENSIONS.”
Part number
Item
MB90676 MB90677 MB90678 MB90T678 MB90P678 MB90V670
Input capture (ICU) Number of channels: 4
Rewriting a register value upon a pin input (rising, falling, or both edges)
DTP/external inter-
rupt circuit
Number of inputs: 4
Started by a rising edge, a falling edge, an “H” level input, or an “L” level input.
External interrupt circuit or extended intelligent I/O service (EI2OS) can be used.
Wake-up interrupt Number of inputs: 8
Started by an “L” level input.
Delayed interrupt
generation module An interrupt generation module for switching tasks used in realtime operating systems.
I2C interface Serial I/O port for supporting Inter IC BUS
Timebase timer 18-bit counter
Interrupt interval: 1.024 ms, 4.096 ms, 16.384 ms, 131.072 ms
(at oscillation of 4 MHz)
Watchdog timer Reset generation interval: 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms
(at oscillation of 4 MHz, minimum value)
Low-power con-
sumption (stand-
by) mode Sleep/stop/CPU intermittent operation/timebase timer/hardware stand-by
Process CMOS
Power supply volt-
age for operation* 2.7 V to 5.5 V
Package
MB90671
MB90672
MB90673
MB90T673
MB90P673
MB90676
MB90677
MB90678
MB90T678
MB90P678 MB90V670
FPT-80P-M05 ×××
FPT-80P-M06 ×××
FPT-100P-M05 ×× ×
FPT-100P-M06 ×× ×
MB90670/675 Series
8
■DIFFERENCES AMONG PRODUCTS
1. Memory Size
In evaluation with an evaluation product, note the difference between the evaluation chip and the chip actually
used. The following items must be taken into consideration.
• The MB90V670 does not have an internal ROM, ho wever, operations equivalent to chips with an internal ROM
can be evaluated by using a dedicated development tool, enabling selection of ROM size by settings of the
development tool.
• In the MB90V670, images from FF4400H to FFFFFFH are mapped to bank 00, and FE0000H to FF3FFFH to
mapped to bank FEH and FFH only. (This setting can be changed by configuring the development tool.)
• In the MB90678/MB90P678, images from FF4000H to FFFFFFH are mapped to bank 00, and FF0000H to
FF3FFFH to bank FF only.
2. Mask Options
Functions selected by optional settings and methods f or setting the options are dependent on the product types.
Refer to “■ Mask Options” for detailed information.
Note that mask option is fixed in MB90V670 series.
MB90670/675 Series
9
■PIN ASSIGNMENTS
(Continued)
P17/AD15/WI7
P16/AD14/WI6
P15/AD13/WI5
P14/AD12/WI4
P13/AD11/WI3
P12/AD10/WI2
P11/AD09/WI1
P10/AD08/WI0
P07/AD07
P06/AD06
P05/AD05
P04/AD04
P03/AD03
P02/AD02
P01/AD01
P00/AD00
VCC
X1
X0
VSS
P43/SIN1
P44/SOT1
P45/SCK1
P46/PPG0
P47/ATG
AVCC
AVRH
AVRL
AVSS
P50/AN0
P51/AN1
VSS
P52/AN2
P53/AN3
P54/AN4
P55/AN5
P56/AN6
P57/AN7
MD0
MD1
RST
P80/PPG1
P77/DOT7
P76/DOT6
P75/DOT5
P74/DOT4
P73/DOT3
P72/DOT2
P71/DOT1
P70/DOT0
P67/ASR3
P66/ASR2
P65/ASR1
P64/ASR0
P63/INT3
P62/INT2
P61/INT1
P60/INT0
HST
MD2
P20/A16
P21/A17
P22/A18
P23/A19
P24/TIN0
P25/TIN1
P26/TOT0
P27/TOT1
VSS
P30/ALE
P31/RD
P32/WRL/WR
P33/WRH
P34/HRQ
P35/HAK
P36/RDY
P37/CLK
P40/SIN0
P41/SOT0
P42/SCK0
(Top view)
(FPT-80P-M05)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
MB90670/675 Series
10
(Continued)
P15/AD13/WI5
P14/AD12/WI4
P13/AD11/WI3
P12/AD10/WI2
P11/AD09/WI1
P10/AD08/WI0
P07/AD07
P06/AD06
P05/AD05
P04/AD04
P03/AD03
P02/AD02
P01/AD01
P00/AD00
VCC
X1
(Top view)
(FPT-80P-M06)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
P45/SCK1
P46/PPG0
P47/ATG
AVCC
AVRH
AVRL
AVSS
P50/AN0
P51/AN1
VSS
P52/AN2
P53/AN3
P54/AN4
P55/AN5
P56/AN6
P57/AN7
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
X0
VSS
RST
P80/PPG1
P77/DOT7
P76/DOT6
P75/DOT5
P74/DOT4
P73/DOT3
P72/DOT2
P71/DOT1
P70/DOT0
P67/ASR3
P66/ASR2
P65/ASR1
P64/ASR0
P63/INT3
P62/INT2
P61/INT1
P60/INT0
HST
MD2
MD1
MD0
P16/AD14/WI6
P17/AD15/WI7
P20/A16
P21/A17
P22/A18
P23/A19
P24/TIN0
P25/TIN1
P26/TOT0
P27/TOT1
VSS
P30/ALE
P31/RD
P32/WRL/WR
P33/WRH
P34/HRQ
P35/HAK
P36/RDY
P37/CLK
P40/SIN0
P41/SOT0
P42/SCK0
P43/SIN1
P44/SOT10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
MB90670/675 Series
11
(Continued)
P21/A17
P20/A16
P17/AD15/WI7
P16/AD14/WI6
P15/AD13/WI5
P14/AD12/WI4
P13/AD11/WI3
P12/AD10/WI2
P11/AD09/WI1
P10/AD08/WI0
P07/AD07
P06/AD06
P05/AD05
P04/AD04
P03/AD03
P02/AD02
P01/AD01
P00/AD00
VCC
X1
X0
VSS
PB2
PB1
PB0
P81
P82
P83
P84
P85
P86
AVCC
AVRH
AVRL
AVSS
P50/AN0
P51/AN1
VSS
P52/AN2
P53/AN3
P54/AN4
P55/AN5
P56/AN6
P57/AN7
P90/SDA
P91/SCL
MD0
MD1
MD2
HST
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
RST
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
P77/DOT7
P76/DOT6
P75/DOT5
P74/DOT4
P73/DOT3
P72/DOT2
P71/DOT1
P70/DOT0
P67/ASR3
P66/ASR2
P65/ASR1
P64/ASR0
P63/INT3
P62/INT2
P61/INT1
P60/INT0
P22/A18
P23/A19
P24/TIN0
P25/TIN1
P26/TOT0
P27/TOT1
P30/ALE
P31/RD
VSS
P32/WRL/WR
P33/WRH
P34/HRQ
P35/HAK
P36/RDY
P37/CLK
P40/SIN0
P41/SOT0
P42/SCK0
P43/SIN1
P44/SOT1
VCC
P45/SCK1
P46/PPG0
P47/ATG
P80/PPG1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
(Top view)
(FPT-100P-M05)
MB90670/675 Series
12
(Continued)
P17/AD15/WI7
P16/AD14/WI6
P15/AD13/WI5
P14/AD12/WI4
P13/AD11/WI3
P12/AD10/WI2
P11/AD09/WI1
P10/AD08/WI0
P07/AD07
P06/AD06
P05/AD05
P04/AD04
P03/AD03
P02/AD02
P01/AD01
P00/AD00
VCC
X1
X0
VSS
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P84
P85
P86
AVCC
AVRH
AVRL
AVSS
P50/AN0
P51/AN1
VSS
P52/AN2
P53/AN3
P54/AN4
P55/AN5
P56/AN6
P57/AN7
P90/SDA
P91/SCL
MD0
MD1
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
P20/A16
P21/A17
P22/A18
P23/A19
P24/TIN0
P25/TIN1
P26/TOT0
P27/TOT1
P30/ALE
P31/RD
VSS
P32/WRL/WR
P33/WRH
P34/HRQ
P35/HAK
P36/RDY
P37/CLK
P40/SIN0
P41/SOT0
P42/SCK0
P43/SIN1
P44/SOT1
VCC
P45/SCK1
P46/PPG0
P47/ATG
P80/PPG1
P81
P82
P83
PB2
PB1
PB0
RST
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
P77/DOT7
P76/DOT6
P75/DOT5
P74/DOT4
P73/DOT3
P72/DOT2
P71/DOT1
P70/DOT0
P67/ASR3
P66/ASR2
P65/ASR1
P64/ASR0
P63/INT3
P62/INT2
P61/INT1
P60/INT0
HST
MD2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
(Top view)
(FPT-100P-M06)
MB90670/675 Series
13
■PIN DESCRIPTION
(Continued)
*1: FPT-80P-M05
*2: FPT-80P-M06
*3: FPT-100P-M05
*4: FPT-100P-M06
Pin no. Pin name Circuit type Function
LQFP
-80*1QFP
-80*2LQFP
-100*3QFP
-100*4
62 64 80 82 X0 A
(Oscillation) Crystal oscillator pins
63 65 81 83 X1
39 to 41 41 to 43 47 to 49 49 to 51 MD0 to
MD2 F
(CMOS) Input pins for selecting operation modes
Connect directly to VCC or VSS.
60 62 75 77 RST H
(CMOS/H) External reset request input
42 44 50 52 HST G
(CMOS/H) Hardware standby input pin
65 to 72 67 to 74 83 to 90 85 to 92
P00 to P07
B
(CMOS)
General-purpose I/O port
This function is valid in the single-chip mode.
AD00 to
AD07
I/O pins for the lower 8-bit of the external ad-
dress data bus
This function is valid in the mode where the ex-
ternal bus is valid.
73 to 78,
79, 80 75 to 80,
1, 2 91 to 96,
97, 98 93 to 98,
99, 100
P10 to P15,
P16, P17
B
(CMOS)
General-purpose I/O port
This function is valid in the single-chip mode.
AD08 to
AD13,
AD14,
AD15
I/O pins for the upper 8-bit of the external ad-
dress data bus
This function is valid in the mode where the ex-
ternal bus is valid.
WI0 to WI5,
WI6, WI7
I/O pins for wake-up interrupts
This function is valid in the single-chip mode.
Because the input of the DTP/external inter-
rupt circuit is used as required when the DTP/
external interrupt circuit is enabled, and it is
necessary to stop outputs by other functions
unless such outputs are made intentionally.
1, 2, 3, 4 3, 4, 5, 6 99, 100,
1, 2 1, 2, 3, 4
P20, P21,
P22, P23
B
(CMOS)
General-purpose I/O port
This function becomes valid in the single-chip
mode or the external address output control
register is set to select a port.
A16, A17,
A18, 19
Output pins for the external address bus of A16
to A19
This function is valid in the mode where the ex-
ternal bus is valid and the upper address con-
trol register is set to select an address.
MB90670/675 Series
14
(Continued)
*1: FPT-80P-M05
*2: FPT-80P-M06
*3: FPT-100P-M05
*4: FPT-100P-M06
Pin no. Pin name Circuit type Function
LQFP
-80*1QFP
-80*2LQFP
-100*3QFP
-100*4
5, 6 7, 8 3, 4 5, 6
P24, P25
E
(CMOS/H)
General-purpose I/O port
This function is always valid.
TIN0, TIN1
Event input pins of 16-bit reload timer 0 and 1
Because this input is used as required when the
16-bit reload timer is performing input operations,
and it is necessary to stop outputs by other func-
tions unless such outputs are made intentionally.
7, 8 9, 10 5, 6 7, 8
P26, P27 E
(CMOS/H)
General-purpose I/O port
This function is valid when outputs from 16-bit re-
load timer 0 and 1 are disabled.
TOT0,
TOT1 Output pins for 16-bit reload timer 0 and 1
This function is valid when output from 16-bit re-
load timer 0 and 1 are enabled.
10 12 7 9
P30 B
(CMOS)
General-purpose I/O port
This function is valid in the single-chip mode.
ALE Address latch enable output pin
This function is valid in the mode where the exter-
nal bus is valid.
11 13 8 10
P31 B
(CMOS)
General-purpose I/O port
This function is valid in the single-chip mode.
RD Read strobe output pin for the data bus
This function is valid in the mode where the exter-
nal bus is valid.
12 14 10 12
P32
B
(CMOS)
General-purpose I/O port
This function is valid in the single-chip mode or
WRL/WR pin output is disabled.
WRL Write strobe output pin for the data bus
This function is valid when WRL/WR pin output is
enabled in the mode where external bus is valid.
WRL is used for holding the lower 8-bit for write
strobe in 16-bit access operations, while WR is
used for holding 8-bit data for write strobe in
8-bit access operations.
WR
13 15 11 13
P33
B
(CMOS)
General-purpose I/O port
This function is valid in the single-chip mode, in the
external bus 8-bit mode, or WRH pin output is dis-
abled.
WRH
Write strobe output pin for the upper 8-bit of the
data bus
This function is valid when the external bus 16-bit
mode is selected in the mode where the external
bus is valid, and WRH output pin is enabled.
MB90670/675 Series
15
(Continued)
*1: FPT-80P-M05
*2: FPT-80P-M06
*3: FPT-100P-M05
*4: FPT-100P-M06
Pin no. Pin name Circuit type Function
LQFP
-80*1QFP
-80*2LQFP
-100*3QFP
-100*4
14 16 12 14
P34
B
(CMOS)
General-purpose I/O port
This function is valid when both the single-chip
mode and the hold function are disabled.
HRQ Hold request input pin
This function is valid in the mode where the exter-
nal bus is valid or when the hold function is en-
abled.
15 17 13 15
P35
B
(CMOS)
General-purpose I/O port
This function is valid when both the single-chip
mode and the hold function are disabled.
HAK Hold acknowledge output pin
This function is valid in the mode where the exter-
nal bus is valid or when the hold function is en-
abled.
16 18 14 16
P36
B
(CMOS)
General-purpose I/O port
This function is valid when both the single-chip
mode and the external ready function are disabled.
RDY Ready input pin
This function is valid when the external ready func-
tion is enabled in the mode where the external bus
is valid.
17 19 15 17
P37 B
(CMOS)
General-purpose I/O port
This function is valid in the single-chip mode or
when the CLK output is disabled.
CLK CLK output pin
This function is valid when CLK output is disabled
in the mode where the external bus is valid.
18 20 16 18
P40
E
(CMOS/H)
General-purpose I/O port
This function is always valid.
SIN0
Serial data input pin of UART0
Because this input is used as required when
UART0 is performing input operations, and it is
necessary to stop outputs by other functions un-
less such outputs are made intentionally.
19 21 17 19
P41 E
(CMOS/H)
General-purpose I/O port
This function is valid when serial data output from
UART0 is disabled.
SOT0 Serial data output pin of UART0
This function is valid when serial data output from
UART0 is enabled.
MB90670/675 Series
16
(Continued)
*1: FPT-80P-M05
*2: FPT-80P-M06
*3: FPT-100P-M05
*4: FPT-100P-M06
Pin no. Pin name Circuit type Function
LQFP
-80*1QFP
-80*2LQFP
-100*3QFP
-100*4
20 22 18 20
P42
E
(CMOS/H)
General-purpose I/O port
This function is valid when clock output from
UART0 is disabled.
SCK0
Clock I/O pin of UART0
This function is valid when clock output from
UART0 is enabled.
Because this input is used as required when
UART0 is performing input operations, and it is
necessary to stop outputs by other functions un-
less such outputs are made intentionally.
21 23 19 21
P43
E
(CMOS/H)
General-purpose I/O port
This function is always valid.
SIN1
Serial data input pin of UART1 (SCI)
Because this input is used as required when
UART1 (SCI) is performing input operations, and it
is necessary to stop outputs by other functions un-
less such outputs are made intentionally.
22 24 20 22
P44 E
(CMOS/H)
General-purpose I/O port
This function is valid when serial data output from
UART1 (SCI) is disabled.
SOT1 Serial data output pin of UART1 (SCI)
This function is valid when serial data output from
UART1 (SCI) is enabled.
23 25 22 24
P45
E
(CMOS/H)
General-purpose I/O port
This function is valid when clock output from
UART1 (SCI) is disabled.
SCK1
Clock I/O pin of UART1 (SCI)
This function is valid when clock output from
UART1 (SCI) is enabled.
Because this input is used as required when
UART1 (SCI) is performing input operations, and it
is necessary to stop outputs by other functions un-
less such outputs are made intentionally.
24 26 23 25
P46 E
(CMOS/H)
General-purpose I/O port
This function is valid when waveform output from
8/16-bit PPG timer 0 is disabled.
PPG0 Output pin of 8/16-bit PPG timer 0
This function is valid when waveform output from
8/16-bit PPG timer 0 is enabled.
MB90670/675 Series
17
(Continued)
*1: FPT-80P-M05
*2: FPT-80P-M06
*3: FPT-100P-M05
*4: FPT-100P-M06
Pin no. Pin name Circuit type Function
LQFP
-80*1QFP
-80*2LQFP
-100*3QFP
-100*4
25 27 24 26
P47
E
(CMOS/H)
General-purpose I/O port
This function is always valid.
ATG
Trigger input pin of the 8/10-bit A/D converter
Because this input is used as required when the
8/10-bit A/D converter is performing input opera-
tions, and it is necessary to stop outputs by other
functions unless such outputs are made intention-
ally.
30, 31,
33, 34,
35 to 38
32, 33,
35, 36,
37 to 40
36, 37,
38, 39,
41 to 44
38, 39,
40, 41,
43 to 46
P50, P51,
P52, P53,
P54 to P57 C
(CMOS/H)
I/O port of an open-drain type
The input function is valid when the analog input
enable register is set to select a port.
AN0, AN1,
AN2, AN3,
AN4 to AN7
Analog input pins of the 8/10-bit A/D converter
This function is valid when the analog input en-
able register is set to select AD.
43 to 46 45 to 48 51 to 54 53 to 56
P60 to P63
E
(CMOS/H)
General-purpose I/O port
This function is always valid.
INT0 to
INT3
Request input pins of the DTP/external interrupt
circuit
Because this input is used as required when the
DTP/external interrupt circuit is performing input
operations, and it is necessary to stop outputs
from other functions unless such outputs are
made intentionally.
47 to 50 49 to 52 55 to 58 57 to 60
P64 to P67
E
(CMOS/H)
General-purpose I/O port
This function is always valid.
ASR0 to
ASR3
Sample data input pins for ICU0 to ICU3
Because this input is used as required when the
input capture (ICU) is performing input opera-
tions, and it is necessary to stop outputs from oth-
er functions unless such outputs are made
intentionally.
51 to 58 53 to 60 59 to 66 61 to 68
P70 to P77
E
(CMOS/H)
General-purpose I/O port
This function is valid when waveform output from
the output compare (OCU) is disabled.
DOT0 to
DOT7
Waveform output pins of OCU0 and OCU1
This function is valid when waveform output from
the output compare (OCU) is enabled and output
from the port is selected.
MB90670/675 Series
18
(Continued)
*1: FPT-80P-M05
*2: FPT-80P-M06
*3: FPT-100P-M05
*4: FPT-100P-M06
Pin no. Pin name Circuit type Function
LQFP
-80*1QFP
-80*2LQFP
-100*3QFP
-100*4
59 61 25 27
P80 E
(CMOS/H)
General-purpose I/O port
This function is valid when waveform output from
8/16-bit PPG timer 1 is disabled.
PPG1 Output pin of 8/16-bit PPG timer 1
This function is valid when waveform output from
8/16-bit PPG timer 1 is enabled.
— — 26 to 31 28 to 33 P81 to P86 E
(CMOS/H) General-purpose I/O port
This function is always valid.
——4547
P90
D
(NMOS/H)
I/O port of an open-drain type
This function is always valid.
SDA
I/O pin of the I2C interface
This function is valid when operation of the I2C
interface is enabled.
Hold the port output in the high-impedance sta-
tus (PDR = 1) when the I2C interface is in opera-
tion.
——4648
P91
D
(NMOS/H)
I/O port of an open-drain type
This function is always valid.
SCL
Clock I/O pin of the I2C interface
This function is valid when operation of the I2C
interface is enabled.
Hold the port output in the high-impedance sta-
tus (PDR = 1) when the I2C interface is in opera-
tion.
— — 67 to 74 69 to 76 PA0 to PA7 E
(CMOS/H) General-purpose I/O port
This function is always valid.
— — 76 to 78 78 to 80 PB0 to PB2 E
(CMOS/H) General-purpose I/O port
This function is always valid.
64 66 21, 82 23, 84 VCC Power
supply Power supply to the digital circuit
9, 32,
61 11, 34,
63 9, 40,
79 11, 42,
81 VSS Power
supply Ground level of the digital circuit
26 28 32 34 AVCC Power
supply Power supply to the analog circuit
Make sure to turn on/turn off this power supply
with a voltage exceeding AVCC applied to VCC.
27 29 33 35 AVRH Power
supply Reference voltage input to the analog circuit
Make sure to turn on/turn off this power supply
with a voltage exceeding AVRH applied to AVCC.
28 30 34 36 AVRL Power
supply Reference voltage input to the analog circuit
29 31 35 37 AVSS Power
supply Ground level of the analog circuit
MB90670/675 Series
19
■I/O CIRCUIT TYPE
(Continued)
Type Circuit Remarks
A
• External clock frequency 3 MHz to 32
MHz
• Oscillation feedback resistor approx.
1MΩ
B
• CMOS level input/output
(with standby control)
• Pull-up option selectable
(with standby control)
• No pull-up resistor in the MB90V670
C
• N-ch open-drain output
• CMOS level hystheresis input
(with A/D control)
D
• NMOS open-drain output
• CMOS level hysteresis input
(with standby control)
Standby control signal
X1
X0 P-ch N-ch Clock input
P-ch
N-ch
Digital output
Digital output
Digital input
Standby control signal
R
Digital output
Digital input
A/D input
A/D disable
Digital output
Digital input
P-ch
N-ch
Standby control signal
MB90670/675 Series
20
(Continued)
Type Circuit Remarks
E
• CMOS level output
• CMOS level hysteresis input
(with standby control)
• Pull-up option selectable
(with standby control)
• No pull-up resistor in the MB90V670
F
• CMOS level input/output
(without standby control)
• Pull-up/pull-down option selectable
(without stand-by control)
• In mask ROM versions, MD2 pin is fixed
to pull-down resistor , and optionally se-
lectable the resistor in other pins.
• The MB90V670 has no pull-up/pull-
down resistors.
G
• CMOS level hysteresis input
(without standby control)
H
• CMOS level hysteresis input
(without standby control)
• Pull-up option selectable
(without standby control)
• No pull-up resistor in the MB90V670
P-ch
N-ch
Digital output
Digital output
Digital input
Standby control signal
R
P-ch
N-ch
Digital input
R
R
P-ch
N-ch
Digital input
P-ch
N-ch
Digital input
R
MB90670/675 Series
21
■HANDLING DEVICES
1. Make Sure that the Voltage not Exceed the Maximum Rating (to Avoid a Latch-up).
In CMOS ICs, a latch-up phenomenon is caused when an voltage exceeding VCC or an voltage below VSS is
applied to input or output pins or a voltage exceeding the rating is applied across VCC and VSS.
When a latch-up is caused, the power supply current may be dramatically increased causing resultant thermal
break-down of devices. To avoid the latch-up, make sure that the voltage not exceed the maximum rating.
In turning on/turning off the analog power supply, make sure the analog pow er voltage (AVCC, A VRH) and analog
input voltages not exceed the digital voltage (VCC).
2. Connection of Unused Pins
Leaving unused pins open may result in abnormal operations. Clamp the pin level by connecting it to a pull-up
or a pull-down resistor.
3. Notes on Using External Clock
In using the external clock, drive X0 pin only and leave X1 pin unconnected.
4. Power Supply Pins
In products with multiple VCC or VSS pins, the pins of a same potential are intern ally connected in the device to
avoid abnormal operations including latch-up. However, connect the pins external power and ground lines to
lower the electro-magnetic emission level and abnor mal operation of strobe signals caused by the r ise in the
ground level, and to conform to the total current rating.
Make sure to connect VCC and VSS pins via lowest impedance to power lines.
It is recommended to provide a bypass capacitor of around 0.1 µF between VCC and VSS pin near the device.
5. Crystal Oscillator Circuit
Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass
capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines , and
make sure, to the utmost effort , that lines of oscillation circuit not cross the lines of other circuits.
It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with an grand
area for stabilizing the operation.
6. Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs
Make sure to turn on the A/D conv erter power supply (AVCC, AVRH, A VRL) and analog inputs (AN0 to AN7) after
turning-on the digital power supply (VCC).
Tur n-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure
that the v oltage not exceed AVRH or AVCC (turning on/off the analog and digital power supplies simu ltaneously
is acceptable).
• Using external clock
X0
X1
Open
MB90670/675 series
MB90670/675 Series
22
7. Connection of Unused Pins of A/D Converter
Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVRH = VSS.
8. “MOV @AL, AH”, “MOVW @AL, AH” Instructions
When the above instruction is performed to I/O space, an unnecessary writing operation (#FF, #FFFF) may be
performed in the internal bus.
Use the compiler function for inser ting an NOP instruction before the above instructions to avoid the writing
operation.
Accessing RAM space with the above instruction does not cause any problem.
9. Initialization
In the device, there are internal registers which is initialized only by a power-on reset. To initialize these registers,
turning on the power again.
10. Caution on operations during PLL clock mode
If the PLL clock mode is selected, the microcontroller attempt to be w orking with the self-oscillating circuit e ven
when there is no external oscillator or external clock input is stopped. Performance of this operation, however,
cannot be guaranteed.
MB90670/675 Series
23
■PROGRAMMING TO THE ONE-TIME PROM ON THE MB90P673/P678
The MB90P673 and MB90P678 has a PROM mode for emulation operation of the MBM27C1000/1000A, to
which writing codes by a general-purpose ROM writer can be done via a dedicated adapter. Please note that
the device is not compatible with the electronic signature (device ID code) mode.
1. Writing Sequence
The memory map for the PROM mode is shown as follows. Write option data to the option setting area according
by referring to “7. PROM Option Bit Map”.
Write data to the one-time PROM microcontrollers according to the following sequence.
(1) Set the PROM programer to select the MBM27C1000/1000A.
(2) Load the program data to the ROM programer address *1 to 1FFFFH. To select a PROM option, load the
option data from 00000H to 0002CH referring to “7. PROM Option Bit Map”.
(3) Set the chip to the adapter socket and load the socket to the ROM programer. Make sure that the device
and adapter socket are properly oriented.
(4) Progr a m from 00000H to 1FFFFH.
Notes:
• In mask-ROM products, there is no PROM mode and it is impossible to read data by a ROM programer.
• Contact sales personnel when purchasing a ROM programer.
2. Program Mode
In the MB90P673/P678, all the bits are set to “1” upon shipping from FUJITSU or erasing operation. To write
data, set desired bit selectively to “0”. However it is impossible to write electronically to the bits.
Note: The ROM image size for bank 00 is 48 Kbytes (ROM image for between FF4000H to FFFFFFH).
Type Address*1Address*2Number of bytes
MB90P673 14000HFF4000H48 Kbytes
MB90P678 10000HFF0000H64 Kbytes
FFFFFFH
010000H
004000H
000000H
Address*2Address*1
1FFFFFH
00000H
0002CH
Normal operation mode PROM mode
Program area
(PROM) Program area
(PROM)
ROM image
Option
setting area
MB90670/675 Series
24
3. Recommended Screening Conditions
High-temperature aging is recommended as the pre-assemb ly screening procedure for a product with a b lanked
One-time PROM microcomputer program.
4. Programming Yield
All bits cannot be programmed at Fujitsu shipping test to a blanked One-time PROM microcomputer, due to its
nature. For this reason, a programming yield of 100% cannot be assured at all times.
5. EPROM Programmer Socket Adapter and Recommended Programmer Manufacturer
Inquiry: San Hayato Co., Ltd.: TEL: (81)-3-3986-0403
FAX: (81)-3-5396-9106
Minato Electronics Inc.: TEL: USA (1)-916-348-6066
JAPAN (81)-45-591-5611
Data I/O Co., Ltd.: TEL: USA/ASIA (1)-206-881-6444
EUROPE (49)-8-985-8580
Part no. MB90P673PF MB90P673PFV MB90P678PF MB90P678PFV
Package QFP-80 LQFP-80 QFP-100 LQFP-100
Compatible socket adapter
Sun Hayato Co., Ltd. ROM-80QF-
32DP-16L ROM-80SQF-
32DP-16L ROM-100QF-
32DP-16L ROM-100SQF-
32DP-16L
Minato Electronics Inc.
1890A — — — Recommended
1891 — — — Recommended
1930 — — — Recommended
Data I/O Co., Ltd.
UNISITE — — — Recommended
3900 — — — Recommended
2900 — — — Recommended
Program, verify
Aging
+150°C, 48 h
Data verification
Assembly
Recommended programmer manufacturer
and programmer name
MB90670/675 Series
25
6. Pin Assignment for EPROM Mode
• MBM27C1000/1000A pin compatible
MBM27C1000/1000A MB90P673/MB90P678 MBM27C1000/1000A MB90P673/MB90P678
Pin no. Pin name Pin no. Pin name Pin no. Pin name Pin no. Pin name
1V
PP MD2 32 VCC VCC
2 OE P32 31 PGM P33
3A15 P17 30N.C. —
4A12 P14 29A14 P16
5A07 P27 28A13 P15
6A06 P26 27A08 P10
7A05 P25 26A09 P11
8A04 P24 25A11 P13
9A03 P23 24A16 P30
10 A02 P22 23 A10 P12
11 A01 P21 22 CE P31
12 A00 P20 21 D07 P07
13 D00 P00 20 D06 P06
14 D01 P01 19 D05 P05
15 D02 P02 18 D04 P04
16 GND VSS 17 D03 P03
Pin no. Pin name processing Type Pin no. Pin name
MD0
MD1
X0
Connect a pull-up resis-
tor of 4.7 kΩ.Power supply Refer to pin
assignments. HST
VCC
X1 OPEN
AVCC
AVRH
P37
P40 to P47
P50 to P57
P60 to P67
P70 to P77
P80 to P86
P90
P91
PA0 to PA7
PB0 to PB2
GND Refer to pin
assignments.
P34
P35
P36
RST
AVRL
AVSS
VSS
Connect a pull-up
resistor having
a resistance of
approximately
1 MΩ to each pin.
• Pin assignments for products not compatible
with MBM27C1000/1000A • Power supply, GND connected pin
Refer to pin assignments.
Note: Only MB90675 series has P81 to P86, P90, P91, PA0 to PA7, PB0 to PB2 pins.
Refer to pin assignments.
Refer to pin assignments.
MB90670/675 Series
26
7. PROM Option Bit Map
Notes:
• Data “1” must be programed to the reserved bits and address other than listed above.
• Only MB90P678 has pull-up options for P81 to P86, PA0 to PA7, and PB0 to PB2 pins.
• Data “1” must be programed for the MB90P673.
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
00000HVacancy RST
Pull-up
1: No
0: Yes Vacancy MD1
Pull-up
1: No
0: Yes
MD1
Pull-down
1: No
0: Yes
MD0
Pull-up
1: No
0: Yes
MD0
Pull-down
1: No
0: Yes Vacancy
00004H
P07
Pull-up
1: No
0: Yes
P06
Pull-up
1: No
0: Yes
P05
Pull-up
1: No
0: Yes
P04
Pull-up
1: No
0: Yes
P03
Pull-up
1: No
0: Yes
P02
Pull-up
1: No
0: Yes
P01
Pull-up
1: No
0: Yes
P00
Pull-up
1: No
0: Yes
00008H
P17
Pull-up
1: No
0: Yes
P16
Pull-up
1: No
0: Yes
P15
Pull-up
1: No
0: Yes
P14
Pull-up
1: No
0: Yes
P13
Pull-up
1: No
0: Yes
P12
Pull-up
1: No
0: Yes
P11
Pull-up
1: No
0: Yes
P10
Pull-up
1: No
0: Yes
0000CH
P27
Pull-up
1: No
0: Yes
P26
Pull-up
1: No
0: Yes
P25
Pull-up
1: No
0: Yes
P24
Pull-up
1: No
0: Yes
P23
Pull-up
1: No
0: Yes
P22
Pull-up
1: No
0: Yes
P21
Pull-up
1: No
0: Yes
P20
Pull-up
1: No
0: Yes
00010H
P37
Pull-up
1: No
0: Yes
P36
Pull-up
1: No
0: Yes
P35
Pull-up
1: No
0: Yes
P34
Pull-up
1: No
0: Yes
P33
Pull-up
1: No
0: Yes
P32
Pull-up
1: No
0: Yes
P31
Pull-up
1: No
0: Yes
P30
Pull-up
1: No
0: Yes
00014H
P47
Pull-up
1: No
0: Yes
P46
Pull-up
1: No
0: Yes
P45
Pull-up
1: No
0: Yes
P44
Pull-up
1: No
0: Yes
P43
Pull-up
1: No
0: Yes
P42
Pull-up
1: No
0: Yes
P41
Pull-up
1: No
0: Yes
P40
Pull-up
1: No
0: Yes
0001CH
P67
Pull-up
1: No
0: Yes
P66
Pull-up
1: No
0: Yes
P65
Pull-up
1: No
0: Yes
P64
Pull-up
1: No
0: Yes
P63
Pull-up
1: No
0: Yes
P62
Pull-up
1: No
0: Yes
P61
Pull-up
1: No
0: Yes
P60
Pull-up
1: No
0: Yes
00020H
P77
Pull-up
1: No
0: Yes
P76
Pull-up
1: No
0: Yes
P75
Pull-up
1: No
0: Yes
P74
Pull-up
1: No
0: Yes
P73
Pull-up
1: No
0: Yes
P72
Pull-up
1: No
0: Yes
P71
Pull-up
1: No
0: Yes
P70
Pull-up
1: No
0: Yes
00024HVacancy P86
Pull-up
1: No
0: Yes
P85
Pull-up
1: No
0: Yes
P84
Pull-up
1: No
0: Yes
P83
Pull-up
1: No
0: Yes
P82
Pull-up
1: No
0: Yes
P81
Pull-up
1: No
0: Yes
P80
Pull-up
1: No
0: Yes
00028H
PA5
Pull-up
1: No
0: Yes
PA4
Pull-up
1: No
0: Yes
PA3
Pull-up
1: No
0: Yes
PA2
Pull-up
1: No
0: Yes
PA1
Pull-up
1: No
0: Yes
PA0
Pull-up
1: No
0: Yes Vacancy Vacancy
0002CHVacancy Vacancy Vacancy PB2
Pull-up
1: No
0: Yes
PB1
Pull-up
1: No
0: Yes
PB0
Pull-up
1: No
0: Yes
PA7
Pull-up
1: No
0: Yes
PA6
Pull-up
1: No
0: Yes
MB90670/675 Series
27
■BLOCK DIAGRAM
Port 0, 1
F2MC–16L
CPU
Clock control block
(including timebase timer)
Wake-up
interrupt
External bus
interface
Port 2, 3
16-bit
reload timer 0
16-bit
reload timer 1
Port 7
Output compare
Output compare
(unit 1)
Port 9*
I2C interface *
Other pins
VCC,VSS,
MD0 to MD2
Interrupt controller
Port 5
8/10-bit
A/D converter
Internal data bus
Port 4
UART0
UART1
(SCI)
16-bit PPG timer
8-bit
PPG timer 0
8-bit
PPG timer 1
Port 8
Port 6
DTP/external
interrupt circuit
0 to 3
Input capture
(ICU)
24-bit
free run timer
Port A, B *
RAM
ROM
X0
X1
RST
HST
P10/AD08/WI0 to
P17/AD15/WI7
P00/AD00 to
P07/AD07
P20/A16 to P23/A19
P30/ALE
P31/RD
P32/WRL/WR
P33/WRH
P34/HRQ
P35/HAK
P36/RDY
P37/CLK
P24/TIN0
P26/TOT0
P25/TIN1
P27/TOT1
P70/DOT0 to
P77/DOT7
P90/SDA
P91/SCL
P50/AN0 to
P57/AN7
AVCC
AVRH
AVRL
AVSS
P47/ATG
P40/SIN0
P41/SOT0
P42/SCK0
P43/SIN1
P44/SOT1
P45/SCK1
P46/PPG0
P80/PPG1
P81 to P86
P60/INT0 to
P63/INT3
P64/ASR0 to
P67/ASR3
PA0 to PA7
PB0 to PB2
88
816
4
2
10
84
4
2
8
8
6
4
4
4
4
3
8
*Not included in the MB90670 series.
MB90670/675 Series
28
■MEMORY MAP
Notes:
• The ROM data of bank FF is reflected in the upper address of bank 00, realizing eff ective use of the C compiler
small model. The lowe r 16-bit of bank FF and the lower 16-bit of bank 00 is assigned to the same address,
enabling reference of the table on the ROM without stating “far”.
However, the ROM area of the MB90678/P678 exceeds 48 Kbytes, and for this reason, the image from FF4000H
to FFFFFFH is reflected on bank 00 and image from FF0000H to FF3FFFH bank FF only.
• In the MB90670/675 series, the upper 4-bit of the address are not output to the e xternal bus. F or this reason,
the maximum area accessib le is 1 Mb yte . The same address is accessed through diff erent banks in different
images.
For example, accessing “A00000H” and “B00000H” accesses the same address on the external bus.
• To prevent the memor y or I/O from being accessed through images, and the data from being destroyed, it is
recommended to limit number of banks to a maximum of 16 so that the banks are mapped without interfering
each other. Caution must be also taken when masking the upper address with the exter nal address output
control register (HACR).
Part number Address #1*2Address #2 *2Address #3 *2
MB90671 FFC000H00C000H000380H
MB90672 FF8000H008000H000780H
MB90673 FF4000H004000H000900H
MB90T673 — — 000900H
MB90P673 FF4000H004000H000900H
MB90676 FF8000H008000H000780H
MB90677 FF4000H004000H000900H
MB90678 FF0000H004000H000D00H
MB90T678 — — 000D00H
MB90P678 FF0000H004000H000D00H
FFFFFFH
Address#1
100000H
010000H
Address #2
Address #3
000100H
0000C0H
000000H
ROM area ROM area
ROM area
(image of
bank FF)
ROM area
(image of
bank FF)
External area
External area
External area
External area
RAM RAM RAM
Register Register Register
PeripheralPeripheral Peripheral
Single-chip mode Internal ROM
external bus mode External ROM
external bus mode
: Internal access memory
: External access memory
*1: The same external memory is accessed for bank 0F, 1F, 2F through FF.
*2: Addresses #1, #2 and #3 are unique to the product type.
: Inhibited area
002000H
004000H
*1
External area
MB90670/675 Series
29
■F2MC-16L CPU PROGRAMMING MODEL
(1) Dedicated Registers
: Accumulator (A)
Dual 16-bit register used for storing results of calculation etc. The two 16-bit reg-
isters can be combined to be used as a 32-bit register.
: Additional data bank register (ADB)
The 8-bit register indicating the additional space.
: User stack pointer (USP)
The 16-bit pointer indicating a user stack address.
: User stack bank register (USB)
The 8-bit register indicating the user stack space.
: System stack pointer (SSP)
The 16-bit pointer indicating the status of the system stack address.
: Processor status (PS)
The 16-bit register indicating the system status.
: Program bank register (PCB)
The 8-bit register indicating the program space.
: Data bank register (DTB)
The 8-bit register indicating the data space.
: Program counter (PC)
The 16-bit register indicating storing location of the current instruction code.
: Direct page register (DPR)
The 8-bit register for specifying bit 8 through 15 of the operand address in the
short direct addressing mode.
: System stack bank register (SSB)
The 8-bit register indicating the system stack space.
AH AL
USP
SSP
DPR
PCB
DTB
USB
SSB
ADB
PS
PC
8-bit
16-bit
32-bit
MB90670/675 Series
30
(2) General-purpose Registers
(3) Processor Status (PS)
Maximum of 32 banks
000180 H + (RP × 10 H )
R7
R5
R3
R1
R6
R4
R2
R0
RW7
RW6
RW5
RW4
RL3
RL2
RL1
RL0
RW3
RW2
RW1
RW0
16-bit
ILM RP CCR
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
ILM2 B4ILM1 ILM0 B3 B2 B1 B0 —ISTNZVC
00 000 000 10XXXXX
—
PS
Initial value
X : Indeterminate
— : Unused
MB90670/675 Series
31
■I/O MAP
(Continued)
Address Abbreviated
register name Register name Read/
write Resource name Initial value
000000HPDR0 Port 0 data register R/W Port 0 XXXXXXXXB
000001HPDR1 Port 1 data register R/W Port 1 XXXXXXXXB
000002HPDR2 Port 2 data register R/W Port 2 XXXXXXXXB
000003HPDR3 Port 3 data register R/W Port 3 XXXXXXXXB
000004HPDR4 Port 4 data register R/W Port 4 XXXXXXXXB
000005HPDR5 Port 5 data register R/W Port 5 1 1 1 11 1 1 1B
000006HPDR6 Port 6 data register R/W Port 6 XXXXXXXXB
000007HPDR7 Port 7 data register R Port 7 XXXXXXXXB
000008HPDR8 Port 8 data register R/W Port 8*5–XXXXXXXB
000009HPDR9 Port 9 data register R/W Port 9*5 – – – – – – 1 1 B
00000AHPDRA Port A data register R/W Port A*5XXXXXXXXB
00000BHPDRB Port B data register R/W Port B*5 – – – – – XXXB
00000CH
to
00000EH(Vacancy)*3
00000FHEIFR Wake-up interrupt flag register R/W Wake-up
interrupt – – – – – – – 0B
000010HDDR0 Port 0 data direction register R/W Port 0 00000000B
000011HDDR1 Port 1 data direction register R/W Port 1 00000000B
000012HDDR2 Port 2 data direction register R/W Port 2 00000000B
000013HDDR3 Port 3 data direction register R/W Port 3 00000000B
000014HDDR4 Port 4 data direction register R/W Port 4 00000000B
000015HADER Analog input enable register R/W Port 5,
analog input 11111111B
000016HDDR6 Port 6 data direction register R/W Port 6 00000000B
000017HDDR7 Port 7 data direction register R/W Port 7 00000000B
000018HDDR8 Port 8 data direction register R/W Port 8*5–0000000B
000019H(Vacancy)*3
00001AHDDRA Port A data direction register R/W Port A*500000000B
00001BHDDRB Port B data direction register R/W Port B*5 – – – – – 000B
00001CH
to
00001EH(Vacancy)*3
00001FHEICR Wake-up interrupt enable register W Wake-up
interrupt 00000000B
MB90670/675 Series
32
(Continued)
Address Abbreviated
register name Register name Read/
write Resource name Initial value
000020HUMC0 Mode control register 0 R/W!
UART0
00000100B
000021HUSR0 Status register 0 R/W! 00010000B
000022HUIDR0/
UODR0 Input data register 0/
output data register 0 R/W XXXXXXXXB
000023HURD0 Rate and data register 0 R/W 00000000B
000024HSMR1 Mode register 1 R/W
UART1
(SCI)
00000000B
000025HSCR1 Control register 1 R/W! 00000100B
000026HSIDR1/
SODR1 Input data register 1/
output data register 1 R/W XXXXXXXXB
000027HSSR1 Status register 1 R/W! 00001–00B
000028HENIR DTP/interrupt enable register R/W DTP/external in-
terrupt circuit
– – – – 0000B
000029HEIRR DTP/interrupt factor register R/W – – – – 0000B
00002AHELVR Request level setting register R/W 00000000B
00002BH(Vacancy)*3
00002CHADCS A/D convertor control status reg-
ister R/W! 8/10-bit A/D
converter
00000000B
00002DH00000000B
00002EHADCR A/D convertor data register R/W!*4XXXXXXXXB
00002FH000000XXB
000030HPPGC0 PPG0 operating mode control
register R/W! 8/16-bit PPG
timer 0 0–000001B
000031HPPGC1 PPG1 operating mode control
register R/W! 8/16-bit PPG
timer 1 00000000B
000032H(Vacancy)*3
000033H
000034HPRLL0 PPG0 reload register R/W 8/16-bit PPG
timer 0 XXXXXXXXB
000035HPRLH0 R/W XXXXXXXXB
000036HPRLL1 PPG1 reload register R/W 8/16-bit PPG
timer 1 XXXXXXXXB
000037HPRLH1 R/W XXXXXXXXB
000038HTMCSR0 Timer control status register 0 R/W! 16-bit reload
timer 0
00000000B
000039H – – – – 0000B
00003AHTMR0/
TMRLR0 16-bit timer register 0/
16-bit reload register 0 R/W XXXXXXXXB
00003BHXXXXXXXXB
00003CHTMCSR1 Timer control status register 1 R/W! 16-bit reload
timer 1
00000000B
00003DH – – – – 0000B
00003EHTMR1/
TMRLR1 16-bit timer register 1/
16-bit reload register 1 R/W XXXXXXXXB
00003FHXXXXXXXXB
MB90670/675 Series
33
(Continued)
Address Abbreviated
register name Register name Read/
write Resource name Initial value
000040HIBSR I2C bus status register R
I2C interface*6
00000000B
000041HIBCR I2C bus control register R/W 00000000B
000042HICCR I2C bus clock control register R/W – – 0XXXXXB
000043HIADR I2C bus address register R/W –XXXXXXXB
000044HIDAR I2C bus data register R/W XXXXXXXXB
000045H
to
00004FH(Vacancy)*3
000050HTCCR Free-run timer control register R/W! 24-bit free-run
timer 11000000B
000051H – – 111111B
000052HICC ICU control register R/W Input capture
(ICU) 00000000B
000053H00000000B
000054HTCRL Free-run timer lower data register R 24-bit free-run
timer
00000000B
000055H00000000B
000056HTCRH Free-run timer upper data register R 00000000B
000057H00000000B
000058HCCR00 OCU control register 00 R/W Output compare
(OCU)
(unit 0)
11110000B
000059H – – – – 0000B
00005AHCCR01 OCU control register 01 R/W – – – – 0000B
00005BH00000000B
00005CHCCR10 OCU control register 10 R/W Output compare
(OCU)
(unit 1)
11110000B
00005DH – – – – 0000B
00005EHCCR11 OCU control register 11 R/W – – – – 0000B
00005FH00000000B
000060HICDR0L ICU lower data register 0 R
Input capture
(ICU)
XXXXXXXXB
000061HXXXXXXXXB
000062HICDR0H ICU upper data register 0 R XXXXXXXXB
000063H00000000B
000064HICDR1L ICU lower data register 1 R XXXXXXXXB
000065HXXXXXXXXB
000066HICDR1H ICU upper data register 1 R XXXXXXXXB
000067H00000000B
000068HICDR2L ICU lower data register 2 R XXXXXXXXB
000069HXXXXXXXXB
MB90670/675 Series
34
(Continued)
Address Abbreviated
register name Register name Read/
write Resource name Initial value
00006AHICDR2H ICU upper data register 2 R
Input capture
(ICU)
XXXXXXXXB
00006BH00000000B
00006CHICDR3L ICU lower data register 3 R XXXXXXXXB
00006DHXXXXXXXXB
00006EHICDR3H ICU upper data register 3 R XXXXXXXXB
00006FH00000000B
000070HCPR00L OCU compare lower data
register 0 R/W
Output compare
(OCU)
(unit 0)
00000000B
000071H00000000B
000072HCPR00H OCU compare upper data
register 0 R/W 00000000B
000073H00000000B
000074HCPR01L OCU compare lower data
register 1 R/W 00000000B
000075H00000000B
000076HCPR01H OCU compare upper data
register 1 R/W 00000000B
000077H00000000B
000078HCPR02L OCU compare lower data
register 2 R/W 00000000B
000079H00000000B
00007AHCPR02H OCU compare upper data
register 2 R/W 00000000B
00007BH00000000B
00007CHCPR03L OCU compare lower data
register 3 R/W 00000000B
00007DH00000000B
00007EHCPR03H OCU compare upper data register
3R/W 00000000B
00007FH00000000B
000080HCPR04L OCU compare lower data
register 4 R/W
Output compare
(OCU)
(unit 1)
00000000B
000081H00000000B
000082HCPR04H OCU compare upper data
register 4 R/W 00000000B
000083H00000000B
000084HCPR05L OCU compare lower data
register 5 R/W 00000000B
000085H00000000B
000086HCPR05H OCU compare upper data
register 5 R/W 00000000B
000087H00000000B
000088HCPR06L OCU compare lower data
register 6 R/W 00000000B
000089H00000000B
00008AHCPR06H OCU compare upper data
register 6 R/W 00000000B
00008BH00000000B
MB90670/675 Series
35
(Continued)
Address Abbreviated
register name Register name Read/
write Resource name Initial value
00008CHCPR07L OCU compare lower data
register 7 R/W Output compare
(OCU)
(unit 1)
00000000B
00008DH00000000B
00008EHCPR07H OCU compare upper data
register 7 R/W 00000000B
00008FH00000000B
000090H
to
00009EH(System reservation area)*1
00009FHDIRR Delayed interrupt factor genera-
tion/
cancellation register R/W
Delayed
interrupt
generation
module
– – – – – – – 0B
0000A0HLPMCR Low-power consumption mode
control register R/W! Low-power
consumption
(stand-by) mode 00011000B
0000A1HCKSCR Clock selection register R/W! Low-power
consumption
(stand-by) mode 11111100B
0000A2H
to
0000A4H(Vacancy)*3
0000A5HARSR Automatic ready function select
register W External bus pin 0011 – – 00B
0000A6HHACR Upper address control register W External bus pin – – – – 0000B
0000A7HEPCR Bus control signal select register W External bus pin 0000*00–B
0000A8HWDTC Watchdog timer control register R/W! Watchdog timer XXXXX111B
0000A9HTBTC Timebase timer control register R/W! Timebase timer 1 – – 00100B
0000AAH
to
0000AFH(Vacancy)*3
0000B0HICR00 Interrupt control register 00 R/W!
Interrupt
controller
00000111B
0000B1HICR01 Interrupt control register 01 R/W! 00000111B
0000B2HICR02 Interrupt control register 02 R/W! 00000111B
0000B3HICR03 Interrupt control register 03 R/W! 00000111B
0000B4HICR04 Interrupt control register 04 R/W! 00000111B
0000B5HICR05 Interrupt control register 05 R/W! 00000111B
0000B6HICR06 Interrupt control register 06 R/W! 00000111B
0000B7HICR07 Interrupt control register 07 R/W! 00000111B
0000B8HICR08 Interrupt control register 08 R/W! 00000111B
0000B9HICR09 Interrupt control register 09 R/W! 00000111B
MB90670/675 Series
36
(Continued)
Descriptions for read/write
R/W: Readable and writable
R: Read only
W: Write only
R/W!: Bits f or reading operation only or writing operation only are included. Ref er to the register lists f or specific
resource for detailed information.
Descriptions for initial value
0 : The initial value of this bit is “0”.
1 : The initial value of this bit is “1”.
* : The initial value of this bit is “1” or “0” (decided by levels on pins of MD0 through MD2).
X : The initial value of this bit is indeterminate.
– : This bit is not used. The initial value is indeterminate.
*1: Access prohibited.
*2: This area is the only e xternal access area having an address of 0000FFH or lo wer. An access operation to this
area is handled as that to external I/O area.
*3: The area corresponding to the “(Vacancy)” on the I/O map is reserved, and accessing oper ation to this area is
handled as that to internal area. No access signal to external devices are generated.
*4: Only bit 15 is writable. Reading bit 10 through bit 15 returns “0” as a reading result.
*5: In the MB90670 series, P81 through P86, P90, P91, PA0 through PA7, PB0 through PB2 are not present. For
this reason, bits corresponding to these pins are not used.
*6: The MB90670 series does not have the I2C interface . For this reason, this area is “(Vacancy)” in the MB90670
series.
Note: F or bits that is only allow ed to progr am, the initial v alue set b y the reset operation is listed as an initial value.
Note that the values are different from reading results.
For LPMCR/CKSCR/WDTC, there are cases where initialization is performed or not performed, depending
on the types of the reset. However initial value for resets that initializes the value are listed.
Address Abbreviated
register name Register name Read/
write Resource name Initial value
0000BAHICR10 Interrupt control register 10 R/W!
Interrupt
controller
00000111B
0000BBHICR11 Interrupt control register 11 R/W! 00000111B
0000BCHICR12 Interrupt control register 12 R/W! 00000111B
0000BDHICR13 Interrupt control register 13 R/W! 00000111B
0000BEHICR14 Interrupt control register 14 R/W! 00000111B
0000BFHICR15 Interrupt control register 15 R/W! 00000111B
0000C0H
to
0000FFH(External area)*2
MB90670/675 Series
37
■INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER
(Continued)
Interrupt source EI2OS
support Interrupt vector Interrupt control register Priority*4
Number Address ICR Address
Reset ×# 08 08HFFFFDCH——High
INT9 instruction ×# 09 09HFFFFD8H——
Exception ×# 10 0AHFFFFD4H——
DTP/external interrupt circuit
Channel 0 # 11 0BHFFFFD0HICR00 0000B0H*2
DTP/external interrupt circuit
Channel 1 # 12 0CHFFFFCCH
DTP/external interrupt circuit
Channel 2 # 13 0DHFFFFC8HICR01 0000B1H*2
DTP/external interrupt circuit
Channel 3 # 14 0EHFFFFC4H
Output compare Channel 0 # 15 0FHFFFFC0HICR02 0000B2H*2
Output compare Channel 1 # 16 10HFFFFBCH
Output compare Channel 2 # 17 11HFFFFB8HICR03 0000B3H*2
Output compare Channel 3 # 18 12HFFFFB4H
Output compare Channel 4 # 19 13HFFFFB0HICR04 0000B4H*2
Output compare Channel 5 # 20 14HFFFFACH
Output compare Channel 6 # 21 15HFFFFA8HICR05 0000B5H*2
Output compare Channel 7 # 22 16HFFFFA4H
24-bit free-run timer Overflow # 23 17HFFFFA0HICR06 0000B6H*2
24-bit free-run timer Intermediate
bit # 24 18HFFFF9CH
Input capture Channel 0 # 25 19HFFFF98HICR07 0000B7H*2
Input capture Channel 1 # 26 1AHFFFF94H
Input capture Channel 2 # 27 1BHFFFF90HICR08 0000B8H*2
Input capture Channel 3 # 28 1CHFFFF8CH
16-bit reload timer/
8/16-bit PPG timer 0 # 29 1DHFFFF88HICR09 0000B9H*2, *3
16-bit reload timer/
8/16-bit PPG timer 1 # 30 1EHFFFF84H
8/10-bit A/D converter measure-
ment complete # 31 1FHFFFF80HICR10 0000BAH
Wake-up interrupt ×# 33 21HFFFF78HICR11 0000BBH*2
Timebase timer interval interrupt ×# 34 22HFFFF74HLow
MB90670/675 Series
38
(Continued)
: Can be used
: Can not be used
: Can be used. With EI2OS stop function.
: Can be used if interrupt request using ICR are not commonly used.
*1: In MB90670 series, this interrupt vector is not used because the series does not have the I2C interface.
*2: • Interrupt levels for peripherals that commonly use the ICR register are in the same level.
• When the e xtended intelligent I/O service (EI2OS) is specified in a peripheral device commonly using the ICR
register, only one of the functions can be used.
• When the extended intelligent I/O ser vice (EI2OS) is specified for one of the per ipheral functions, interrupts
can not be used on the other function.
*3: Only 16-bit reload timer conforms to the extended intelligent I/O service (EI2OS). Because the 8/16-bit PPG
timer does not conform to the extended intelligent I/O service (EI2OS), disable interrupts of the 8/16-bit PPG
timer when using the extended intelligent I/O service (EI2OS) in the 16-bit reload timer.
*4: The level shows priority of same level of interrupt invoked simultaneously.
Interrupt sour ce EI2OS
support Interrupt vector Interrupt control regis-
ter Priority*4
Number Address ICR Address
UART1 (SCI) transmission com-
plete # 35 23HFFFF70HICR12 0000BCH*2High
UART0 transmission complete # 36 24HFFFF6CH
UART1 (SCI) reception complete # 37 25HFFFF68HICR13 0000BDH*2
I2C interface*1×# 38 26HFFFF64H
UART0 reception complete # 39 27HFFFF60HICR14 0000BEH
Delayed interrupt generation
module ×# 42 2AHFFFF54HICR15 0000BFHLow
×
MB90670/675 Series
39
■PERIPHERALS
1. I/O Port
(1) Input/output Port
Port 0 to 4, 6, 8, A, and B are general-purpose I/O ports ha ving a combined function as an e xternal bus pin and
a resource input. The input output ports function as general-purpose I/O port only in the single-chip mode. In
the external bus mode, the ports are configured as external bus pins, and part of pins for port 3 can be configured
as general-purpose I/O port by setting the bus control signal select register (ECSR). Each pin corresponding
to upper 4-bit of the port 2 can be switched between a resource and a port bitwise.
Only MB90675 series has port A and port B.
• Operation as output port
The pin is configured as an output port by setting the corresponding bit of the DDR register to “1”.
Writing data to PDR register when the port is configured as output, the data is retained in the output latch in
the PDR and directly output to the pin.
The v alue of the pin (the same v alue retained in the output latch of PDR) can be read out b y reading the PDR
register.
Note: When a read-modify-write instruction (e.g. bit set instruction) is perf ormed to the port data register , the
destination bit of the operation is set to the specified value, not affecting the bits configured by the
DDR register f or output, howe ver , v alues of bits configured by the DDR register as inputs are changed
because input v alues to the pins are written into the output latch. To av oid this situation, configure the
pins by the DDR register as output after writing output data to the PDR register when configuring the
bit used as input as outputs.
• Operation as input port
The pin is configured as an input by setting the corresponding bit of the DDR register to “0”.
When the pin is configured as an input, the output buff er is turned-off and the pin is put into a high-impedance
status.
When a data is written into the PDR register, the data is retained in the output latch of the PDR, but pin outputs
are unaffected.
Reading the PDR register reads out the pin level (“0” or “1”)
• Block diagram
PDR (port data register)
DDR (port direction register)
PDR read
PDR write
DDR write
DDR read
Direction latch
Output latch
Internal data bus
Standby control: Stop, timebase timer mode and SPL=1, or hardware standby mode
Standby control (SPL=1)
P-ch
N-ch
Pin
MB90670/675 Series
40
(2) N-ch Open-drain Port
Port 5 and port 9 are general-purpose I/O ports having a combined function as resource input/output. Each pin
can be switched between resource and port bitwise.
Only MB90675 series has port 9.
• Operation as output port
When a data is written into the PDR register, the data is latched to the output latch of PDR. When the output
latch v alue is set to “0”, the output transistor is turned on and the pin status is put into an “L” le vel output, while
writing “1” turns off the transistor and put the pin in a high-impedance status.
If the output pin is pulled-up, setting output latch value to “1” puts the pin in the pull-up status.
Reading the PDR register returns the pin value (same as the output latch value in the PDR).
Note: Execution of a read-modify-write instruction (e.g. bit set instruction) reads out the output latch value
rather than the pin value, leaving output latch that is not manipulated unchanged.
• Operation as input port
Setting corresponding bit of the PDR register to “1” turns off the output transistor and the pin is put into a high-
impedance status.
Reading the PDR register returns the pin level (“0” or “1”).
• Block diagram of port 5
Internal data bus
ADER (analog input enable register)
PDR (port data register)
ADER read
ADER write
ADER latch
PDR write
PDR read
Output latch
Standby control: Stop, timebase timer mode and SPL=1, or hardware standby mode
Standby control (SPL=1)
To analog input
Pin
Output trigger
RMW
(read-modify-write
instruction)
• Block diagram of port 9
Internal data bus
To resource input
PDR write
PDR read
Output latch
PDR (port data register)
From resource output
Output
trigger
Standby control: Stop, timebase timer mode and SPL=1, or hardware standby mode
Pin
RMW
(read-modify-
write instruc-
tion)
Standby control
(SPL=1)
MB90670/675 Series
41
(3) Output Port
Port 7 is a general-purpose output port having a combined function as an output compare (OCU) output. Note
that only OCU output can be output when the pin is configured as an output, and it is not used for outputting
given data by writing to the data register. Each pin can be switched between an output compare output and a
port bitwise.
• Operation as output port (operation of OCU output)
Setting the corresponding bit of the DDR register to “1” configures the pin as an output port. In this case, lower
4-bit of CCR01 and CCR register are output.
When configured as an output, the output buffer is turned on and data retained in the output latch in the PDR
of the output compare is output to the pin.
Writing data to DOT bit of the OCU control register (CCR01, CCR11) corresponding to each pin writes data
in synchronization to a match operation of the output compare and output to the pin.
Reading the PDR register returns the pin level (same as the output latch value of the PDR).
When output of output compare is enabled, an output value from the output compare can be read out.
• Operation as input port
Setting corresponding bit of the DDR register to “0” configures the pin as input port.
When the pin is configured as an input port, the output buffer is turned off and the pin is put into a high-
impedance status.
Reading the PDR register returns the pin level (“0” or “1”).
•Block diagram
DDR read
OCU control register
OCU control register write
DDR (port direction register)
Direction latch
Standby control (SPL=1)
Standby control: Stop, timebase timer mode and SPL=1, or hardware standby mode
P-ch
N-ch
PDR (port data register)
Internal data bus
Pin
DDR write
PDR read
MB90670/675 Series
42
(4) Register Configuration
(Continued)
. . . . . . . . . . . .
. . . . . . . . . . . .
. . . . . . . . . . . .
. . . . . . . . . . . .
. . . . . . . . . . . .
. . . . . . . . . . . .
. . . . . . . . . . . .
. . . . . . . . . . . .
. . . . . . . . . . . .
. . . . . . . . . . . .
. . . . . . . . . . . .
. . . . . . . . . . . .
bit 15 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
(PDR1)
(PDR3)
(PDR5)
(PDR7)
(PDR9)
(PDRB)
P17 P16 P15 P14 P13 P12 P11 P10
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
bit 15 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
P07 P06 P05 P04 P03 P02 P01 P00
P27 P26 P25 P24 P23 P22 P21 P20
R/W R/W R/W R/W R/W R/W R/W R/W
P37 P36 P35 P34 P33 P32 P31 P30
(PDR0)
(PDR2)
(PDR4)
(PDR6)
(PDR8)
(PDRA)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 0
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 0
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 0
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 0
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 0
bit 15 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
bit 15 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
bit 15 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
bit 15 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
P47 P46 P45 P44 P43 P42 P41 P40
P67 P66 P65 P64 P63 P62 P61 P60
— P86 P85 P84 P83 P82 P81 P80
PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
R/W R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
P57 P56 P55 P54 P53 P52 P51 P50
P77 P76 P75 P74 P73 P72 P71 P70
——————P91P90
— — — — — PB2 PB1 PB0
Port 0 data register
(PDR0)
Port 1 data register
(PDR1)
Port 2 data register
(PDR2)
Port 3 data register
(PDR3)
Port 4 data register
(PDR4)
Port 5 data register
(PDR5)
Port 6 data register
(PDR6)
Port 7 data register
(PDR7)
Port 8 data register
(PDR8)
Port 9 data register
(PDR9)
Port A data register
(PDRA)
Port B data register
(PDRB)
Address
000000H
Address
000002H
Address
000001H
Address
000003H
Address
000004H
Address
000005H
Address
000006H
Address
000007H
Address
000008H
Address
000009H
Address
00000AH
Address
00000BH
R/W R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
MB90670/675 Series
43
(Continued)
. . . . . . . . . . . .
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. . . . . . . . . . . .
. . . . . . . . . . . .
. . . . . . . . . . . .
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. . . . . . . . . . . .
. . . . . . . . . . . .
. . . . . . . . . . . .
. . . . . . . . . . . .
. . . . . . . . . . . .
Note: Only MB90675 series has P81 through P86, P90, PA0 through PA7, and PB0 through PB2, and
MB90670 series does not have such pins.
bit-15 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
P07 P06 P05 P04 P03 P02 P01 P00 Port 0 data direction register
(DDR0)
Address
000010H(DDR1)
P17 P16 P15 P14 P13 P12 P11 P10
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
(DDR0) Port 1 data direction register
(DDR1)
Address
000011H
(DDR3)
bit 15 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
P27 P26 P25 P24 P23 P22 P21 P20
R/W R/W R/W R/W R/W R/W R/W R/W
Port 2 data direction register
(DDR2)
Address
000012H
P37 P36 P35 P34 P33 P32 P31 P30 (DDR2)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 0 Port 3 data direction register
(DDR3)
Address
000013H
R/W R/W R/W R/W R/W R/W R/W R/W
(ADER)
bit 15 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
P47 P46 P45 P44 P43 P42 P41 P40
R/W R/W R/W R/W R/W R/W R/W R/W
Port 4 data direction register
(DDR4)
Address
000014H
(DDR4)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 0
P57 P56 P55 P54 P53 P52 P51 P50 Analog input enable register
(ADER)
Address
000015H
R/W R/W R/W R/W R/W R/W R/W R/W
(DDR7)
bit 15 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
P67 P66 P65 P64 P63 P62 P61 P60
R/W R/W R/W R/W R/W R/W R/W R/W
Port 6 data direction register
(DDR6)
Address
000016H
(DDR6)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 0
P77 P76 P75 P74 P73 P72 P71 P70 Port 7 data direction register
(DDR7)
Address
000017H
R/W R/W R/W R/W R/W R/W R/W R/W
(Vacancy)
bit 15 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
— P86 P85 P84 P83 P82 P81 P80
R/W R/W R/W R/W R/W R/W R/W R/W
Port 8 data direction register
(DDR8)
Address
000018H
bit 15 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
R/W R/W R/W R/W R/W R/W R/W R/W
Port A data direction register
(DDRA)
Address
00001AH(DDRB)
(DDRA)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 0
— — — — — PB2 PB1 PB0 Port B data direction register
(DDRB)
Address
00001BH
R/W R/W R/W R/W R/W R/W R/W R/W
MB90670/675 Series
44
2. Timebase Timer
The timebase timer is a 18-bit free run counter (timebase counter) for counting up in synchronization to the
internal count clock (divided-b y-2 of oscillation) with an interval timer function f or selecting an interval time from
four types of 212/HCLK, 214/HCLK, 216/HCLK, and 219/HCLK.
The timebase timer also has a function for supplying operating clocks for the timer output for the oscillation
stabilization time or the watchdog timer etc.
(1) Register Configuration
(2) Block Diagram
. . . . . . . . . . . .
• Timebase timer control register (TBTC)
RESV —
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 0
R/W — — R/W R/W W R/W R/W
(WDTC) Initial value
1--00100B
Address
0000A9H—TBIE TBOF TBR TBC1 TBC0
: Readable and writable
: Read only
: Unused
R/W
W
—
. . . . . .
To PPG timer
Timebase timer counter
Divided-by-2
of HCLK
Power-on reset
Start stop mode
CKSCR : MCS = 1→0*1
Counter
clear circuit Interval
timer selector
Clear TBOF Set TBOF
Timebase timer control register
(TBTC)
Timebase timer
interrupt signal
#34(22H)*2
: Overflow
: Oscillation clock
: Switch machine clock from oscillation clock to PLL clock
: Interrupt number
OF
HCLK
*1
*2
———
TBIE TBRTBOF TBC1 TBC0
To oscillation stabilization
time selector of clock control block
To watchdog timer
OF OF
OF OF
× 21× 22× 23× 28× 29× 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218
MB90670/675 Series
45
3. Watchdog Timer
The watchdog timer is a 2-bit counter oper ating with an output of the timebase timer and resets the CPU when
the counter is not cleared for a preset period of time.
(1) Register Configuration
(2) Block Diagram
• Watchdog timer control register (WDTC)
Address
0000A8H
bit 15 bit 8
PONR STBR WRST ERST SRST WTE WT1 WT0(TBTC)
R : Read only
W : Write only
X : Indeterminate
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
RRRRRWWW
............ Initial value
XXXXX111B
HCLK: Oscillation clock
PONR STBR WRST ERST SRST WTE WT1 WT0
Watchdog timer control register (WDTC)
Start sleep mode
CLR and start
Watchdog timer
Overflow
To internal reset
generation circuit
Counter clear
control circuit Count clock
selector 2-bit
counter Watchdog reset
generation circuit
Clear
Divided-by-2
of HCLK
(Timebase timer counter)
× 21× 22... × 28× 29× 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218
CLR
2
4
CLR
Start stop mode
Start hold status
MB90670/675 Series
46
4. 8/16-bit PPG Timer
The 8/16-bit PPG timer is 2-channel reload timer module for outputting pulse having given frequencies/duty ratios.
The two modules performs the following operation by combining functions.
• 8-bit PPG output 2-channel independent operation mode
This is a mode for operating independent 2-channel 8-bit PPG timer, in which PPG0 and PPG1 pins correspond
to outputs from PPG0 and PPG1 respectively.
• 16-bit PPG output operation mode
In this mode, PPG0 and PPG1 are combined to be operated as a 1-channel 8/16-bit PPG timer operating as
a 16-bit timer. Because PPG0 and PPG1 outputs are reversed by an underflow from PPG1 outputting the
same output pulses from PPG0 and PPG1 pins.
• 8 + 8-bit PPG output operation mode
In this mode, PPG0 is oper ated as an 8-bit prescaler , in which an underflow output of PPG0 is used as a cloc k
source for PPG1. A toggle output of PPG0 and PPG output of PPG1 are output from PPG0 and PPG1
respectively.
The module can also be used as a D/A converter with an external add-on circuit.
(1) Register Configuration
• PPG0 operating mode control register (PPGC0)
• PPG1 operating mode control register (PPGC 1)
• PPG reload register (PRLL0,PRLH0,PRLL1,PRLH1)
Address
000030H
bit 15 bit 8
PEN0 — POE0 PIE0 PUF0 PCM1 PCM0 RESV(PPGC1)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
R/W — R/W R/W R/W R/W R/W R/W
............
Address
000031H
bit 7 bit 0
PEN1 PCS1 POE1 PIE1 PUF1 MD1 MD0 RESV
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ............
(PPGC0)
Address
PRLH0:000035H
PRLH1:000037H
bit 15 bit 8
(PRLH0,PRLH1)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
............
R/W R/W R/W R/W R/W R/W R/W R/W
bit 7 bit 0bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ............
(PRLL0,PRLL1)
R/W R/W R/W R/W R/W R/W R/W R/W
Address
PRLL0:000034H
PRLL1:000036H
R/W : Readable and writable
— : Unused
X : Indeterminate
Initial value
XXXXXXXXB
Initial value
XXXXXXXXB
Initial value
00000001B
Initial value
0-000001B
MB90670/675 Series
47
(2) Block Diagram
• Block diagram of 8/16-bit PPG timer 0
PRLH0
Timebase timer output (512/HCLK)
Peripheral clock (16/φ)
Peripheral clock (4/φ)
Peripheral clock (1/φ)
PEN0
Data bus for “H” digits
— POE0 PIE0 PUF0 PCM1 PCM0 RESV
Data bus for “L” digits
PPG0 operating mode control register (PPGC0)
PPG0 reload
register
PRLL0
Temporary buffer
(PRLBH0)
Reload selector
(L/H selector)
Down counter
(PCNT0)
Count value
Clear
CLK
2
Select signal
reload
Underflow Pulse selector
PPG0
output latch
Reverse
PPG output
control circuit
Mode control signal
Pin
P46/PPG0
Count clock selector
PPG1 underflow
PPG0 underflow
(to PPG1)
Select signal
* : Interrupt number
HCLK : Oscillation clock
φ :Machine clock frequency
2
R
SQ Interrupt request
#29 (1DH)*
MB90670/675 Series
48
• Block diagram of 8/16-bit PPG timer 1
PPG1 underflow
(to PPG0)
Timebase timer output (512/HCLK)
* : Interrupt number
HCLK : Oscillation clock
φ : Machine clock frequency
PRLH1 PEN1
Data bus for “H” digits
PCS1 POE1 PIE1 PUF1 MD1 MD0 RESV
Data bus for “L” digits
PPG1 operating mode control register (PPGC1)
PRLL1
Temporary buffer
(PRLBH0)
Reload selector
(L/H selector)
Down counter
(PCNT1) PPG1
output latch Pin
Count value Clear
2
Select signal
reload
Underflow
Reverse
PPG output control circuit P80/PPG1
Count clock selector
Select signal
R
SQ
PPG1 reload
register
Operating mode
control signal
PPG0 underflow
CLK MD0
Interrupt request
#30 (1EH)*
Peripheral clock (1/φ)
MB90670/675 Series
49
5. 16-bit Reload Timer
The 16-bit reload timer has an internal clock mode f or counting down in synchronization to three types of internal
clocks and an event count mode f or counting do wn detecting a giv en edge of the pulse input to the e xternal bus
pin, and either of the two functions can be selectively used.
For this timer, an “underflow” is defined as the counter v alue of “0000 H” to “FFFFH”. According to this definition,
an underflow occurs after [reload register setting value + 1] counts.
In operating the counter , the reload mode for repeating counting operation after reloading a counter setting value
after an underflow or the one-shot mode for stopping the counting operation after an underflow can be selectively
used.
Because the timer can generate an interrupt upon an underflow, the timer conforms to the extended intelligent
I/O service (EI2OS).
The MB90670/675 series has 2 channels of 16-bit reload timers.
(1) Register Configuration
Initial value
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
bit 7 bit 0
• Timer control status register upper digits (TMCSR0,TMCSR1 : H)
Address
TMCSR0:000039H
TMCSR1:00003DH— — — — CSL1 CSL0 MOD2 MOD1 (TMCSR : L)
————R/WR/WR/WR/W
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ............. Initial value
----0000B
bit 15 bit 8
• Timer control status register lower digits (TMCSR0,TMCSR1 : L)
Address
TMCSR0:000038H
TMCSR1:00003CHOUTEMOD1
(TMCSR : H) R/W R/W R/W R/W R/W R/W R/W R/W
bit 7 bit 6 bit 5 bit 4 Initial value
00000000B
RELDOUTL UFINTE TRGCNTE
............. bit 3 bit 2 bit 1 bit 0
• 16-bit timer register 0, 1 (TMR0,TMR1)
Address
00003AH
00003BH
00003EH
00003FH
bit 15 Initial value
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
bit 14bit 13bit 12bit 11bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
RRRRRRRRRRRRRRRR
• 16-bit reload register 0, 1 (TMRL0,TMRL1)
Address
00003AH
00003BH
00003EH
00003FH
bit 15bit 14bit 13bit 12bit 11bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
WWWWWWWWWWWWWWWW
R/W : Readable and writable
R : Read only
W : Write only
— : Unused
X : Indeterminate
MB90670/675 Series
50
(2) Block Diagram
Internal data bus
TMRLR0*1
<TMRLR1>
16-bit reload register
TMRR0*1
<TMR1>
reload signal reload
control circuit
16-bit timer register (down counter) UF
Count clock generation circuit CLK
Prescaler Valid clock
decision
circuitCLK
Gate input
3
φ
Clear
Wait signal
Internal
clock
Pin Input
control
circuit
Clock
selector
Output control circuit
Output
generation circuit
To UART0, 1*1
<To 8/10-bit A/D converter>
Reverse EN
Pin
P26/TOT0*1
<P27/TOT1>
P24/TIN0*1
<P25/TIN1>
External
clock
32
Function select
Select
signal Operation
control circuit
————
CSL1 CSL0 MOD2MOD1MOD0OUTE OUTL RELD INTE UF CNTE TRG
Timer control status register (TMCSR0)*1
<TMCSR1> Interrupt request signal
#29 (1DH)*2
<#30 (1EH)>
*1 :The timer has ch.0 and ch.1, and listed in the parenthesis <> are for ch.1.
*2 :Interrupt number
φ :Machine clock frequency
MB90670/675 Series
51
6. 24-bit Free run Timer
The 24-bit free-run timer is a 24-bit up counter for counting up in synchronization to divided-by-3 or divided-by-
4 of the machine clock, in which an interrupt factor can be selected from the overflow interrupt and four types
of timer intermediate bit interrupt to be operated as an interval timer.
The free-run timer can be used to generating reference timing signals for the input capture (ICU) and output
compare (OCU).
(1) Register Configuration
bit 7 bit 0
• Free-r un timer control register upper digits (TCCR : H)
— — RESV RESV RESV RESV RESV PR0 (TCCR : L)
— — R/W R/W R/W R/W R/W R/W
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ............. Initial value
- -111111B
bit 15 bit 8
• Free-run timer control register lower digits (TCCR : L)
CLRSTP
(TCCR : H) W W R/W R/W R/W R/W R/W R/W
bit 7 bit 6 bit 5 bit 4 Initial value
11000000B
IVFEIVF TIMETIM TIS0TIS1
............. bit 3 bit 2 bit 1 bit 0
• Free-run timer upper data register (TCRH)
Address
000056H
000057H
bit 15 Initial value
00000000B
00000000B
bit 14bit 13bit 12bit 11bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
RRRRRRRRRRRRRRRR
R/W : Readable and writable
R : Read only
W : Write only
— : Unused
Address
000051H
Address
000050H
— — — — — — — — T23 T22 T21 T20 T19 T18 T17 T16
• Free-r un timer lower data register (TCRL)
Address
000054H
000055H
bit 15 Initial value
00000000B
00000000B
bit 14bit 13bit 12bit 11bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
RRRRRRRRRRRRRRRR
T15 T14 T13 T12 T11 T10 T9 T8 T7 T6 T5 T4 T3 T2 T1 T0
MB90670/675 Series
52
(2) Block Diagram
Internal data bus
Intermediate bit interrupt
request signal
#24 (18H)*
* : Interrupt number
φ : Machine clock frequency
24-bit counter
(TCR)
Output buffer
T16 to T23
T0 to T15
8To output compare (OCU)
To input capture (ICU)
16
TCRH TCRL
Upper 8-bit counter Lower 16-bit counter
Carry
Carry
4
Count
clock
selector Intermediate
bit interrupt
control circuit
Prescaler
Select signal
φφ/3
φ/4
Pause Carry
detection
Overflow
——
RESVRESVRESVRESVRESV PR0 STP CLR IVF IVFE TIM TIME TIS1 TIS0
Free-run timer control register (TCCR)
Overflow interrupt
request signal
#23 (17H)*
MB90670/675 Series
53
7. Input Capture (ICU)
The input capture (ICU) generates an interrupt request to the CPU simultaneously with a storing operation of
current counter v alue of the 24-bit free run timer to the ICU data register (ICDR) upon an input of a trigger edge
to the external pin.
There are four sets (four channels) of the input capture exter nal pins and ICU data registers (ICDR), enabling
measurements of maximum of four events.
• The input capture has four sets of external input pins (ASR0 to ASR3) and ICU registers (ICDR), enabling
measurements of maximum of four events.
• A trigger edge direction can be selected from rising/falling/both edges.
• The input capture can be set to generate an interrupt request at the storage timing of the counter v alue of the
24-bit free run timer to the ICU data register (ICDR).
• The input compare conforms to the extended intelligent I/O service (EI2OS).
• The input capture function is suited for measurements of intervals (frequencies) and pulse-widths.
(1) Register Configuration
• ICU control register upper digits (ICC : H)
Address
000053H
Initial value
00000000B
IRE3 IRE2 IRE1 IRE0 IR3 IR2 IR1 IR0 (ICC : L)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 0
.............
R/W R/W R/W R/W R/W R/W R/W R/W
• ICU control register lower digits (ICC : L)
Address
000052H
Initial value
00000000B
EG3B EG3A EG2B EG2A EG1B EG1A EG0B EG0A(ICC : H)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0bit 15 bit 8
............
R/W R/W R/W R/W R/W R/W R/W R/W
• ICU upper data register 0 to 3 (ICDR0H to ICDR3H) Initial value
00000000B
————————
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
RRRRRRRR
Address
ICDR0H : 000063H
ICDR1H : 000067H
ICDR2H : 00006BH
ICDR3H : 00006FH
Address
ICDR0H : 000062H
ICDR1H : 000066H
ICDR2H : 00006AH
ICDR3H : 00006EH
D23 D22 D21 D20 D19 D18 D17 D16
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
RRRRRRRR
Initial value
XXXXXXXXB
• ICU lower data register 0 to 3 (ICDR0L to ICDR3L)
D15 D14 D13 D12 D11 D10 D9 D8
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
RRRRRRRR
Address
ICDR0L : 000061H
ICDR1L : 000065H
ICDR2L : 000069H
ICDR3L : 00006DH
Address
ICDR0L : 000060H
ICDR1L : 000064H
ICDR2L : 000068H
ICDR3L : 00006CH
D7 D6 D5 D4 D3 D2 D1 D0
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
RRRRRRRR
Initial value
XXXXXXXXB
Initial value
XXXXXXXXB
R/W : Readable and writable
R : Read only
— : Unused
X : Indeterminate
MB90670/675 Series
54
(2) Block Diagram
Internal data bus
Edge detection circuit
Data latch signal
Latch
signal
Output latch ICU data register
(ICDR)
ICDR0H ICDR0L
ICDR1H ICDR1L
ICDR2H ICDR2L
ICDR3H ICDR3L
24
24
24
24
24-bit free-run
timer
2
2
2
2
P61/ASR0
Pin
P65/ASR1
Pin
P66/ASR2
Pin
P67/ASR3
Pin
ICU control
register (ICC)
#25 (19H)*
#26 (1AH)*
#27 (1BH)*
#28 (1CH)*
Input capture interrupt
request signal
*: Interrupt number
IRE3 IRE2 IRE1 IRE0 IR3 IR2 IR1 IR0 EG3BEG3AEG2B EG2A EG1AEG0BEG0AEG1B
MB90670/675 Series
55
8. Output Compare (OCU)
The output compare (OCU) is two sets of compare units consisting of four-channel OCU compare data registers,
a comparator and a control register.
An interrupt request can be generated for each channel upon a match detection by performing time-division
comparison between the OCU compare data register setting va lue and the counter value of the 24-bit free-run
timer.
The DOT pin can be used as a wavefor m output pin for reversing output upon a match detection or a general-
purpose output port for directly outputting the setting value of the DOT bit.
(1) Register Configuration
(Continued)
Initial value
11110000B
— — — — MD3 MD2 MD1 MD0 (CCR00 : L)
• OCU control register 00 upper digits (CCR00 : H)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 0
————R/WR/WR/WR/W
Address
000059H
Initial value
----0000B
.............
RESV RESV RESV RESV CPE3 CPE2 CPE1 CPE0(CCR00 : H)
• OCU control register 00 lower digits (CCR00 : L)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0bit 15 bit 8
R/W R/W R/W R/W R/W R/W R/W R/W
Address
000058H
............
Initial value
00000000B
ICE3 ICE2 ICE1 ICE0 IC3 IC2 IC1 IC0 (CCR01 : L)
• OCU control register 01 upper digits (CCR01 : H)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
Address
00005BH
Initial value
----0000B
.............
— — — — DOT3 DOT2 DOT1 DOT0(CCR01 : H)
• OCU control register 01 lower digits (CCR01 : L)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0bit 15 bit 8
————R/WR/WR/WR/W
Address
00005AH
............
R/W : Readable and writable
— : Unused
MB90670/675 Series
56
(Continued)
• OCU compare upper data register 0 to 7 (CPR00H to CPR07H)
• OCU compare lower data register 0 to 7 (CPR00L to CPR07L)
Initial value
00000000B
Address
CPR00H : 000073H
CPR01H : 000077H
CPR02H : 00007BH
CPR03H : 00007FH
CPR04H : 000083H
CPR05H : 000087H
CPR06H : 00008BH
CPR07H : 00008FH
————————
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
R/W R/W R/W R/W R/W R/W R/W R/W
D23 D22 D21 D20 D19 D18 D17 D16
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
Initial value
00000000B
Address
CPR00H : 000072H
CPR01H : 000076H
CPR02H : 00007AH
CPR03H : 00007EH
CPR04H : 000082H
CPR05H : 000086H
CPR06H : 00008AH
CPR07H : 00008EH
Initial value
00000000B
Address
CPR00L : 000071H
CPR01L : 000075H
CPR02L : 000079H
CPR03L : 00007DH
CPR04L : 000081H
CPR05L : 000085H
CPR06L : 000089H
CPR07L : 00008DH
D15 D14 D13 D12 D11 D10 D9 D8
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
R/W R/W R/W R/W R/W R/W R/W R/W
D7 D6 D5 D4 D3 D2 D1 D0
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
Initial value
00000000B
Address
CPR00L : 000070H
CPR01L : 000074H
CPR02L : 000078H
CPR03L : 00007CH
CPR04L : 000080H
CPR05L : 000084H
CPR06L : 000088H
CPR07L : 00008CH
R/W : Readable and writable
— : Unused
MB90670/675 Series
57
(2) Block Diagram of Output Compare (OCU)
• Overall block diagram
Output compare unit 00 to 03
(unit 0)
Free-run timer data
MATCH0 to MATCH3
T1 to T23
RB15 to RB0
EXT0 to EXT3
ICOMP0 to ICOMP3
DOT0 to DOT3
Output compare unit 04 to 07
(unit 1)
MATCH4 to MATCH7
T1 to T23
RB15 to RB0
EXT0 to EXT3
ICOMP4 to ICOMP7
DOT4 to DOT7
OPEN
Interrupt request
(ICOMP0 to ICOMP3)
Interrupt request
(ICOMP4 to ICOMP7)
P70/DOT0 to P73/DOT3
P74/DOT4 to P77/DOT7Pin
Pin
Output compare unit
Internal data bus
23
16
4
4
16
4
4
4
4
MB90670/675 Series
58
•Block diagram of unit 0
Internal data bus
OCU control register 00 (CCR00)
MD3 MD2 MD1 MD0 RESVRESV RESV CPE3 CPE2 CPE1 CPE0
————
Compare circuit
24-bit free-run timer
Compare control block
Data latch
bit 23 to bit 2 Compare
control
T1 T0
General-purpose port/
compare pin switching
CPR00H
CPR01H
CPR02H
CPR03H
CPR00L
CPR01L
CPR02L
CPR03L
OCU compare data register 0 to 3
IC3 IC2 IC1 IC0
——— —
DOT3 DOT2 DOT1 DOT0
ICE3 ICE2 ICE1 ICE0
OCU control register 01 (CCR01)
#15 (0FH)*
#16 (10H)*
#17 (11H)*
#18 (12H)*
Output compare
interrupt request signal
Match operation enabled
MATCH0 to MATCH3
(to unit 1)
Output
control circuit
Clock
selector
Output
latch
Pin
Pin
Pin
Pin
P73/DOT3
P72/DOT2
P71/DOT1
P70/DOT0
*: Interrupt number
44
4
2
44
RESV
Match
signal
MB90670/675 Series
59
•Block diagram of unit 1
Internal data bus
OCU control register10 (CCR10)
MD3 MD2 MD1 MD0 SEL1SEL2 SEL0 CPE3 CPE2 CPE1 CPE0
————
SEL3
General-purpose port/compare pin switching
MATCH0 to MATCH3
(from unit 0)
24-bit free-run timer
Compare control block
bit 23 to bit 2 Compare
control
T1 T0
Data latch
CPR04H
CPR05H
CPR06H
CPR07H
CPR04L
CPR05L
CPR06L
CPR07L
OCU compare data register 4 to 7
IC3 IC2 IC1 IC0
——— —
DOT3 DOT2 DOT1 DOT0
ICE3 ICE2 ICE1 ICE0
OCU control register 11 (CCR11)
#19 (13H)*
#20 (14H)*
#21 (15H)*
#22 (16H)*
Output compare
interrupt request signal
*: Interrupt number
Match
operation
enabled
2
Output control circuit
Clock
selector
Factor
selector
Output
latch
Pin
Pin
Pin
Pin
P77/DOT7
P76/DOT6
P75/DOT5
P74/DOT4
4
4
4
444
4
4
Match
signal
Compare circuit
MB90670/675 Series
60
9. I2C Interface (Included Only in MB90675 Series)
The I2C interface is a serial I/O port supporting Inter IC BUS operating as master/sla ve devices on I2C bus and
has the following features.
• Master/slave transmission/reception
• Arbitration function
• Clock synchronization function
• Slave address/general call address detection function
• Transmission direction detection function
• Repeated generation function start condition and detection function
• Bus error detection function
(1) Register Configuration
. . . . . . . . . . . .
. . . . . . . . . . . .
. . . . . . . . . . . .
. . . . . . . . . . . .
. . . . . . . . . . . .
•I
2C b us status register (IBSR)
bit 15 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
(IBCR)
BER BEIE SCC MSS ACK GCAA INTE INT
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 0
RRRRRRRR
R/W R/W R/W R/W R/W R/W R/W R/W
BB RSC AL LRB TRX AAS GCA FBT
(IBSR)
Initial value
00000000B
Address
000040H
Address
000041H
Initial value
00000000B
bit 15 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
(IADR)
——R/W
— — EN CS4 CS3 CS2 CS1 CS0
Initial value
--0XXXXXB
Address
000042H
R/W R/WR/W R/W R/W
•I
2C bus control register (IBCR)
•I
2C bus clock control register (ICCR)
—A6A5A4A3A2A1A0
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 0
— R/W R/W R/W R/W R/W R/W R/W
(ICCR)
Address
000043HInitial value
-XXXXXXXB
(IADR)
bit 15 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
(Reserved area) D7
Initial value
XXXXXXXXB
Address
000044H
R/W R/WR/W R/W R/W
D6 D5 D4 D3 D2 D1 D0
R/WR/WR/W
(IDAR)
: Readable and writable
: Read only
: Unused
: Indeterminate
R/W
R
—
X
•I
2C address register (IADR)
MB90670/675 Series
61
(2) Bloc k Diagram
Internal data bus
I2C bus control register
(IBCR) I2C bus status register
(IBSR)
BER BEIE SCC MSS ACK
GCAA INTE
INT BB RSC AL LRB TRX AAS GCA FBT
Error
Start
Master
ACK enable
GC-ACK enable
Interrupt enable
Transmission
enable flag
Bus busy
Repeat start
Last bit
Transmit/receive
Slave
General call
Detection of first byte
Number of in-
terrupt re-
quest
generated
Start stop condition
generation circuit Start stop condition
detection circuit
Interrupt request signal
#38 (26H)*
SDA line
CCL line Pin
P90/SDA
Pin
P91/SCL
I2C enable
IDAR register
Slave address
comparison circuit
IADR register
Arbitration lost
detection circuit
Clock control block
4
φ
Clock di-
vider 1
(1/5 to 1/
8)
Count
clock
selector 1 Clock
divider 2
Count
clock
selector 2
Shift clock
generation
circuit
Sync
8
I2C enable
— — EN CS4 CS3 CS2 CS1 CS0
I2C bus clock control register
(ICCR)
φ:Machine clock frequency
*:Interrupt number
MB90670/675 Series
62
10. UART0
UAR T0 is a general-purpose serial data communication interface f or performing synchronous or asynchronous
communication (start-stop synchronization system). In addition to the nor mal duplex communication function
(normal mode), UART0 has a master/slave type communication function (multi-processor mode).
• Data buffer: Full-duplex double buffer
• Transfer mode: Clock synchronized (with start and stop bit)
Clock asynchronized (start-stop synchronization system)
• Baud rate: With dedicated baud rate generator, selectable from 12 types
External clock input possible
Internal clock (a clock supplied from 16-bit reload timer can be used.)
• Data length: 7 bits to 9 bits selective (with a parity bit)
6 bits to 8 bits selective (without a parity bit)
• Signal format: NRZ (Non Return to Zero) system
• Reception error detection:Framing error
Overrun error
Parity error (not available in multi-processor mode)
• Interrupt request:Receive interrupt (reception complete, receive error detection)
Receive interrupt (transmission complete)
Transmit/receive conforms to extended intelligent I/O service (EI2OS)
• Master/slave type communication function (multi-processor mode): 1 (master) to n (slave) communication
possible
(1) Register Configuration
• Status register 0 (USR0)
RDRF ORFE PE TDRE RIE TIE RBF TBF
R/W R/W R/W R/W R/W R/W R/W R/W
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
Address
000021H
Initial value
00100000B
(UMC0)
bit 7 bit 0
.............
• Mode control register 0 (UMC0)
PEN SBL MC1 MC0 SMDE RFC SCKE SOE
R/W R/W R/W R/W R/W R/W R/W R/W
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Address
000020H
Initial value
00000100B
(USR0)
bit 15 bit 8
............
• Rate and data register 0 (URD0)
BCH RC3 RC2 RC1 RC0 BCH0 P D8
R/W R/W R/W R/W R/W R/W R/W R/W
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8Address
000023H
Initial value
00000000B
(UIDR0/UODR0)
bit 7 bit 0
.............
• Input data register 0 (UIDR0)
D7 D6 D5 D4 D3 D2 D1 D0
RR RRRR RR
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0Address
000022H
Initial value
XXXXXXXXB
(URD0)
bit 15 bit 9
.... . bit 8
D8
R
• Output data register 0 (UODR)
D7 D6 D5 D4 D3 D2 D1 D0
WW WWWW WW
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0Address
000022HInitial value
XXXXXXXXB
(URD0)
bit 15 bit 9
.... . bit 8
D8
W
R/W : Readable and writable
R : Read only
W: Write only
X : Indeterminate
MB90670/675 Series
63
(2) Block Diagram
Clock
selector
Dedicated baud
rate generator
16-bit reload
timer 0
Pin
P42/SCK0
Pin
P40/SIN0
Receive condition
decision circuit
UMC0
register USR0
register URD0
register
Receive
clock Receive
control circuit
Start bit
detection circuit
Receive bit
counter
Receive parity
counter
Shift register for
reception
UIDR0 UODR0
Transmit
Transmit
control circuit
Transmit start
circuit
Transmit bit
counter
Transmit parity
counter
Shift register for
transmission
Receive
interrupt signal
#39 (27H)*
Transmit
interrupt signal
#36 (24H)*
Pin
P42/SOT0
Start transmission
To EI2OS reception
error generation
signal (to CPU)
Internal data bus
PEN
SBL
MC1
MC0
SMDE
RFC
SCKE
SOE
RDRF
ORFE
PE
TDRE
RIE
TIE
RBF
TBF
BCH
RC2
RC1
RC0
BCH0
P
D8
*: Interrupt number
Control bus
Reception
complete
RC3
MB90670/675 Series
64
11. UART1 (SCI)
UART1 (SCI) is a general-purpose serial data communication interface for performing synchronous or asyn-
chronous communication (start-stop synchronization system). In addition to the normal duplex communication
function (normal mode), UART1 has a master-slave type communication function (multi-processor mode).
• Data buffer: Full-duplex double buffer
• Transfer mode: Clock synchronized (no start or stop bit)
Clock asynchronized (start-stop synchronization system)
• Baud rate: With dedicated baud rate generator, selectable from 8 types
External clock input possible
Internal clock (a internal clock supplied from 16-bit reload timer can be used.)
• Data length: 7 bits (for asynchronous normal mode only)
8 bits
• Signal format: NRZ (Non Return to Zero) system
• Reception error detection:Framing error
Overrun error
Parity error (not available in multi-processor mode)
• Interrupt request:Receive interrupt (reception complete, receive error detection)
Receive interrupt (transmission complete)
Transmit/receive conforms to extended intelligent I/O service (EI2OS)
• Master/slave type communication function (multi-processor mode):1 (master) to n (slave) communication pos-
sible (supported only for master station)
(1) Register Configuration
• Control register 1 (SCR1)
R/W : Readable and writable
R : Read only
W : Write only
— : Unused
X : Indeterminate
Address
000025H
bit 7 bit 0
PEN
Initial value
00000100B
P SBL CL A/D REC RXE TXE (SMR1)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
R/W R/W R/W R/W R/W R/W R/W R/W
............
Address
000024H
bit 15 bit 8
(SCR1) Initial value
00000000B
............
MD0 CS2 CS1 CS0 BCH
SCKE
SOE
R/W R/W R/W R/W R/W R/W R/W R/W
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
MD1
Address
000027H
bit 7 bit 0
PE
Initial value
00001-00B
ORE FRE
RDRF TDRE
— RIE TIE (SIDR1/SODR1)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
RRRRR—R/WR/W
............
Address
000026H
bit 15 bit 8
(SSR1) Initial value
XXXXXXXXB
............
D6 D5 D4 D3 D2 D1 D0
RRRRRRRR
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
D7
Address
000026H
bit 15 bit 8
(SSR1) Initial value
XXXXXXXXB
............
D6 D5 D4 D3 D2 D1 D0
WWWWWWWW
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
D7
• Mode register 1 (SMR1)
• Status register 1 (SSR1)
• Input data register 1 (SIDR1)
• Output data register 1 (SODR1)
MB90670/675 Series
65
(2) Bloc k Diagram
*: Interrupt number
Pin
Clock
selector
MD1
MD0
CS2
CS1
CS0
BCH
SCKE
SOE
Internal data bus
PEN
P
SBL
CL
A/D
REC
RXE
TXE
PE
ORE
FRE
RDRF
TDRE
RIE
TIE
Start transmission
Transmit
control circuit
Transmit
clock
Receive
clock Receive
control circuit
Receive
interrupt signal
#37 (25H)*
Transmit
interrupt signal
#35 (23H)*
Dedicated baud
rate generator
16-bit reload
timer 1
P45/SCK1
Pin
P43/SIN1
Pin
P44/SOT1
Start bit
detection circuit
Receive bit
counter
Receive parity
counter
Transmit start
circuit
Transmit bit
counter
Transmit parity
counter
Shift register for
reception Shift register for
transmission
SIDR1
Receive condition
decision circuit
SODR1
Reception
complete
To EI2OS reception
error generation
signal (to CPU)
SMR1
register SCR1
register SSR1
register
Control bus
MB90670/675 Series
66
12. DTP/External Interrupt Circuit
The DTP (Data Transfer Peripheral)/external interrupt circuit is located between peripheral equipment connected
externally and the F2MC-16L CPU and transmits interrupt requests or data transfer requests generated by
peripheral equipment to the CPU, generates exter nal interrupt request and star ts the extended intelligent I/O
service (EI2OS).
(1) Register Configuration
• DTP/interrupt factor register (EIRR)
Address
000029H
bit 7 bit 0
— — — — ER3 ER2 ER1 ER0
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ............
(ENIR) Initial value
- - - -0000B
————R/WR/WR/WR/W
Address
000028H
bit 15 bit 8
— — — — EN3 EN2 EN1 EN0(EIRR)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
............
— — — — R/W R/W R/W R/W
Initial value
- - - -0000B
Address
00002AH
bit 15 bit 8
LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0(Vacancy)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
............
R/W R/W R/W R/W R/W R/W R/W R/W
Initial value
00000000B
• DTP/interrupt enable register (ENIR)
• Request level setting register (ELVR)
R/W : Readable and writable
— : Unused
MB90670/675 Series
67
(2) Bloc k Diagram
#14 (0EH)*
#13 (0DH)*
#14 (0CH)*
#11 (0BH)*
Pin
Request level setting register (ELVR)
P60/INT0
Pin
P61/INT1
Pin
P62/INT2
Pin
P63/INT3
LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0
Level edge
selector 3 Level edge
selector 1
Level edge
selector 2 Level edge
selector 0
DTP/external interrupt input
detection circuit
DTP/interrupt factor register
(EIRR)
DTP/interrupt enable register
(ENIR)
*: Interrupt signal
Internal data bus
Interrupt request signal
— — — — ER3 ER2 ER1 ER0
— — — — EN3 EN2 EN1 EN0
22 2
2
MB90670/675 Series
68
13. Wake-up Interrupt
W ak e-up interrupts transmits interrupt request (“L” lev el) generated b y peripheral de vice located between e xter-
nal peripheral devices and the F2MC-16L CPU to the CPU and invokes interrupt processing.
The interrupt does not conform to the extended intelligent I/O service (EI2OS).
(1) Register Configuration
(2) Bloc k Diagram
bit 7 bit 0bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ............
• Wake-up interrupt flag register (EIFR)
Address
00000FH———————WIF (Vacancy) Initial value
-------0B
R/W : Readable and writable
— : Unused
———————R/W
• Wake-up interrupt enable register (EICR)
EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 (Vacancy)
bit 7 bit 0bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ............
Address
00001FHInitial value
00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
P10/AD08/WI0 Pin
Wake-up interrupt
enable register (EICR)
Interrupt request detection circuit
Internal data bus
Wake-up interrupt flag
register (EIFR)
*: Interrupt number
Wake-up interrupt
request
#33 (21H)*
Pin
Pin
Pin
Pin
Pin
Pin
Pin
EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 — — — ————WIF
P11/AD09/WI1
P12/AD10/WI2
P13/AD11/WI3
P14/AD12/WI4
P15/AD13/WI5
P16/AD14/WI6
P17/AD15/WI7
MB90670/675 Series
69
14. Delayed Interrupt Generation Module
The dela y ed interrupt generation module generates interrupts f or s witching tasks f or de v elopment on a realtime
operating system (REALOS softw are). The module can be used to generate hardw are interrupt requests to the
CPU with software and cancel the interrupt requests.
This module does not conform to the extended intelligent I/O service (EI2OS).
(1) Register Configuration
(2) Bloc k Diagram
• Delayed interrupt factor generation/cancellation register (DIRR)
Address
00009FH
bit 7 bit 0
———————R0
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ............
(Reserved area)
———————R/W
Initial value
-------0B
R/W : Readable and writable
— : Unused
Delayed interrupt factor generation/
cancellation register (DIRR)
*: Interrupt signal
—S factor
——————R0
Internal data bus
Interrupt request signal
#42 (2AH)*
R latch
MB90670/675 Series
70
15. 8/10-bit A/D Converter
The 8/10-bit A/D converter has a function of converting analog voltage input to the analog input pins (input
voltage) to digital values (A/D conversion) and has the following features.
• Minimum conversion time: 6.13 µs (at machine clock of 16 MHz, including sampling time)
• Minimum sampling time: 3.75 µs (at machine clock of 16 MHz)
• Conversion method: RC successive approximation method with a sample and hold circuit.
• Resolution: 10-bit or 8-bit selective
• Analog input pins: Selectable from eight channels by software
One-shot conversion mode:Stops conversion after completing a conversion for a stopped channel (one
channel only) or for successive channels (maximum of eight channels can be
specified)
Continuous conversion mode:Continues conversions for a specified channel (one channel only) or for
successive channels (maximum of eight channels can be specified)
Stop conversion mode:Stops conversion after completing a conversion for one channel and wait for the next
activation.
• Interrupt requests can be generated and the e xtended intelligent I/O service (EI2OS) can be started after the
end of A/D conversion.
• When interrupts are enabled, there is no loss of data even in continuous operations because the conversion
data protection function is in effect.
• Starting factors for conversion:Selected from software activation, 16-bit reload timer 1 output (rising edge),
and external trigger (falling edge).
(1) Register Configuration
• A/D control status register upper digits (ADCS: H)
Address
00002DH
bit 7 bit 0
BUSY INT INTE PAUS STS1 STS0 STRT RESV
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ............
(ADCS: L)
R/W R/W R/W R/W R/W R/W W R/W
Address
00002CH
bit 15 bit 8
MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0(ADCS: H)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
............
R/W : Readable and writable
R : Read only
W: Write only
—: Unused
X : Indeterminate
• A/D control status register lower digits (ADCS: L)
Address
00002EHS10
• A/D data register (ADCR)
— — — — —D9D8D7D6D5D4D3D2D1D0
bit 15bit 14 bit 13 bit 12bit 11 bit 10
bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
R/W—————RRRRRRRRRR
Initial value
00000000B
Initial value
00000000B
Initial value
XXXXXXXXB
0000000XB
MB90670/675 Series
71
(2) Bloc k Diagram
φ : Machine clock frequency
TO : 16-bit reload timer channel 1 output
* : Interrupt number
Interrupt request signal #31 (1FH)*
Clock selector Decoder
Sample hold
circuit Control circuit
D/A converter
Analog
channel
selector
Comparator
A/D data register
(ADCR)
AVR
AVCC
AVSS
P47/ATG
TO
A/D control status
register (ADCS)
BUSY
INT INTE PAUS STS1 STS0 STRT RESV MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0
S10— — — — —D9D8D7D6D5D4D3D2D1D0
Internal data bus
P57/AN7
P56/AN6
P55/AN5
P54/AN4
P53/AN3
P52/AN2
P51/AN1
P50/AN0
2
6
φ
MB90670/675 Series
72
16. Low-power Consumption (Standby) Mode
The F2MC-16L has the following CPU operating mode configured by selection of an operating clock and clock
operation control.
•Clock mode
PLL clock mode: A mode in which the CPU and peripheral equipment are driven b y PLL-multiplied oscillation
clock (HCLK).
Main clock mode: A mode in which the CPU and peripheral equipment are driven by divided-by-2 of the
oscillation clock (HCLK).
The PLL multiplication circuits stops in the main clock mode.
• CPU intermittent operation mode
The CPU intermittent operation mode is a mode for reducing power consumption by operating the CPU
intermittently while external bus and peripheral functions are operated at a high-speed.
• Hardware stand-by mode
The hardware standby mode is a mode for reducing power consumption by stopping clock supply (sleep mode)
to the CPU by the low-power consumption control circuit, stopping clock supplies to the CPU and peripheral
functions (timebase timer mode), and stopping oscillation clock (stop mode, hardware standby mode).
Of these modes, modes other than the PLL clock mode are power consumption modes.
(1) Register Configuration
• Clock select register (CKSCR)
Address
0000A1H
bit 7 bit 0
RESV MCM WS1 WS0 RESV MCS CS1 CS0
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ............
(LPMCR)
R/W R R/W R/W R/W R/W W R/W
Address
0000A0H
bit 15 bit 8
STP SLP SPL RST RESV CG1 CG0 RESV(CKSCR)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
W W R/W W R/W R/W R/W R/W
............
R/W : Readable and writable
R : Read only
W : Write only
• Low-power consumption mode control register (LPMCR)
Initial value
00011000B
Initial value
11111100B
MB90670/675 Series
73
(2) Bloc k Diagram
Pin Hi-z control
Low-power consumption mode control register (LPMCR)
Internal reset
Select intermittent cycle
CPU clock
Stop and sleep signal
Stop signal
Main clock
Clock selection register (CKSCR)
Clock selector
Cancellation of
oscillation
stabilization time
Machine clock
Cancellation of interrupt
Cancellation of reset
RST
HST
CPU intermittent
operation
selector
Standby control
circuit
RST
Internal reset
generation
circuit
Pin
Pin
X0 Pin
X1 Pin
STP SLP SPL RST RESV CG1 CG0 RESV
RESV MCM WS1 WS0 RESV MCS CS1 CS0
Pin
high-impedance
control circuit
CPU clock
control circuit
Peripheral clock
control circuit
Divided
-by-2 Divided
-by-2048 Divided
-by-4 Divided
-by-4 Divided
-by-8
Peripheral clock
Timebase timer
System clock
generation
circuit
Clock
generation
block
Oscillation
stabilization
time selector
2
2
2
PLL multiplication
circuit
MB90670/675 Series
74
■ELECTRICAL CHARACTERISTICS
1. Absolute Maximu m Ratings (AVSS = VSS = 0.0 V)
*1:AVCC shall ne v er exceed VCC. AVRH shall ne v er exceed VCC and AVCC. Also , AVRL shall nev er exceed VCC, AVCC
and AVRH.
*2:VI and VO shall never exceed VCC + 0.3 V.
*3:The maximum output current is a peak value for a corresponding pin.
*4:Average output current is an average current value observed for a 100 ms period for a corresponding pin.
*5:Total average current is an average current value observed for a 100 ms period for all corresponding pins.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
Parameter Symbol Value Unit Remarks
Min. Max.
Power supply voltage
VCC VSS – 0.3 VSS + 7.0 V
AVCC VSS – 0.3 VSS + 7.0 V *1
AVRH,
AVRL VSS – 0.3 VSS + 7.0 V *1
Input voltage VIVSS – 0.3 VCC + 0.3 V *2
Output voltage VOVSS – 0.3 VCC + 0.3 V *2
“L” level maximum output current IOL 15 mA *3
“L” level average output current IOLAV 4mA*4
“L” level total maximum output current ΣIOL 100 mA
“L” level total average output current ΣIOLAV 50 mA *5
“H” level maximum output current IOH –15 mA *3
“H” level average output current IOHAV –4 mA *4
“H” level total maximum output current ΣIOH –100 mA
“H” level total average output current ΣIOHAV –50 mA *5
Power consumption PD400 mW
Operating temperature TA–40 +85 °C
Storage temperature Tstg –55 +150 °C
MB90670/675 Series
75
2. Recommended Operating Conditions (AVSS = VSS = 0.0 V)
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device's electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor de vices within their recommended oper ating condition r anges . Oper ation
outside these ranges may adversely affect reliability and could result in device failure.
No warr anty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
Parameter Symbol Value Unit Remarks
Min. Max.
Power supply voltage VCC 2.7 5.5 V Normal operation
VCC 2.0 5.5 V Retains status at the time of opera-
tion stop
Operating temperature TA–40 +85 °C
MB90670/675 Series
76
3. DC Characteristics (AVCC = VCC = 2.7 V to 5.5 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
(Continued)
Parameter Symbol Pin name Condition Value Unit Remarks
Min. Typ. Max.
“H” level in-
put voltage
VIH Pins other than VIHS
and VIHM
—
0.7 VCC —VCC + 0.3 V
VIHS
Hysteresis input pins
P24 to P27, P40 to
P47,
P60 to P67, P70 to
P77,
P80, HST, RST
0.8 VCC —VCC + 0.3 V MB90670
series
VIHS
Hysteresis input pins
P24 to P27, P40 to
P47,
P60 to P67, P70 to
P77,
P80 to P86, HST,
RST,
P90, P91, PA0 to
PA7,
PB0 to PB2
0.8 VCC —VCC + 0.3 V MB90675
series
VIHM MD pin input VCC – 0.3 — VCC + 0.3 V
“L” level in-
put voltage
VIL Pins other than VILS
and VILM VSS – 0.3 — 0.3 VCC V
VILS
Hysteresis input pins
P24 to P27, P40 to
P47,
P60 to P67, P70 to
P77,
P80, HST, RST
VSS – 0.3 — 0.2 VCC VMB90670
series
VILS
Hysteresis input pins
P24 to P27, P40 to
P47,
P60 to P67, P70 to
P77,
P80 to P86, HST,
RST,
P90, P91, PA0 to
PA7,
PB0 to PB2
VSS – 0.3 — 0.2 VCC VMB90675
series
VILM MD pin input VSS – 0.3 — VSS + 0.3 V
“H” level
output volt-
age
VOH Other than P50 to P57 VCC = 4.5 V
IOH = –4.0 mA VCC – 0.5 — — V
VOH Other than P50 to P57 VCC = 2.7 V
IOH = –1.6 mA VCC – 0.3 — — V
“L” level
output volt-
age
VOL All output pins VCC = 4.5 V
IOL = 4.0 mA ——0.4V
VOL All output pins VCC = 2.7 V
IOL = 2.0 mA ——0.4V
Open-drain
output leak-
age current Ileak P50 to P57, P90,
P91*1 ——0.110µA
MB90670/675 Series
77
(Continued)
(AVCC = VCC = 2.7 V to 5.5 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
*1: Only MB90675 series has P90 and P91 pins.
*2: The current value is preliminary value and may be subject to change for enhanced characteristics without
previous notice.
Parameter Symbol Pin name Condition Value Unit Remarks
Min. Typ. Max.
Input leak-
age current IIL Other than P50 to
P57, P90 and P91 VCC = 5.5 V
VSS < VI < VCC –10 — 10 µA
Pull-up re-
sistance R—V
CC = 5.0 V 25 45 100 kΩ
R—VCC = 3.0 V 40 95 200 kΩ
Pull-down
resistance R—V
CC = 5.0 V 25 50 200 kΩ
R—VCC = 3.0 V 40 100 400 kΩ
Power sup-
ply current
ICC —
Internal opera-
tion at
16 MHz
VCC at 5.0 V
—5070mA
Normal op-
eration*2
ICCS —
Internal opera-
tion at
16 MHz
VCC at 5.0 V
—1030mA
In sleep
mode*2
ICC —
Internal opera-
tion at
8 MHz
VCC at 3.0 V
—1220mA
Normal op-
eration*2
ICCS —
Internal opera-
tion at
8 MHz
VCC at 3.0 V
—2.510mA
In sleep
mode*2
ICCH —TA = +25°C—0.110µA
In stop
mode and
hardware
standby
mode*2
Input ca-
pacitance CIN Other than AVCC,
AVSS, VCC, VSS ——10—pF
MB90670/675 Series
78
4. AC Characteristics
(1) Reset Input Timing, Hardware Standby Input Timing
(AVCC = VCC = 2.7 V to 5.5 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
*: For tCP (internal operating clock cycle time), refer to “(3) Clock Timings.”
Parameter Symbol Pin name Condition Value Unit Remarks
Min. Max.
Reset input time tRSTL RST —16 tCP*— ns
Hardware standby input time tHSTL HST 16 tCP*— ns
0.2 VCC
tRSTL, tHSTL
RST
HST 0.2 VCC
• Measurement conditions f or AC ratings
Pin
CL
CL is a load capacitance connected to a pin under test.
CLK, ALE: CL = 30 pF
Address data bus (AD15 to AD00), RD, WR: CL = 80 pF
MB90670/675 Series
79
(2)Specification for Power-on Reset (AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
*: VCC must be kept lower than 0.2 V before power-on.
Notes : • The above ratings are values for causing a power-on reset.
• When HST is set to “L” le vel, apply power according to this tab le to cause a power-on reset irrespective of
whether or not a power-on reset is required.
• For built-in resources in the device, re-apply power to the resources to cause a power-on reset.
• There are internal registers which can be initialized only by a power-on reset. Apply power according to this
rating to ensure initialization of the registers.
Parameter Symbol Pin name Condi-
tion Value Unit Remarks
Min. Max.
Power supply rising time tRVCC ——30ms*
Power supply cut-off time tOFF VCC 1—ms
Due to repeated
operations
VCC
tOFF
0.2 V
2.7 V 0.2 V 0.2 V
tR
RAM data retained
VSS
Sudden changes in the power supply voltage may cause a power-on reset.
To change the power supply voltage while the device is in operation, it is recommended to raise the voltage
smoothly to suppress fluctuations as shown below.
Main power
supply voltage
Sub power supply voltage It is recommended to keep the rising
speed of the supply voltage at 50 mV/ms
or slower.
VCC
MB90670/675 Series
80
(3) Cloc k Timing
•Operation at 5.0 V ±
±±
± 10% (AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
*: The frequency fluctuation rate is the maximum deviation rate of the preset center frequency when the multiplied
PLL signal is loc ked.
The PLL frequency de viation changes periodically from the preset frequency “(about CLK × (1CYC to 50 CYC)”,
thus minimizing the chance of worst values to be repeated (errors are minimal and negligible for pulses with
long intervals).
Parameter Symbol Pin name Condition Value Unit Remarks
Min. Typ. Max.
Clock frequency FCX0, X1
—
3—32MHz
Clock cycle time tCX0, X1 31.25 — 333 ns
Input clock pulse width PWH,
PWL X0 10 — — ns Recommended
duty ratio of
30% to 70%
Input clock rising/falling time tCR,
tCF X0 — — 5 ns
Internal operating clock fre-
quency fCP —1.5—16MHz
Internal operating clock cycle
time tCP — 62.5 — 666 ns
Frequency fluctuation rate
locked ∆fP37/CLK ——3%*
| α |
fOCenter frequency
+
–
+ α
fO
– α
∆f = × 100 (%)
MB90670/675 Series
81
• Operation at VCC = 2.7 V (minimum value) (AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
*: The frequency fluctuation rate is the maxim um de viation r ate of the preset center frequency when the multiplied
PLL signal is locked.
The PLL frequency de viation changes periodically from the preset frequency “(about CLK × (1CYC to 50 CYC)”,
thus minimizing the chance of worst values to be repeated (errors are minimal and negligible for pulses with
long intervals).
Parameter Symbol Pin name Condi-
tion Value Unit Remarks
Min. Typ. Max.
Clock frequency FCX0, X1
—
3—16MHz
Clock cycle time tCX0, X1 62.5 — 333 ns
Input clock pulse width PWH,
PWL X0 20 — — ns Recommended
duty ratio of
30% to 70%
Input clock rising/falling time tCR,
tCF X0 — — 5 ns
Internal operating clock fre-
quency fCP —1.5—8MHz
Internal operating clock cycle
time tCP — 125 — 666 ns
Frequency fluctuation rate
locked ∆fP37/CLK ——3%*
| α |
fOCenter frequency
+
–
+ α
fO
– α
∆f = × 100 (%)
MB90670/675 Series
82
The AC ratings are measured for the following measurement reference voltages.
•Clock timing
PWH
0.2 VCC
0.8 VCC 0.8 VCC 0.8 VCC
0.2 VCC
PWL
tCF tCR
tC
Note : The operation guarantee range on the lower voltage is 2.7 V for the evaluation chips.
• PLL operation guarantee range
Relationship between internal operating clock frequency and power supply voltage
1.5 83 16 (MHz)
Internal clock fCP
5.5
4.5
3.3
2.7
Power supply voltage V
CC
(V)
Normal operation
range PLL operation
guarantee range
Relationship between clock frequency and internal operating clock frequency
(MHz)
Multiplied-by-4
Multiplied-by-3 Not multiplied
Multiplied-
by-2 Multiplied-by-1
Internal clock f
CP
Oscillation clock FC
3 4 8 16 24 32 (MHz)
• Input signal waveform • Output signal waveform
0.8 VCC
0.2 VCC
Hystheresis input pin
0.7 VCC
0.3 VCC
Pins other than hystheresis input/MD input
Output pin
2.4 V
0.8 V
MB90670/675 Series
83
(4) Recommended Resonator Manufacturers
• Sample application of piezoelectric resonator (FAR family)
Inquiry: FUJITSU MEDIA DEVICES LIMITED
FAR part number
(built-in capacitor type) Frequency
(MHz) Dumping
resistor
Initial deviation
of FAR frequen-
cy
(TA = +25°C)
Temperature char-
acteristics of FAR
frequency
(TA = –20°C to
+60°C)
Loading ca-
pacitors*2
FAR-C4 C-2000- 20 2.00 510 Ω±0.5% ±0.5% Built-in
FAR-C4 A-4000- 01 4.00 — ±0.5% ±0.5% Built-in
FAR-C4 B-4000- 02 4.00 — ±0.5% ±0.5% Built-in
FAR-C4 B-4000- 00 4.00 — ±0.5% ±0.5% Built-in
FAR-C4 B-8000- 02 8.00 — ±0.5% ±0.5% Built-in
FAR-C4 B-12000- 02 12.00 — ±0.5% ±0.5% Built-in
FAR-C4 B-16000- 02 16.00 — ±0.5% ±0.5% Built-in
FAR-C4 B-20000-L14B 20.00 — ±0.5% ±0.5% Built-in
FAR-C4 B-24000-L14A 24.00 — ±0.5% ±0.5% Built-in
*1: FUJITSU MEDIA DEVICES Acoustic Resonator
C1*2C2*2
FAR*1
X0
R
X1
MB90670/675 Series
84
(Continued)
• Sample application of ceramic resonator
•Mask ROM product
Resonator
manufacturer Resonator Frequency
(MHz) C1 (pF) C2 (pF) R
Kyocera
Corporation
KBR-2.0MS 2.00 150 150 Not required
PBRC-2.00A 2.00 150 150 Not required
KBR-4.0MSA 4.00 33 33 680 Ω
KBR-4.0MKS 4.00 Built-in Built-in 680 Ω
PBRC4.00A 4.00 33 33 680 Ω
PBRC4.00B 4.00 Built-in Built-in 680 Ω
KBR-6.0MSA 6.00 33 33 Not required
KBR-6.0MKS 6.00 Built-in Built-in Not required
PBRC6.00A 6.00 33 33 Not required
PBRC6.00B 6.00 Built-in Built-in Not required
KBR-8.0M 8.00 33 33 560 Ω
PBRC8.00A 8.00 33 33 Not required
PBRC8.00B 8.00 Built-in Built-in Not required
KBR-10.0M 10.00 33 33 330 Ω
PBRC10.00B 10.00 Built-in Built-in 680 Ω
KBR-12.0M 12.00 33 33 330 Ω
PBRC-12.00B 12.00 Built-in Built-in 680 Ω
Murata
Mfg. Co., Ltd.
CSA2.00MG040 2.00 100 100 Not required
CST2.00MG040 2.00 Built-in Built-in Not required
CSA4.00MG040 4.00 100 100 Not required
CST4.00MGW040 4.00 Built-in Built-in Not required
CSA6.00MG 6.00 30 30 Not required
CST6.00MGW 6.00 Built-in Built-in Not required
CSA8.00MTZ 8.00 30 30 Not required
CST8.00MTW 8.00 Built-in Built-in Not required
C1C2
X0
R
X1
*
MB90670/675 Series
85
(Continued)
•One-time product
Inquiry:Kyocera Corporation
•AVX Corporation
North American Sales Headquarters: TEL 1-803-448-9411
•AVX Limited
European Sales Headquarters: TEL 44-1252-770000
•AVX/Kyocera H.K. Ltd.
Asian Sales Headquarters: TEL 852-363-3303
Murata Mfg. Co., Ltd.
•Murata Electronics North America, Inc.: TEL 1-404-436-1300
•Murata Europe Management GmbH: TEL 49-911-66870
•Murata Electronics Singapore (Pte.) Ltd.: TEL 65-758-4233
TDK Corporation
•TDK Corporation of America
Chicago Regional Office: TEL 1-708-803-6100
•TDK Electronics Europe GmbH
Components Division: TEL 49-2102-9450
•TDK Singapore (PTE) Ltd.: TEL 65-273-5022
•TDK Hongkong Co., Ltd.: TEL 852-736-2238
•Korea Branch, TDK Corporation: TEL 82-2-554-6633
Resonator
manufacturer Resonator Frequency
(MHz) C1 (pF) C2 (pF) R
Murata
Mfg. Co., Ltd.
CSA10.0MTZ 10.00 30 30 Not required
CST10.0MTW 10.00 Built-in Built-in Not required
CSA12.0MTZ 12.00 30 30 Not required
CST12.0MTW 12.00 Built-in Built-in Not required
CSA16.00MXZ040 16.00 15 15 Not required
CST16.00MXW0C3 16.00 Built-in Built-in Not required
CSA20.00MXZ040 20.00 10 10 Not required
CSA24.00MXZ040 24.00 5 5 Not required
CST24.00MXW0H1 24.00 Built-in Built-in Not required
CSA32.00MXZ040 32.00 5 5 Not required
CST32.00MXW040 32.00 Built-in Built-in Not required
TDK Corporation FCR4.0MC5 4.00 Built-in Built-in Not required
Resonator
manufacturer Resonator Frequency
(MHz) C1 (pF) C2 (pF) R
Murata
Mfg. Co., Ltd.
CSTCS4.00MG0C5 4.0 Built-in Built-in Not required
CST8.00MTW 8.00 Built-in Built-in Not required
CSACS8.00MT 8.00 30 30 Not required
CSA10.0MTZ 10.00 30 30 Not required
CST10.0MTW 10.00 Built-in Built-in Not required
TDK Corporation FCR4.0MC5 4.00 Built-in Built-in Not required
MB90670/675 Series
86
(5) Clock Output Timing (AVCC = VCC = 2.7 V to 5.5V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
*: For tCP (internal operating clock cycle time), refer to “(3) Clock Timing”.
Parameter Symbol Pin name Condition Value Unit Remarks
Min. Max.
Cycle time tCYC CLK — 1 tCP*—ns
CLK ↑ → CLK ↓tCHCL CLK VCC = 5.0 V ± 10 % 1 tCP*/2 – 20 1 tCP*/2 + 20 ns 5.0 V ± 10 % is ± 20
tCHCL CLK VCC = 3.0 V ± 10 % 1 tCP*/2 – 35 1 tCP*/2 + 35 ns 3.0 V ± 10 % is ± 35
2.4 V 0.8 V
tCYC
tCHCL
2.4 V
CLK
MB90670/675 Series
87
(6) Bus Read Timing (AVCC = VCC = 2.7 V to 5.5 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
* : For tCP (internal operating clock cycle time), refer to “(3) Clock Timing”.
Parameter Symbol Pin name Condition Value Unit Remarks
Min. Max.
ALE pulse width tLHLL ALE VCC = 5.0 V ±10% 1 tCP*/2 – 20 — ns
tLHLL ALE VCC = 3.0 V ±10% 1 tCP*/2 – 35 — ns
Effective address →
ALE ↓ time tAVLL AD15 to AD00 VCC = 5.0 V ±10% 1 tCP*/2 – 25 — ns
tAVLL AD15 to AD00 VCC = 3.0 V ±10% 1 tCP*/2 – 40 — ns
ALE ↓ → address effec-
tive time tLLAX AD15 to AD00 —1 tCP*/2 – 15 — ns
Effective address → RD
↓ time tAVRL AD15 to AD00 1 tCP* – 15 — ns
Effective address →
read data time tAVDV AD15 to AD00 VCC = 5.0 V ±10% — 5 tCP*/2 – 60 ns
tAVDV AD15 to AD00 VCC = 3.0 V ±10% — 5 tCP*/2 – 80 ns
RD pulse width tRLRH RD —3 tCP*/2 – 20 — ns
RD ↓ → read data time tRLDV AD15 to AD00 VCC = 5.0 V ±10% — 3 tCP*/2 – 60 ns
tRLDV AD15 to AD00 VCC = 3.0 V ±10% — 3 tCP*/2 – 80 ns
RD ↑ → data hold time tRHDX AD15 to AD00
—
0—ns
RD ↑ → ALE ↑ time tRHLH RD, ALE 1 tCP*/2 – 15 — ns
RD ↑ → address disap-
pear time tRHAX RD,
A19 to A16 1 tCP*/2 – 10 — ns
Effective address →
CLK ↑ time tAVCH CLK,
A19 to A16 1 tCP*/2 – 20 — ns
RD ↓ → CLK ↑ time tRLCH RD, CLK 1 tCP*/2 – 20 — ns
MB90670/675 Series
88
CLK 2.4 V
tAVCH
ALE
RD
AD19 to AD16
0.7 VCC
0.3 VCC
AD15 to AD00 Address Read data
2.4 V
2.4 V 2.4 V
0.8 V 2.4 V
0.8 V 2.4 V
2.4 V
0.8 V 2.4 V
0.8 V
2.4 V
0.8 V
2.4 V
0.8 V 0.7 VCC
0.3 VCC
tRLCH
tRHLH
tLHLL
tAVLL tLLAX tRLRH
tAVRL tRLDV tRHAX
tAVDV tRHDX
MB90670/675 Series
89
(7) Bus Write Timing (AVCC = VCC = 2.7 V to 5.5 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
*: For tCP (internal operating clock cycle time), refer to “(3) Clock Timing”.
Parameter Symbol Pin name Condition Value Unit Remarks
Min. Max.
Effective address → WR
↓ time tAVWL A19 to A00 —1 tCP – 15 — ns
WR pulse width tWLWH WR 3 tCP*/2 – 20 — ns
Write data → WR ↑ time tDVWH AD15 to AD00 3 tCP*/2 – 20 — ns
WR ↑ → data hold time tWHDX AD15 to AD00 VCC = 5.0 V ±10% 20 — ns
tWHDX AD15 to AD00 VCC = 3.0 V ±10% 30 — ns
WR ↑ → address disap-
pear time tWHAX A19 to A00 —1 tCP*/2 – 10 — ns
WR ↑ → ALE ↑ time tWHLH WRL, ALE 1 tCP*/2 – 15 — ns
WR ↓ → CLK ↑ time tWLCH WRH, CLK 1 tCP*/2 – 20 — ns
CLK
2.4 V
tWLCH
ALE
WRL, WRH
A19 to A16
2.4 V
0.8 V
AD15 to AD00 Address Write data
tWHLH
tAVWL tWLWH
tDVWH tWHDX
tWHAX
2.4 V
2.4 V
0.8 V 2.4 V
0.8 V
2.4 V
0.8 V
2.4 V
0.8 V
2.4 V
0.8 V
MB90670/675 Series
90
(8) Ready Input Timing (AVCC = VCC = 2.7 V to 5.5 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Note : Use the auto-ready function when the setup time for the rising of the RDY signal is not sufficient.
(9) Hold Timing (AVCC = VCC = 2.7 V to 5.5 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
* : For tCP (internal operating clock cycle time), refer to “(3) Clock Timing”.
Note : More than 1 machine cycle is needed before HAK changes after HRQ pin is fetched.
Parameter Symbol Pin name Condition Value Unit Remarks
Min. Max.
RDY setup time tRYHS RDY VCC = 5.0 V ±10% 45 — ns
tRYHS RDY VCC = 3.0 V ±10% 70 — ns
RDY hold time tRYHH RDY — 0 — ns
Parameter Symbol Pin name Condition Value Unit Remarks
Min. Max.
Pins in floating status →
HAK ↓ time tXHAL HAK —30 1 tCP*ns
HAK ↑ → pin valid time tHAHV HAK 1 tCP*2 tCP*ns
CLK 2.4 V
0.8 VCC
tRYHS
ALE
RD/WR
RDY
(WAIT inserted)
RDY
(WAIT inserted)
2.4 V
tRYHS
0.2 VCC 0.2 VCC
0.8 VCC
tRYHH
Pins
HAK
High impedance
tXHAL
2.4 V
0.8 V
2.4 V
0.8 V
tHAHV
0.8 V 2.4 V
MB90670/675 Series
91
(10) UART0 Timing (AVCC = VCC = 2.7 V to 5.5 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
* : For tCP (internal operating clock cycle time), refer to “(3) Clock Timing”.
Notes : • These are AC ratings in the CLK synchronous mode.
• CL is the load capacitor connected to pins while testing.
Parameter Symbol Pin name Condition Value Unit Remarks
Min. Max.
Serial clock cycle time tSCYC ——8 tCP*—ns
Internal shift
clock mode
CL = 80 pF
+ 1 TTL for an
output pin
SCK ↓ → SOT delay
time tSLOV —VCC = 5.0 V ±10% – 80 80 ns
tSLOV —VCC = 3.0 V ±10% – 120 120 ns
Valid SIN → SCK ↑ tIVSH —VCC = 5.0 V ±10% 100 — ns
tIVSH —VCC = 3.0 V ±10% 200 — ns
SCK ↑ → valid SIN hold
time tSHIX —
—
1 tCP*—ns
Serial clock “H” pulse
width tSHSL —4 tCP*—ns
External shift
clock mode
CL = 80 pF
+ 1 TTL for an
output pin
Serial clock “L” pulse
width tSLSH —4 tCP*—ns
SCK ↓ → SOT delay
time tSLOV —VCC = 5.0 V ±10% — 150 ns
tSLOV —VCC = 3.0 V ±10% — 200 ns
Valid SIN → SCK ↑ tIVSH —VCC = 5.0 V ±10% 60 — ns
tIVSH —VCC = 3.0 V ±10% 120 — ns
SCK ↑ → valid SIN hold
time tSHIX —VCC = 5.0 V ±10% 60 — ns
tSHIX —VCC = 3.0 V ±10% 120 — ns
MB90670/675 Series
92
•
Internal shift clock mode
• External shift clock mode
SCK 2.4 V
0.8 V
SOT
SIN
SCK
SOT
SIN
0.8 V
2.4 V
0.8 V
2.4 VCC
0.8 VCC
2.4 VCC
0.8 VCC
0.8 VCC
0.2 VCC
2.4 V
0.2 V
0.8 VCC
0.2 VCC
0.2 VCC
0.8 VCC
0.2 VCC
0.8 VCC
tSCYC
tIVSH tSHIX
tSLOV
tSLSH tSHSL
tIVSH tSHIX
tIVSH
MB90670/675 Series
93
(11) UART1 Timing (AVCC = VCC = 2.7 V to 5.5 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
* : For tCP (internal operating clock cycle time), refer to “(3) Clock Timing”.
Notes : • These are AC ratings in the CLK synchronous mode.
• CL is the load capacitor connected to pins while testing.
Parameter Symbol Pin name Condition Value Unit Remarks
Min. Max.
Serial clock cycle time tSCYC ——8 tCP*—ns
Internal shift
clock mode
CL = 80 pF
+ 1 TTL for an
output pin
SCK ↓ → SOT delay
time tSLOV —VCC = 5.0 V ±10% – 80 80 ns
tSLOV —VCC = 3.0 V ±10% – 120 120 ns
Valid SIN → SCK ↑ tIVSH —VCC = 5.0 V ±10% 100 — ns
tIVSH —VCC = 3.0 V ±10% 200 — ns
SCK ↑ → valid SIN hold
time tSHIX —
—
1 tCP*—ns
Serial clock “H” pulse
width tSHSL —4 tCP*—ns
External shift
clock mode
CL = 80 pF
+ 1 TTL for an
output pin
Serial clock “L” pulse
width tSLSH —4 tCP*—ns
SCK ↓ → SOT delay
time tSLOV —VCC = 5.0 V ±10% — 150 ns
tSLOV —VCC = 3.0 V ±10% — 200 ns
Valid SIN → SCK ↑ tIVSH —VCC = 5.0 V ±10% 60 — ns
tIVSH —VCC = 3.0 V ±10% 120 — ns
SCK ↑ → valid SIN hold
time tSHIX —VCC = 5.0 V ±10% 60 — ns
tSHIX —VCC = 3.0 V ±10% 120 — ns
MB90670/675 Series
94
•
Internal shift clock mode
• External shift clock mode
SCK 2.4 V
0.8 V
SOT
SIN
SCK
SOT
SIN
0.8 V
2.4 V
0.2 V
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
2.4 V
0.8 V
0.8 VCC
0.2 VCC
0.2 VCC
0.8 VCC
0.2 VCC
0.8 VCC
tSCYC
tIVSH tSHIX
tSLOV
tSLSH tSHSL
tIVSH tSHIX
tSLOV
MB90670/675 Series
95
(12) Timer Input Timing (AVCC = VCC = 2.7 V to 5.5 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
* : For tCP (internal operating clock cycle time), refer to “(3) Clock Timing”.
(13) Timer Output Timing (AVCC = VCC = 2.7 V to 5.5 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Parameter Symbol Pin name Condition Value Unit Remarks
Min. Max.
Input pulse width tTIWH,
tTIWL TIN0, TON1 — 4 tCP*—ns
Parameter Symbol Pin name Condition Value Unit Remarks
Min. Max.
CLK ↑ → TOUT
transition time tTO TOT0, TOT1 VCC = 5.0 V ±10% 30 — ns
tTO TOT0, TOT1 VCC = 3.0 V ±10% 80 — ns
tTIWH
0.8 VCC
0.2 VCC
tTIWL
0.8 VCC
0.2 VCC
TIN
CLK
tTO
2.4 V
TOUT 2.4 V
0.8 V
MB90670/675 Series
96
(14) I2C Timing (AVCC = VCC = 5.0 V ±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Note : Only MB90675 series has I2C.
Parameter Symbol Pin name Condition Value Unit Remarks
Min. Max.
SCL clock frequency fSCL —
—
0 100 kHz
Bus free time between
stop and start conditions tBUS —4.7—µs
Hold time
(re-transmission) start tHDSTA —4.0—µs
The first clock
pulse is gener-
ated after this
period.
LOW status hold time of
SCL clock tLOW —4.7—µs
HIGH status hold time of
SCL clock tHIGH —4.0—µs
Setup time for conditions
for starting re-transmis-
sion tSUSTA —4.7—µs
Data hold time tHDDAT —0—µs
Data setup time tSUDAT —250—ns
Rising time of SDA and
SCL signals tR— — 1000 ns
Falling time of SDA and
SCL signals tF— — 300 ns
Setup time for stop con-
ditions tSUSTO —4.0—µs
tBUS
SDA
SCL
tLOW
tRtF
tHDSTA tHDDAT tHIGH
tSUDAT
fSCL
tHDSTA
tSUSTA tSUSTO
0.8 VCC
0.2 VCC
0.2 VCC
0.8 VCC
MB90670/675 Series
97
5. A/D Converter Electrical Characteristics
(AVCC = VCC = 2.7 V to 5.5 V, AVSS = VSS = 0.0 V, 2.7 V AVRH – AVRL, TA = –40°C to +85°C)
Parameter Symbol Pin name Condition Value Unit
Min. Typ. Max.
Resolution — —
—
— — 10 bit
Total error — — — — ±3.0 LSB
Linearity error — — — — ±2.0 LSB
Differential linearity error — — — — ±1.5 LSB
Zero transition voltage VOT AN0 to
AN7
AVRL
– 1.5
LSB
AVRL
+ 0.5
LSB
AVRL
+ 2.5
LSB mV
Full-scale transition voltage VFST AN0 to
AN7
AVRH
– 4.5
LSB
AVRH
– 1.5
LSB
AVRH
+ 0.5
LSB mV
Conversion time
——
VCC = 5.0 V ±10%
at machine clock of
16 MHz 6.125 — — µs
——
VCC = 3.0 V ±10%
at machine clock of
8 MHz 12.25 — — µs
Analog port input current IAIN AN0 to
AN7
—
—0.110µA
Analog input voltage VAIN AN0 to
AN7 AVRL — AVRH V
Reference voltage — AVRH AVRL
– 2.7 —AV
CC V
— AVRL 0 — AVRH
– 2.7 V
Power supply current
IAAVCC —3—mA
IAH AVCC
Supply current
when CPU stopped
and A/D converter
not in operation
(VCC = AVCC =
AVRH = 5.0 V)
—— 5µA
Reference voltage supply cur-
rent
IRAVRH — — 200 — µA
IRH AVRH
Supply current
when CPU stopped
and A/D converter
not in operation
(VCC = AVCC =
AVRH = 5.0 V)
—— 5µA
Offset between channels — AN0 to
AN7 ———4LSB
≤
MB90670/675 Series
98
6. A/D Converter Glossary
Resolution: Analog changes that are identifiable with the A/D converter
Linearity error:The deviation of the straight line connecting the zero transition point (“00 0000 0000” ↔ “00 0000
0001”) with the full-scale transition point (“11 1111 1110” ↔ “11 1111 1111”) from actual con-
version characteristics
Differential linearity error:The deviation of input voltage needed to change the output code by 1 LSB from the
theoretical value
Total error:The total error is defined as a difference between the actual value and the theoretical value, which
includes zero-transition error/full-scale transition error and linearity error.
(Continued)
Total error
3FF
3FE
3FD
004
003
002
001
Analog input
AVRL AVRH
Actual conversion
characteristics
Digital output
VNT
(Measured value)
0.5 LSB’
Actual conversion
characteristics
Theoretical
characteristics
0.5 LSB’
{1 LSB × (N – 1) + 0.5 LSB}
[V]
AVRH – AVRL
1024
1 LSB’ = (Theoretical value)
VOT’ (Theoretical value) = AVRL + 0.5 LSB’ [V]
VFST’ (Theoretical value) = AVRH – 1.5 LSB’ [V]
Total error for digital output N [LSB]
VNT – {1 LSB’ × (N – 1) + 0.5 LSB’}
1 LSB’
=
VNT: Voltage at a transition of digital output from (N – 1) to N
MB90670/675 Series
99
(Continued)
7. Notes on Using A/D Converter
Select the output impedance value for the external circuit of analog input according to the fo llowing conditions.
Output impedance values of the external circuit of 7 kΩ or lower are recommended.
When capacitors are connected to external pins, the capacitance of several thousand times the internal capacitor
value is recommended to minimized the effect of voltage distribution between the e xternal capacitor and internal
capacitor.
When the output impedance of the e xternal circuit is too high, the sampling time f or analog v oltages ma y not be
sufficient (sampling time = 3.75 µs @machine clock of 16 MHz).
•Error
The smaller the | AVRH – AVRL |, the greater the error would become relatively.
Linearity error
N + 1
3FF
3FE
3FD
004
003
002
001
Analog inputAVRL AVRH Analog inputAVRL AVRH
Actual conversion
characteristics
VOT (Measured value)
VFST
(Measured value)
Actual conversion
characteristics
VNT
{1 LSB × (N – 1)
+ VOT’}
Theoretical
characteristics
Digital output
Digital output
Differential linearity error
Theoretical
characteristics
V(N + 1)T
(Measured value)
Actual conversion
characteristics
VNT (Measured value)
Actual conversion
characteristics
Linearity error of
digital output N
VOT:Voltage at transition of digital output from “000H” to “001H”
VFST:Voltage at transition of digital output from “3FEH” to “3FFH”
[LSB]
VNT – {1 LSB × (N – 1) + VOT}
1 LSB’
=
[V]
AVRH – AVRL
1022
=
1 LSB
– 1 LSB [LSB]
V(N + 1)T – VNT
1 LSB’
=
Differential linearity error
of digital output N
N – 2
N – 1
N
• Block diagram of analog input circuit model
Note : Listed values must be considered as standards.
Comparator
Sample hold circuit
Analog input
RON1: Approx. 1.5 kΩ(VCC = 5.0 V)
RON2: Approx. 0.5 kΩ (VCC = 5.0 V)
RON3: Approx. 0.5 kΩ(VCC = 5.0 V) C0: Approx. 60 pF
RON4: Approx. 0.5 kΩ (VCC = 5.0 V) C1: Approx. 4 pF
RON1 RON2 RON3 RON4
C0
C1
MB90670/675 Series
100
■EXAMPLE CHARACTERISTICS
(3) “H” Level Input Voltage/“L” Level Input Voltage
(1) “H” Level Output Voltage (2) “L” Level Output Voltage
(4) “H” Level Input Voltage/“L” Level Input Voltage
(CMOS Input) (Hysteresis Input)
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
VOH (V) VCC = 2.7 V
VOH vs. IOH
TA = +25°C
IOH (mA)
VCC = 3.0 V
VCC = 3.5 V
VCC = 4.0 V
VCC = 4.5 V
VCC = 5.0 V
–2 –4 –6 –8
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
VOL (V)
VCC = 2.7 V
VOL vs. IOL
IOL (mA)
VCC = 3.0 V
VCC = 3.5 V
VCC = 4.0 V
VCC = 4.5 V
VCC = 5.0 V
24 6 8
VIHS:Threshold when input voltage in hysteresis
characteristics is set to “H” level
TA = +25°C
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VIN vs. VCC
VCC (V)
345
TA = +25°C
26
VIN (V)
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VIN vs. VCC
VCC (V)
345
TA = +25°C
26
VIN (V)
VILS:Threshold when input voltage in hysteresis
characteristics is set to “L” level
VIHS
VILS
MB90670/675 Series
101
(5) Power Supply Current (fCP = Internal Operating Clock Frequency)
(6) Pull-up Resistance
ICC vs. VCC
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
ICC (mA)
VCC (V)
3.0 4.0 5.0 6.0
TA = +25°CfCP = 16 MHz
fCP = 12.5 MHz
fCP = 8 MHz
fCP = 4 MHz
ICCS vs. VCC
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ICCS (mA)
VCC (V)
3.0 4.0 5.0 6.0
TA = +25°CfCP = 16 MHz
fCP = 12.5 MHz
fCP = 8 MHz
fCP = 4 MHz
IA vs. AVCC
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
IA (mA)
AVCC (V)
3.0 4.0 5.0 6.0
TA = +25°C
fCP = 16 MHz
IR vs. AVR
0.30
0.20
0.10
0
IA (mA)
AVR (V)
3.0 4.0 5.0 6.0
TA = +25°C
fCP = 16 MHz
R vs. VCC
TA = +25°C
1000
100
10
VCC (V)
4.5 5.0 5.5 6.0
R (kΩ)
2.5 3.0 3.5 4.0
MB90670/675 Series
102
■MASK OPTIONS
•MB90670 series
•MB90675 series
Notes : • The pull-up register configured as a port pin is switched-off in the stop mode and during the
hardware standby.
• In turning on power, option settings can not be made until cloc ks are supplied because 8 machine cycles
are needed for option settings for the MB90P670/P675.
No. Part number
MB90671
MB90672
MB90673
MB90P673 MB90V670
Specifying procedure Specif y when ordering
masking Set with EPROM pro-
grammer Setting not possible
1
Pull-up resistors
P00 to P07, P10 to P17,
P20 to P27, P30 to P37,
P40 to P47, P60 to P67,
P70 to P77, P80,
RST, MD1, MD0
Specify by pin Specify by pin Without pull-up resistor
2Pull-down resistors
MD1, MD0 Specify by pin Specify by pin Without pull-up resistor
No. Part number
MB90676
MB90677
MB90678
MB90P678 MB90V670
Specifying procedure Specif y when ordering
masking Set with EPROM pro-
grammer Setting not possible
1
Pull-up resistors
P00 to P07, P10 to P17,
P20 to P27, P30 to P37,
P40 to P47, P60 to P67,
P70 to P77, P80 to P86,
P90, P91, PA0 to PA7,
PB0 to PB2,
RST, MD1, MD0
Specify by pin Specify by pin Without pull-up resistor
2Pull-down resistors
MD1, MD0 Specify by pin Specify by pin Without pull-up resistor
MB90670/675 Series
103
■ORDERING INFORMATION
Part number Package Remarks
MB90671PFV
MB90672PFV
MB90673PFV
MB90T673PFV
MB90P673PFV
80-pin Plastic LQFP
(FPT-80P-M05)
MB90671PF
MB90672PF
MB90673PF
MB90T673PF
MB90P673PF
80-pin Plastic QFP
(FPT-80P-M06)
MB90676PFV
MB90677PFV
MB90678PFV
MB90T678PFV
MB90P678PFV
100-pin Plastic LQFP
(FPT-100P-M05)
MB90676PF
MB90677PF
MB90678PF
MB90T678PF
MB90P678PF
100-pin Plastic QFP
(FPT-100P-M06)
MB90670/675 Series
104
■PACKAGE DIMENSIONS
(Continued)
C
2000 FUJITSU LIMITED F80008S-c-3-7
120
40
21
60 41
80
61
INDEX
12.00±0.10(.472±.004)SQ
14.00±0.20(.551±.008)SQ
0.50(.020) 0.20±0.05
(.008±.002)
M
0.08(.003)
0.145±0.055
(.006±.002)
0.08(.003)
"A"
0°~8°
.059
–.004
+.008
–0.10
+0.20
1.50
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.10±0.10
(.004±.004)
(Stand off)
0.25(.010)
Details of "A" part
LEAD No.
(Mounting height)
(Mounting height)
(FPT-80P-M05) Note: pins width and pins thickness include plating thickness.
80-pin Plastic LQFP
C
2001 FUJITSU LIMITED F80010S-c-4-4
1 24
25
40
4164
65
80
20.00±0.20(.787±.008)
23.90±0.40(.941±.016)
14.00±0.20
(.551±.008)
17.90±0.40
(.705±.016)
INDEX
0.80(.031) 0.37±0.05
(.015±.002) M
0.20(.008)
"A"
0.17±0.06
(.007±.002)
0.10(.004)
0.80±0.20
(.031±.008)
0.88±0.15
(.035±.006)
0~8°
.120 –.008
+.012
–0.20
+0.30
3.05 0.25(.010)
0.30 +0.10
–0.25
+.004
–.010
.012
(Stand off)
Details of "A" part
(Mounting height)
(FPT-80P-M06)
80-pin
Plastic QFP
Note: pins width and pins thickness include plating thickness.
Dimensions in mm (inches)
Dimensions in mm (inches)
MB90670/675 Series
105
(Continued)
C
2001 FUJITSU LIMITED F100008S-c-4-4
1 30
31
50
5180
81
100
20.00±0.20(.787±.008)
23.90±0.40(.941±.016)
14.00±0.20
(.551±.008)
17.90±0.40
(.705±.016)
INDEX
0.65(.026) 0.32±0.05
(.013±.002) M
0.13(.005)
"A"
0.17±0.06
(.007±.002)
0.10(.004)
Details of "A" part
0~8°
(.035±.006)
0.88±0.15
(.031±.008)
0.80±0.20
0.25(.010)
3.00 +0.35
–0.20
+.014
–.008
.118
(Mounting height)
0.25±0.20
(.010±.008)
(Stand off)
Dimensions in mm (inches)
Note: pins width and pins thickness include plating thickness.
(FPT-100P-M06)
100-pin Plastic QFP
C
2000 FUJITSU LIMITED F100007S-3c-5
14.00±0.10(.551±.004)SQ
16.00±0.20(.630±.008)SQ
125
26
51
76 50
75
100
0.50(.020) 0.20±0.05
(.008±.002) M
0.08(.003) 0.145±0.055
(.0057±.0022)
0.08(.003)
"A"
INDEX .059 –.004
+.008
–0.10
+0.20
1.50
(Mounting height)
0°~8°
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.25(.010)
0.10±0.10
(.004±.004)
Details of "A" part
(Stand off)
(FPT-100P-M05)
Dimensions in mm (inches)
Note: pins width and pins thickness include plating thickness.
100-pin Plastic LQFP
MB90670/675 Series
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Marketing Division
Electronic Devices
Shinjuku Dai-Ichi Seimei Bldg. 7-1,
Nishishinjuku 2-chome, Shinjuku-k u,
Tokyo 163-0721, Japan
Tel: +81-3-5322-3353
Fax: +81-3-5322-3386
http://edevice.fujitsu.com/
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FUJITSU MICROELECTR ONICS ASIA PTE. LTD .
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F0111
FUJITSU LIMITED Printed in Japan
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
