37LV36-I/P - Microchip Technology

 2004 Microchip Technology Inc. DS21109F-page 1

37LV36/65/128

FEATURES

• Operati onally equi valen t to Xil inx XC 1700 f amily

• Wide voltage range 3.0 V to 6.0 V

• Maximum read current 10 mA at 5.0 V

• Standby cu rrent 100 µA typical

• Industry standard Synchronous Serial Interface/

1 bit per rising edge of clock

• Full Static Operation

• Seque nti al Read/ Program

• Cascadable Output Enable

• 10 MHz Maximum Cl ock Rate @ 5.0 Vdc

• Programmable Polarity on Hardware Reset

• Programming with industry standard EPROM pro-

grammers

• Electrostatic discharge protection > 4,000 volts

• 8-pin PDIP/SOIC and 20-pin PLCC packages

• Data Retention > 200 years

• Temperature ranges:

- Commercial: 0°C to +70°C

- Industrial: -40°C to +85°C

DESCRIPTION

The Microchip Technology Inc. 37LV36/65/128 is a

family of Serial OTP EPROM devices organized inter-

nally in a x32 configuratio n. Th e fam il y al so feat ures a

cascadable option for increased memory storage

where needed. The 37LV36/65/128 is suitable for

many applications in which look-up table information

storage i s desirab le and prov ides full static operation i n

the 3.0V to 6.0V VCC range. The devices also support

the industry standard serial interface to the popular

RAM-ba sed Fiel d Programmab le Gate Array s (FPGA).

Advance d CM OS te chnol ogy m akes thi s an ideal boot-

strap solution for today's high speed SRAM-based

FPGAs. The 37LV36/65/128 family is available in the

standard 8-pin plastic DIP, 8-pin SOIC and 20-pin

PLCC pac k age s.

Device Bits Programming Word

37LV36 36,288 1134 x 32

37LV65 65,536 2048 x 32

37LV128 131,072 4096 x 32

PACKAGE TYPES

BLOCK DIAGRAM

CLK

ESET/OE

CE CEO

VPP

Vss

DATA

VCC

VPP

CEO

VSS

DATA

CLK

ESET/OE

DATA

CLK

ESET/OE

VCC

VPP

CEO

VSS

PDIP

37LV36

37LV65

37LV128

SOIC

PLCC

37LV36

37LV65

37LV128

37LV36

37LV65

37LV128

36K, 64K, and 128K Serial EPROM Family

Xilinx is a registered trademark of Xilinx Corporation.

Obsolete Device

37LV36/65/128

DS21109F-page 2  2004 Microchip Technology Inc.

1.0 ELECTRICAL CHARACTERISTICS

1.1 Maximum Ratings*

VCC and input voltages w.r.t. VSS..........-0.6V to +0.6V

VPP voltage w.r.t. VSS during

programming......................................-0.6V to +14.0V

Output voltage w.r.t. VSS .......... ..... .-0.6V to VCC +0.6V

Storage temperature ..........................-65°C to +150°C

Ambient temp. with power applied.....-65°C to +125°C

Soldering temperature of leads (10 sec.).........+300°C

ESD protection on all pins ..................................... ≥ 4 kV

*Notice: Stresses above those listed under “Maximum Ratings”

may cause per mane nt damage t o the devic e. This is a stre ss rat-

ing only and functional operation of the device at those or any

other conditions above those indicated in the operation listings of

this spe cification is not implied . Exposure to maximum rating con-

ditio ns for extended pe riods may affect device reliability.

TABLE 1-1: PIN FUNCTION TABLE

Name Function 8 20

DATA Data I/O 1 2

CLK Clock Input 2 4

RESET/OE Reset Input and Output

Enable 36

CE Chip Enable Input 4 8

VSS Ground 5 10

CEO Chip Enable Output 6 14

VPP Programmi ng Voltage Supply 7 17

VCC +3.0V to 6.0V Power Supply 8 20

Not Labeled Not utilized, not connected

TABLE 1-2: READ OPERATION DC CHARACTERISTICS

VCC = +3.0 to 6.0V

Commercial (C): Tamb = 0°C to +70°C

Industrial (I): Tamb = -40°C to +85°C

Parameter Symbol Min. Max. Units Conditions

DATA, CE, CEO and Res et p ins :

High level input voltage

Low level input voltage

High lev el outp ut vol t ag e

Low level output voltage

VIH

VIL

VOH1

VOH2

VOL

2.0

-0.3

3.86

2.4

—

VCC

0.8

.32

IOH = -4 mA VCC ≥ 4.5 V

IOH = -4 mA VCC ≥ 3.0 V

IOL = 4.0 mA

Input Leakage ILI -10 10 µAVIN = .1V to VCC

Output Lea ka ge ILO -10 10 µAVOUT = .1V to VCC

Input Capacitance

(all inputs/outpu ts) CINT — 10 pF Tamb = 25°C; FCLK = 1 MHz (Note 1)

Operati ng Curren t ICC Read —

—10

2mA

mA VCC = 6.0V, CLK = 10 MHz

VCC = 3.6V, CLK = 2.5 MHz

Outputs open

Standby Current ICCS —100

50 µA

µAVCC = 6.0V, CE = 5.8V

VCC = 3.6V, CE = 3.4V

Note 1: This parameter is initially characterized and not 100% tested.

 2004 Microchip Technology Inc. DS21109F-page 3

37LV36/65/128

2.0 DATA

2.1 Data I/O

Three-state DATA output for reading and input during

programming.

3.0 CLK

3.1 Clock Input

Used to increment the internal address and bit counters

for reading and programming.

4.0 RESET/OE

4.1 Reset Input and Output Enable

A LOW level on both the CE and RESET/OE inputs

enables the data output driver. A HIGH level on

RESET/OE resets both the address and bit counters.

In the 37LVXXX, the logic polarity of this input is pro-

grammable as either RESET/OE or OE/RESET. This

document describes the pin as RESET/OE although

the opposite polarity is also possible. This option is

defined and set at device program time.

5.0 CE

5.1 Chip Enable Input

CE is used for device selection. A LOW level on both

CE and OE enables the data output driver. A HIGH

level on C E disa ble s both the add res s and bi t c ou nte rs

and forces the device into a low power mode.

6.0 CEO

6.1 Chip Enable Output

This signal is asserted LOW on the clock cycle follow-

ing the last bit read from the memory. It will stay LOW

as long as CE and OE are both LOW. It will then follow

CE until OE goes HIGH. Thereafter, CEO will stay

HIGH until the entire EPROM is read again. This pin

also used to sense the status of RESET polarity when

Programming Mode is entered.

7.0 VPP

7.1 Programming Voltage Supply

Used to enter programming mode (+13 volts) and to

program the memory (+13 volts). Must be connected

directly to Vcc for normal Read operation. No over-

shoot above +14 volts is permitted.

8.0 CASCADING SERIAL EPROMS

Cascading Serial EPROMs provide additional memory

for multiple FPGAs configured as a daisy-chain, or for

future applications requiring larger configuration mem-

ories.

When the last bit from the first Serial EPROM is read,

the next clock signal to the Serial EPROM asserts its

CEO outpu t LOW a nd dis ables it s DATA line. The sec-

ond Serial EPR OM recognizes the LO W level on its CE

input and enables its DATA output.

When configuration is complete, the address counters

of all cascaded Serial EPROMs are reset if RESET

goes LOW forcing the RESET/OE on each Serial

EPROM to go HIGH. If the a ddress co unters are not to

be reset upon completion, then the RESET/OE inputs

can be tied to ground.

Addition al logic ma y be requ ired i f cas caded memo ries

are so large that the rippled chip enable is not fast

enough to activat e succ essive Serial EPROMs.

9.0 STANDBY MODE

The 37LVXXX enters a low-power Standby Mode

whenever CE is HIGH. In Standby Mode, the Serial

EPROM consumes less than 100 µA of current. The

output will remain in a high-i mpedance state rega rdless

of the state of the OE input.

10.0 PROGRAMMING MODE

Programming Mode is entered by holding VPP HIGH

(+13 volts) for two clock edges and then holding VPP =

VDD for one clock edge. Programming mode is exited

by dr iving a LOW on both CE and OE and then remov-

ing power from the device. Figures 4 through 7 show

the programming alg orithm.

11.0 37LVXXX RESET POLARITY

The 37LVXXX lets the us er choose the rese t polarity as

either RESET/OE or OE/RESET. Any third-party com-

mercial programmer should prompt the user for the

desired reset polarity.

The programming of the overflow word should be han-

dled transparently by the EPROM programmer; it is

mentioned here as supplemental information only.

The polarity is programm ed in to the first ov erfl ow wo rd

location, maximum address+1. 00000000 in these

locations makes the reset active LOW, FFFFFFFF in

these locations makes the reset active HIGH. The

default condition is RESET active HIGH.

37LV36/65/128

DS21109F-page 4  2004 Microchip Technology Inc.

FIGURE 11-1: READ CHARACTERISTICS TIMING

TABLE 11-1: READ CHARACTERISTICS

AC Testing Waveform: VIL = 0.2V; VIH = 3.0V

AC Test Load: 50 pF

VOL = V OL_MAX; VOH = VOH_MIN

Symbol Parameter

Limits 3.0V ≤

Vcc ≤ 6.0V Limits 4.5V ≤

Vcc ≤ 6.0V Units Conditions

Min. Max. Min. Max.

TOE OE to Data Delay — 45 — 45 ns

TCE CE to Data Delay — 60 — 50 ns

TCAC CLK to Data Delay — 200 — 60 ns

TOH Data Hold from CE, OE or CLK 0 — 0 — ns

TDF CE or OE to Data Float Delay — 50 — 50 ns Notes 1, 2

TLC CLK Low Time 100 — 25 — ns

THC CLK High Time 100 — 25 — ns

TSCE CE Set up Time to CLK

(to guarantee proper counting) 40 — 25 — ns Note 1

TSCED CE setup time to CLK

(to guarantee proper DATA read) 100 — 80 — ns

THCE CE Hold Time to CLK

(to guarantee proper counting) 0 — 0 — ns Note 1

THCED CE hold time to CLK

(to guarantee proper DATA read) 50 — 0 — ns

THOE OE High Time

(Guarantees counters are Reset) 100 20 — ns

CLK max Clock Frequency — 2.5 — 10 MHz

Note 1: This parameter is periodically sampled and not 100% tested.

2: Float delays are measured with output pulled through 1kΩ to VLOAD = VCC/2.

 2004 Microchip Technology Inc. DS21109F-page 5

37LV36/65/128

FIGURE 11-2: READ CHARACTERISTICS AT END OF ARRAY TIMING

TABLE 11-2: READ CHARACTERISTICS AT END OF ARRAY

AC Testing Waveform: VIL = 0.2V; VIH = 3.0V

AC Test Load: 50 pF

VOL = VOL_MAX; VOH = VOH_MIN

Symbol Parameter

Limit s 3.0V ≤ Vcc ≤

6.0V Limits 4.5V ≤ Vcc ≤

6.0V Units Conditions

Min. Max. Min. Max.

TCDF CLK to Data Float Delay — 50 — 50 ns Notes 1, 2

TOCK CLK to CEO Delay — 65 — 40 ns

TOCE CE to CEO Delay — 45 — 40 ns

TOOE RESET/OE to CEO Delay — 45 — 40 ns

Note 1: This parameter is periodically sampled and not 100% tested.

2: Float delays are measured with output pulled through 1kΩ to VLOAD = VCC/2.

37LV36/65/128

DS21109F-page 6  2004 Microchip Technology Inc.

TABLE 11-3: PIN ASSIGNMENTS IN THE PROGRAMMING MODE

DIP/SOIC

Pin PLCC Pin Name I/O Description

1 2 DATA I/O The rising ed ge of t he clock s hi ft s a d at a word in or ou t of the

EPROM one bit at a time.

2 4 CLK I Clock Input. Used to increment the internal address/word

counter for reading and programming operation.

3 6 RESET/OE I The rising edge of CLK shifts a data word into the EPROM

when CE and OE are HIGH; it shifts a data word out of the

EPROM when CE is LOW and OE is HIGH. The address/

word counter is incremented on the rising edge of CLK while

CE is held HIGH and OE is held LOW.

Note 1: Any modified polarity of the RESET/OE pin is

ignored in the programming mo de.

48CEI The rising edge of CLK shifts a data word into the EPROM

when CE and OE are HIGH; it shifts a data word out of the

EPROM when CE is LOW and OE is HIGH. The address/

word counter is incremented on the rising edge of CLK while

CE is held HIGH and OE is held LOW.

510V

SS Ground pin.

614CEO

O The polarity of the RESET/OE pi n can be read by sens ing the

CEO pin.

Note 1: The polarity of the RESET/OE pin i s ignored w hile in

the Programming Mode. In final verification, this pin

must be monitored to go LOW one clock cycle after

the last data bit has been read.

717VPP Programm ing V oltage Supply . Prog ramming Mode is e ntered

by ho lding CE and OE HIGH and VPP at VPP1 for two rising

clock edges and then lowering VPP to VPP2 for one more ris-

ing cloc k edge. A word is programmed by strobing the devi ce

with VPP for the duratio n TPGM . V PP must be tied to VCC for

normal read operation.

820V

CC +5 V power supply input.

 2004 Microchip Technology Inc. DS21109F-page 7

37LV36/65/128

TABLE 11-4: DC PROGRAMMING SPECIFICATIONS

TABLE 11-5: AC PROGRAMMING SPECIFICATIONS (SEE NOTE 2)

Symbol Parameter Ambient Temperature: Tamb = 25°C ±5°CLimits Units

Min. Max.

VCCP Supply voltage du ring programming 5.0 6.0 V

VIL Low-level input voltage 0.0 0.5 V

VIH High-level input voltage 2.4 VCC V

VOL Low-level output voltage — 0.4 V

VOH High-level output voltage 3.7 — V

VPP1 Programming voltage* 12.5 13.5 V

VPP2 Programming Mode access voltage VCCP VCCP+1 V

IPPP Supply current in Programming Mode — 100 mA

ILInput or output leakage current -10 10 µA

VCCL First pass Low-level supply voltage for final verification 2.8 3.0 V

VCCH Second pass High-level supply voltage for final verification 6.4 6.6 V

* No overshoot is permitted on this signal. VPP must not be allowed to exceed 14 volts.

Symbol Parameter Limits Units Conditions

Min. Max.

TRPP 10% to 90% Rise Time of VPP 1µsNote 1

TFPP 90% to 10% Fall Time of VPP 1µsNote 1

TPGM VPP Programming Pulse Width .50 1.05 ms

TSVC VPP Setup to CLK for Entering Programming Mode 100 ns Note 1

TSVCE CE Setup to CLK for Entering Programming Mode 100 ns Note 1

TSVOE OE Setup to CLK for Entering Programming Mode 100 ns Note 1

THVC VPP Hold from CLK for Entering Programming Mode 300 ns Note 1

TSDP Data Setup to CLK for Programming 50 ns

THDP Data Hold from CLK for Programming 0 ns

TLCE CE Low time to clear data latches 100 ns

TSCC CE Setu p to C LK for Pro gramming/Verifying 100 ns

TSIC OE Setup to CLK for Incrementing Address Counter 100 ns

THIC OE Hold from CLK for Incrementing Address Counter 0 ns

THOV OE Hold from VPP 200 ns Note 1

TPCAC CLK to Data Valid 400 ns

TPOH Data Hold from CLK 0 ns

TPCE CE Low to Da ta Valid 250 ns

Note 1: This parameter is periodically sampled and not 100% tested.

Note 2: While in Pro gramming Mode, CE should o nly be changed while O E is HIG H and has bee n HIGH for 200 ns,

and OE should only be changed while CE is HIGH and has been HIGH for 200 ns.

37LV36/65/128

DS21109F-page 8  2004 Microchip Technology Inc.

FIGURE 11-3: ENTER AND EXIT PROGRAMMING MODES

FIGURE 11-4: PROGRAMMING CYCLE OVERVIEW (NO VERIFY UNTIL ENTIRE ARRAY IS

PROGRAMMED)

FIGURE 11-5: DETAILS OF PROGRAM CYCLE

VCC

VPP

VPP2

VPP1

VCCP

TRPP TFPP

TSVC THVC TSVC

TSVCE

TSVOE

CLK

DATA

RESET/OE

Enter Mode Exit Mode

32 Clocks

*Note: The CEO pin is high impedance when V

= V

High if RESET/OE configured

Low if RESET/OE configured

2 CLKS **Load

Word 1 **Load

Word 2 **Load

Word 3 **Load

Word 4 **Load

Word 5

CE low to clear

data latches Clock Increments

Address Counter

Enter

Programming

Mode

500 µs

Programming

Mode

500 µs

Programming

Mode

500 µs

Programming

Mode

500 µs

Programming

Mode

= V

PP2

= V

CCP

PP1

CLK

RESET/OE

CEO **** *

 2004 Microchip Technology Inc. DS21109F-page 9

37LV36/65/128

FIGURE 11-6: READ MANUFACTURER AND DEVICE ID OVERVIEW

FIGURE 11-7: DETAILS OF READ MANUFACTURER AND DEVICE ID

37LV36/65/128

DS21109F-page 10  2004 Microchip Technology Inc.

FIGURE 11-8: 37LVX XX PROGRAMM ING SPECIFICATIONS

Device Passed

Device Fai lu re

1st Pass? Verify

All Data Bits (Read Mode)

VCC = VPP = VCCL and

VCC = VPP = VCCH

Exit Programming Mo de

Device Power Off

Device Power On

Pulse VPP to VPP1

(13V) for Tpgm

(500 µs)

Load 32-bit word to be

programmed

CE low to clear

EPROM internal data

latches

32 bit data word to be

programmed =

FFFFFFFFhex

Last Word?

Increment Address

Counter

Device Power Of f

Device Power On

Check Device ID

Start

Enter Programm ing Mode

1. VCC = VCCP VPP = VPP2 CE = OE = VIH

2. VPP = VPP1 for 2 CLK Rising Edges

3. VPP = VPP2 for 1 CLK Rising Edge

Pass

Fail

Yes

37LV36/65/128

 2004 Microchip Technology Inc. DS21109F-page 11

37LV36/65/128 Product Identificatio n System

To order or to obtain information, e.g., on pricing or delivery, please us e the listed part numbers, and refe r to the factory or the listed

sales offices.

Package: P = Plastic DIP, 8 lead

SN = Plastic SOIC (150 mil Body), 8 lead

L = Plastic Leaded Chip Carrier (PLCC), 20 lead

Temperature Blank = 0°C to +70°C

Range: I=-40°C to +85°C

Shipping: Blank = Tube

T = Tape and Reel

Device: 37LV128 128K Serial EPROM

37LV65 64K Serial EPROM

37LV36 36K Serial EPROM

37LV36/65 /12 8 – I T /P

37LV36/65/128

DS21109F-page 12  2004 Microchip Technology Inc.

NOTES:

 2004 Microchip Technology Inc. DS21109F-page 13

Information contained in this publication regarding device

applications and the like is intended through sug gestion only

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

No representation or warranty is given and no liability is

assumed by Microc hip Technology Incorporat ed with respect

to the accuracy or use of such inf orm ation, or inf ringement of

patents or other intellectual property rights arising from such

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components in life support systems is not authorized except

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conveyed, implicitly or otherwise, under any intellectual

property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICST ART,

PRO MATE, PowerSmart, rfPIC, and SmartShunt are

registered trademarks of Microchip Technology Incorporated

in the U.S.A. and other countries.

AmpLab, FilterLab, MX DE V, MXLAB, PICMASTER, SEEV AL,

SmartSensor and The Embedded Control Solutions Company

are registered trademarks of Microchip Technology

Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, dsPICDEM,

dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,

FanSense, FlexROM, fuzzyLAB, In-Circuit Serial

Programming, ICSP, ICEPI C, Migra table Memory, MPASM,

MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net,

PICLAB, PICtail, PowerCal, PowerInfo, PowerMate,

PowerTool, rfLAB , rfPICD EM, Select Mode, Smart Serial,

SmartTel and Total Endurance are trademarks of Microchip

Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that it s family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is c onstantly evolving. We a t Microchip are committed to continuously improving t he c ode protect ion f eatures of our

products. Attempts to break Microchip’ s code protection f eature may be a violati on of t he Digit al Millennium Copyright Act. If such act s

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Microchip received ISO/TS-16949:2002 quality system certification for

its worldwide headquarters, design and wafer fabrication facilities in

Chandler and Tempe, Arizona and Mountain View, California in

October 2003. The Company’s quality system processes and

procedures are for its PICmicro® 8-bit MC Us, KEELOQ® code hopping

devices, Serial EEPROMs, micro peripherals, nonvolat ile memory and

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and manufacture of development systems is ISO 9001:2000 certified.

 2004 Microchip Technology Inc.

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13F-3, No. 295, Sec. 2, Kung Fu Road

Hsinchu City 300, Taiwan

Tel: 886-3-572-9526

Fax: 886-3-572-6459

EUROPE

Austria

Durisolstrasse 2

A-4600 Wels

Austria

Tel: 43-7242-2244-399

Fax: 43-7242-2244-393

Denmark

Regus Business Centre

Lautrup hoj 1-3

Ballerup DK-2750 Denmark

Tel: 45-4420-9895 Fax: 45-4420-9910

France

Parc d’Activite du Moulin de Massy

43 Rue du Saule Trapu

Batiment A - l er Etage

91300 Massy, France

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

Germany

Steinheilstrasse 10

D-85737 Ismaning, Germany

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Italy

Via Salvatore Quasimodo, 12

20025 Legnano (MI)

Milan, Italy

Tel: 39-0331-742611

Fax: 39-0331-466781

Netherlands

Waegenburghtplein 4

NL-5152 JR, Drunen, Netherlands

Tel: 31-416-690399

Fax: 31-416-690340

United Kingdom

505 Eskdale Road

Winnersh Triangle

Wokingham

Berk shire, England RG41 5TU

Tel: 44-118-921-5869

Fax: 44-118-921-5820

07/12/04

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