2003 Microchip Technology Inc. Advance Information DS70082C-page 239
dsPIC30F
Multi-Master Communication, Bus Collision
and Bus Arbitration ........................................... 118
Reception.................................................................. 117
Transmission............................................................. 117
I2C Module ........................................................................ 113
Addresses ................................................................. 115
Bus Data Timing Characteristics
Master Mode..................................................... 211
Slave Mode....................................................... 213
Bus Data Timing Requirements
Master Mode..................................................... 212
Slave Mode....................................................... 214
Bus Start/Stop Bits Timing Characteristics
Master Mode..................................................... 211
Slave Mode....................................................... 213
General Call Address Support .................................. 117
Interrupts................................................................... 116
IPMI Support ............................................................. 117
Master Operation ...................................................... 117
Master Support ......................................................... 117
Operating Function Description ................................ 113
Operation During CPU Sleep and Idle Modes .......... 118
Pin Configuration ...................................................... 113
Register Map............................................................. 119
Registers................................................................... 113
Slope Control ............................................................ 117
Software Controlled Clock Stretching (STREN = 1).. 116
Various Modes .......................................................... 113
I2C Module
Programmer’s Model................................................. 113
Idle Current (IIDLE) ............................................................ 180
In-Circuit Serial Programming (ICSP) ............................... 149
Independent PWM Output ................................................ 105
Initialization Condition for RCON Register Case 1 ........... 157
Initialization Condition for RCON Register Case 2 ........... 157
Initialization Condition for RCON Register, Case 1 .......... 157
Input Capture (CAPX) Timing Characteristics .................. 198
Input Capture Interrupts ...................................................... 86
Register Map............................................................... 87
Input Capture Module ......................................................... 85
In CPU Sleep Mode .................................................... 86
Simple Capture Event Mode ....................................... 85
Input Capture Timing Requirements ................................. 198
Input Change Notification Module....................................... 70
Register Map (bit 15-8) ............................................... 70
Register Map (bits 15-8) ............................................. 70
Register Map (bits 7-0) ............................................... 70
Input Characteristics
QEA/QEB.................................................................. 201
Instruction Addressing Modes............................................. 41
File Register Instructions ............................................ 42
Fundamental Modes Supported.................................. 41
MAC Instructions......................................................... 42
MCU Instructions ........................................................ 42
Move and Accumulator Instructions............................ 42
Other Instructions........................................................ 42
Instruction Flow................................................................... 20
Pipeline - 1-Word, 1-Cycle (Figure) ............................ 20
Pipeline - 1-Word, 2-Cycle (Figure) ............................ 20
Pipeline - 1-Word, 2-Cycle MOV.D Operations
(Figure) ............................................................... 21
Pipeline - 1-Word, 2-Cycle Table Operations
(Figure) ............................................................... 21
Pipeline - 1-Word, 2-Cycle with Instruction Stall
(Figure) ............................................................... 22
Pipeline - 2-Word, 2-Cycle DO, DOW (Figure)........... 22
Pipeline - 2-Word, 2-Cycle GOTO, CALL (Figure) ..... 21
Instruction Set................................................................... 161
Instruction Set Overview................................................... 163
Instruction Stalls ................................................................. 43
Introduction................................................................. 43
Raw Dependency Detection ....................................... 43
Inter-Integrated Circuit. See I2C
Internal Clock Timing Examples ....................................... 191
Interrupt Controller
Register Map .............................................................. 54
Interrupt Priority
Traps .......................................................................... 51
Interrupt Sequence ............................................................. 52
Interrupt Stack Frame................................................. 53
L
Load Conditions................................................................ 189
Low-Voltage Detect Characteristics.................................. 186
LVDL Characteristics........................................................ 187
M
Memory Organization ......................................................... 29
Modulo Addressing............................................................. 44
Applicability................................................................. 46
Decrementing Buffer Operation Example................... 46
Incrementing Buffer Operation Example .................... 45
Restrictions................................................................. 46
Start and End Address ............................................... 44
W Address Register Selection.................................... 45
Motor Control PWM Module ............................................... 99
Fault Timing Characteristics ..................................... 200
Timing Characteristics .............................................. 200
Timing Requirements ............................................... 200
MPLAB ASM30 Assembler, Linker, Librarian................... 170
MPLAB ICD 2 In-Circuit Debugger ................................... 171
MPLAB ICE 2000 High Performance Universal
In-Circuit Emulator.................................................... 171
MPLAB ICE 4000 High Performance Universal
In-Circuit Emulator.................................................... 171
MPLAB Integrated Development Environment Software.. 169
MPLINK Object Linker/MPLIB Object Librarian................ 170
O
OC/PWM Module Timing Characteristics ......................... 199
Operating Current (IDD) .................................................... 177
Operating Frequency vs Voltage
dsPIC30Fxxxx-20 (Extended)................................... 176
Oscillator Configurations................................................... 151
Fail-Safe Clock Monitor ............................................ 153
Fast RC (FRC).......................................................... 152
Initial Clock Source Selection ................................... 151
Low Power RC (LPRC)............................................. 152
LP Oscillator Control................................................. 152
Phase Locked Loop (PLL) ........................................ 152
Start-up Timer (OST)................................................ 152
Oscillator Operating Modes Table .................................... 149
Oscillator Selection........................................................... 149
Oscillator Start-up Timer
Timing Characteristics .............................................. 193
Timing Requirements ............................................... 194
Output Compare Interrupts................................................. 91
Output Compare Mode
Register Map .............................................................. 92