PIC16(L)F1615/9 14/20-Pin, 8-Bit Flash Microcontroller Description PIC16(L)F1615/9 microcontrollers deliver on-chip features that are unique to the design for embedded control of small motors and general purpose applications in 14/20-pin count packages. Features like 10-bit A/D, CCP, 24-bit SMT and Zero-Cross Detection offer an excellent solution to the variety of applications. The product family also has a CRC+ memory scan and Windowed WDT to support safety-critical systems in home appliances, white goods and other end equipment. Core Features Digital Peripherals * C Compiler Optimized RISC Architecture * Only 49 Instructions * Operating Speed: - DC - 32 MHz clock input - 125 ns minimum instruction cycle * Interrupt Capability * 16-Level Deep Hardware Stack * One 8-Bit Timer * Three 16-bit Timers * Low Current Power-on Reset (POR) * Configurable Power-up Timer (PWRT) * Brown-out Reset (BOR) with Selectable Trip Point * Windowed Watchdog Timer (WWDT): - Variable prescaler selection - Variable window size selection - All sources configurable in hardware or software * Configurable Logic Cell (CLC): - Four CLCs - Integrated combinational and sequential logic * Complementary Waveform Generator (CWG): - Rising and falling edge dead-band control - Full-bridge, half-bridge, 1-channel drive - Multiple signal sources * Two Capture/Compare/PWM (CCP) modules * PWM: Two 10-bit Pulse-Width Modulators * Two Signal Measurement Timers (SMT): - 24-bit timer/counter with prescaler - Multiple gate and clock inputs * Angular Timer: - Single pulse - Multiple pulses with missing pulse recovery * Three Hardware Limit Timers (HLT): - 8-bit timer with prescaler - 8-bit period register and postscaler - Asynchronous H/W Reset sources * Math Accelerator with Proportional-IntegralDerivative (PID): - Four operation modes - Add and multiply - Simple multiplier - Multiply and Accumulate - Programmable PID controller * Cyclic Redundancy Check with Memory Scan (CRC/SCAN): - Software configurable * Serial Communications: - Enhanced USART (EUSART) - SPI, I2CTM, RS-232, RS-485, LIN compatible - Auto-Baud Detect, Auto-Wake-up on start * Up to 17 I/O Pins and One Input-only Pin: - Individually programmable pull-ups - Slew rate control - Interrupt-on-change with edge-select - Two High Current Drive pins * Peripheral Pin Select (PPS): - Enables pin mapping of digital I/O Memory * * * * 8 KW Flash Program Memory 1024 Bytes Data SRAM Memory Direct, Indirect and Relative Addressing modes High-Endurance Flash Data Memory (HEF): - 128 B (nonvolatile), 100K erase/write cycles Operating Characteristics * Operating Voltage Range: - 1.8V to 3.6V (PIC16LF1615/9) - 2.3V to 5.5V (PIC16F1615/9) * Temperature Range: - Industrial: -40C to 85C - Extended: -40C to 125C eXtreme Low-Power (XLP) Features * * * * Sleep mode: 50 nA @ 1.8V, typical Watchdog Timer: 500 nA @ 1.8V, typical Secondary Oscillator: 500 nA @ 32 kHz Operating Current: - 8 uA @ 32 kHz, 1.8V, typical - 32 uA/MHz @ 1.8V, typical 2014 Microchip Technology Inc. Preliminary DS40001770A-page 1 PIC16(L)F1615/9 Intelligent Analog Peripherals Clocking Structure * 10-Bit Analog-to-Digital Converter (ADC): - Up to 12 external channels - Conversion available during Sleep * Two Comparators (COMP): - Low-Power/High-Speed mode - Up to three external inverting inputs - Fixed Voltage Reference at non-inverting input(s) - Comparator outputs externally accessible * 8-Bit Digital-to-Analog Converter (DAC): - 8-bit resolution, rail-to-rail - Positive Reference Selection * Voltage Reference: - Fixed Voltage Reference (FVR): 1.024V, 2.048V and 4.096V output levels * Zero-Cross Detect (ZCD): - Detect when AC signal on pin crosses ground * 16 MHz Internal Oscillator: - 1% at calibration - Selectable frequency range from 32 MHz to 31 kHz * 31 kHz Low-Power Internal Oscillator * 4x Phase-Locked Loop (PLL): - For up to 32 MHz internal operation * External Oscillator Block with: - Three external clock modes up to 32 MHz - One crystal resonator mode up to 32 MHz * Fail-Safe Clock Monitor: - Allows for safe shutdown if peripheral clock stops * Two-Speed Oscillator Start-up * Oscillator Start-up Timer (OST) Program Memory Flash (W) Data SRAM (bytes) I/O Pins 8-bit/16-bit Timers Comparators 10-bit ADC (ch) Zero-Cross Detect CCP/10-bit PWM CWG CLC SMT/HLT Angular Timer Windowed Watchdog Timer CRC with Memory Scan Math Accelerator with PID High Current I/O Pins PPS EUSART I2CTM/SPI Debug(1) PIC12/16(L)F161X FAMILY TYPES Data Sheet Index TABLE 1: PIC12(L)F1612 (A) 2048 256 6 1/1 1 4 1 2/0 1 0 2/3 0 Y Y 0 0 N 0 0 I/H PIC16(L)F1613 (A) 2048 256 12 1/1 2 8 1 2/0 1 0 2/3 0 Y Y 0 0 N 0 0 I/H PIC16(L)F1614 (B) 4096 512 12 1/3 2 8 1 2/2 1 2 2/3 1 Y Y 1 2 Y 1 1 I/H PIC16(L)F1615 (C) 8192 1024 12 1/3 2 8 1 2/2 1 4 2/3 1 Y Y 1 2 Y 1 1 I/H PIC16(L)F1618 (B) 4096 512 18 1/3 2 12 1 2/2 1 2 2/3 1 Y Y 1 2 Y 1 1 I/H PIC16(L)F1619 (C) 8192 1024 18 1/3 2 12 1 2/2 1 4 2/3 1 Y Y 1 2 Y 1 1 I/H Device Note 1: Debugging Methods: (I) - Integrated on Chip; (H) - via ICD Header; E - using Emulation Product Data Sheet Index: A. DS40001737 PIC12(L)F1612/16(L)F1613 Data Sheet, 8/14-Pin, 8-bit Flash Microcontrollers B. DS40001769 PIC16(L)F1614/8 Data Sheet, 14/20-Pin, 8-bit Flash Microcontrollers C. DS40001770 PIC16(L)F1615/9 Data Sheet, 14/20-Pin, 8-bit Flash Microcontrollers Note: For other small form-factor package availability and marking information, please visit http://www.microchip.com/packaging or contact your local sales office. DS40001770A-page 2 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 TABLE 2: PACKAGES Packages PIC16(L)F1615 PIC16(L)F1619 Note: PDIP SOIC DFN UDFN TSSOP QFN UQFN SSOP Pin details are subject to change. PIN DIAGRAMS 14-PIN PDIP, SOIC, TSSOP VDD 1 14 2 13 VSS RA0/ICSPDAT 3 4 12 RA1/ICSPCLK MCLR/VPP/RA3 11 RA2 RC5 5 10 RC0 RC4 6 9 RC1 8 RC2 RA5 RA4 RC3 7 16-PIN QFN VDD NC NC Vss FIGURE 2: PIC16(L)F1615 FIGURE 1: 16 15 14 13 12 C 1 PI 16 2 11 )F (L 3 10 16 15 RA5 RA4 RA3/MCLR/VPP RC5 4 6 7 8 RC4 RC3 RC2 RC1 5 9 RA0 RA1 RA2 RC0 20-PIN PDIP, SOIC, SSOP VDD 2014 Microchip Technology Inc. 1 20 VSS RA5 2 19 RA0 RA4 3 4 18 RA1 MCLR/VPP/RA3 17 RA2 RC5 5 16 RC0 RC4 6 15 RC1 RC3 7 14 RC2 RC6 8 13 RB4 RC7 9 12 RB5 RB7 10 11 RB6 PIC16(L)F1619 FIGURE 3: Preliminary DS40001770A-page 3 PIC16(L)F1615/9 20-PIN UQFN, QFN RA4 RA5 VDD Vss RA0 FIGURE 4: 16 1 )F 16 (L PI C 1 2 3 4 5 9 20 19 18 17 16 RA3/MCLR/VPP RC5 RC4 RC3 RC6 15 14 13 12 11 RA1 RA2 RC0 RC1 RC2 RC7 RB7 RB6 RB5 RB4 6 7 8 9 10 DS40001770A-page 4 Preliminary 2014 Microchip Technology Inc. Comparator Timers CCP CWG ZCD CLC EUSART SMT Angular Timer MSSP PWM High Current I/O Interrupt Pull-up RA0 13 12 AN0 DAC1OUT1 C1IN+ -- -- -- -- -- -- -- -- -- -- -- IOC Y ICSPDAT RA1 12 11 AN1 VREF+ C1IN0C2IN0- -- -- -- -- -- -- -- -- -- -- -- IOC Y ICSPCLK RA2 11 10 AN2 -- -- T0CKI(1) -- CWG1IN(1) ZCD1IN -- -- -- -- -- -- -- INT IOC Y -- RA3 4 3 -- -- -- T6IN(1) -- -- -- -- -- SMTWIN2(1) -- -- -- -- IOC Y MCLR/VPP RA4 3 2 AN3 -- -- (1) -- -- -- -- -- SMTSIG1(1) -- -- -- -- IOC Y CLKOUT RA5 2 1 -- -- -- T1CKI(1) T2IN(1) -- -- -- -- -- SMTWIN1(1) -- -- -- -- IOC Y CLKIN RC0 10 9 AN4 -- C2IN+ T5CKI(1) -- -- -- -- -- -- -- SCK(1,3) -- -- IOC Y -- RC1 9 8 AN5 -- C1IN1C2IN1- T4IN(1) -- -- -- -- -- RC2 8 7 AN6 -- C1IN2C2IN2- -- -- -- -- -- -- RC3 7 6 AN7 -- C1IN3C2IN3- T5G(1) CCP2(1) -- -- CLCIN0(1) RC4 6 5 -- -- -- T3G(1) -- -- -- RC5 5 4 -- -- -- VDD 1 16 -- -- -- -- VSS 14 13 -- -- -- -- Note 1: 2: 3: (1) T3CKI SMTSIG2 (1) (1) -- SDI -- -- IOC Y -- -- -- -- -- -- IOC Y -- -- -- ATCC(1) SS(1) -- -- IOC Y -- CLCIN1(1) CK(1) -- -- -- -- HIC4 IOC Y -- -- ATIN(1) -- -- HIC5 IOC Y -- -- -- -- RX(1,3) -- -- -- -- -- -- -- -- -- -- -- -- VDD -- -- -- -- -- -- -- -- -- -- -- -- VSS CCP1 (1) ZCD1OUT CLC1OUT DT (3) -- -- -- -- C1OUT -- CCP1 CWG1A -- -- SDO PWM3OUT -- -- -- -- -- -- -- -- C2OUT -- CCP2 CWG1B -- CLC2OUT CK -- -- SCK(3) PWM4OUT -- -- -- -- -- -- -- -- -- -- -- CWG1C -- -- TX -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CWG1D -- -- -- -- -- -- -- -- -- -- -- Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections. PIC16(L)F1615/9 DS40001770A-page 5 OUT(2) T1G Basic Reference Preliminary I/O A/D 14/16-PIN ALLOCATION TABLE (PIC16(L)F1615) 16-Pin UQFN TABLE 3: 14-Pin PDIP, SOIC, TSSOP 2014 Microchip Technology Inc. PIN ALLOCATION TABLES A/D Reference Timers CCP CWG ZCD CLC EUSART SMT Angular Timer MSSP PWM High Current I/O Interrupt Pull-up 19 16 AN0 DAC1OUT C1IN+ -- -- -- -- -- -- -- -- -- -- -- IOC Y ICSPDAT RA1 18 15 AN1 VREF+ C1IN0C2IN0- -- -- -- -- -- -- -- -- -- -- -- IOC Y ICSPCLK RA2 17 14 AN2 -- -- T0CKI(1) -- CWG1IN(1) ZCD1IN -- -- -- -- -- -- -- INT IOC Y -- RA3 4 1 -- -- -- T6IN(1) -- -- -- -- -- SMTWIN2(1) -- -- -- -- IOC Y MCLR VPP RA4 3 20 AN3 -- -- T1G(1) -- -- -- -- -- SMTSIG1(1) -- -- -- -- IOC Y CLKOUT -- T1CKI(1) (1) -- -- -- -- SMTWIN1(1) -- -- -- -- IOC Y CLKIN -- -- -- -- -- -- -- SDI(1) -- -- IOC Y -- -- -- -- -- -- IOC Y -- Y -- RA5 2 19 -- -- CLCIN3 (1) Basic 20-Pin UQFN RA0 Comparator 20-Pin PDIP, SOIC, SSOP Preliminary I/O 20-PIN ALLOCATION TABLE (PIC16(L)F1619) T2IN RB4 13 10 AN10 -- -- -- RX (1,3) RB5 12 9 AN11 -- -- -- -- -- -- -- RB6 11 8 -- -- -- -- -- -- -- -- -- -- -- SCK(1,3) -- -- IOC -- -- -- -- -- CK(1) -- -- -- -- -- IOC Y -- Y -- 2014 Microchip Technology Inc. RB7 10 7 -- -- -- RC0 16 13 AN4 -- C2IN+ -- -- -- -- -- -- -- -- -- -- IOC RC1 15 12 AN5 -- C1IN1C2IN1- T4IN(1) -- -- -- CLCIN(2) -- SMTSIG2(1) -- -- -- -- IOC Y -- RC2 14 11 AN6 -- C1IN2C2IN2- -- -- -- -- -- -- -- -- -- -- -- IOC Y -- RC3 7 4 AN7 -- C1IN3C2IN3- T5G(1) CCP2(1) -- -- CLCIN0(1) -- -- ATCC(1) -- -- -- IOC Y -- RC4 6 3 -- -- -- T3G(1) -- -- -- CLCIN1(1) -- -- -- -- -- HIC4 IOC Y -- -- -- -- -- -- ATIN(1) -- -- HIC5 IOC Y -- (1) T5CKI (1) RC5 5 2 -- -- -- RC6 8 5 AN8 -- -- -- -- -- -- -- -- -- -- SS(1) -- -- IOC Y -- RC7 9 6 AN9 -- -- -- -- -- -- -- -- -- -- -- -- -- IOC Y -- VDD 1 18 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- VSS 20 17 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Note 1: 2: 3: T3CKI (1) CCP1 Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections. PIC16(L)F1615/9 DS40001770A-page 6 TABLE 4: Note 1: 2: 3: Reference Comparator Timers CCP CWG ZCD CLC EUSART MSSP PWM High Current I/O Interrupt Pull-up Basic -- -- -- C1OUT -- CCP1 CWG1A ZCD1OUT CLC1OUT DT(3) -- -- SDO PWM3OUT -- -- -- -- -- -- -- -- C2OUT -- CCP2 CWG1B -- CLC2OUT CK -- -- SCK(3) PWM4OUT -- -- -- -- -- -- -- -- -- -- -- CWG1C -- CLC3OUT TX -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CWG1D -- CLC4OUT -- -- -- -- -- -- -- -- -- Angular Timer A/D -- SMT 20-Pin UQFN OUT(2) 20-PIN ALLOCATION TABLE (PIC16(L)F1619) 20-Pin PDIP, SOIC, SSOP I/O 2014 Microchip Technology Inc. TABLE 4: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections. Preliminary PIC16(L)F1615/9 DS40001770A-page 7 PIC16(L)F1615/9 TABLE OF CONTENTS 1.0 Device Overview ........................................................................................................................................................................... 10 2.0 Enhanced Mid-Range CPU ........................................................................................................................................................... 19 3.0 Memory Organization .................................................................................................................................................................... 21 4.0 Device Configuration ..................................................................................................................................................................... 68 5.0 Oscillator Module .......................................................................................................................................................................... 76 6.0 Resets ........................................................................................................................................................................................... 92 7.0 Interrupts ..................................................................................................................................................................................... 100 8.0 Power-Down Mode (Sleep) ......................................................................................................................................................... 117 9.0 Windowed Watchdog Timer (WDT) ............................................................................................................................................ 120 10.0 Flash Program Memory Control ................................................................................................................................................ 128 11.0 Cyclic Redundancy Check (CRC) Module ................................................................................................................................ 144 12.0 I/O Ports .................................................................................................................................................................................... 156 13.0 Peripheral Pin Select (PPS) Module ......................................................................................................................................... 178 14.0 Interrupt-On-Change ................................................................................................................................................................. 186 15.0 Fixed Voltage Reference (FVR) ................................................................................................................................................ 192 16.0 Temperature Indicator Module .................................................................................................................................................. 195 17.0 Analog-to-Digital Converter (ADC) Module ............................................................................................................................... 197 18.0 8-bit Digital-to-Analog Converter (DAC1) Module ..................................................................................................................... 212 19.0 Comparator Module .................................................................................................................................................................. 216 20.0 Zero-Cross Detection (ZCD) Module ........................................................................................................................................ 224 21.0 Timer0 Module .......................................................................................................................................................................... 229 22.0 Timer1 Module with Gate Control ............................................................................................................................................. 232 23.0 Timer2/4/6 Module .................................................................................................................................................................... 243 24.0 Master Synchronous Serial Port (MSSP) Module ..................................................................................................................... 265 25.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) Module ................................................... 318 26.0 Capture/Compare/PWM Modules ............................................................................................................................................. 350 27.0 Pulse Width Modulation (PWM) Module ................................................................................................................................... 364 28.0 Complementary Waveform Generator (CWG) Module ............................................................................................................. 371 29.0 Configurable Logic Cell (CLC.................................................................................................................................................... 398 30.0 Signal Measurement Timer (SMTx) .......................................................................................................................................... 415 31.0 IAngular Timer (AT) Module ...................................................................................................................................................... 462 32.0 Proportional-Integral-Derivative (PID) Module .......................................................................................................................... 492 33.0 In-Circuit Serial ProgrammingTM (ICSPTM) ................................................................................................................................ 508 34.0 Instruction Set Summary........................................................................................................................................................... 510 35.0 Electrical Specifications ............................................................................................................................................................ 524 36.0 DC and AC Characteristics Graphs and Charts........................................................................................................................ 548 37.0 Development Support ............................................................................................................................................................... 566 38.0 Packaging Information .............................................................................................................................................................. 570 Appendix A: Data Sheet Revision History......................................................................................................................................... 593 The Microchip Web Site .................................................................................................................................................................... 594 Customer Change Notification Service ............................................................................................................................................. 594 Customer Support ............................................................................................................................................................................. 594 Product Identification System............................................................................................................................................................ 595 DS40001770A-page 8 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: * Microchip's Worldwide Web site; http://www.microchip.com * Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 9 PIC16(L)F1615/9 DEVICE OVERVIEW TABLE 1-1: DEVICE PERIPHERAL SUMMARY Peripheral PIC16(L)F1619 The PIC16(L)F1615/9 are described within this data sheet. The block diagram of these devices are shown in Figure 1-1, the available peripherals are shown in Table 1-1, and the pin out descriptions are shown in Tables 1-2 and 1-3. PIC16(L)F1615 1.0 Analog-to-Digital Converter (ADC) Complementary Wave Generator (CWG) Cyclic Redundancy Check (CRC) Digital-to-Analog Converter (DAC) Enhanced Universal Synchronous/Asynchronous Receiver/Transmitter (EUSART) Fixed Voltage Reference (FVR) Temperature Indicator Windowed Watchdog Timer (WDT) Zero Cross Detection (ZCD) CCP1 CCP2 C1 C2 CLC1 CLC2 CLC3 CLC4 MSSP1 PWM3 PWM4 SMT1 SMT2 Timer0 Timer1 Timer2 Timer3 Timer4 Timer5 Timer6 Capture/Compare/PWM (CCP) Modules Comparators Configurable Logic Cell (CLC) Master Synchronous Serial Ports Pulse-Width Modulator (PWM) Signal Measurement Timer (SMT) Timers DS40001770A-page 10 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 1.1 1.1.1 1.1.2.3 Register and Bit Naming Conventions REGISTER NAMES When there are multiple instances of the same peripheral in a device, the peripheral control registers will be depicted as the concatenation of a peripheral identifier, peripheral instance, and control identifier. The control registers section will show just one instance of all the register names with an `x' in the place of the peripheral instance number. This naming convention may also be applied to peripherals when there is only one instance of that peripheral in the device to maintain compatibility with other devices in the family that contain more than one. 1.1.2 BIT NAMES There are two variants for bit names: * Short name: Bit function abbreviation * Long name: Peripheral abbreviation + short name 1.1.2.1 Short Bit Names Short bit names are an abbreviation for the bit function. For example, some peripherals are enabled with the EN bit. The bit names shown in the registers are the short name variant. Short bit names are useful when accessing bits in C programs. The general format for accessing bits by the short name is RegisterNamebits.ShortName. For example, the enable bit, EN, in the COG1CON0 register can be set in C programs with the instruction COG1CON0bits.EN = 1. Short names are generally not useful in assembly programs because the same name may be used by different peripherals in different bit positions. When this occurs, during the include file generation, all instances of that short bit name are appended with an underscore plus the name of the register in which the bit resides to avoid naming contentions. 1.1.2.2 Long Bit Names Long bit names are constructed by adding a peripheral abbreviation prefix to the short name. The prefix is unique to the peripheral, thereby making every long bit name unique. The long bit name for the COG1 enable bit is the COG1 prefix, G1, appended with the enable bit short name, EN, resulting in the unique bit name G1EN. Long bit names are useful in both C and assembly programs. For example, in C the COG1CON0 enable bit can be set with the G1EN = 1 instruction. In assembly, this bit can be set with the BSF COG1CON0,G1EN instruction. 2014 Microchip Technology Inc. Bit Fields Bit fields are two or more adjacent bits in the same register. Bit fields adhere only to the short bit naming convention. For example, the three Least Significant bits of the COG1CON0 register contain the mode control bits. The short name for this field is MD. There is no long bit name variant. Bit field access is only possible in C programs. The following example demonstrates a C program instruction for setting the COG1 to the Push-Pull mode: COG1CON0bits.MD = 0x5; Individual bits in a bit field can also be accessed with long and short bit names. Each bit is the field name appended with the number of the bit position within the field. For example, the Most Significant mode bit has the short bit name MD2 and the long bit name is G1MD2. The following two examples demonstrate assembly program sequences for setting the COG1 to Push-Pull mode: Example 1: MOVLW ANDWF MOVLW IORWF ~(1<<G1MD1) COG1CON0,F 1<<G1MD2 | 1<<G1MD0 COG1CON0,F Example 2: BSF BCF BSF COG1CON0,G1MD2 COG1CON0,G1MD1 COG1CON0,G1MD0 1.1.3 1.1.3.1 REGISTER AND BIT NAMING EXCEPTIONS Status, Interrupt, and Mirror Bits Status, interrupt enables, interrupt flags, and mirror bits are contained in registers that span more than one peripheral. In these cases, the bit name shown is unique so there is no prefix or short name variant. 1.1.3.2 Legacy Peripherals There are some peripherals that do not strictly adhere to these naming conventions. Peripherals that have existed for many years and are present in almost every device are the exceptions. These exceptions were necessary to limit the adverse impact of the new conventions on legacy code. Peripherals that do adhere to the new convention will include a table in the registers section indicating the long name prefix for each peripheral instance. Peripherals that fall into the exception category will not have this table. These peripherals include, but are not limited to, the following: * EUSART * MSSP Preliminary DS40001770A-page 11 PIC16(L)F1615/9 BLOCK DIAGRAM Rev. 10-000039H 5/23/2014 Program Flash Memory RAM PORTA CLKOUT /OSC2 CLKIN/ OSC1 (4) Timing Generation PORTB CPU PORTC INTRC Oscillator (Note 3) MCLR Preliminary TMR6 CWG1 2014 Microchip Technology Inc. Note TMR5 SMT2 1: 2: 3: 4: TMR4 SMT1 AT TMR3 TMR2 PID TMR1 TMR0 EUSART MSSP See applicable chapters for more information on peripherals. See Table 1-1 for peripherals available on specific devices. See Figure 2-1. PIC16(L)F1619 only. PWM4 CLC4 PWM3 CLC3 CLC2 C2 C1 CLC1 Temp Indicator Scanner CRC ADC 10-bit ZCD1 DAC CCP2 FVR CCP1 PIC16(L)F1615/9 DS40001770A-page 12 FIGURE 1-1: PIC16(L)F1615/9 TABLE 1-2: PIC16(L)F1615 PINOUT DESCRIPTION Name RA0/AN0/C1IN+/DAC1OUT1/ ICSPDAT RA1/AN1/VREF+/C1IN0-/C2IN0-/ ICSPCLK RA2/AN2/T0CKI(1)/CWG1IN(1) ZCD1IN/INT RA3/VPP/T6IN(1)/SMTWIN2(1)/ MCLR RA4/AN3/T1G(1)/SMTSIG1(1)/ CLKOUT RA5/CLKIN/T1CKI(1)/T2IN(1)/ SMTWIN1(1) Function Input Type RA0 TTL/ST AN0 AN Output Type Description CMOS/OD General purpose I/O. -- ADC Channel input. C1IN+ AN -- Comparator positive input. DAC1OUT1 -- AN Digital-to-Analog Converter output. ICSPDAT ST CMOS RA1 TTL/ST ICSPTM Data I/O. CMOS/OD General purpose I/O. AN1 AN -- VREF+ AN -- ADC Channel input. Voltage Reference input. C1IN0- AN -- Comparator negative input. C2IN0- AN CMOS/OD Comparator negative input. ICSPCLK ST RA2 TTL/ST -- ICSP Programming Clock. CMOS/OD General purpose I/O. AN2 AN -- ADC Channel input. T0CKI TTL/ST -- Timer0 clock input. CWG1IN TTL/ST -- CWG complementary input. ZCD1IN AN -- Zero-Cross Detect input. INT TTL/ST -- External interrupt. RA3 TTL/ST -- General purpose input with IOC and WPU. VPP HV -- Programming voltage. T6IN TTL/ST -- Timer6 input. SMTWIN2 TTL/ST -- SMT2 window input. MCLR TTL/ST -- Master Clear with internal pull-up. RA4 TTL/ST AN3 AN -- ADC Channel input. T1G TTL/ST -- Timer1 Gate input. SMTSIG1 TTL/ST -- SMT1 signal input. CLKOUT -- RA5 TTL/ST CMOS/OD General purpose I/O. CMOS FOSC/4 output. CMOS/OD General purpose I/O. CLKIN CMOS -- External clock input (EC mode). T1CKI TTL/ST -- Timer1 clock input. T2IN TTL/ST -- Timer2 input. SMTWIN1 TTL/ST -- SMT1 window input. RC0/AN4/C2IN+/T5CKI(1)/ RC0 TTL/ST SCK(1) AN4 AN -- ADC Channel input. C2IN+ AN -- Comparator positive input. T5CKI TTL/ST -- Timer5 clock input. SCK ST CMOS CMOS/OD General purpose I/O. SPI clock. AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2CTM = Schmitt Trigger input with I2CTM HV = High Voltage XTAL = Crystal levels 1: Alternate pin function selected with the APFCON register (Register 12-1). 2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. See Register 13-1. Legend: Note 2014 Microchip Technology Inc. Preliminary DS40001770A-page 13 PIC16(L)F1615/9 TABLE 1-2: PIC16(L)F1615 PINOUT DESCRIPTION (CONTINUED) Name RC1/AN5/C1IN1-/C2IN1-/ T4IN(1)/SMTSIG2(1)/SDI(1) RC2/AN6/C1IN2-/C2IN2- RC3/AN7/C1IN3-/C2IN3-/T5G(1)/ CCP2(1)/CLCIN0(1)/ATCC(1)/SS Function Input Type RC1 TTL/ST Output Type Description CMOS/OD General purpose I/O. AN5 AN -- ADC Channel input. C1IN1- AN -- Comparator negative input. C2IN1- AN -- Comparator negative input. T4IN TTL/ST -- Timer4 input. SMTSIG2 TTL/ST -- SMT2 signal input. SDI CMOS -- SPI data input. RC2 TTL/ST AN6 AN -- ADC Channel input. C1IN2- AN -- Comparator negative input. C2IN2- AN -- Comparator negative input. RC3 TTL/ST -- General purpose input with IOC and WPU. AN7 AN -- ADC Channel input. C1IN3- AN -- Comparator negative input. C2IN3- AN -- Comparator negative input. T5G ST -- Timer5 Gate input. CCP2 TTL/ST CLCIN0 ST CMOS/OD General purpose I/O. CMOS/OD Capture/Compare/PWM2. -- Configurable Logic Cell source input. -- Slave Select input. ATCC RC4/T3G(1)/CLCIN1(1)/CK(1)/ HIC4 SS ST RC4 TTL/ST CMOS/OD General purpose I/O. T3G TTL/ST -- CLCIN1 ST -- CK ST CMOS Timer3 Gate input. Configurable Logic Cell source input. EUSART synchronous clock. HIC4 (1) (1) (1) RC5/T3CKI /CCP1 /RX / ATIN(1)/HIC5 RC5 TTL/ST CMOS/OD General purpose I/O. CCP1 TTL/ST CMOS/OD Capture/Compare/PWM1. RX ST T3CKI -- EUSART asynchronous input. ATIN HIC5 AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2CTM = Schmitt Trigger input with I2CTM HV = High Voltage XTAL = Crystal levels 1: Alternate pin function selected with the APFCON register (Register 12-1). 2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. See Register 13-1. Legend: Note DS40001770A-page 14 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 TABLE 1-2: PIC16(L)F1615 PINOUT DESCRIPTION (CONTINUED) Name OUT(2) Function Input Type Output Type C1OUT -- CMOS Comparator output. C2OUT -- CMOS Comparator output. CCP1 -- CMOS Capture/Compare/PWM1 output. CCP2 -- CMOS Capture/Compare/PWM2 output. PWM3OUT -- CMOS PWM3 output. Description PWM4OUT -- CMOS PWM4 output. CWG1A -- CMOS Complementary Output Generator Output A. CWG1B -- CMOS Complementary Output Generator Output B. CWG1C -- CMOS Complementary Output Generator Output C. CWG1D -- CMOS Complementary Output Generator Output D. SDO -- CMOS SPI data output. SCK -- CMOS SPI clock output. CMOS EUSART asynchronous TX data/synchronous clock output. TX/CK -- DT -- CMOS EUSART synchronous data output.E CLC1OUT -- CMOS Configurable Logic Cell 1 source output. Configurable Logic Cell 2 source output. CLC2OUT -- CMOS ZCD1OUT -- CMOS VDD VDD Power -- Positive supply. VSS VSS Power -- Ground reference. AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2CTM = Schmitt Trigger input with I2CTM HV = High Voltage XTAL = Crystal levels 1: Alternate pin function selected with the APFCON register (Register 12-1). 2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. See Register 13-1. Legend: Note 2014 Microchip Technology Inc. Preliminary DS40001770A-page 15 PIC16(L)F1615/9 TABLE 1-3: PIC16(L)F1619 PINOUT DESCRIPTION Name RA0/AN0/C1IN+/DAC1OUT/ ICSPDAT RA1/AN1/VREF+/C1IN0-/C2IN0-/ ICSPCLK RA2/AN2/T0CKI(1)/CWG1IN(1)/ ZCD1IN/INT RA3/VPP/T6IN(1)/SMTWIN2(1)/ MCLR RA4/AN3/T1G(1)/SMTSIG1(1)/ CLKOUT RA5/CLKIN/T1CKI(1)/T2IN(1)/ CLCIN3(1)/SMTWIN1 (1) RB4/AN10/SDI RB5/AN11/RX(1, 3) Function Input Type RA0 TTL/ST AN0 AN Output Type Description CMOS/OD General purpose I/O. -- ADC Channel input. C1IN+ AN -- Comparator positive input. DAC1OUT -- AN Digital-to-Analog Converter output. ICSPDAT ST CMOS RA1 TTL/ST ICSPTM Data I/O. CMOS/OD General purpose I/O. AN1 AN -- VREF+ AN -- ADC Channel input. Voltage Reference input. C1IN0- AN -- Comparator negative input. C2IN0- AN CMOS/OD Comparator negative input. ICSPCLK ST RA2 TTL/ST ICSP Programming Clock. CMOS/OD General purpose I/O. AN2 AN -- ADC Channel input. T0CKI TTL/ST -- Timer0 clock input. CWG1IN TTL/ST -- CWG complementary input. ZCD1IN AN -- Zero-Cross Detect input. INT TTL/ST -- External interrupt. RA3 TTL/ST -- General purpose input with IOC and WPU. VPP HV -- Programming voltage. T6IN TTL/ST -- Timer6 input. SMTWIN2 TTL/ST -- SMT2 window input. MCLR TTL/ST -- Master Clear with internal pull-up. RA4 TTL/ST AN3 AN -- ADC Channel input. T1G TTL/ST -- Timer1 Gate input. SMTSIG1 TTL/ST -- SMT1 signal input. CLKOUT -- RA5 TTL/ST CMOS/OD General purpose I/O. CMOS FOSC/4 output. CMOS/OD General purpose I/O. CLKIN CMOS -- External clock input (EC mode). T1CKI TTL/ST -- Timer1 clock input. T2IN TTL/ST -- Timer2 input. CLCIN3 ST -- Configurable Logic Cell source input. SMTWIN1 TTL/ST -- SMT1 window input. RB4 TTL/ST AN10 AN CMOS/OD General purpose I/O. -- ADC Channel input. SDI CMOS -- SPI data input. RB5 TTL/ST AN11 AN CMOS/OD General purpose I/O. -- ADC Channel input. RX ST -- EUSART asynchronous input. AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2CTM = Schmitt Trigger input with I2CTM HV = High Voltage XTAL = Crystal levels 1: Alternate pin function selected with the APFCON register (Register 12-1). 2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. See Register 13-1. 3: These I2C functions are bidirectional. The output pin selections must be the same as the input pin selections. Legend: Note DS40001770A-page 16 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 TABLE 1-3: PIC16(L)F1619 PINOUT DESCRIPTION (CONTINUED) Name RB6/SCK(1, 3) RB7/CK(1) RC0/AN4/C2IN+/T5CKI(1) RC1/AN5/C1IN1-/C2IN1-/ T4IN(1)/CLCIN(2)/SMTSIG2(1) Function Input Type RB6 TTL/ST SCK ST RB7 TTL/ST CK ST RC0 TTL/ST Output Type Description CMOS/OD General purpose I/O. CMOS SPI clock. CMOS/OD General purpose I/O. CMOS EUSART synchronous clock. CMOS/OD General purpose I/O. AN4 AN -- ADC Channel input. C2IN+ AN -- Comparator positive input. -- Timer5 clock input. T5CKI TTL/ST RC1 TTL/ST CMOS/OD General purpose I/O. AN5 AN -- ADC Channel input. C1IN1- AN -- Comparator negative input. C2IN1- AN -- Comparator negative input. T4IN TTL/ST -- Timer4 input. -- SMT2 signal input. CLCIN RC2/AN6/C1IN2-/C2IN2- RC3/AN7/C1IN3-/C2IN3-/T5G(1)/ CCP2(1)/CLCIN0(1)/ATCC(1) SMTSIG2 TTL/ST RC2 TTL/ST AN6 AN -- ADC Channel input. C1IN2- AN -- Comparator negative input. C2IN2- AN -- Comparator negative input. RC3 TTL/ST -- General purpose input with IOC and WPU. AN7 AN -- ADC Channel input. C1IN3- AN -- Comparator negative input. C2IN3- AN -- Comparator negative input. T5G ST -- CCP2 ST CMOS CLCIN0 ST -- CMOS/OD General purpose I/O. Timer5 Gate input. Capture/Compare/PWM2. Configurable Logic Cell source input. ATCC RC4/T3G(1)/CLCIN1(1)/HIC4 RC4 TTL/ST T3G ST CMOS/OD General purpose I/O. -- Timer3 Gate input. CLCIN1 ST -- Configurable Logic Cell source input. HIC4 RC5/T3CKI(1)/CCP1(1)/ATIN(1)/ HIC5 RC5 TTL/ST T3CKI TTL/ST CCP1 TTL/ST CMOS/OD General purpose I/O. -- Timer3 clock input. CMOS/OD Capture/Compare/PWM1. ATIN HIC5 AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2CTM = Schmitt Trigger input with I2CTM HV = High Voltage XTAL = Crystal levels 1: Alternate pin function selected with the APFCON register (Register 12-1). 2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. See Register 13-1. 3: These I2C functions are bidirectional. The output pin selections must be the same as the input pin selections. Legend: Note 2014 Microchip Technology Inc. Preliminary DS40001770A-page 17 PIC16(L)F1615/9 TABLE 1-3: PIC16(L)F1619 PINOUT DESCRIPTION (CONTINUED) Name OUT(2) Function Input Type Output Type C1OUT -- CMOS Comparator output. C2OUT -- CMOS Comparator output. CCP1 -- CMOS Capture/Compare/PWM1 output. CCP2 -- CMOS Capture/Compare/PWM2 output. PWM3OUT -- CMOS PWM3 output. Description PWM4OUT -- CMOS PWM4 output. CWG1A -- CMOS Complementary Output Generator Output A. CWG1B -- CMOS Complementary Output Generator Output B. CWG1C -- CMOS Complementary Output Generator Output C. CWG1D -- CMOS Complementary Output Generator Output D. SDO -- CMOS SPI data output. SCK -- CMOS SPI clock output. CMOS EUSART asynchronous TX data/synchronous clock output. TX/CK -- DT -- CMOS EUSART synchronous data output. CLC1OUT -- CMOS Configurable Logic Cell 1 source output. CLC2OUT -- CMOS Configurable Logic Cell 2 source output. CLC3OUT -- CMOS Configurable Logic Cell 3 source output. CLC4OUT -- CMOS Configurable Logic Cell 4 source output. ZCD1OUT -- CMOS VDD VDD Power -- Positive supply. VSS VSS Power -- Ground reference. AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2CTM = Schmitt Trigger input with I2CTM HV = High Voltage XTAL = Crystal levels 1: Alternate pin function selected with the APFCON register (Register 12-1). 2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. See Register 13-1. 3: These I2C functions are bidirectional. The output pin selections must be the same as the input pin selections. Legend: Note DS40001770A-page 18 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 2.0 * * * * ENHANCED MID-RANGE CPU This family of devices contain an enhanced mid-range 8-bit CPU core. The CPU has 49 instructions. Interrupt capability includes automatic context saving. The hardware stack is 16 levels deep and has Overflow and Underflow Reset capability. Direct, Indirect, and Relative Addressing modes are available. Two File Select Registers (FSRs) provide the ability to read program and data memory. FIGURE 2-1: Automatic Interrupt Context Saving 16-level Stack with Overflow and Underflow File Select Registers Instruction Set CORE BLOCK DIAGRAM Rev. 10-000055A 7/30/2013 15 Configuration 15 MUX Flash Program Memory Data Bus 16-Level Stack (15-bit) RAM 14 Program Bus 8 Program Counter 12 Program Memory Read (PMR) RAM Addr Addr MUX Instruction Reg Direct Addr 7 5 Indirect Addr 12 12 BSR Reg 15 FSR0 Reg 15 FSR1 Reg STATUS Reg 8 Instruction Decode and Control CLKIN CLKOUT Timing Generation Internal Oscillator Block 2014 Microchip Technology Inc. Power-up Timer Power-on Reset Watchdog Timer Brown-out Reset VDD 3 8 MUX ALU W Reg VSS Preliminary DS40001770A-page 19 PIC16(L)F1615/9 2.1 Automatic Interrupt Context Saving During interrupts, certain registers are automatically saved in shadow registers and restored when returning from the interrupt. This saves stack space and user code. See Section 7.5 "Automatic Context Saving", for more information. 2.2 16-Level Stack with Overflow and Underflow These devices have a hardware stack memory 15 bits wide and 16 words deep. A Stack Overflow or Underflow will set the appropriate bit (STKOVF or STKUNF) in the PCON register, and if enabled, will cause a software Reset. See section Section 3.4 "Stack" for more details. 2.3 File Select Registers There are two 16-bit File Select Registers (FSR). FSRs can access all file registers and program memory, which allows one Data Pointer for all memory. When an FSR points to program memory, there is one additional instruction cycle in instructions using INDF to allow the data to be fetched. General purpose memory can now also be addressed linearly, providing the ability to access contiguous data larger than 80 bytes. There are also new instructions to support the FSRs. See Section 3.5 "Indirect Addressing" for more details. 2.4 Instruction Set There are 49 instructions for the enhanced mid-range CPU to support the features of the CPU. See Section 34.0 "Instruction Set Summary" for more details. DS40001770A-page 20 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 3.0 MEMORY ORGANIZATION 3.1 These devices contain the following types of memory: * Program Memory - Configuration Words - Device ID - User ID - Flash Program Memory * Data Memory - Core Registers - Special Function Registers - General Purpose RAM - Common RAM Program Memory Organization The enhanced mid-range core has a 15-bit program counter capable of addressing a 32K x 14 program memory space. Table 3-1 shows the memory sizes implemented. Accessing a location above these boundaries will cause a wrap-around within the implemented memory space. The Reset vector is at 0000h and the interrupt vector is at 0004h (See Figure 3-1). The following features are associated with access and control of program memory and data memory: * PCL and PCLATH * Stack * Indirect Addressing TABLE 3-1: DEVICE SIZES AND ADDRESSES Device PIC16(L)F1615/9 2014 Microchip Technology Inc. Program Memory Space (Words) Last Program Memory Address 8,192 1FFFh Preliminary DS40001770A-page 21 PIC16(L)F1615/9 FIGURE 3-1: PROGRAM MEMORY MAP AND STACK FOR PIC16(L)F1615/9 Rev. 10-000040B 7/30/2013 PC<14:0> CALL, CALLW RETURN, RETLW Interrupt, RETFIE 3.1.1 There are two methods of accessing constants in program memory. The first method is to use tables of RETLW instructions. The second method is to set an FSR to point to the program memory. 3.1.1.1 15 READING PROGRAM MEMORY AS DATA RETLW Instruction The RETLW instruction can be used to provide access to tables of constants. The recommended way to create such a table is shown in Example 3-1. Stack Level 0 Stack Level 1 EXAMPLE 3-1: constants BRW Stack Level 15 Reset Vector 0000h Interrupt Vector 0004h 0005h Page 0 07FFh 0800h Page 1 On-chip Program Memory 0FFFh 1000h Page 2 17FFh 1800h Page 3 Rollover to Page 0 1FFFh 2000h Rollover to Page 3 7FFFh DS40001770A-page 22 RETLW RETLW RETLW RETLW DATA0 DATA1 DATA2 DATA3 RETLW INSTRUCTION ;Add Index in W to ;program counter to ;select data ;Index0 data ;Index1 data my_function ;... LOTS OF CODE... MOVLW DATA_INDEX call constants ;... THE CONSTANT IS IN W The BRW instruction makes this type of table very simple to implement. If your code must remain portable with previous generations of microcontrollers, then the BRW instruction is not available, so the older table read method must be used. Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 3.1.1.2 Indirect Read with FSR The program memory can be accessed as data by setting bit 7 of the FSRxH register and reading the matching INDFx register. The MOVIW instruction will place the lower eight bits of the addressed word in the W register. Writes to the program memory cannot be performed via the INDF registers. Instructions that access the program memory via the FSR require one extra instruction cycle to complete. Example 3-2 demonstrates accessing the program memory via an FSR. The HIGH operator will set bit<7> if a label points to a location in program memory. EXAMPLE 3-2: ACCESSING PROGRAM MEMORY VIA FSR constants RETLW DATA0 ;Index0 data RETLW DATA1 ;Index1 data RETLW DATA2 RETLW DATA3 my_function ;... LOTS OF CODE... MOVLW LOW constants MOVWF FSR1L MOVLW HIGH constants MOVWF FSR1H MOVIW 0[FSR1] ;THE PROGRAM MEMORY IS IN W 2014 Microchip Technology Inc. Preliminary DS40001770A-page 23 PIC16(L)F1615/9 3.2 Data Memory Organization The data memory is partitioned in 32 memory banks with 128 bytes in a bank. Each bank consists of (Figure 3-2): * * * * 12 core registers 20 Special Function Registers (SFR) Up to 80 bytes of General Purpose RAM (GPR) 16 bytes of common RAM Data memory uses a 12-bit address. The upper five bits of the address define the Bank address and the lower seven bits select the registers/RAM in that bank. 3.2.1 The active bank is selected by writing the bank number into the Bank Select Register (BSR). Unimplemented memory will read as `0'. All data memory can be accessed either directly (via instructions that use the TABLE 3-2: file registers) or indirectly via the two File Select Registers (FSR). See Section 3.5 "Indirect Addressing" for more information. CORE REGISTERS The core registers contain the registers that directly affect the basic operation. The core registers occupy the first 12 addresses of every data memory bank (addresses x00h/x08h through x0Bh/x8Bh). These registers are listed below in Table 3-2. For detailed CORE REGISTERS Addresses BANKx x00h or x80h x01h or x81h x02h or x82h x03h or x83h x04h or x84h x05h or x85h x06h or x86h x07h or x87h x08h or x88h x09h or x89h x0Ah or x8Ah x0Bh or x8Bh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON DS40001770A-page 24 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 3.2.1.1 STATUS Register The STATUS register, shown in Register 3-1, contains: * the arithmetic status of the ALU * the Reset status The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. REGISTER 3-1: U-0 It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect any Status bits. For other instructions not affecting any Status bits (Refer to Section 34.0 "Instruction Set Summary"). Note 1: The C and DC bits operate as Borrow and Digit Borrow out bits, respectively, in subtraction. STATUS: STATUS REGISTER U-0 -- For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as `000u u1uu' (where u = unchanged). -- U-0 R-1/q -- TO R-1/q PD R/W-0/u Z R/W-0/u (1) DC bit 7 R/W-0/u C(1) bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-5 Unimplemented: Read as `0' bit 4 TO: Time-Out bit 1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred bit 3 PD: Power-Down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit Carry/Digit Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1) 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result bit 0 C: Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 25 PIC16(L)F1615/9 3.2.2 SPECIAL FUNCTION REGISTER FIGURE 3-2: The Special Function Registers are registers used by the application to control the desired operation of peripheral functions in the device. The Special Function Registers occupy the 20 bytes after the core registers of every data memory bank (addresses x0Ch/x8Ch through x1Fh/x9Fh). The registers associated with the operation of the peripherals are described in the appropriate peripheral chapter of this data sheet. 3.2.3 Rev. 10-000041A 7/30/2013 7-bit Bank Offset GENERAL PURPOSE RAM There are up to 80 bytes of GPR in each data memory bank. The Special Function Registers occupy the 20 bytes after the core registers of every data memory bank (addresses x0Ch/x8Ch through x1Fh/x9Fh). 3.2.3.1 BANKED MEMORY PARTITIONING Memory Region 00h Core Registers (12 bytes) 0Bh 0Ch Special Function Registers (20 bytes maximum) 1Fh 20h Linear Access to GPR The general purpose RAM can be accessed in a nonbanked method via the FSRs. This can simplify access to large memory structures. See Section 3.5.2 "Linear Data Memory" for more information. 3.2.4 General Purpose RAM (80 bytes maximum) COMMON RAM There are 16 bytes of common RAM accessible from all banks. 3.2.5 DEVICE MEMORY MAPS The memory maps for PIC16(L)F1615/9 are as shown in Table 3-3 through Table 3-14. 6Fh 70h Common RAM (16 bytes) 7Fh DS40001770A-page 26 Preliminary 2014 Microchip Technology Inc. 2014 Microchip Technology Inc. TABLE 3-3: PIC16(L)F1615 MEMORY MAP, BANK 0-7 BANK 0 000h BANK 1 080h Core Registers (Table 3-2) Preliminary 00Bh 00Ch 00Dh 00Eh 00Fh 010h 011h 012h 013h 014h 015h 016h 017h 018h 019h 01Ah 01Bh 01Ch 01Dh 01Eh 01Fh 020h PORTA -- PORTC -- PIR1 PIR2 PIR3 PIR4 PIR5 TMR0 TMR1L TMR1H T1CON T1GCON TMR2 PR2 T2CON T2HLT T2CLKCON T2RST 07Fh Legend: Core Registers (Table 3-2) 08Bh 08Ch 08Dh 08Eh 08Fh 090h 091h 092h 093h 094h 095h 096h 097h 098h 099h 09Ah 09Bh 09Ch 09Dh 09Eh 09Fh 0A0h TRISA -- TRISC -- PIE1 PIE2 PIE3 PIE4 PIE5 OPTION_REG PCON -- OSCTUNE OSCCON OSCSTAT ADRESL ADRESH ADCON0 ADCON1 ADCON2 Core Registers (Table 3-2) 10Bh 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh 11Fh 120h General Purpose Register 80 Bytes 0EFh 0F0h 0FFh Common RAM (Accesses 70h - 7Fh) BANK 3 180h LATA -- LATC -- -- CM1CON0 CM1CON1 CM2CON0 CM2CON1 CMOUT BORCON FVRCON DAC1CON0 DAC1CON1 -- -- ZCD1CON -- -- -- Core Registers (Table 3-2) 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh 1A0h General Purpose Register 80 Bytes 16Fh 170h 17Fh Common RAM (Accesses 70h - 7Fh) = Unimplemented data memory locations, read as `0'. BANK 4 200h ANSELA -- ANSELC -- -- PMADRL PMADRH PMDATL PMDATH PMCON1 PMCON2 VREGCON -- RC1REG TX1REG SP1BRGL SP1BRGH RC1STA TX1STA BAUD1CON Core Registers (Table 3-2) 20Bh 20Ch 20Dh 20Eh 20Fh 210h 211h 212h 213h 214h 215h 216h 217h 218h 219h 21Ah 21Bh 21Ch 21Dh 21Eh 21Fh 220h General Purpose Register 80 Bytes 1EFh 1F0h 1FFh Common RAM (Accesses 70h - 7Fh) BANK 5 280h WPUA -- WPUC -- -- SSP1BUF SSP1ADD SSP1MSK SSP1STAT SSP1CON SSP1CON2 SSP1CON3 -- -- -- -- -- -- -- -- Core Registers (Table 3-2) 28Bh 28Ch 28Dh 28Eh 28Fh 290h 291h 292h 293h 294h 295h 296h 297h 298h 299h 29Ah 29Bh 29Ch CCPR1L CCPR1H CCP1CON CCP1CAP -- -- -- 29Dh 29Eh 29Fh 2A0h CCPTMRS -- General Purpose Register 80 Bytes 26Fh 270h 27Fh Common RAM (Accesses 70h - 7Fh) BANK 6 300h ODCONA -- ODCONC -- -- CCPR2L CCPR2H CCP2CON CCP2CAP -- -- Core Registers (Table 3-2) 30Bh 30Ch 30Dh 30Eh 30Fh 310h 311h 312h 313h 314h 315h 316h 317h 318h 319h 31Ah 31Bh 31Ch 31Dh 31Eh 31Fh 320h General Purpose Register 80 Bytes 2EFh 2F0h 2FFh Common RAM (Accesses 70h - 7Fh) BANK 7 380h SLRCONA -- SLRCONC -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Core Registers (Table 3-2) 38Bh 38Ch 38Dh 38Eh 38Fh 390h 391h 392h 393h 394h 395h 396h 397h 398h 399h 39Ah 39Bh 39Ch 39Dh 39Eh 39Fh 3A0h General Purpose Register 80 Bytes 36Fh 370h 37Fh Common RAM (Accesses 70h - 7Fh) INLVLA -- INLVLC -- -- IOCAP IOCAN IOCAF -- -- -- IOCCP IOCCN IOCCF -- -- -- -- -- -- General Purpose Register 80 Bytes 3EFh 3F0h 3FFh Common RAM (Accesses 70h - 7Fh) DS40001770A-page 27 PIC16(L)F1615/9 General Purpose Register 96 Bytes BANK 2 100h PIC16(L)F1619 MEMORY MAP, BANK 0-7 BANK 0 000h BANK 1 080h Core Registers (Table 3-2) Preliminary 00Bh 00Ch 00Dh 00Eh 00Fh 010h 011h 012h 013h 014h 015h 016h 017h 018h 019h 01Ah 01Bh 01Ch 01Dh 01Eh 01Fh 020h PORTA PORTB PORTC -- PIR1 PIR2 PIR3 PIR4 PIR5 TMR0 TMR1L TMR1H T1CON T1GCON TMR2 PR2 T2CON T2HLT T2CLKCON T2RST General Purpose Register 96 Bytes 2014 Microchip Technology Inc. 07Fh Legend: BANK 2 100h Core Registers (Table 3-2) 08Bh 08Ch 08Dh 08Eh 08Fh 090h 091h 092h 093h 094h 095h 096h 097h 098h 099h 09Ah 09Bh 09Ch 09Dh 09Eh 09Fh 0A0h TRISA TRISB TRISC -- PIE1 PIE2 PIE3 PIE4 PIE5 OPTION_REG PCON -- OSCTUNE OSCCON OSCSTAT ADRESL ADRESH ADCON0 ADCON1 ADCON2 Core Registers (Table 3-2) 10Bh 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh 11Fh 120h General Purpose Register 80 Bytes 0EFh 0F0h 0FFh Common RAM (Accesses 70h - 7Fh) BANK 3 180h LATA LATB LATC -- -- CM1CON0 CM1CON1 CM2CON0 CM2CON1 CMOUT BORCON FVRCON DAC1CON0 DAC1CON1 -- -- ZCD1CON -- -- -- Core Registers (Table 3-2) 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh 1A0h General Purpose Register 80 Bytes 16Fh 170h 17Fh Common RAM (Accesses 70h - 7Fh) = Unimplemented data memory locations, read as `0'. BANK 4 200h ANSELA ANSELB ANSELC -- -- PMADRL PMADRH PMDATL PMDATH PMCON1 PMCON2 VREGCON -- RC1REG TX1REG SP1BRGL SP1BRGH RC1STA TX1STA BAUD1CON Core Registers (Table 3-2) 20Bh 20Ch 20Eh 20Eh 20Fh 210h 211h 212h 213h 214h 215h 216h 217h 218h 219h 21Ah 21Bh 21Ch 21Dh 21Eh 21Fh 220h General Purpose Register 80 Bytes 1EFh 1F0h 1FFh Common RAM (Accesses 70h - 7Fh) BANK 5 280h WPUA WPUB WPUC -- -- SSP1BUF SSP1ADD SSP1MSK SSP1STAT SSP1CON SSP1CON2 SSP1CON3 -- -- -- -- -- -- -- -- Core Registers (Table 3-2) 28Bh 28Ch 28Eh 28Eh 28Fh 290h 291h 292h 293h 294h 295h 296h 297h 298h 299h 29Ah 29Bh 29Ch CCP1RL CCP1RH CCP1CON CCP1CAP -- -- -- 29Dh 29Eh 29Fh 2A0h CCPTMRS -- General Purpose Register 80 Bytes 26Fh 270h 27Fh Common RAM (Accesses 70h - 7Fh) BANK 6 300h ODCONA ODCONB ODCONC -- -- CCP2RL CCP2RH CCP2CON CCP2CAP -- -- Core Registers (Table 3-2) 30Bh 30Ch 30Eh 30Eh 30Fh 310h 311h 312h 313h 314h 315h 316h 317h 318h 319h 31Ah 31Bh 31Ch 31Dh 31Eh 31Fh 320h General Purpose Register 80 Bytes 2EFh 2F0h 2FFh Common RAM (Accesses 70h - 7Fh) BANK 7 380h SLRCONA SLRCONB SLRCONC -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Core Registers (Table 3-2) 38Bh 38Ch 38Eh 38Eh 38Fh 390h 391h 392h 393h 394h 395h 396h 397h 398h 399h 39Ah 39Bh 39Ch 39Dh 39Eh 39Fh 3A0h General Purpose Register 80 Bytes 36Fh 370h 37Fh Common RAM (Accesses 70h - 7Fh) INLVLA INLVLB INLVLC -- -- IOCAP IOCAN IOCAF IOCBP IOCBN IOCBF IOCCP IOCCN IOCCF -- -- -- -- -- -- General Purpose Register 80 Bytes 3EFh 3F0h 3FFh Common RAM (Accesses 70h - 7Fh) PIC16(L)F1615/9 DS40001770A-page 28 TABLE 3-4: 2014 Microchip Technology Inc. TABLE 3-5: PIC16(L)F1615/9 MEMORY MAP, BANK 8-15 BANK 8 400h BANK 9 480h Core Registers (Table 3-2) Preliminary 40Bh 40Ch 40Dh 40Eh 40Fh 410h 411h 412h 413h 414h 415h 416h 417h 418h 419h 41Ah 41Bh 41Ch 41Dh 41Eh 41Fh 420h -- -- HDRVENC -- -- -- -- TMR4 PR4 T4CON T4HLT T4CLKCON T4RST -- TMR6 PR6 T6CON T6HLT T6CLKCON T6RST Core Registers (Table 3-2) 48Bh 48Ch 48Dh 48Eh 48Fh 490h 491h 492h 493h 494h 495h 496h 497h 498h 499h 49Ah 49Bh 49Ch 49Dh 49Eh 49Fh 4A0h General Purpose Register 80 Bytes 46Fh 470h Legend: Accesses 70h - 7Fh -- -- -- -- -- -- -- TMR3L TMR3H T3CON T3GCON -- -- -- TMR5L TMR5H T5CON T5GCON -- -- Core Registers (Table 3-2) 50Bh 50Ch 50Dh 50Eh 50Fh 510h 511h 512h 513h 514h 515h 516h 517h 518h 519h 51Ah 51Bh 51Ch 51Dh 51Eh 51Fh 520h General Purpose Register 80 Bytes 4EFh 4F0h 4FFh Accesses 70h - 7Fh BANK 11 580h -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Core Registers (Table 3-2) 58Bh 58Ch 58Dh 58Eh 58Fh 590h 591h 592h 593h 594h 595h 596h 597h 598h 599h 59Ah 59Bh 59Ch 59Dh 59Eh 59Fh 5A0h General Purpose Register 80 Bytes 56Fh 570h 57Fh Accesses 70h - 7Fh = Unimplemented data memory locations, read as `0'. PID1SETL PID1SETH PID1INL PID1INH PID1K1L PID1K1H PID1K2L PID1K2H PID1K3L PID1K3H PID1OUTLL PID1OUTLH PID1OUTHL PID1OUTHH PID1OUTUL PID1Z1L PID1Z1H PID1Z1U -- -- General Purpose Register 80 Bytes 5EFh 5F0h 5FFh BANK 12 600h Accesses 70h - 7Fh BANK 13 680h Core Registers (Table 3-2) 60Bh 60Ch PID1Z2L 60Dh PID1Z2H 60Eh PID1Z2U 60Fh PID1ACCLL 610h PID1ACCLH 611h PID1ACCHL 612h PID1ACCHH 613h PID1ACCUL 614h PID1CON1 615h -- 616h -- 617h PWM3DCL 618h PWM3DCH 619h PWM3CON 61Ah PWM4DCL 61Bh PWM4DCH 61Ch PWM4CON 61Dh -- 61Eh -- 61Fh -- 620h General Purpose Register 32 Bytes 63Fh 640h Unimplemented Read as `0' 66Fh 670h Accesses 70h - 7Fh 67Fh BANK 14 700h Core Registers (Table 3-2) 68Bh 68Ch 68Dh 68Eh 68Fh 690h 691h 692h 693h 694h 695h 696h 697h 698h 699h 69Ah 69Bh 69Ch 69Dh 69Eh 69Fh 6A0h -- -- -- -- -- CWG1DBR CWG1DBF CWG1AS0 CWG1AS1 CWG1OCON0 CWG1CON0 CWG1CON1 -- CWG1CLKCON CWG1ISM -- -- -- -- -- Core Registers (Table 3-2) 70Bh 70Ch 70Dh 70Eh 70Fh 710h 711h 712h 713h 714h 715h 716h 717h 718h 719h 71Ah 71Bh 71Ch 71Dh 71Eh 71Fh 720h Unimplemented Read as `0' 6EFh 6F0h 6FFh Accesses 70h - 7Fh BANK 15 780h -- -- -- -- -- WDTCON0 WDTCON1 WDTPSL WDTPSH WDTTMR -- -- SCANLADRL SCANLADRH SCANHADRL SCANHADRH SCANCON0 SCANTRIG -- -- Core Registers (Table 3-2) 78Bh 78Ch 78Dh 78Eh 78Fh 790h 791h 792h 793h 794h 795h 796h 797h 798h 799h 79Ah 79Bh 79Ch 79Dh 79Eh 79Fh 7A0h Unimplemented Read as `0' 76Fh 770h 77Fh Accesses 70h - 7Fh -- -- -- -- -- CRCDATL CRCDATH CRCACCL CRCACCH CRCSHIFTL CRCSHIFTH CRCXORL CRCXORH CRCCON0 CRCCON1 -- -- -- -- -- Unimplemented Read as `0' 7EFh 7F0h 7FFh Accesses 70h - 7Fh DS40001770A-page 29 PIC16(L)F1615/9 47Fh BANK 10 500h PIC16(L)F1615/9 MEMORY MAP, BANK 16-23 BANK 16 800h BANK 17 880h Core Registers (Table 3-2 ) Preliminary 80Bh 80Ch 80Dh 80Eh 80Fh 810h 811h 812h 813h 814h 815h 816h 817h 818h 819h 81Ah 81Bh 81Ch 81Dh 86Fh 870h 87Fh Legend: AT1RESL AT1RESH AT1MISSL AT1MISSH AT1PERL AT1PERH AT1PHSL AT1PHSH AT1CON0 AT1CON1 AT1IR0 AT1IE0 AT1IR1 AT1IE1 AT1STPTL AT1STPTH AT1ERRL AT1ERRH Accesses 70h - 7Fh BANK 18 900h Core Registers (Table 3-2) 88Bh 88Ch 88Dh 88Eh 88Fh 890h 891h 892h 893h 894h 895h 896h 897h 898h 899h 89Ah 8EFh 8F0h 8FFh AT1CLK AT1SIG AT1CSEL1 AT1CC1L AT1CC1H AT1CCON1 AT1CSEL2 AT1CC2L AT1CC2H AT1CCON2 AT1CSEL2 AT1CC3L AT1CC3H AT1CCON3 Accesses 70h - 7Fh BANK 19 980h Core Registers (Table 3-2) 90Bh 90Ch Core Registers (Table 3-2) 98Bh 98Ch Unimplemented Read as `0' 96Fh 970h 97Fh Accesses 70h - 7Fh = Unimplemented data memory locations, read as `0'. BANK 20 A00h Core Registers (Table 3-2) A0Bh A0Ch Unimplemented Read as `0' 9EFh 9F0h 9FFh Accesses 70h - 7Fh BANK 21 A80h Core Registers (Table 3-2) A8Bh A8Ch Unimplemented Read as `0' A6Fh A70h A7Fh Accesses 70h - 7Fh BANK 22 B00h Core Registers (Table 3-2) B0Bh B0Ch Unimplemented Read as `0' AEFh AF0h AFFh Accesses 70h - 7Fh BANK 23 B80h Core Registers (Table 3-2) B8Bh B8Ch Unimplemented Read as `0' B6Fh B70h B7Fh Accesses 70h - 7Fh Unimplemented Read as `0' BEFh BF0h BFFh Accesses 70h - 7Fh PIC16(L)F1615/9 DS40001770A-page 30 TABLE 3-6: 2014 Microchip Technology Inc. 2014 Microchip Technology Inc. TABLE 3-7: PIC16(L)F1615/9 MEMORY MAP, BANK 24-31 BANK 24 C00h BANK 25 C80h Core Registers (Table 3-2) Preliminary C0Bh C0Ch C0Dh C0Eh C0Fh C10h C11h C12h C13h C14h C15h C16h C17h C18h C19h C1Ah C1Bh C1Ch C1Dh C1Eh C1Fh C20h -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Core Registers (Table 3-2) C8Bh C8Ch C8Dh C8Eh C8Fh C90h C91h C92h C93h C94h C95h C96h C97h C98h C99h C9Ah C9Bh C9Ch C9Dh C9Eh C9Fh CA0h Unimplemented Read as `0' CFFh Core Registers (Table 3-2) D0Bh D0Ch D0Dh D0Eh D0Fh D10h D11h D12h D13h D14h D15h D16h D17h D18h D19h D1Ah D1Bh D1Ch D1Dh D1Eh D1Fh D20h Unimplemented Read as `0' CEFh CF0h Accesses 70h - 7Fh Legend: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BANK 28 E00h Core Registers (Table 3-2) BANK 29 E80h Core Registers (Table 3-2) BANK 30 F00h Core Registers (Table 3-2) D8Bh D8Ch D8Dh D8Eh D8Fh D90h D91h D92h D93h D94h D95h D96h D97h See Table 3-9 for D98h register mapping D99h details D9Ah D9Bh D9Ch D9Dh D9Eh D9Fh DA0h E0Bh E0Ch E0Dh E0Eh E0Fh E10h E11h E12h E13h E14h E15h E16h E17h See Table 3-10 E18h for register mapE19h ping details E1Ah E1Bh E1Ch E1Dh E1Eh E1Fh E20h E8Bh E8Ch E8Dh E8Eh E8Fh E90h E91h E92h E93h E94h E95h E96h E97h E98h E99h E9Ah E9Bh E9Ch E9Dh E9Eh E9Fh EA0h DEFh DF0h E6Fh E70h EEFh EF0h See Table 3-11 and Table 3-12 for register mapping details BANK 31 F80h Core Registers (Table 3-2) Core Registers (Table 3-2) F0Bh F0Ch F0Dh F0Eh F0Fh F10h F11h F12h F13h F14h F15h F16h F17h See Table 3-13 F18h for register mapF19h ping details F1Ah F1Bh F1Ch F1Dh F1Eh F1Fh F20h F8Bh F8Ch F8Dh F8Eh F8Fh F90h F91h F92h F93h F94h F95h F96h F97h See Table 3-14 F98h for register mapF99h ping details F9Ah F9Bh F9Ch F9Dh F9Eh F9Fh FA0h F6Fh F70h FEFh FF0h Unimplemented Read as `0' D6Fh D70h Accesses 70h - 7Fh CFFh BANK 27 D80h Accesses 70h - 7Fh D7Fh = Unimplemented data memory locations, read as `0'. Accesses 70h - 7Fh DFFh Accesses 70h - 7Fh E7Fh Accesses 70h - 7Fh EFFh Accesses 70h - 7Fh F7Fh Accesses 70h - 7Fh FFFh DS40001770A-page 31 PIC16(L)F1615/9 C6Fh C70h BANK 26 D00h PIC16(L)F1615/9 MEMORY MAP, BANK 24-31 BANK 24 C00h BANK 25 C80h Core Registers (Table 3-2) Preliminary C0Bh C0Ch C0Dh C0Eh C0Fh C10h C11h C12h C13h C14h C15h C16h C17h C18h C19h C1Ah C1Bh C1Ch C1Dh C1Eh C1Fh C20h -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Core Registers (Table 3-2) C8Bh C8Ch C8Dh C8Eh C8Fh C90h C91h C92h C93h C94h C95h C96h C97h C98h C99h C9Ah C9Bh C9Ch C9Dh C9Eh C9Fh CA0h Unimplemented Read as `0' C6Fh C70h 2014 Microchip Technology Inc. Legend: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CEFh CF0h D0Bh D0Ch D0Dh D0Eh D0Fh D10h D11h D12h D13h D14h D15h D16h D17h D18h D19h D1Ah D1Bh D1Ch D1Dh D1Eh D1Fh D20h -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BANK 28 E00h Core Registers (Table 3-2) D8Bh D8Ch D8Dh D8Eh D8Fh D90h D91h D92h D93h D94h D95h D96h D97h See Table 3-9 for D98h register mapping D99h details D9Ah D9Bh D9Ch D9Dh D9Eh D9Fh DA0h D6Fh D70h E0Bh E0Ch E0Dh E0Eh E0Fh E10h E11h E12h E13h E14h E15h E16h E17h E18h E19h E1Ah E1Bh E1Ch E1Dh E1Eh E1Fh E20h Accesses 70h - 7Fh = Unimplemented data memory locations, read as `0'. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- E6Fh E70h Accesses 70h - 7Fh DFFh E8Bh E8Ch E8Dh E8Eh E8Fh E90h E91h E92h E93h E94h E95h E96h E97h E98h E99h E9Ah E9Bh E9Ch E9Dh E9Eh E9Fh EA0h -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- EEFh EF0h F0Bh F0Ch F0Dh F0Eh F0Fh F10h F11h F12h F13h F14h F15h F16h F17h F18h F19h F1Ah F1Bh F1Ch F1Dh F1Eh F1Fh F20h -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Core Registers (Table 3-2) F8Bh F8Ch F8Dh F8Eh F8Fh F90h F91h F92h F93h F94h F95h F96h F97h See Table 3-14 F98h for register mapF99h ping details F9Ah F9Bh F9Ch F9Dh F9Eh F9Fh FA0h Unimplemented Read as `0' F6Fh F70h Accesses 70h - 7Fh EFFh BANK 31 F80h Core Registers (Table 3-2) Unimplemented Read as `0' Accesses 70h - 7Fh E7Fh BANK 30 F00h Core Registers (Table 3-2) Unimplemented Read as `0' DEFh DF0h D7Fh BANK 29 E80h Core Registers (Table 3-2) Unimplemented Read as `0' Accesses 70h - 7Fh CFFh BANK 27 D80h Core Registers (Table 3-2) Unimplemented Read as `0' Accesses 70h - 7Fh CFFh BANK 26 D00h FEFh FF0h Accesses 70h - 7Fh F7Fh Accesses 70h - 7Fh FFFh PIC16(L)F1615/9 DS40001770A-page 32 TABLE 3-8: PIC16(L)F1615/9 TABLE 3-9: PIC16(L)F1615/9 MEMORY MAP, BANK 27 TABLE 3-10: PIC16(L)F1615/9 MEMORY MAP, BANK 28 Bank 27 D8Ch D8Dh D8Eh D8Fh D90h D91h D92h D93h D94h D95h D96h D97h D98h D99h D9Ah D9Bh D9Ch D9Dh D9Eh D9Fh DA0h DA1h DA2h DA3h DA4h DA5h DA6h DA7h DA8h DA9h DAAh DABh DACh DADh DAEh DAFh DB0h Bank 28 SMT1TMRL SMT1TMRH SMT1TMRU SMT1CPRL SMT1CPRH SMT1CPRU SMT1CPWL SMT1CPWH SMT1CPWU SMT1PRL SMT1PRH SMT1PRU SMT1CON0 SMT1CON1 SMT1STAT SMT1CLK SMT1SIG SMT1WIN SMT2TMRL SMT2TMRH SMT2TMRU SMT2CPRL SMT2CPRH SMT2CPRU SMT2CPWL SMT2CPWH SMT2CPWU SMT2PRL SMT2PRH SMT2PRU SMT2CON0 SMT2CON1 SMT2STAT SMT2CLK SMT2SIG SMT2WIN -- DEFh E0Ch E0Dh E0Eh ------- E0Fh PPSLOCK E10h INTPPS E11h T0CKIPPS E12h T1CKIPPS E13h T1GPPS E14h CCP1PPS E15h CCP2PPS E16h ATINPPS E17h CWGINPPS E18h T2PPS E19h E1Ah T3CKIPPS T3GPPS E1Bh T4PPS E1Ch T5CKIPPS E1Dh T5GPPS E1Eh T6PPS E1Fh ATCC1PPS E20h SSPCLKPPS E21h SSPDATPPS E22h SSPSSPPS E23h ATCC2PPS E24h RXPPS E25h CKPPS E26h SMT1SIGPPS E27h SMT1WINPPS E28h CLCIN0PPS E29h E2Ah CLCIN2PPS CLCIN1PPS E2Bh CLCIN3PPS E2Ch SMT2SIGPPS E2Dh SMT2WINPPS E2Eh E2Fh ATCC3PPS -- E6Fh Legend: = Unimplemented data memory locations, read as `0'. Legend: 2014 Microchip Technology Inc. Preliminary = Unimplemented data memory locations, read as `0'. DS40001770A-page 33 PIC16(L)F1615/9 TABLE 3-11: PIC16(L)F1615 MEMORY MAP, BANK 29 TABLE 3-12: PIC16(L)F1619 MEMORY MAP, BANK 29 Bank 29 Bank 29 E8Ch E8Dh E8Eh E8Fh --------- E8Ch E8Dh E8Eh E8Fh --------- E90h RA0PPS E90h RA0PPS E91h RA1PPS E91h RA1PPS E92h RA2PPS E92h RA2PPS E93h -- E93h -- E94h RA4PPS E94h RA4PPS E95h E96h E97h E98h E99h E9Ah E9Bh E9Ch E9Dh E9Eh E9Fh RA5PPS --------------------- E95h E96h E97h E98h E99h E9Ah E9Bh RA5PPS ------------- E9Ch RB4PPS E9Dh RB5PPS E9Eh RB6PPS EA0h E9Fh RC0PPS RB7PPS EA1h EA0h RC1PPS RC0PPS EA2h EA1h RC2PPS RC1PPS EA3h EA2h RC3PPS RC2PPS EA4h EA3h RC4PPS RC3PPS EA5h EA6h EA4h RC5PPS RC4PPS EA5h RC5PPS EA6h RC6PPS EA7h EA8h RC7PPS -- EEFh -- EEFh Legend: = Unimplemented data memory locations, read as `0'. Legend: DS40001770A-page 34 Preliminary = Unimplemented data memory locations, read as `0'. 2014 Microchip Technology Inc. PIC16(L)F1615/9 TABLE 3-13: PIC16(L)F1615/9 MEMORY MAP, BANK 30 TABLE 3-14: PIC16(L)F1615/9 MEMORY MAP, BANK 31 Bank 31 Bank 30 F0Ch --- F0Dh --- F0Eh --- F0Fh CLCDATA F10h CLC1CON F11h CLC1POL F12h CLC1SEL0 F13h CLC1SEL1 F14h CLC1SEL2 F15h CLC1SEL3 F16h CLC1GLS0 F17h CLC1GLS1 F18h CLC1GLS2 F19h CLC1GLS3 F1Ah CLC2CON F1Bh CLC2POL F1Ch CLC2SEL0 F1Dh CLC2SEL1 F1Eh CLC2SEL2 F1Fh CLC2SEL3 F20h CLC2GLS0 F21h CLC2GLS1 F22h CLC2GLS2 F23h F24h F25h F26h F27h F28h F29h F2Ah F2Bh F2Ch F2Dh F2Eh F2Fh F30h F31h F32h F33h F34h F35h F36h F37h F38h CLC2GLS3 CLC3CON CLC3POL CLC3SEL0 CLC3SEL1 CLC3SEL2 CLC3SEL3 CLC3GLS0 CLC3GLS1 CLC3GLS2 CLC3GLS3 CLC4CON CLC4POL CLC4SEL0 CLC4SEL1 CLC4SEL2 CLC4SEL3 CLC4GLS0 CLC4GLS1 CLC4GLS2 CLC4GLS3 F8Ch Unimplemented Read as `0' FE3h FE4h FE5h FE6h FE7h FE8h FE9h FEAh FEBh FECh FEDh FEEh FEFh Legend: STATUS_SHAD WREG_SHAD BSR_SHAD PCLATH_SHAD FSR0L_SHAD FSR0H_SHAD FSR1L_SHAD FSR1H_SHAD -- STKPTR TOSL TOSH = Unimplemented data memory locations, read as `0'. -- F6Fh Legend: = Unimplemented data memory locations, read as `0'. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 35 PIC16(L)F1615/9 3.2.6 CORE FUNCTION REGISTERS SUMMARY The Core Function registers listed in Table 3-15 can be addressed from any Bank. TABLE 3-15: Addr Name CORE FUNCTION REGISTERS SUMMARY Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 0-31 x00h or INDF0 x80h Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx uuuu uuuu x01h or INDF1 x81h Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx uuuu uuuu x02h or PCL x82h Program Counter (PC) Least Significant Byte 0000 0000 0000 0000 ---1 1000 ---q quuu x03h or STATUS x83h -- -- -- TO PD Z DC C x04h or FSR0L x84h Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu x05h or FSR0H x85h Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 x06h or FSR1L x86h Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu x07h or FSR1H x87h Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000 ---0 0000 ---0 0000 0000 0000 uuuu uuuu -000 0000 -000 0000 0000 0000 0000 0000 x08h or BSR x88h -- x09h or WREG x89h -- BSR<4:0> Working Register x0Ah or PCLATH x8Ah -- x0Bh or INTCON x8Bh GIE Legend: -- Write Buffer for the upper 7 bits of the Program Counter PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', r = reserved. Shaded locations are unimplemented, read as `0'. DS40001770A-page 36 Preliminary 2014 Microchip Technology Inc. 2014 Microchip Technology Inc. TABLE 3-16: Addr SPECIAL FUNCTION REGISTER SUMMARY Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets -- -- RA5 RA4 RA3 RA2 RA1 RA0 --xx xxxx --xx xxxx Bank 0 00Ch PORTA (4) 00Dh PORTB 00Eh PORTC RB7 RB6 RB5 RB4 -- -- -- -- xxxx ---- xxxx ---- RC7(4) RC6(4) RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx xxxx xxxx -- -- RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 Preliminary -- PIR1 TMR1GIF ADIF 011h PIR2 OSFIF C2IF C1IF -- BCL1IF TMR6IF TMR4IF CCP2IF -00- 0000 -00- 0000 012h PIR3 -- -- CWGIF ZCDIF CLC4IF CLC3IF CLC2IF CLC1IF --00 0000 --00 0000 013h PIR4 SCANIF CRCIF SMT2PWAIF SMT2PRAIF SMT2IF SMT1PWAIF SMT1PRAIF SMT1IF 0000 0000 0000 0000 014h PIR5 TMR3GIF TMR3IF TMR5GIF TMR5IF -- AT1IF PID1EIF PID1DIF 0000 -000 0000 -000 015h TMR0 Holding Register for the 8-bit Timer0 Count xxxx xxxx uuuu uuuu 016h TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Count xxxx xxxx uuuu uuuu 017h TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Count xxxx xxxx uuuu uuuu 018h T1CON 0000 -0-0 uuuu -u-u 019h T1GCON 0000 0x00 uuuu uxuu 01Ah TMR2 Timer2 Module Register 0000 0000 0000 0000 01Bh PR2 Timer2 Period Register 1111 1111 1111 1111 01Ch T2CON ON 0000 0000 0000 0000 01Dh T2HLT PSYNC CKPOL CKSYNC 01Eh T2CLKCON -- -- -- -- 01Fh T2RST -- -- -- -- Unimplemented TMR1CS<1:0> TMR1GE T1GPOL T1CKPS<1:0> T1GTM T1GSPM CKPS<2:0> -- T1SYNC T1GGO/ DONE T1GVAL OUTPS<3:0> MODE<4:0> -- TMR1ON T1GSS<1:0> 0000 0000 0000 0000 CS<3:0> ---- 0000 ---- 0000 RSEL<3:0> ---- 0000 ---- 0000 Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. Note 1: PIC16F1615/9 only. 2: Unimplemented, read as `1'. 3: PIC16(L)F1615 only. 4: PIC16(L)F1619 only. DS40001770A-page 37 PIC16(L)F1615/9 00Fh 010h Addr SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets -- -- TRISA5 TRISA4 --(2) TRISA2 TRISA1 TRISA0 --11 1111 --11 1111 TRISB7 TRISB6 TRISB5 TRISB4 -- -- -- -- 1111 ---- 1111 ---- TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 Bank 1 08Ch TRISA 08Dh TRISB(4) TRISC7 (4) TRISC6 (4) 08Eh TRISC 1111 1111 1111 1111 08Fh -- Unimplemented -- -- 090h -- Unimplemented -- -- 090h PIE1 TMR1GIE ADIE 091h PIE2 OSFIE C2IE C1IE 092h PIE3 -- -- CWGIE 093h PIE4 SCANIE CRCIE SMT2PWAIE 094h PIE5 TMR3GIE TMR3IE RCIE TXIE Preliminary SSP1IE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 -- BCL1IE TMR6IE TMR4IE CCP2IE -00- 0000 -00- 0000 ZCDIE CLC4IE CLC3IE CLC2IE CLC1IE --00 0000 --00 0000 SMT2PRAIE SMT2IE SMT1PWAIE SMT1PRAIE SMT1IE 0000 0000 0000 0000 TMR5GIE TMR5IE -- AT1IE PID1EIE PID1DIE 0000 -000 0000 -000 1111 1111 1111 1111 BOR 00-1 11qq qq-q qquu 095h OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA 096h PCON STKOVF STKUNF WDTWV RWDT RMCLR 097h -- 098h OSCTUNE PS<2:0> RI POR Unimplemented -- -- TUN<5:0> -- SCS<1:0> -- --00 0000 0011 1-00 0011 1-00 -000 0000 -qqq qqqq 099h OSCCON SPLLEN 09Ah OSCSTAT -- 09Bh ADRESL ADC Result Register Low xxxx xxxx uuuu uuuu 09Ch ADRESH ADC Result Register High xxxx xxxx uuuu uuuu -000 0000 -000 0000 0000 --00 0000 --00 0000 0--- 0000 0--- 09Dh ADCON0 -- 09Eh ADCON1 ADFM 09Fh ADCON2 IRCF<3:0> -- --00 0000 PLLR OSTS HFIOFR HFIOFL MFIOFR CHS<4:0> ADCS<2:0> TRIGSEL<4:0> LFIOFR GO/DONE -- -- -- HFIOFS ADON ADPREF<1:0> -- -- 2014 Microchip Technology Inc. Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. Note 1: PIC16F1615/9 only. 2: Unimplemented, read as `1'. 3: PIC16(L)F1615 only. 4: PIC16(L)F1619 only. PIC16(L)F1615/9 DS40001770A-page 38 TABLE 3-16: 2014 Microchip Technology Inc. TABLE 3-16: Addr SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets --uu uuuu Bank 2 -- -- LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 --xx xxxx LATB7 LATB6 LATB5 LATB4 -- -- -- -- xxxx ---- uuuu ---- LATC7(4) LATC6(4) LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 xxxx xxxx uuuu uuuu -- -- 10Ch LATA 10Dh LATB(4) 10Eh LATC 10Fh -- Unimplemented 110h -- Unimplemented 111h CM1CON0 C1ON C1OUT 112h CM1CON1 C1INTP C1INTN 113h CM2CON0(4) C2ON C2OUT 114h (4) CM2CON1 C2INTP C2INTN 115h CMOUT -- -- -- C1POL C2POL C2PCH<1:0> -- C1SP -- C1PCH<1:0> -- -- -- C1HYS C1SYNC C1NCH<2:0> C2SP -- C2HYS -- -- 00-0 -100 00-0 -100 0000 -000 0000 -000 C2SYNC 00-0 -100 00-0 -100 C2NCH<2:0> Preliminary 0000 -000 0000 -000 -- -- -- MC2OUT MC1OUT ---- --00 ---- --00 -- -- -- BORRDY 10-- ---q uu-- ---u 0q00 0000 0q00 0000 116h BORCON SBOREN BORFS -- -- 117h FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> 118h DAC1CON0 DAC1EN -- DAC1OE1 -- DAC1PSS<1:0> 119h DAC1CON1 ADFVR<1:0> -- -- DAC1R<7:0> 0-0- 00-- 0-0- 00-- 0000 0000 0000 0000 11Ah -- Unimplemented -- -- 11Bh -- Unimplemented -- -- 11Ch ZCD1CON 0-00 --00 0-00 --00 11Dh -- Unimplemented -- -- 11Eh -- Unimplemented -- -- 11Fh -- Unimplemented -- -- ZCD1EN -- ZCD1OUT ZCD1POL -- -- ZCD1INTP ZCD1INTN DS40001770A-page 39 PIC16(L)F1615/9 Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. Note 1: PIC16F1615/9 only. 2: Unimplemented, read as `1'. 3: PIC16(L)F1615 only. 4: PIC16(L)F1619 only. Addr SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 3 Preliminary 18Ch ANSELA -- -- -- ANSA4 -- ANSA2 ANSA1 ANSA0 ---1 -111 ---1 -111 18Dh ANSELB(4) -- -- ANSB5 ANSB4 -- -- -- -- --11 ---- --11 ---- 18Eh ANSELC ANSC7(4) ANSC6(4) -- -- ANSC3 ANSC2 ANSC1 ANSC0 11-- 1111 11-- 1111 18Fh -- Unimplemented -- -- 190h -- Unimplemented -- -- 191h PMADRL Flash Program Memory Address Register Low Byte 0000 0000 0000 0000 192h PMADRH 1000 0000 1000 0000 193h PMDATL xxxx xxxx uuuu uuuu 194h PMDATH -- -- 195h PMCON1 --(2) CFGS 196h PMCON2 197h VREGCON(1) 198h -- Unimplemented 199h RC1REG 19Ah 19Bh --(2) Flash Program Memory Address Register High Byte Flash Program Memory Read Data Register Low Byte Flash Program Memory Read Data Register High Byte LWLO FREE WRERR WREN WR RD -- -- -- VREGPM Reserved Flash Program Memory Control Register 2 -- -- -- --xx xxxx --uu uuuu 1000 x000 1000 q000 0000 0000 0000 0000 ---- --01 ---- --01 -- -- EUSART Receive Data Register 0000 0000 0000 0000 TX1REG EUSART Transmit Data Register 0000 0000 0000 0000 SP1BRGL Baud Rate Generator Data Register Low 0000 0000 0000 0000 19Ch SP1BRGH Baud Rate Generator Data Register High 0000 0000 0000 0000 19Dh RC1STA RX9D 0000 000x 0000 000x 19Eh TX1STA 19Fh BAUD1CON SPEN RX9 SREN CREN ADDEN FERR OERR CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010 ABDOVF RCIDL -- SCKP BRG16 -- WUE ABDEN 01-0 0-00 01-0 0-00 2014 Microchip Technology Inc. Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. Note 1: PIC16F1615/9 only. 2: Unimplemented, read as `1'. 3: PIC16(L)F1615 only. 4: PIC16(L)F1619 only. PIC16(L)F1615/9 DS40001770A-page 40 TABLE 3-16: 2014 Microchip Technology Inc. TABLE 3-16: Addr SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 4 -- -- WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 --11 1111 --11 1111 WPUB7 WPUB6 WPUB5 WPUB4 -- -- -- -- 1111 ---- 1111 ---- WPUC7(4) WPUC6(4) WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 1111 1111 111 1111 -- -- Preliminary 20Ch WPUA 20Dh WPUB(4) 20Eh WPUC 20Fh -- Unimplemented 210h -- Unimplemented 211h SSP1BUF 212h 213h 214h SSP1STAT SMP 215h SSP1CON1 WCOL SSPOV SSPEN CKP 216h SSP1CON2 GCEN ACKSTAT ACKDT 217h SSP1CON3 ACKTIM PCIE SCIE 218h to 21Fh -- -- Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx xxxx xxxx SSP1ADD ADD<7:0> 0000 0000 0000 0000 SSP1MSK MSK<7:0> 1111 1111 1111 1111 0000 0000 0000 0000 -- CKE D/A P S R/W UA BF ACKEN RCEN 0000 0000 0000 0000 PEN RSEN SEN 0000 0000 BOEN SDAHT 0000 0000 SBCDE AHEN DHEN 0000 0000 0000 0000 -- -- SSPM<3:0> Unimplemented Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. Note 1: PIC16F1615/9 only. 2: Unimplemented, read as `1'. 3: PIC16(L)F1615 only. 4: PIC16(L)F1619 only. PIC16(L)F1615/9 DS40001770A-page 41 Addr SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 5 -- -- ODA5 ODA4 -- ODA2 ODA1 ODA0 --00 -000 --00 -000 ODB7 ODB6 ODB5 ODB4 -- -- -- -- 0000 ---- 0000 ---- ODC7(4) ODC6(4) ODC5 ODC4 ODC3 ODC2 ODC1 ODC0 0000 0000 0000 0000 -- -- 28Ch ODCONA 28Dh ODCONB(4) 28Eh ODCONC 28Fh -- Unimplemented 290h -- Unimplemented -- -- 291h CCP1RL Capture/Compare/PWM 1 Register (LSB) xxxx xxxx uuuu uuuu 292h CCP1RH Capture/Compare/PWM 1 Register (MSB) xxxx xxxx uuuu uuuu 293h CCP1CON EN OE OUT FMT 0000 0000 0000 0000 294h CCP1CAP -- -- -- -- ---- -000 ---- -000 -- -- 295h -- 297h -- MODE<3:0> -- CTS<2:0> Unimplemented Preliminary 298h CCP2RL Capture/Compare/PWM 2 Register (LSB) xxxx xxxx uuuu uuuu 299h CCP2RH Capture/Compare/PWM 2 Register (MSB) xxxx xxxx uuuu uuuu 29Ah CCP2CON EN OE OUT FMT 0000 0000 0000 0000 29Bh CCP2CAP -- -- -- -- ---- -000 ---- -000 -- MODE<3:0> -- CTS<2:0> 29Ch -- Unimplemented -- 29Dh -- Unimplemented -- -- 29Eh CCPTMRS 0000 0000 0000 0000 29Fh -- -- -- P4TSEL<1:0> P3TSEL<1:0> C2TSEL<1:0> C1TSEL<1:0> Unimplemented Bank 6 2014 Microchip Technology Inc. 30Ch SLRCONA 30Dh SLRCONB(4) 30Eh SLRCONC 30Fh -- 31Fh -- -- -- SLRA5 SLRA4 -- SLRA2 SLRA1 SLRA0 --11 -111 --11 -111 SLRB7 SLRB6 SLRB5 SLRB4 -- -- -- -- 1111 ---- 1111 ---- SLRC7(4) SLRC6(4) SLRC5 SLRC4 SLRC3 SLRC2 SLRC1 SLRC0 1111 1111 1111 1111 -- -- Unimplemented Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. Note 1: PIC16F1615/9 only. 2: Unimplemented, read as `1'. 3: PIC16(L)F1615 only. 4: PIC16(L)F1619 only. PIC16(L)F1615/9 DS40001770A-page 42 TABLE 3-16: 2014 Microchip Technology Inc. TABLE 3-16: Addr SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets --11 1111 Bank 7 -- -- INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 --11 1111 INLVLB7 INLVLB6 INLVLB5 INLVLB4 -- -- -- -- 1111 ---- 1111 ---- INLVLC7(4) INLVLC6(4) INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 1111 1111 1111 1111 -- -- 38Ch INLVLA 38Dh INLVLB(4) 38Eh INLVLC 30Fh -- Unimplemented 390h -- Unimplemented -- -- 391h IOCAP -- -- IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 --00 0000 --00 0000 392h IOCAN -- -- IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 --00 0000 --00 0000 393h IOCAF -- -- IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 --00 0000 --00 0000 Preliminary 394h IOCBP (4) IOCBP7 IOCBP6 IOCBP5 IOCBP4 -- -- -- -- 0000 ---- 0000 ---- 395h IOCBN(4) IOCBN7 IOCBN6 IOCBN5 IOCBN4 -- -- -- -- 0000 ---- 0000 ---- 396h IOCBF(4) IOCBF7 IOCBF6 IOCBF5 IOCBF4 -- -- -- -- 0000 ---- 0000 ---- 397h IOCCP IOCCP7(4) IOCCP6(4) IOCCP5 IOCCP4 IOCCP3 IOCCP2 IOCCP1 IOCCP0 0000 0000 0000 0000 398h IOCCN IOCCN7(4) IOCCN6(4) IOCCN5 IOCCN4 IOCCN3 IOCCN2 IOCCN1 IOCCN0 0000 0000 0000 0000 IOCCF (4) IOCCF6(4) IOCCF5 IOCCF4 IOCCF3 IOCCF2 IOCCF1 IOCCF0 0000 0000 0000 0000 -- -- 399h 39Ah to 39Fh -- IOCCF7 Unimplemented DS40001770A-page 43 PIC16(L)F1615/9 Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. Note 1: PIC16F1615/9 only. 2: Unimplemented, read as `1'. 3: PIC16(L)F1615 only. 4: PIC16(L)F1619 only. Addr SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 8 40Ch -- Unimplemented -- -- 40Dh -- Unimplemented -- -- 40Eh HIDRVC --00 ---- --00 ---- -- -- 40Fh to 412h -- -- HIDC5 HIDC4 -- -- -- -- Preliminary -- Unimplemented 413h TMR4 Timer4 Module Register 0000 0000 0000 0000 414h PR4 Timer4 Period Register 1111 1111 1111 1111 415h T4CON ON 0000 0000 0000 0000 416h T4HLT PSYNC CKPOL CKSYNC 0000 0000 0000 0000 417h T4CLKCON -- -- -- -- CS<3:0> ---- 0000 ---- 0000 418h T4RST -- -- -- -- RSEL<3:0> ---- 0000 ---- 0000 419h -- Unimplemented 41Ah TMR6 Timer6 Module Register 41Bh PR6 Timer6 Period Register 41Ch T6CON ON 41Dh T6HLT PSYNC CKPOL CKSYNC 41Eh T6CLKCON -- -- -- -- CS<3:0> 41Fh T6RST -- -- -- -- RSEL<3:0> CKPS<2:0> OUTPS<3:0> MODE<4:0> CKPS<2:0> OUTPS<3:0> MODE<4:0> -- -- 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 ---- 0000 ---- 0000 ---- 0000 ---- 0000 Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. Note 1: PIC16F1615/9 only. 2: Unimplemented, read as `1'. 3: PIC16(L)F1615 only. 4: PIC16(L)F1619 only. PIC16(L)F1615/9 DS40001770A-page 44 TABLE 3-16: 2014 Microchip Technology Inc. 2014 Microchip Technology Inc. TABLE 3-16: Addr SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets -- -- Bank 9 48Ch to 492h -- Unimplemented 493h TMR3L Timer3 Module Register xxxx xxxx xxxx xxxx 494h TMR3H Timer3 Module Register xxxx xxxx xxxx xxxx 495h T3CON xxxx -x-x xxxx -x-x 496h T3GCON xxxx xxxx xxxx xxxx -- -- 497h to 499h -- TMR3CS<1:0> TMR3GE T3GPOL T3CKPS<1:0> T3GTM T3GSPM -- T3SYNC T3GGO/ DONE T3GVAL -- TMR3CON T3GSS<1:0> Unimplemented Preliminary 49Ah TMR5L Timer5 Module Register xxxx xxxx xxxx xxxx 49Bh TMR5H Timer5 Module Register xxxx xxxx xxxx xxxx 49Ch T5CON xxxx -x-x xxxx -x-x 49Dh T5GCON xxxx xxxx xxxx xxxx 49Eh -- Unimplemented -- -- 49Fh -- Unimplemented -- -- Unimplemented -- -- TMR5CS<1:0> TMR5GE T5GPOL T5CKPS<1:0> T5GTM T5GSPM -- T5SYNC T5GGO/ DONE T5GVAL -- TMR5CON T5GSS<1:0> Bank 10 50Ch to 51Fh -- DS40001770A-page 45 PIC16(L)F1615/9 Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. Note 1: PIC16F1615/9 only. 2: Unimplemented, read as `1'. 3: PIC16(L)F1615 only. 4: PIC16(L)F1619 only. Addr SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 11 Preliminary 58Ch P1D1INL IN<7:0> xxxx xxxx xxxx xxxx 58Dh P1D1INH IN<15:8> xxxx xxxx xxxx xxxx 58Eh P1D1SETL SET<7:0> 0000 0000 0000 0000 58Fh P1D1SETH SET<15:8> 0000 0000 0000 0000 590h P1D1K1L K1<7:0> xxxx xxxx xxxx xxxx 591h P1D1K1H K1<15:8> xxxx xxxx xxxx xxxx 592h P1D1K2L K2<7:0> xxxx xxxx xxxx xxxx 593h P1D1K2H K2<15:8> xxxx xxxx xxxx xxxx 594h P1D1K3L K3<7:0> xxxx xxxx xxxx xxxx 595h P1D1K3H K3<15:8> xxxx xxxx xxxx xxxx 596h P1D1OUTLL OUT<7:0> 0000 0000 0000 0000 597h P1D1OUTLH OUT<15:8> 0000 0000 0000 0000 598h P1D1OUTHL OUT<23:16> 0000 0000 0000 0000 599h P1D1OUTHH OUT<31:24> 0000 0000 0000 0000 59Ah P1D1OUTU ---- 0000 ---- 0000 -- -- -- -- OUT<35:32> 59Bh P1D1Z1L Z1<7:0> 0000 0000 0000 0000 59Ch P1D1Z1H Z1<15:8> 0000 0000 0000 0000 59Dh P1D1Z1U ---- ---0 ---- ---0 59Eh -- Unimplemented -- -- 59Fh -- Unimplemented -- -- -- -- -- -- -- -- -- Z116 2014 Microchip Technology Inc. Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. Note 1: PIC16F1615/9 only. 2: Unimplemented, read as `1'. 3: PIC16(L)F1615 only. 4: PIC16(L)F1619 only. PIC16(L)F1615/9 DS40001770A-page 46 TABLE 3-16: 2014 Microchip Technology Inc. TABLE 3-16: Addr SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 12 60Ch P1D1Z2L Z2<7:0> 0000 0000 0000 0000 60Dh P1D1Z2H Z2<15:8> 0000 0000 0000 0000 60Eh P1D1Z2U ---- ---0 ---- ---0 60Fh P1D1ACCLL ACC<7:0> 0000 0000 0000 0000 610h P1D1ACCLH ACC<15:8> 0000 0000 0000 0000 611h P1D1ACCHL ACC<23:16> 0000 0000 0000 0000 612h P1D1ACCHH ACC<31:24> 0000 0000 0000 0000 613h P1D1ACCU -- -- -- -- -- -- -- Z216 -- -- -- -- -- ACC<34:32> ---- -000 ---- -000 EN BUSY -- -- -- MODE<2:0> Preliminary 614h P1D1CON1 00-- 0000 00-- 0000 615h -- Unimplemented -- -- 616h -- Unimplemented -- -- 617h PWM3DCL xx-- ---- 618h PWM3DCH 619h PWM3CON 61Ah PWM4DCL 61Bh PWM4DCH 61Ch PWM4CON 61Dh to 61Fh -- DC<1:0> -- -- OUT POL -- -- -- -- -- -- xx-- ---xxxx xxxx xxxx xxxx -- -- -- -- 0-x0 ---- 0-x0 ---- -- -- -- -- xx-- ---- xx-- ---- xxxx xxxx xxxx xxxx 0-x0 ---- 0-x0 ---- -- -- DC<9:2> -- EN DC<1:0> DC<9:2> EN -- OUT POL -- -- -- -- Unimplemented DS40001770A-page 47 PIC16(L)F1615/9 Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. Note 1: PIC16F1615/9 only. 2: Unimplemented, read as `1'. 3: PIC16(L)F1615 only. 4: PIC16(L)F1619 only. Addr SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets -- -- --00 0000 --00 0000 --xx xxxx --xx xxxx Bank 13 68Ch to 690h 691h -- CWG1DBR Unimplemented -- -- DBR<5:0> Preliminary 692h CWG1DBF -- -- 693h CWG1AS0 SHUTDOWN REN 694h CWG1AS1 -- TMR6AS TMR4AS TMR2AS -- C2AS(4) C1AS INAS -000 -000 -000 -000 695h CWG1OCON0 OVRD OVRC OVRB OVRA STRD STRC STRB STRA 0000 0000 0000 0000 696h CWG1CON0 EN LD -- -- -- 00-- -000 00-- -000 697h CWG1CON1 -- -- IN -- POLD POLC POLB POLA --x- 0000 --x- 0000 -- -- -- -- -- CS ---- ---0 ---- --0 ---- 0000 ---- 0000 -- -- DBF<5:0> LSBD<1:0> 698h -- 699h CWG1CLKCON -- -- -- -- 69Ah CWG1ISM -- -- -- -- 69Bh to 6EFh -- -- LSAC<1:0> -- MODE<2:0> 0001 01-- 00001 01-- Unimplemented IS<3:0> Unimplemented Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. Note 1: PIC16F1615/9 only. 2: Unimplemented, read as `1'. 3: PIC16(L)F1615 only. 4: PIC16(L)F1619 only. PIC16(L)F1615/9 DS40001770A-page 48 TABLE 3-16: 2014 Microchip Technology Inc. 2014 Microchip Technology Inc. TABLE 3-16: Addr SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets -- -- --qq qqqq --qq qqqq -qqq -qqq -qqq -qqq 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 Bank 14 70Ch to 710h -- Unimplemented Preliminary 711h WDTCON0 -- 712h WDTCON1 -- 713h WDTPSL 714h WDTPSH 715h WDTTMR 716h -- Unimplemented -- -- 717h -- Unimplemented -- -- 718h SCANLADRL LADR<7:0> 0000 0000 0000 0000 719h SCANLADRH LADR<15:8> 0000 0000 0000 0000 71Ah SCANHADRL HADR<7:0> 1111 1111 1111 1111 71Bh SCANHADRH HADR<15:8> 1111 1111 1111 1111 71Ch SCANCON0 0000 0-00 0000 0-00 71Dh SCANTRIG ---- 0000 ---- 0000 71Eh -- Unimplemented -- -- 71Fh -- Unimplemented -- -- -- WDTPS<4:0> WDTCS<2:0> SEN -- WINDOW<2:0> PSCNT<7:0> PSCNT<15:8> WDTTMR<4:0> EN SCANGO BUSY STATE INVALID INTM -- PSCNT<17:16> MODE<1:0> TSEL<3:0> DS40001770A-page 49 PIC16(L)F1615/9 Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. Note 1: PIC16F1615/9 only. 2: Unimplemented, read as `1'. 3: PIC16(L)F1615 only. 4: PIC16(L)F1619 only. Addr SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets -- -- Banks 15 78Ch to 790h -- Unimplemented Preliminary 791h CRCDATL DAT<7:0> xxxx xxxx xxxx xxxx 792h CRCDATH DAT<15:8> xxxx xxxx xxxx xxxx 793h CRCACCL ACC<7:0> 0000 0000 0000 0000 794h CRCACCH ACC<15:8> 0000 0000 0000 0000 795h CRCSHIFTL SHIFT<7:0> 0000 0000 0000 0000 796h CRCSHIFTH 0000 0000 0000 0000 797h CRCXORL 798h CRCXORH 799h CRCCON0 79Ah CRCCON1 79Bh to 79Fh -- SHIFT<15:8> -- XOR<7:1> XOR<15:8> EN CRCGO BUSY DLEN<3:0> ACCM -- -- SHIFTM PLEN<3:0> FULL xxxx xxx- xxxx xxx- xxxx xxxX xxxx xxxX 0000 --00 0000 -00 0000 0000 0000 0000 -- -- Unimplemented Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. Note 1: PIC16F1615/9 only. 2: Unimplemented, read as `1'. 3: PIC16(L)F1615 only. 4: PIC16(L)F1619 only. PIC16(L)F1615/9 DS40001770A-page 50 TABLE 3-16: 2014 Microchip Technology Inc. 2014 Microchip Technology Inc. TABLE 3-16: Addr SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 -- -- -- -- Bit 3 Bit 2 -- -- Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 16 80Ch AT1RESL 80Dh AT1RESH RES<7:0> RES<9:8> xxxx xxxx xxxx xxxx ---- --xx ---- --xx 80Eh AT1MISSL MISS<7:0> xxxx xxxx xxxx xxxx 80Fh AT1MISSH MISS<15:8> xxxx xxxx xxxx xxxx PER<7:0> xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx ---- --xx ---- --xx Preliminary 810h AT1PERL 811h AT1PERH 812h AT1PHSL 813h AT1PHSH -- -- 814h AT1CON0 EN PREC POL -- APMOD MODE 0x00 --00 0x00 -00 815h AT1CON1 -- PHP -- PRP -- MPP ACCS VALID 0000 0000 0000 0000 816h AT1IR0 -- -- -- -- -- PHSIF MISSIF PERIF ----000 ----000 817h AT1IE0 -- -- -- -- -- PHSIE MISSIE PERIE ----000 ----000 818h AT1IR1 -- -- -- -- -- CC3IF CC2IF CC1IF ----000 ----000 819h AT1IE1 -- -- -- -- -- CC3IE CC2IE CC1IE ----000 ----000 81Ah AT1STPTL xxxx xxxx xxxx xxxx 81Bh AT1STPTH -xxx xxxx -xxx xxxx POV PER<14:8> PHS<7:0> -- -- -- PS<1:0> STPT<7:0> -- STPT<14:8> -- PHS<9:8> 81Ch AT1ERRL ERR<7:0> xxxx xxxx xxxx xxxx 81Dh AT1ERRH ERR<15:8> xxxx xxxx xxxx xxxx 81Eh -- Unimplemented -- -- 81Fh -- Unimplemented -- -- DS40001770A-page 51 PIC16(L)F1615/9 Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. Note 1: PIC16F1615/9 only. 2: Unimplemented, read as `1'. 3: PIC16(L)F1615 only. 4: PIC16(L)F1619 only. Addr SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 -- Bit 1 Bit 0 Value on POR, BOR Value on all other Resets -- CS0 Bank 17 88Ch AT1CLK -- -- -- -- -- ---- ---0 ---- ---0 88Dh AT1SIG -- -- -- -- -- SSEL<2:0> ---- -000 ---- -000 88Eh AT1CSEL1 -- -- -- -- -- CP1S<2:0> ---- -000 ---- -000 88Fh AT1CC1L 890h AT1CC1H 891h CC1<7:0> -- -- -- -- -- -- AT1CCON1 CC1EN -- -- CC1POL CAP1P -- 892h AT1CSEL2 -- -- -- -- -- 893h AT1CC2L 894h AT1CC2H 895h CC1MODE CP2S<2:0> Preliminary -- -- -- -- -- AT1CCON2 CC2EN -- -- CC2POL CAP2P -- 896h AT1CSEL3 -- -- -- -- -- 897h AT1CC1L 898h AT1CC1H 899h AT1CCON1 -- -- CC2<7:0> -- 89Ah to 89Fh CC1<9:8> CC2<9:8> -- CC2MODE CP3S<2:0> CC3<7:0> 0000 0000 0000 0000 ---- -000 ---- -000 0--0 0--0 0--0 0--0 ---- -000 ---- -000 0000 0000 0000 0000 ---- -000 ---- -000 0--0 0--0 0--0 0--0 ---- -000 ---- -000 0000 0000 0000 0000 ---- -000 ---- -000 0--0 0--0 0--0 0--0 Unimplemented -- -- Unimplemented -- -- -- -- -- -- -- -- CC3EN -- -- CC3POL CAP3P -- CC3<9:8> -- CC3MODE Bank 18-26 x0Ch/ x8Ch -- x1Fh/ x9Fh -- 2014 Microchip Technology Inc. Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. Note 1: PIC16F1615/9 only. 2: Unimplemented, read as `1'. 3: PIC16(L)F1615 only. 4: PIC16(L)F1619 only. PIC16(L)F1615/9 DS40001770A-page 52 TABLE 3-16: 2014 Microchip Technology Inc. TABLE 3-16: Addr SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets -- -- Banks 27 D80h to D8Bh -- Unimplemented Preliminary SMT1TMRL SMT1TMR<7:0> 0000 0000 0000 0000 D8Dh SMT1TMRH SMT1TMR<15:8> 0000 0000 0000 0000 D8Eh SMT1TMRU SMT1TMR<23:16> 0000 0000 0000 0000 D8Fh SMT1CPRL SMT1CPR<7:0> xxxx xxxx xxxx xxxx D90h SMT1CPRH SMT1CPR<15:8> xxxx xxxx xxxx xxxx D91h SMT1CPRU SMT1CPR<23:16> xxxx xxxx xxxx xxxx D92h SMT1CPWL SMT1CPW<7:0> xxxx xxxx xxxx xxxx D93h SMT1CPWH SMT1CPW<15:8> xxxx xxxx xxxx xxxx D94h SMT1CPWU SMT1CPW<23:16> xxxx xxxx xxxx xxxx D95h SMT1PRL SMT1PR<7:0> xxxx xxxx xxxx xxxx D96h SMT1PRH SMT1PR<15:8> xxxx xxxx xxxx xxxx D97h SMT1PRU xxxx xxxx xxxx xxxx D98h SMT1CON0 EN -- STP WPOL D99h SMT1CON1 SMT1GO REPEAT -- -- D9Ah SMT1STAT CPRUP CPWUP RST -- -- D9Bh SMT1CLK -- -- -- -- -- D9Ch SMT1SIG -- -- -- D9Dh SMT1WIN -- -- -- D9Eh SMT2TMRL SMT1PR<23:16> SPOL CPOL SMT1PS<1:0> MODE<3:0> TS WS CSEL<2:0> AS 0-00 0000 0-00 0000 00-- 0000 00-- 0000 000- -000 000- -000 ---- -000 ---- -000 SSEL<4:0> ---0 0000 ---0 0000 WSEL<4:0> ---0 0000 ---0 0000 SMT2TMR<7:0> 0000 0000 0000 0000 DS40001770A-page 53 D9Fh SMT2TMRH SMT2TMR<15:8> 0000 0000 0000 0000 DA0h SMT2TMRU SMT2TMR<23:16> 0000 0000 0000 0000 DA1h SMT2CPRL SMT2CPR<7:0> xxxx xxxx xxxx xxxx DA2h SMT2CPRH SMT2CPR<15:8> xxxx xxxx xxxx xxxx DA3h SMT2CPRU SMT2CPR<23:16> xxxx xxxx xxxx xxxx DA4h SMT2CPWL SMT2CPW<7:0> xxxx xxxx xxxx xxxx Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. Note 1: PIC16F1615/9 only. 2: Unimplemented, read as `1'. 3: PIC16(L)F1615 only. 4: PIC16(L)F1619 only. PIC16(L)F1615/9 D8Ch 2014 Microchip Technology Inc. TABLE 3-16: Addr SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 27 (Continued) DA5h SMT2CPWH SMT2CPW<15:8> xxxx xxxx xxxx xxxx DA6h SMT2CPWU SMT2CPW<23:16> xxxx xxxx xxxx xxxx DA7h SMT2PRL SMT2PR<7:0> xxxx xxxx xxxx xxxx DA8h SMT2PRH SMT2PR<15:8> xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx DA9h SMT2PRU DAAh SMT2CON0 EN -- STP WPOL SMT2PR<23:16> DABh SMT2CON1 SMT2GO REPEAT -- -- DACh SMT2STAT CPRUP CPWUP RST -- -- DADh SMT2CLK -- -- -- -- -- ---- -000 ---- -000 DAEh SMT2SIG -- -- -- SSEL<4:0> ---0 0000 ---0 0000 DAFh SMT2WIN -- -- -- WSEL<4:0> ---0 0000 ---0 0000 SPOL CPOL SMT2PS<1:0> MODE<3:0> TS WS CSEL<2:0> AS 0-00 0000 0-00 0000 00-- 0000 00-- 0000 000- -000 000- -000 Preliminary Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. Note 1: PIC16F1615/9 only. 2: Unimplemented, read as `1'. 3: PIC16(L)F1615 only. 4: PIC16(L)F1619 only. PIC16(L)F1615/9 DS40001770A-page 54 Addr SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets -- -- ---- ---0 ---- ---0 Banks 28 E0Ch to E0Eh -- Unimplemented PPSLOCK -- -- -- E10h INTPPS -- -- -- INTPPS<4:0> ---0 0010 ---0 0010 E11h T0CKIPPS -- -- -- T0CKIPPS<4:0> ---0 0010 ---0 0010 E12h T1CKIPPS -- -- -- T1CKIPPS<4:0> ---0 0101 ---0 0101 E13h T1GPPS -- -- -- T1GPPS<4:0> ---0 0100 ---0 0100 E14h CCP1PPS -- -- -- CCP1PPS<4:0> ---1 0101 ---1 0101 E15h CCP2PPS -- -- -- CCP2PPS<4:0> ---1 0011 ---1 0011 E16h ATINPPS -- -- -- ATINPPS<4:0> ---1 0101 ---1 0101 E17h CWGINPPS -- -- -- CWGINPPS<4:0> ---0 0010 ---0 0010 E18h T2PPS -- -- -- T2PPS<4:0> ---0 0101 ---0 0101 E19h T3CKIPPS -- -- -- T3CKIPPS<4:0> ---1 0101 ---1 0101 E1Ah T3GPPS -- -- -- T3GPPS<4:0> ---1 0100 ---1 0100 E1Bh T4PPS -- -- -- T4PPS<4:0> ---1 0001 ---1 0001 E1Ch T5CKIPPS -- -- -- T5CKIPPS<4:0> ---1 0000 ---1 0000 E1Dh T5GPPS -- -- -- T5GPPS<4:0> ---1 0011 ---1 0011 E1Eh T6PPS -- -- -- T6PPS<4:0> ---0 0011 ---0 0011 E1Fh ATCC1PPS -- -- -- ATCC1PPS<4:0> ---1 0011 ---1 0011 E20h SSPCLKPPS (3) -- -- -- SSPCLKPPS<4:0> ---1 0000 ---1 0000 E20h SSPCLKPPS(4) -- -- -- SSPCLKPPS<4:0> ---1 0000 ---0 1110 E21h SSPDATPPS(3) -- -- -- SSPDATPPS<4:0> ---1 0001 ---1 0001 E21h SSPDATPPS(4) -- -- -- SSPDATPPS<4:0> ---1 0001 ---0 1100 E22h SSPSSPPS(3) -- -- -- SSPSSPPS<4:0> ---1 0011 ---1 0011 E22h SSPSSPPS(4) -- -- -- SSPSSPPS<4:0> ---1 0110 ---1 0110 E23h ATCC2PPS -- -- -- ATCC2PPS<4:0> ---1 0100 ---1 0100 E0Fh -- -- -- -- PPSLOCKED Preliminary 2014 Microchip Technology Inc. Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. Note 1: PIC16F1615/9 only. 2: Unimplemented, read as `1'. 3: PIC16(L)F1615 only. 4: PIC16(L)F1619 only. PIC16(L)F1615/9 DS40001770A-page 55 TABLE 3-16: 2014 Microchip Technology Inc. TABLE 3-16: Addr SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Banks 28 (Continued) Preliminary E24h RXPPS(3) -- -- -- RXPPS<4:0> ---1 0101 ---1 0101 E24h RXPPS(4) -- -- -- RXPPS<4:0> ---0 1101 ---0 1101 E25h CKPPS(3) -- -- -- CKPPS<4:0> ---1 0100 ---1 0100 E25h CKPPS(4) -- -- -- CKPPS<4:0> ---0 1111 ---0 1111 E26h SMT1SIGPPS -- -- -- SMT1SIGPPS<4:0> ---0 0100 ---0 0100 E27h SMT1WINPPS -- -- -- SMT1WINPPS<4:0> ---0 0101 ---0 0101 E28h CLCIN0PPS -- -- -- CLCIN0PPS<4:0> ---1 0011 ---1 0011 E29h CLCIN1PPS -- -- -- CLCIN1PPS<4:0> ---1 0100 ---1 0100 E2Ah CLCIN2PPS -- -- -- CLCIN2PPS<4:0> ---1 0001 ---1 0001 E2Bh CLCIN3PPS -- -- -- CLCIN3PPS<4:0> ---0 0101 ---0 0101 E2Ch SMT2SIGPPS -- -- -- SMT2SIGPPS<4:0> ---1 0001 ---1 0001 E2Dh SMT2WINPPS -- -- -- SMT2WINPPS<4:0> ---0 0011 ---0 0011 E2Eh ATCC3PPS -- -- -- ATCC3PPS<4:0> ---1 0101 ---1 0101 -- -- E2Fh to E6Fh -- Unimplemented Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. Note 1: PIC16F1615/9 only. 2: Unimplemented, read as `1'. 3: PIC16(L)F1615 only. 4: PIC16(L)F1619 only. PIC16(L)F1615/9 DS40001770A-page 56 Addr SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets -- -- Banks 29 E8Ch to E8Fh -- Unimplemented E90h RA0PPS -- -- -- RA0PPS<4:0> ---0 0000 ---0 0000 E91h RA1PPS -- -- -- RA1PPS<4:0> ---0 0000 ---0 0000 E92h RA2PPS -- -- -- RA2PPS<4:0> ---0 0000 ---0 0000 E93h -- E94h RA4PPS E95h RA5PPS E96h to E9Bh Unimplemented -- -- -- -- -- -- RA4PPS<4:0> ---0 0000 ---0 0000 -- -- -- RA5PPS<4:0> ---0 0000 ---0 0000 -- -- Unimplemented Preliminary 2014 Microchip Technology Inc. E9Ch RB4PPS(4) -- -- -- RB4PPS<4:0> ---0 0000 ---0 0000 E9Dh RB5PPS(4) -- -- -- RB5PPS<4:0> ---0 0000 ---0 0000 E9Eh (4) RB6PPS -- -- -- RB6PPS<4:0> ---0 0000 ---0 0000 E9Fh RB7PPS(4) -- -- -- RB7PPS<4:0> ---0 0000 ---0 0000 EA0h RC0PPS -- -- -- RC0PPS<4:0> ---0 0000 ---0 0000 EA1h RC1PPS -- -- -- RC1PPS<4:0> ---0 0000 ---0 0000 EA2h RC2PPS -- -- -- RC2PPS<4:0> ---0 0000 ---0 0000 EA3h RC3PPS -- -- -- RC3PPS<4:0> ---0 0000 ---0 0000 EA4h RC4PPS -- -- -- RC4PPS<4:0> ---0 0000 ---0 0000 EA5h RC5PPS -- -- -- RC5PPS<4:0> ---0 0000 ---0 0000 EA6h (4) RC6PPS -- -- -- RC6PPS<4:0> ---0 0000 ---0 0000 EA7h RC7PPS(4) -- -- -- RC7PPS<4:0> ---0 0000 ---0 0000 -- -- EA8h to EEFh -- Unimplemented Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. Note 1: PIC16F1615/9 only. 2: Unimplemented, read as `1'. 3: PIC16(L)F1615 only. 4: PIC16(L)F1619 only. PIC16(L)F1615/9 DS40001770A-page 57 TABLE 3-16: 2014 Microchip Technology Inc. TABLE 3-16: Addr SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets -- -- ---- 0000 ---- 0000 Banks 30 F0Ch to F0Eh -- Unimplemented F0Fh CLCDATA -- -- -- -- MLC4OUT F10h CLC1CON LC1EN -- LC1OUT LC1INTP LC1INTN F11h CLC1POL LC1POL -- -- -- LC1G4POL F12h CLC1SEL0 -- -- F13h CLC1SEL1 -- -- F14h CLC1SEL2 -- F15h CLC1SEL3 F16h F17h MLC3OUT MLC2OUT MLC1OUT LC1MODE<2:0> Preliminary 0-x0 0000 x--- xxxx x--- xxxx LC1D1S<5:0> --xx xxxx --xx xxxx LC1D2S<5:0> --xx xxxx --xx xxxx -- LC1D3S<5:0> --xx xxxx --xx xxxx -- -- LC1D4S<5:0> --xx xxxx --xx xxxx CLC1GLS0 LC1G1D4T LC1G1D4N LC1G1D3T LC1G1D3N LC1G1D2T LC1G1D2N LC1G1D1T LC1G1D1N xxxx xxxx xxxx xxxx CLC1GLS1 LC1G2D4T LC1G2D4N LC1G2D3T LC1G2D3N LC1G2D2T LC1G2D2N LC1G2D1T LC1G2D1N xxxx xxxx xxxx xxxx F18h CLC1GLS2 LC1G3D4T LC1G3D4N LC1G3D3T LC1G3D3N LC1G3D2T LC1G3D2N LC1G3D1T LC1G3D1N xxxx xxxx xxxx xxxx F19h CLC1GLS3 LC1G4D4T LC1G4D4N LC1G4D3T LC1G4D3N LC1G4D2T LC1G4D2N LC1G4D1T LC1G4D1N xxxx xxxx xxxx xxxx F1Ah CLC2CON LC2EN -- LC2OUT LC2INTP LC2INTN 0-x0 0000 0-x0 0000 F1Bh CLC2POL LC2POL -- -- -- LC2G4POL LC2G1POL x--- xxxx x--- xxxx F1Ch CLC2SEL0 -- -- LC2D1S<5:0> --xx xxxx --xx xxxx F1Dh CLC2SEL1 -- -- LC2D2S<5:0> --xx xxxx --xx xxxx F1Eh CLC2SEL2 -- -- LC2D3S<5:0> --xx xxxx --xx xxxx F1Fh CLC2SEL3 -- -- LC2D4S<5:0> --xx xxxx --xx xxxx F20h CLC2GLS0 LC2G1D4T LC2G1D4N LC2G1D3T LC2G1D3N LC2G1D2T LC2G1D2N LC2G1D1T LC2G1D1N xxxx xxxx xxxx xxxx F21h CLC2GLS1 LC2G2D4T LC2G2D4N LC2G2D3T LC2G2D3N LC2G2D2T LC2G2D2N LC2G2D1T LC2G2D1N xxxx xxxx xxxx xxxx F22h CLC2GLS2 LC2G3D4T LC2G3D4N LC2G3D3T LC2G3D3N LC2G3D2T LC2G3D2N LC2G3D1T LC2G3D1N xxxx xxxx xxxx xxxx F23h CLC2GLS3 LC2G4D4T LC2G4D4N LC2G4D3T LC2G4D3N LC2G4D2T LC2G4D2N LC2G4D1T LC2G4D1N xxxx xxxx xxxx xxxx LC1G3POL LC1G2POL LC1G1POL LC2MODE<2:0> LC2G3POL LC2G2POL DS40001770A-page 58 Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. Note 1: PIC16F1615/9 only. 2: Unimplemented, read as `1'. 3: PIC16(L)F1615 only. 4: PIC16(L)F1619 only. PIC16(L)F1615/9 0-x0 0000 Addr SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets 0-x0 0000 0-x0 0000 LC3G1POL x--- xxxx x--- xxxx Banks 30 (Continued) Preliminary F24h CLC3CON LC3EN -- LC3OUT LC3INTP LC3INTN F25h CLC3POL LC3POL -- -- -- LC3G4POL F26h CLC3SEL0 -- -- LC3D1S<5:0> --xx xxxx --xx xxxx F27h CLC3SEL1 -- -- LC3D2S<5:0> --xx xxxx --xx xxxx F28h CLC3SEL2 -- -- LC3D3S<5:0> --xx xxxx --xx xxxx F29h CLC3SEL3 -- -- LC3D4S<5:0> --xx xxxx --xx xxxx F2Ah CLC3GLS0 LC3G1D4T LC3G1D4N LC3G1D3T LC3G1D3N LC3G1D2T LC3G1D2N LC3G1D1T LC3G1D1N xxxx xxxx xxxx xxxx F2Bh CLC3GLS1 LC3G2D4T LC3G2D4N LC3G2D3T LC3G2D3N LC3G2D2T LC3G2D2N LC3G2D1T LC3G2D1N xxxx xxxx xxxx xxxx F2Ch CLC3GLS2 LC3G3D4T LC3G3D4N LC3G3D3T LC3G3D3N LC3G3D2T LC3G3D2N LC3G3D1T LC3G3D1N xxxx xxxx xxxx xxxx F2Dh CLC3GLS3 LC3G4D4T LC3G4D4N LC3G4D3T LC3G4D3N LC3G4D2T LC3G4D2N LC3G4D1T LC3G4D1N xxxx xxxx xxxx xxxx F2Eh CLC4CON LC4EN -- LC4OUT LC4INTP LC4INTN 0-x0 0000 0-x0 0000 F2Fh CLC4POL LC4POL -- -- -- LC4G4POL LC4G1POL x--- xxxx x--- xxxx F30h CLC4SEL0 -- -- LC4D1S<5:0> --xx xxxx --xx xxxx F31h CLC4SEL1 -- -- LC4D2S<5:0> --xx xxxx --xx xxxx F32h CLC4SEL2 -- -- LC4D3S<5:0> --xx xxxx --xx xxxx F33h CLC4SEL3 -- -- LC4D4S<5:0> --xx xxxx --xx xxxx F34h CLC4GLS0 LC4G1D4T LC4G1D4N LC4G1D3T LC4G1D3N LC4G1D2T LC4G1D2N LC4G1D1T LC4G1D1N xxxx xxxx xxxx xxxx F35h CLC4GLS1 LC4G2D4T LC4G2D4N LC4G2D3T LC4G2D3N LC4G2D2T LC4G2D2N LC4G2D1T LC4G2D1N xxxx xxxx xxxx xxxx F36h CLC4GLS2 LC4G3D4T LC4G3D4N LC4G3D3T LC4G3D3N LC4G3D2T LC4G3D2N LC4G3D1T LC4G3D1N xxxx xxxx xxxx xxxx F37h CLC4GLS3 LC4G4D4T LC4G4D4N LC4G4D3T LC4G4D3N LC4G4D2T LC4G4D2N LC4G4D1T LC4G4D1N xxxx xxxx xxxx xxxx -- -- F38h to F6Fh -- LC3MODE<2:0> LC3G3POL LC3G2POL LC4MODE<2:0> LC4G3POL LC4G2POL Unimplemented 2014 Microchip Technology Inc. Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. Note 1: PIC16F1615/9 only. 2: Unimplemented, read as `1'. 3: PIC16(L)F1615 only. 4: PIC16(L)F1619 only. PIC16(L)F1615/9 DS40001770A-page 59 TABLE 3-16: 2014 Microchip Technology Inc. TABLE 3-16: Addr SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Value on POR, BOR Value on all other Resets -- -- ---- -xxx ---- -uuu xxxx xxxx uuuu uuuu ---x xxxx ---u uuuu -xxx xxxx uuuu uuuu Indirect Data Memory Address 0 Low Pointer Shadow xxxx xxxx uuuu uuuu Indirect Data Memory Address 0 High Pointer Shadow xxxx xxxx uuuu uuuu Indirect Data Memory Address 1 Low Pointer Shadow xxxx xxxx uuuu uuuu Indirect Data Memory Address 1 High Pointer Shadow xxxx xxxx uuuu uuuu Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bank 31 F8Ch -- FE3h FE4h -- STATUS_ Unimplemented -- -- -- -- -- Z_SHAD DC_SHAD C_SHAD SHAD FE5h WREG_ Working Register Shadow SHAD FE6h BSR_ -- -- -- Bank Select Register Shadow SHAD FE7h PCLATH_ -- Program Counter Latch High Register Shadow SHAD FE8h FSR0L_ Preliminary SHAD FE9h FSR0H_ SHAD FEAh FSR1L_ SHAD FEBh FSR1H_ FECh -- SHAD STKPTR FEEh TOSL FEFh TOSH Unimplemented -- -- Top-of-Stack Low byte -- Top-of-Stack High byte -- Current Stack Pointer -- -- ---1 1111 ---1 1111 xxxx xxxx uuuu uuuu -xxx xxxx -uuu uuuu DS40001770A-page 60 Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. Note 1: PIC16F1615/9 only. 2: Unimplemented, read as `1'. 3: PIC16(L)F1615 only. 4: PIC16(L)F1619 only. PIC16(L)F1615/9 FEDh PIC16(L)F1615/9 3.3 3.3.2 PCL and PCLATH The Program Counter (PC) is 15 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<14:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 3-3 shows the five situations for the loading of the PC. FIGURE 3-3: LOADING OF PC IN DIFFERENT SITUATIONS Rev. 10-000042A 7/30/2013 14 PCH PCL 0 PC 7 6 ALU result 14 PCH PCL 0 PC 6 4 0 PCLATH 14 11 PCH PCL 0 6 7 0 PCLATH 14 PC PCH CALLW 0 PCL 0 BRW 15 PCH PC If using BRW, load the W register with the desired unsigned address and execute BRW. The entire PC will be loaded with the address PC + 1 + W. BRA If using BRA, the entire PC will be loaded with PC + 1 +, the signed value of the operand of the BRA instruction. 15 PC + OPCODE <8:0> 3.3.1 BRANCHING The branching instructions add an offset to the PC. This allows relocatable code and code that crosses page boundaries. There are two forms of branching, BRW and BRA. The PC will have incremented to fetch the next instruction in both cases. When using either branching instruction, a PCL memory boundary may be crossed. PC + W 14 COMPUTED FUNCTION CALLS A computed function CALL allows programs to maintain tables of functions and provide another way to execute state machines or look-up tables. When performing a table read using a computed function CALL, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). 3.3.4 8 W PCL 3.3.3 The CALLW instruction enables computed calls by combining PCLATH and W to form the destination address. A computed CALLW is accomplished by loading the W register with the desired address and executing CALLW. The PCL register is loaded with the value of W and PCH is loaded with PCLATH. GOTO, CALL OPCODE <10:0> PC A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When performing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). Refer to Application Note AN556, "Implementing a Table Read" (DS00556). If using the CALL instruction, the PCH<2:0> and PCL registers are loaded with the operand of the CALL instruction. PCH<6:3> is loaded with PCLATH<6:3>. 8 0 PCLATH Instruction with PCL as Destination COMPUTED GOTO MODIFYING PCL Executing any instruction with the PCL register as the destination simultaneously causes the Program Counter PC<14:8> bits (PCH) to be replaced by the contents of the PCLATH register. This allows the entire contents of the program counter to be changed by writing the desired upper seven bits to the PCLATH register. When the lower eight bits are written to the PCL register, all 15 bits of the program counter will change to the values contained in the PCLATH register and those being written to the PCL register. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 61 PIC16(L)F1615/9 3.4 3.4.1 Stack The stack is available through the TOSH, TOSL and STKPTR registers. STKPTR is the current value of the Stack Pointer. TOSH:TOSL register pair points to the TOP of the stack. Both registers are read/writable. TOS is split into TOSH and TOSL due to the 15-bit size of the PC. To access the stack, adjust the value of STKPTR, which will position TOSH:TOSL, then read/write to TOSH:TOSL. STKPTR is five bits to allow detection of overflow and underflow. All devices have a 16-level x 15-bit wide hardware stack (refer to Figures 3-4 through 3-7). The stack space is not part of either program or data space. The PC is PUSHed onto the stack when CALL or CALLW instructions are executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation. The stack operates as a circular buffer if the STVREN bit is programmed to `0' (Configuration Words). This means that after the stack has been PUSHed sixteen times, the seventeenth PUSH overwrites the value that was stored from the first PUSH. The eighteenth PUSH overwrites the second PUSH (and so on). The STKOVF and STKUNF flag bits will be set on an Overflow/Underflow, regardless of whether the Reset is enabled. Note: Care should be taken when modifying the STKPTR while interrupts are enabled. During normal program operation, CALL, CALLW and Interrupts will increment STKPTR while RETLW, RETURN, and RETFIE will decrement STKPTR. At any time STKPTR can be inspected to see how much stack is left. The STKPTR always points at the currently used place on the stack. Therefore, a CALL or CALLW will increment the STKPTR and then write the PC, and a return will unload the PC and then decrement the STKPTR. Note 1: There are no instructions/mnemonics called PUSH or POP. These are actions that occur from the execution of the CALL, CALLW, RETURN, RETLW and RETFIE instructions or the vectoring to an interrupt address. FIGURE 3-4: ACCESSING THE STACK Reference Figure 3-4 through Figure 3-7 for examples of accessing the stack. ACCESSING THE STACK EXAMPLE 1 Rev. 10-000043A 7/30/2013 TOSH:TOSL 0x0F STKPTR = 0x1F Stack Reset Disabled (STVREN = 0) 0x0E 0x0D 0x0C 0x0B Initial Stack Configuration: 0x0A After Reset, the stack is empty. The empty stack is initialized so the Stack Pointer is pointing at 0x1F. If the Stack Overflow/Underflow Reset is enabled, the TOSH/TOSL register will return `0'. If the Stack Overflow/Underflow Reset is disabled, the TOSH/TOSL register will return the contents of stack address 0x0F. 0x09 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 0x00 TOSH:TOSL DS40001770A-page 62 0x1F 0x0000 Preliminary STKPTR = 0x1F Stack Reset Enabled (STVREN = 1) 2014 Microchip Technology Inc. PIC16(L)F1615/9 FIGURE 3-5: ACCESSING THE STACK EXAMPLE 2 Rev. 10-000043B 7/30/2013 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A This figure shows the stack configuration after the first CALL or a single interrupt. If a RETURN instruction is executed, the return address will be placed in the Program Counter and the Stack Pointer decremented to the empty state (0x1F). 0x09 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 TOSH:TOSL FIGURE 3-6: 0x00 Return Address STKPTR = 0x00 ACCESSING THE STACK EXAMPLE 3 Rev. 10-000043C 7/30/2013 0x0F 0x0E 0x0D 0x0C After seven CALLs or six CALLs and an interrupt, the stack looks like the figure on the left. A series of RETURN instructions will repeatedly place the return addresses into the Program Counter and pop the stack. 0x0B 0x0A 0x09 0x08 0x07 TOSH:TOSL 2014 Microchip Technology Inc. 0x06 Return Address 0x05 Return Address 0x04 Return Address 0x03 Return Address 0x02 Return Address 0x01 Return Address 0x00 Return Address STKPTR = 0x06 Preliminary DS40001770A-page 63 PIC16(L)F1615/9 FIGURE 3-7: ACCESSING THE STACK EXAMPLE 4 Rev. 10-000043D 7/30/2013 TOSH:TOSL 3.4.2 0x0F Return Address 0x0E Return Address 0x0D Return Address 0x0C Return Address 0x0B Return Address 0x0A Return Address 0x09 Return Address 0x08 Return Address 0x07 Return Address 0x06 Return Address 0x05 Return Address 0x04 Return Address 0x03 Return Address 0x02 Return Address 0x01 Return Address 0x00 Return Address When the stack is full, the next CALL or an interrupt will set the Stack Pointer to 0x10. This is identical to address 0x00 so the stack will wrap and overwrite the return address at 0x00. If the Stack Overflow/Underflow Reset is enabled, a Reset will occur and location 0x00 will not be overwritten. STKPTR = 0x10 OVERFLOW/UNDERFLOW RESET If the STVREN bit in Configuration Words is programmed to `1', the device will be reset if the stack is PUSHed beyond the sixteenth level or POPed beyond the first level, setting the appropriate bits (STKOVF or STKUNF, respectively) in the PCON register. 3.5 Indirect Addressing The INDFn registers are not physical registers. Any instruction that accesses an INDFn register actually accesses the register at the address specified by the File Select Registers (FSR). If the FSRn address specifies one of the two INDFn registers, the read will return `0' and the write will not occur (though Status bits may be affected). The FSRn register value is created by the pair FSRnH and FSRnL. The FSR registers form a 16-bit address that allows an addressing space with 65536 locations. These locations are divided into three memory regions: * Traditional Data Memory * Linear Data Memory * Program Flash Memory DS40001770A-page 64 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 FIGURE 3-8: INDIRECT ADDRESSING Rev. 10-000044A 7/30/2013 0x0000 0x0000 Traditional Data Memory 0x0FFF 0x1000 0x0FFF Reserved 0x1FFF 0x2000 Linear Data Memory 0x29AF 0x29B0 Reserved FSR Address Range 0x7FFF 0x8000 0x0000 Program Flash Memory 0xFFFF Note: 0x7FFF Not all memory regions are completely implemented. Consult device memory tables for memory limits. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 65 PIC16(L)F1615/9 3.5.1 TRADITIONAL DATA MEMORY The traditional data memory is a region from FSR address 0x000 to FSR address 0xFFF. The addresses correspond to the absolute addresses of all SFR, GPR and common registers. FIGURE 3-9: TRADITIONAL DATA MEMORY MAP Rev. 10-000056A 7/31/2013 Direct Addressing 4 BSR 0 Indirect Addressing From Opcode 6 0 Bank Select 7 FSRxH 0 0 0 0 Location Select 0x00 00000 Bank Select 00001 00010 11111 Bank 0 Bank 1 Bank 2 Bank 31 0 7 FSRxL 0 Location Select 0x7F DS40001770A-page 66 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 3.5.2 3.5.3 LINEAR DATA MEMORY The linear data memory is the region from FSR address 0x2000 to FSR address 0x29AF. This region is a virtual region that points back to the 80-byte blocks of GPR memory in all the banks. Unimplemented memory reads as 0x00. Use of the linear data memory region allows buffers to be larger than 80 bytes because incrementing the FSR beyond one bank will go directly to the GPR memory of the next bank. The 16 bytes of common memory are not included in the linear data memory region. FIGURE 3-10: LINEAR DATA MEMORY MAP PROGRAM FLASH MEMORY To make constant data access easier, the entire program Flash memory is mapped to the upper half of the FSR address space. When the MSb of FSRnH is set, the lower 15 bits are the address in program memory which will be accessed through INDF. Only the lower eight bits of each memory location is accessible via INDF. Writing to the program Flash memory cannot be accomplished via the FSR/INDF interface. All instructions that access program Flash memory via the FSR/INDF interface will require one additional instruction cycle to complete. FIGURE 3-11: PROGRAM FLASH MEMORY MAP Rev. 10-000057A 7/31/2013 7 FSRnH 0 0 1 0 7 FSRnL Rev. 10-000058A 7/31/2013 7 1 0 FSRnH 0 Location Select Location Select 0x2000 7 FSRnL 0 0x8000 0x0A0 Bank 1 0x0EF Program Flash Memory (low 8 bits) 0x120 Bank 2 0x16F 0x29AF 2014 Microchip Technology Inc. 0x0000 0x020 Bank 0 0x06F 0xF20 Bank 30 0xF6F 0xFFFF Preliminary 0x7FFF DS40001770A-page 67 PIC16(L)F1615/9 4.0 DEVICE CONFIGURATION Device configuration consists of Configuration Words, Code Protection and Device ID. 4.1 Configuration Words There are several Configuration Word bits that allow different oscillator and memory protection options. These are implemented as Configuration Word 1 at 8007h, Configuration Word 2 at 8008h, and Configuration 3 at 8009h. Note: The DEBUG bit in Configuration Words is managed automatically by device development tools including debuggers and programmers. For normal device operation, this bit should be maintained as a `1'. DS40001770A-page 68 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 4.2 Register Definitions: Configuration Words REGISTER 4-1: CONFIG1: CONFIGURATION WORD 1 R/P-1 R/P-1 R/P-1 FCMEN IESO CLKOUTEN R/P-1 R/P-1 BOREN<1:0>(1) -- bit 13 R/P-1 R/P-1 R/P-1 CP(2) MCLRE PWRTE U-1 bit 8 U-1 U-1 -- R/P-1 -- R/P-1 R/P-1 FOSC<2:0> bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as `1' `0' = Bit is cleared `1' = Bit is set -n = Value when blank or after Bulk Erase bit 13 FCMEN: Fail Clock Monitor Enable bit 1 = Fail-Safe Clock Monitor is enabled 0 = Fail-Safe Clock Monitor is disabled bit 12 IESO: Internal/External Switch Over bit 1 = Internal/External Switch Over mode is enabled 0 = Internal/External Switch Over mode is disabled bit 11 CLKOUTEN: Clock Out Enable bit 1 = CLKOUT function is disabled. I/O function on the CLKOUT pin 0 = CLKOUT function is enabled on the CLKOUT pin bit 10-9 BOREN<1:0>: Brown-Out Reset Enable bits(1) 11 = BOR enabled 10 = BOR enabled during operation and disabled in Sleep 01 = BOR controlled by SBOREN bit of the BORCON register 00 = BOR disabled bit 8 Unimplemented: Read as `1' bit 7 CP: Code Protection bit(2) 1 = Program memory code protection is disabled 0 = Program memory code protection is enabled bit 6 MCLRE: MCLR/VPP Pin Function Select bit If LVP bit = 1: This bit is ignored. If LVP bit = 0: 1 =MCLR/VPP pin function is MCLR; Weak pull-up enabled. 0 =MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of WPUA3 bit. bit 5 PWRTE: Power-Up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled bit 4-3 Unimplemented: Read as `1' 2014 Microchip Technology Inc. Preliminary DS40001770A-page 69 PIC16(L)F1615/9 REGISTER 4-1: bit 2-0 Note 1: 2: CONFIG1: CONFIGURATION WORD 1 (CONTINUED) FOSC<2:0>: Oscillator Selection bits 111 =ECH: External clock, High-Power mode: on CLKIN pin 110 =ECM: External clock, Medium-Power mode: on CLKIN pin 101 =ECL: External clock, Low-Power mode: on CLKIN pin 100 =INTOSC oscillator: I/O function on CLKIN pin 011 =Reserved 010 =HS: HS oscillator, high-speed crystal/resonator connected between OSC1 and OSC2 pins 001 =Reserved 000 =Reserved Enabling Brown-out Reset does not automatically enable Power-up Timer. Once enabled, code-protect can only be disabled by bulk erasing the device. DS40001770A-page 70 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 REGISTER 4-2: CONFIG2: CONFIGURATION WORD 2 R/P-1 (1) LVP R/P-1 DEBUG(3) R/P-1 R/P-1 R/P-1 R/P-1 LPBOR BORV(2) STVREN PLLEN bit 13 bit 8 R/P-1 U-1 U-1 U-1 U-1 R/P-1 ZCD -- -- -- -- PPS1WAY R/P-1 R/P-1 WRT<1:0> bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as `1' `0' = Bit is cleared `1' = Bit is set -n = Value when blank or after Bulk Erase bit 13 LVP: Low-Voltage Programming Enable bit(1) 1 = Low-voltage programming enabled 0 = High-voltage on MCLR must be used for programming bit 12 DEBUG: In-Circuit Debugger Mode bit(3) 1 = In-Circuit Debugger disabled, ICSPCLK and ICSPDAT are general purpose I/O pins 0 = In-Circuit Debugger enabled, ICSPCLK and ICSPDAT are dedicated to the debugger bit 11 LPBOR: Low-Power BOR Enable bit 1 = Low-Power Brown-out Reset is disabled 0 = Low-Power Brown-out Reset is enabled bit 10 BORV: Brown-Out Reset Voltage Selection bit(2) 1 = Brown-out Reset voltage (VBOR), low trip point selected 0 = Brown-out Reset voltage (VBOR), high trip point selected bit 9 STVREN: Stack Overflow/Underflow Reset Enable bit 1 = Stack Overflow or Underflow will cause a Reset 0 = Stack Overflow or Underflow will not cause a Reset bit 8 PLLEN: PLL Enable bit 1 = 4xPLL enabled 0 = 4xPLL disabled bit 7 ZCD: ZCD Disable bit 1 = ZCD disabled. ZCD can be enabled by setting the ZCD1EN bit of ZCD1CON 0 = ZCD always enabled bit 6-3 Unimplemented: Read as `1' bit 2 PPS1WAY: PPSLOCK Bit One-Way Set Enable bit 1 = The PPSLOCK bit can only be set once after an unlocking sequence is executed; once PPSLOCK is set, all future changes to PPS registers are prevented 0 = The PPSLOCK bit can be set and cleared as needed (provided an unlocking sequence is executed) bit 1-0 WRT<1:0>: Flash Memory Self-Write Protection bits 8 kW Flash memory (PIC16(L)F1615/9): 11 = OFF - Write protection off 10 = BOOT - 000h to 01FFh write-protected, 200h to 1FFFh may be modified by PMCON control 01 = HALF - 000h to 0FFFh write-protected, 1000h to 1FFFh may be modified by PMCON control 00 = ALL - 000h to 1FFFh write-protected, no addresses may be modified by PMCON control Note 1: 2: 3: The LVP bit cannot be programmed to `0' when Programming mode is entered via LVP. See VBOR parameter for specific trip point voltages. The DEBUG bit in Configuration Words is managed automatically by device development tools including debuggers and programmers. For normal device operation, this bit should be maintained as a `1'. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 71 PIC16(L)F1615/9 REGISTER 4-3: CONFIG3: CONFIGURATION WORD 3 R/P-0 R/P-0 R/P-1 R/P-1 WDTCCS<2:0> R/P-1 R/P-1 WDTCWS<2:0> bit 13 U-1 R/P-1 -- bit 8 R/P-1 R/P-1 R/P-1 R/P-1 WDTE<1:0> R/P-1 R/P-1 WDTCPS<4:0> bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as `1' `0' = Bit is cleared `1' = Bit is set -n = Value when blank or after Bulk Erase bit 13-11 WDTCCS<2:0>: WDT Configuration Clock Select bits 111 =Software Control; WDT clock selected by CS<2:0> 110 =Reserved * * * 010 =Reserved 001 =WDT reference clock is MFINTOSC, 31.25 kHz (default value) 000 =WDT reference clock is LFINTOSC, 31.00 kHz output bit 10-8 WDTCWS<2:0>: WDT Configuration Window Select bits. WINDOW at POR Value Window delay Percent of time Window opening Percent of time Software control of WINDOW? Keyed access required? 111 111 n/a 100 Yes No 110 111 n/a 100 101 101 25 75 100 100 37.5 62.5 011 011 50 50 No Yes 010 010 62.5 37.5 001 001 75 25 000 000 87.5 12.5(1) WDTCWS <2:0> Default fuse = 111 bit 7 Unimplemented: Read as `1' bit 6-5 WDTE<1:0>: Watchdog Timer Enable bits 11 =WDT enabled in all modes, the SEN bit in the WDTCON0 register is ignored 10 =WDT enabled while running and disabled in Sleep 01 =WDT controlled by the SEN bit in the WDTCON0 register 00 = WDT disabled DS40001770A-page 72 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 REGISTER 4-3: bit 4-0 CONFIG3: CONFIGURATION WORD 3 (CONTINUED) WDTCPS<4:0>: WDT Configuration Period Select bits WDTPS at POR Note 1: Software control of WDTPS WDTCPS <4:0> Value 11111 01011 1:65536 216 2s Yes 10011 ... 11110 10011 ... 11110 1:32 25 1 ms No Divider Ratio Typical time out (FIN = 31 kHz) 10010 10010 1:8388608 223 256 s 10001 10001 1:4194304 222 128 s 10000 10000 1:2097152 221 64 s 01111 01111 1:1048576 220 32 s 01110 01110 1:524299 219 16 s 01101 01101 1:262144 218 8s 01100 01100 1:131072 217 4s 01011 01011 1:65536 216 2s 01010 01010 1:32768 215 1s 01001 01001 1:16384 214 512 ms 01000 01000 1:8192 213 256 ms 00111 00111 1:4096 212 128 ms 00110 00110 1:2048 211 64 ms 00101 00101 1:1024 210 32 ms 00100 00100 1:512 29 16 ms 00011 00011 1:256 28 8 ms 00010 00010 1:128 27 4 ms 00001 00001 1:64 26 2 ms 00000 00000 1:32 25 1 ms Default fuse = 11111 No A window delay of 12.5% is only available in Software Control mode via the WDTCON1 register. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 73 PIC16(L)F1615/9 4.3 Code Protection Code protection allows the device to be protected from unauthorized access. Internal access to the program memory is unaffected by any code protection setting. 4.3.1 PROGRAM MEMORY PROTECTION The entire program memory space is protected from external reads and writes by the CP bit in Configuration Words. When CP = 0, external reads and writes of program memory are inhibited and a read will return all `0's. The CPU can continue to read program memory, regardless of the protection bit settings. Writing the program memory is dependent upon the write protection setting. See Section 4.4 "Write Protection" for more information. 4.4 Write Protection Write protection allows the device to be protected from unintended self-writes. Applications, such as boot loader software, can be protected while allowing other regions of the program memory to be modified. The WRT<1:0> bits in Configuration Words define the size of the program memory block that is protected. 4.5 User ID Four memory locations (8000h-8003h) are designated as ID locations where the user can store checksum or other code identification numbers. These locations are readable and writable during normal execution. See Section 10.4 "User ID, Device ID and Configuration Word Access" for more information on accessing these memory locations. For more information on checksum calculation, see the "PIC12(L)F1612/16(L)F161X Memory Programming Specification" (DS40001720). DS40001770A-page 74 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 4.6 Device ID and Revision ID The 14-bit Device ID word is located at 8006h and the 14-bit Revision ID is located at 8005h. These locations are read-only and cannot be erased or modified. See Section 10.4 "User ID, Device ID and Configuration Word Access" for more information on accessing these memory locations. Development tools, such as device programmers and debuggers, may be used to read the Device ID and Revision ID. 4.7 Register Definitions: Device ID REGISTER 4-4: DEVID: DEVICE ID REGISTER R R R R R R DEV<13:8> bit 13 R R bit 8 R R R R R R DEV<7:0> bit 7 bit 0 Legend: R = Readable bit `1' = Bit is set bit 13-0 `0' = Bit is cleared DEV<13:0>: Device ID bits Device DEVID<13:0> Values PIC16F1615 11 0000 0111 1100 (307Ch) PIC16LF1615 11 0000 0111 1110 (307Eh) PIC16F1619 11 0000 0111 1101 (307Dh) PIC16LF1619 11 0000 0111 1111 (307Fh) REGISTER 4-5: REVID: REVISION ID REGISTER R R R R R R REV<13:8> bit 13 R R bit 8 R R R R R R REV<7:0> bit 7 bit 0 Legend: R = Readable bit `1' = Bit is set bit 13-0 `0' = Bit is cleared REV<13:0>: Revision ID bits 2014 Microchip Technology Inc. Preliminary DS40001770A-page 75 PIC16(L)F1615/9 5.0 OSCILLATOR MODULE The oscillator module can be configured in one of the following clock modes. 5.1 Overview 1. The oscillator module has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption. Figure 5-1 illustrates a block diagram of the oscillator module. Clock sources can be supplied from external oscillators. In addition, the system clock source can be supplied from one of two internal oscillators and PLL circuits, with a choice of speeds selectable via software. Additional clock features include: * Selectable system clock source between external or internal sources via software. * Two-Speed Start-up mode, which minimizes latency between external oscillator start-up and code execution. * Fail-Safe Clock Monitor (FSCM) designed to detect a failure of the external clock source (HS, ECH, ECM, or ECL modes) and switch automatically to the internal oscillator. * Oscillator Start-up Timer (OST) ensures stability of crystal oscillator sources DS40001770A-page 76 2. 3. 4. 5. ECL - External Clock Low-Power mode (0 MHz to 0.5 MHz) ECM - External Clock Medium-Power mode (0.5 MHz to 4 MHz) ECH - External Clock High-Power mode (4 MHz to 32 MHz) INTOSC - Internal oscillator (31 kHz to 32 MHz). HS - High Gain Crystal or Ceramic Resonator mode (4 MHz to 10 MHz) Clock Source modes are selected by the FOSC<1:0> bits in the Configuration Words. The FOSC bits determine the type of oscillator that will be used when the device is first powered. The ECH, ECM, and ECL Clock modes rely on an external logic level signal as the device clock source.The HS Clock mode requires an external crystal or resonator to be connected to the device. The INTOSC internal oscillator block produces low, medium, and high-frequency clock sources, designated LFINTOSC, MFINTOSC and HFINTOSC. (see Internal Oscillator Block, Figure 5-1). A wide selection of device clock frequencies may be derived from these three clock sources. Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 SIMPLIFIED PIC(R) MCU CLOCK SOURCE BLOCK DIAGRAM FIGURE 5-1: Rev. 10-000155C 5/14/2014 FOSC<2:0> CLKIN/ OSC1 Sleep 3 Primary Oscillator (OSC) 0 1 4x PLL(2) CLKOUT/ OSC2 FOSC(1) 00 to CPU and Peripherals PLLEN SPLLEN INTOSC 1x 16 MHz 8 MHz 2 4 MHz MFINTOSC 500 kHz Oscillator (1) 2 MHz Prescaler HFINTOSC HFPLL 16 MHz (1) SCS<1:0> 1 MHz *500 kHz *250 kHz *125 kHz 62.5 kHz *31.25 kHz *31 kHz Internal Oscillator Block 4 IRCF<3:0> LFINTOSC(1) 31 kHz Oscillator FRC(1) 600 kHz Oscillator to WDT, PWRT, and other Peripherals to Peripherals to ADC and other Peripherals * Available with more than one IRCF selection Note 1: 2: See Section FIGURE 5-1: "Simplified PIC(R) MCU Clock Source Block Diagram". If FOSC<1:0> = 00, 4x PLL can only be used if IRCF<3:0> = 1110. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 77 PIC16(L)F1615/9 5.2 Clock Source Types Clock sources can be classified as external or internal. External clock sources rely on external circuitry for the clock source to function. Examples are: oscillator modules (ECH, ECM, ECL modes) and quartz crystal resonators or ceramic resonators (HS mode). Internal clock sources are contained within the oscillator module. The internal oscillator block has two internal oscillators and a dedicated Phase-Lock Loop (HFPLL) that are used to generate three internal system clock sources: the 16 MHz High-Frequency Internal Oscillator (HFINTOSC), 500 kHz (MFINTOSC) and the 31 kHz Low-Frequency Internal Oscillator (LFINTOSC). The system clock can be selected between external or internal clock sources via the System Clock Select (SCS) bits in the OSCCON register. See Section 5.3 "Clock Switching" for additional information. 5.2.1 The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in operation after a Power-On Reset (POR) or wake-up from Sleep. Because the PIC(R) MCU design is fully static, stopping the external clock input will have the effect of limiting the device while leaving all data intact. Upon restarting the external clock, the device will resume operation as if no time had elapsed. FIGURE 5-2: EXTERNAL CLOCK (EC) MODE OPERATION CLKIN Clock from Ext. System PIC(R) MCU CLKOUT FOSC/4 or I/O(1) Output depends upon CLKOUTEN bit of the Configuration Words. Note 1: EXTERNAL CLOCK SOURCES An external clock source can be used as the device system clock by performing one of the following actions: 5.2.1.2 * Program the FOSC<1:0> bits in the Configuration Words to select an external clock source that will be used as the default system clock upon a device Reset. * Write the SCS<1:0> bits in the OSCCON register to switch the system clock source to: - An external clock source determined by the value of the FOSC bits. FIGURE 5-3: HS Mode The HS mode supports the use of quartz crystal resonators or ceramic resonators connected to OSC1 and OSC2. Figure 5-3 and Figure 5-4 show typical circuits for quartz crystal and ceramic resonators, respectively. QUARTZ CRYSTAL OPERATION (HS MODE) Rev. 10-000059A 7/30/2013 See Section 5.3 "Clock Switching"for more information. PIC(R) MCU OSC1/CLKIN 5.2.1.1 EC Mode C1 The External Clock (EC) mode allows an externally generated logic level signal to be the system clock source. When operating in this mode, an external clock source is connected to the CLKIN input. CLKOUT is available for general purpose I/O or CLKOUT. Figure 5-2 shows the pin connections for EC mode. EC mode has three power modes to select from through the FOSC bits in the Configuration Words: C2 Note 1: * ECH - High power, 4-20 MHz * ECM - Medium power, 0.5-4 MHz * ECL - Low power, 0-0.5 MHz DS40001770A-page 78 2: Preliminary To Internal Logic Quartz Crystal RF(2) RS(1) OSC2/CLKOUT Sleep A series resistor (Rs) may be required for quartz crystals with low drive level. The value of RF varies with the Oscillator mode selected (typically between 2 M and 10 M). 2014 Microchip Technology Inc. PIC16(L)F1615/9 FIGURE 5-4: CERAMIC RESONATOR OPERATION (HS MODE) Rev. 10-000060A 7/30/2013 PIC(R) MCU Ceramic Resonator OSC1/CLKIN C1 To Internal Logic RP(3) C2 Note 1: 5.2.1.3 RS(1) RF(2) Sleep OSC2/CLKOUT A series resistor (Rs) may be required for ceramic resonators with low drive level. 2: The value of RF varies with the Oscillator mode selected (typically between 2 M and 10 M). 3. An additional parallel feedback resistor (RP) may be required for proper ceramic resonator operation. Oscillator Start-up Timer (OST) If the oscillator module is configured for HS modes, the Oscillator Start-up Timer (OST) counts 1024 oscillations from OSC1. This occurs following a Poweron Reset (POR) and when the Power-up Timer (PWRT) has expired (if configured), or a wake-up from Sleep. During this time, the program counter does not increment and program execution is suspended. The OST ensures that the oscillator circuit, using a quartz crystal resonator or ceramic resonator, has started and is providing a stable system clock to the oscillator module. In order to minimize latency between external oscillator start-up and code execution, the Two-Speed Clock Start-up mode can be selected (see Section 5.4 "TwoSpeed Clock Start-up Mode"). 2014 Microchip Technology Inc. Preliminary DS40001770A-page 79 PIC16(L)F1615/9 5.2.2 INTERNAL CLOCK SOURCES 5.2.2.1 The device may be configured to use the internal oscillator block as the system clock by performing one of the following actions: * Program the FOSC<1:0> bits in Configuration Words to select the INTOSC clock source, which will be used as the default system clock upon a device Reset. * Write the SCS<1:0> bits in the OSCCON register to switch the system clock source to the internal oscillator during run-time. See Section 5.3 "Clock Switching"for more information. In INTOSC mode, CLKIN is available for general purpose I/O. CLKOUT is available for general purpose I/O or CLKOUT. The function of the OSC2/CLKOUT pin is determined by the CLKOUTEN bit in Configuration Words. The internal oscillator block has two independent oscillators and a dedicated Phase-Lock Loop, HFPLL that can produce one of three internal system clock sources. 1. 2. 3. The HFINTOSC (High-Frequency Internal Oscillator) is factory calibrated and operates at 16 MHz. The HFINTOSC source is generated from the 500 kHz MFINTOSC source and the dedicated Phase-Lock Loop, HFPLL. The frequency of the HFINTOSC can be useradjusted via software using the OSCTUNE register (Register 5-3). The MFINTOSC (Medium-Frequency Internal Oscillator) is factory calibrated and operates at 500 kHz. The frequency of the MFINTOSC can be user-adjusted via software using the OSCTUNE register (Register 5-3). The LFINTOSC (Low-Frequency Internal Oscillator) is uncalibrated and operates at 31 kHz. HFINTOSC The High-Frequency Internal Oscillator (HFINTOSC) is a factory calibrated 16 MHz internal clock source. The frequency of the HFINTOSC can be altered via software using the OSCTUNE register (Register 5-3). The output of the HFINTOSC connects to a postscaler and multiplexer (see Figure 5-1). One of multiple frequencies derived from the HFINTOSC can be selected via software using the IRCF<3:0> bits of the OSCCON register. See Section 5.2.2.8 "Internal Oscillator Clock Switch Timing" for more information. The HFINTOSC is enabled by: * Configure the IRCF<3:0> bits of the OSCCON register for the desired HF frequency, and * FOSC<1:0> = 00, or * Set the System Clock Source (SCS) bits of the OSCCON register to `1x'. A fast start-up oscillator allows internal circuits to power up and stabilize before switching to HFINTOSC. The High-Frequency Internal Oscillator Ready bit (HFIOFR) of the OSCSTAT register indicates when the HFINTOSC is running. The High-Frequency Internal Oscillator Status Locked bit (HFIOFL) of the OSCSTAT register indicates when the HFINTOSC is running within 2% of its final value. The High-Frequency Internal Oscillator Stable bit (HFIOFS) of the OSCSTAT register indicates when the HFINTOSC is running within 0.5% of its final value. 5.2.2.2 MFINTOSC The Medium-Frequency Internal Oscillator (MFINTOSC) is a factory calibrated 500 kHz internal clock source. The frequency of the MFINTOSC can be altered via software using the OSCTUNE register (Register 5-3). The output of the MFINTOSC connects to a postscaler and multiplexer (see Figure 5-1). One of nine frequencies derived from the MFINTOSC can be selected via software using the IRCF<3:0> bits of the OSCCON register. See Section 5.2.2.8 "Internal Oscillator Clock Switch Timing" for more information. The MFINTOSC is enabled by: * Configure the IRCF<3:0> bits of the OSCCON register for the desired HF frequency, and * FOSC<1:0> = 00, or * Set the System Clock Source (SCS) bits of the OSCCON register to `1x' The Medium-Frequency Internal Oscillator Ready bit (MFIOFR) of the OSCSTAT register indicates when the MFINTOSC is running. DS40001770A-page 80 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 5.2.2.3 Internal Oscillator Frequency Adjustment 5.2.2.5 The 500 kHz internal oscillator is factory calibrated. This internal oscillator can be adjusted in software by writing to the OSCTUNE register (Register 5-3). Since the HFINTOSC and MFINTOSC clock sources are derived from the 500 kHz internal oscillator a change in the OSCTUNE register value will apply to both. The default value of the OSCTUNE register is `0'. The value is a 6-bit two's complement number. A value of 1Fh will provide an adjustment to the maximum frequency. A value of 20h will provide an adjustment to the minimum frequency. When the OSCTUNE register is modified, the oscillator frequency will begin shifting to the new frequency. Code execution continues during this shift. There is no indication that the shift has occurred. OSCTUNE does not affect the LFINTOSC frequency. Operation of features that depend on the LFINTOSC clock source frequency, such as the Power-up Timer (PWRT), Watchdog Timer (WDT), and peripherals, are not affected by the change in frequency. 5.2.2.4 LFINTOSC The Low-Frequency Internal Oscillator (LFINTOSC) is an uncalibrated 31 kHz internal clock source. The output of the LFINTOSC connects to a multiplexer (see Figure 5-1). Select 31 kHz, via software, using the IRCF<3:0> bits of the OSCCON register. See Section 5.2.2.8 "Internal Oscillator Clock Switch Timing" for more information. The LFINTOSC is also the frequency for the Power-up Timer (PWRT), Watchdog Timer (WDT) and Fail-Safe Clock Monitor (FSCM). The LFINTOSC is enabled by selecting 31 kHz (IRCF<3:0> bits of the OSCCON register = 000) as the system clock source (SCS bits of the OSCCON register = 1x), or when any of the following are enabled: * Configure the IRCF<3:0> bits of the OSCCON register for the desired LF frequency, and * FOSC<1:0> = 00, or * Set the System Clock Source (SCS) bits of the OSCCON register to `1x' Peripherals that use the LFINTOSC are: FRC The FRC clock is an uncalibrated, nominal 600 kHz peripheral clock source. The FRC is automatically turned on by the peripherals requesting the FRC clock. The FRC clock will continue to run during Sleep. 5.2.2.6 Internal Oscillator Frequency Selection The system clock speed can be selected via software using the Internal Oscillator Frequency Select bits IRCF<3:0> of the OSCCON register. The postscaler outputs of the 16 MHz HFINTOSC, 500 kHz MFINTOSC, and 31 kHz LFINTOSC output connect to a multiplexer (see Figure 5-1). The Internal Oscillator Frequency Select bits IRCF<3:0> of the OSCCON register select the frequency output of the internal oscillators. One of the following frequencies can be selected via software: - 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz (default after Reset) 250 kHz 125 kHz 62.5 kHz 31.25 kHz 31 kHz (LFINTOSC) Note: Following any Reset, the IRCF<3:0> bits of the OSCCON register are set to `0111' and the frequency selection is set to 500 kHz. The user can modify the IRCF bits to select a different frequency. The IRCF<3:0> bits of the OSCCON register allow duplicate selections for some frequencies. These duplicate choices can offer system design trade-offs. Lower power consumption can be obtained when changing oscillator sources for a given frequency. Faster transition times can be obtained between frequency changes that use the same oscillator source. * Power-up Timer (PWRT) * Watchdog Timer (WDT) * Fail-Safe Clock Monitor (FSCM) The Low-Frequency Internal Oscillator Ready bit (LFIOFR) of the OSCSTAT register indicates when the LFINTOSC is running. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 81 PIC16(L)F1615/9 5.2.2.7 32 MHz Internal Oscillator Frequency Selection 5.2.2.8 The Internal Oscillator Block can be used with the 4x PLL associated with the External Oscillator Block to produce a 32 MHz internal system clock source. Either the 8 or 16 MHz internal oscillator settings can be used, with the 16 MHz being divided by two before being input into the PLL. The following settings are required to use the 32 MHz internal clock source: * The FOSC bits in Configuration Words must be set to use the INTOSC source as the device system clock (FOSC<1:0> = 00). * The SCS bits in the OSCCON register must be cleared to use the clock determined by FOSC<1:0> in Configuration Words (SCS<1:0> = 00). * The IRCF bits in the OSCCON register must be set to either the 16 MHz (IRCF<3:0> = 1111) or the 8 MHz HFINTOSC (IRCF<3:0> = 1110). * The SPLLEN bit in the OSCCON register must be set to enable the 4x PLL, or the PLLEN bit of the Configuration Words must be programmed to a `1'. Note: When using the PLLEN bit of the Configuration Words, the 4x PLL cannot be disabled by software and the 8/16 MHz HFINTOSC option will no longer be available. The 4x PLL is not available for use with the internal oscillator when the SCS bits of the OSCCON register are set to `1x'. The SCS bits must be set to `00' to use the 4x PLL with the internal oscillator. DS40001770A-page 82 Internal Oscillator Clock Switch Timing When switching between the HFINTOSC, MFINTOSC and the LFINTOSC, the new oscillator may already be shut down to save power (see Figure 5-5). If this is the case, there is a delay after the IRCF<3:0> bits of the OSCCON register are modified before the frequency selection takes place. The OSCSTAT register will reflect the current active status of the HFINTOSC, MFINTOSC and LFINTOSC oscillators. The sequence of a frequency selection is as follows: 1. 2. 3. 4. 5. 6. 7. IRCF<3:0> bits of the OSCCON register are modified. If the new clock is shut down, a clock start-up delay is started. Clock switch circuitry waits for a falling edge of the current clock. The current clock is held low and the clock switch circuitry waits for a rising edge in the new clock. The new clock is now active. The OSCSTAT register is updated as required. Clock switch is complete. See Figure 5-5 for more details. If the internal oscillator speed is switched between two clocks of the same source, there is no start-up delay before the new frequency is selected. Clock switching time delays are shown in Table 5-1. Start-up delay specifications are located in the oscillator tables of Section 35.0 "Electrical Specifications". Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 FIGURE 5-5: HFINTOSC/ MFINTOSC INTERNAL OSCILLATOR SWITCH TIMING LFINTOSC (WDT disabled) HFINTOSC/ MFINTOSC Start-up Time 2-cycle Sync Running 2-cycle Sync Running LFINTOSC IRCF <3:0> 0 0 System Clock HFINTOSC/ MFINTOSC LFINTOSC (WDT enabled) HFINTOSC/ MFINTOSC LFINTOSC 0 IRCF <3:0> 0 System Clock LFINTOSC HFINTOSC/MFINTOSC LFINTOSC turns off unless WDT is enabled LFINTOSC Start-up Time 2-cycle Sync Running HFINTOSC/ MFINTOSC IRCF <3:0> =0 0 System Clock 2014 Microchip Technology Inc. Preliminary DS40001770A-page 83 PIC16(L)F1615/9 5.3 Clock Switching The system clock source can be switched between external and internal clock sources via software using the System Clock Select (SCS) bits of the OSCCON register. The following clock sources can be selected using the SCS bits: When switching between clock sources, a delay is required to allow the new clock to stabilize. These oscillator delays are shown in Table 5-1. * Default system oscillator determined by FOSC bits in Configuration Words * Internal Oscillator Block (INTOSC) 5.3.1 SYSTEM CLOCK SELECT (SCS) BITS The System Clock Select (SCS) bits of the OSCCON register selects the system clock source that is used for the CPU and peripherals. * When the SCS bits of the OSCCON register = 00, the system clock source is determined by value of the FOSC<1:0> bits in the Configuration Words. * When the SCS bits of the OSCCON register = 1x, the system clock source is chosen by the internal oscillator frequency selected by the IRCF<3:0> bits of the OSCCON register. After a Reset, the SCS bits of the OSCCON register are always cleared. TABLE 5-1: OSCILLATOR SWITCHING DELAYS Switch From Switch To (1) Frequency Oscillator Delay Sleep/POR LFINTOSC MFINTOSC(1) HFINTOSC(1) 31 kHz 31.25 kHz-500 kHz 31.25 kHz-16 MHz Oscillator Warm-up Delay (TWARM) Sleep/POR EC(1) DC - 32 MHz 2 cycles LFINTOSC (1) EC DC - 32 MHz 1 cycle of each Any clock source MFINTOSC(1) HFINTOSC(1) 31.25 kHz-500 kHz 31.25 kHz-16 MHz 2 s (approx.) (1) Any clock source LFINTOSC 31 kHz 1 cycle of each PLL inactive PLL active 16-32 MHz 2 ms (approx.) Note 1: PLL inactive. DS40001770A-page 84 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 5.4 Two-Speed Clock Start-up Mode Two-Speed Start-up mode provides additional power savings by minimizing the latency between external oscillator start-up and code execution. In applications that make heavy use of the Sleep mode, Two-Speed Start-up will remove the external oscillator start-up time from the time spent awake and can reduce the overall power consumption of the device. This mode allows the application to wake-up from Sleep, perform a few instructions using the INTOSC internal oscillator block as the clock source and go back to Sleep without waiting for the external oscillator to become stable. Two-Speed Start-up provides benefits when the oscillator module is configured for HS modes. The Oscillator Startup Timer (OST) is enabled for these modes and must count 1024 oscillations before the oscillator can be used as the system clock source. If the oscillator module is configured for any mode other than HS mode, then Two-Speed Start-up is disabled. This is because the external clock oscillator does not require any stabilization time after POR or an exit from Sleep. If the OST count reaches 1024 before the device enters Sleep mode, the OSTS bit of the OSCSTAT register is set and program execution switches to the external oscillator. However, the system may never operate from the external oscillator if the time spent awake is very short. Note: Executing a SLEEP instruction will abort the oscillator start-up time and will cause the OSTS bit of the OSCSTAT register to remain clear. 5.4.1 TWO-SPEED START-UP MODE CONFIGURATION Two-Speed Start-up mode is configured by the following settings: * IESO (of the Configuration Words) = 1; Internal/ External Switchover bit (Two-Speed Start-up mode enabled). * SCS (of the OSCCON register) = 00. * FOSC<2:0> bits in the Configuration Words configured for HS mode. Two-Speed Start-up mode is entered after: * Power-On Reset (POR) and, if enabled, after Power-up Timer (PWRT) has expired, or * Wake-up from Sleep. Note: 5.4.2 1. 2. 3. 4. 5. 6. 7. When FSCM is enabled, Two-Speed Startup will automatically be enabled. TWO-SPEED START-UP SEQUENCE Wake-up from Power-on Reset or Sleep. Instructions begin execution by the internal oscillator at the frequency set in the IRCF<3:0> bits of the OSCCON register. OST enabled to count 1024 clock cycles. OST timed out, wait for falling edge of the internal oscillator. OSTS is set. System clock held low until the next falling edge of new clock (HS mode). System clock is switched to external clock source. 5.4.3 CHECKING TWO-SPEED CLOCK STATUS Checking the state of the OSTS bit of the OSCSTAT register will confirm if the CPU is running from the external clock source, as defined by the FOSC<2:0> bits in the Configuration Words, or the internal oscillator. See Table 5-2. TABLE 5-2: Switch From Any clock source OSCILLATOR SWITCHING DELAYS Switch To Oscillator Delay LFINTOSC 1 cycle of each clock source HFINTOSC 2 s (approx.) ECH, ECM, ECL, EXTRC 2 cycles HS 1024 Clock Cycles (OST) Secondary Oscillator 1024 Secondary Oscillator Cycles 2014 Microchip Technology Inc. Preliminary DS40001770A-page 85 PIC16(L)F1615/9 FIGURE 5-6: TWO-SPEED START-UP INTOSC TOST OSC1 0 1 1022 1023 OSC2 Program Counter PC - N PC + 1 PC System Clock DS40001770A-page 86 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 5.5 5.5.3 Fail-Safe Clock Monitor The Fail-Safe Clock Monitor (FSCM) allows the device to continue operating should the external oscillator or external clock fail. If an oscillator mode is selected, the FSCM can detect oscillator failure any time after the Oscillator Start-up Timer (OST) has expired. When an external clock mode is selected, the FSCM can detect failure as soon as the device is released from Reset. FSCM is enabled by setting the FCMEN bit in the Configuration Words. The FSCM is applicable to external oscillator modes (HS) and external clock modes (ECH, ECM, ECL, EXTRC) and the Secondary Oscillator (SOSC). FIGURE 5-7: FSCM BLOCK DIAGRAM LFINTOSC Oscillator / 64 31 kHz (~32 s) 488 Hz (~2 ms) S Q R Q Sample Clock 5.5.1 The next sections describe how to clear the Fail-Safe condition for specific clock selections (FOSC bits) and clock switching modes (SCS bit settings). 5.5.3.1 When a Fail-Safe condition occurs with the FOSC bits selecting external oscillator (FOSC<2:0> = HS) and the clock switch has been selected to run from the FOSC selection (SCS<1:0> = 00), the condition is cleared by performing the following procedure. Change the SCS bits in the OSCCON register to select the internal oscillator block. This resets the OST timer and allows it to operate again. OSFIF = 0: Clear the OSFIF bit in the PIR2 register. SCS<1:0> = 00: Change the SCS bits in the OSCCON register to select the FOSC Configuration Word clock selection. This will start the OST. The CPU will continue to operate from the internal oscillator until the OST count is reached. When OST expires, the clock module will switch to the external oscillator and the Fail-Safe condition will be cleared. Clock Failure Detected FAIL-SAFE DETECTION FAIL-SAFE OPERATION When the external clock fails, the FSCM switches the CPU clock to an internal clock source and sets the OSFIF bit of the PIR2 register. The internal clock source is determined by the IRCF<3:0> bits in the OSCCON register. If the Fail-Safe condition still exists, the OSFIF bit will again be set by hardware. 5.5.3.2 External Clock with SCS<1:0> = 00 When a Fail-Safe condition occurs with the FOSC bits selecting external clock (FOSC<2:0> = ECH, ECM, ECL, EXTRC) and the clock switch has selected to run from the FOSC selection (SCS<1:0> = 00), the condition is cleared by performing the following procedure. When SCS<1:0> = 00 (Running from FOSC selection) When the OSFIF bit is set, an interrupt will be generated, if the OSFIE bit in the PIE2 register is enabled. The user's firmware in the Interrupt Service Routine (ISR) can then take steps to mitigate the problems that may arise from the failed clock. The system clock will continue to be sourced from the internal clock source until the Fail-Safe condition has been cleared, see Section 5.5.3 "Fail-Safe Condition Clearing". 2014 Microchip Technology Inc. External Oscillator with SCS<1:0> = 00 SCS<1:0> = 1x: The FSCM module detects a failed oscillator by monitoring falling clock edges and using LFINTOSC as a time base. See Figure 5-7. Detection of a failed oscillator will take 32 to 96 cycles of the LFINTOSC. Figure 5-10 shows a timing diagram of the FSCM module. 5.5.2 When a Fail-Safe condition exists, the user must take the following actions to clear the condition before returning to normal operation with the external source. When SCS<1:0> = 00 (Running from FOSC selection) Clock Monitor Latch External Clock FAIL-SAFE CONDITION CLEARING Preliminary SCS<1:0> = 1x: Change the SCS bits in the OSCCON register to select the internal oscillator block. This resets the OST timer and allows it to operate again. OSFIF = 0: Clear the OSFIF bit in the PIR2 register. SCS<1:0> = 00: DS40001770A-page 87 PIC16(L)F1615/9 Change the SCS bits in the OSCCON register to select the FOSC Configuration Word clock selection. Since the OST is not applicable with external clocks, the clock module will immediately switch to the external clock, and the Fail-Safe condition will be cleared. If the Fail-Safe condition still exists, the OSFIF bit will again be set by hardware. 5.5.4 When the FSCM is used with external clocks, the OST is not used and the FSCM will be active as soon as the Reset or wake-up has completed. When the FSCM is enabled, the Two-Speed Start-up is also enabled. Therefore, the device will always be executing code while the OST is operating. Due to the wide range of oscillator start-up times, the Fail-Safe circuit is not active during oscillator start-up (i.e., after exiting Reset or Sleep). Note: RESET OR WAKE-UP FROM SLEEP The FSCM is designed to detect external oscillator or external clock failures. When FSCM is used with an external oscillator, the Oscillator Start-up Timer (OST) count must expire before the FSCM becomes active. The OST is used after waking up from Sleep and after any type of Reset. FIGURE 5-8: FSCM TIMING DIAGRAM Sample Clock Oscillator Failure System Clock Output Clock Monitor Output (Q) Failure Detected OSFIF Test Note: Test Test The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. DS40001770A-page 88 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 5.6 Register Definitions: Oscillator Control REGISTER 5-1: R/W-0/0 OSCCON: OSCILLATOR CONTROL REGISTER R/W-0/0 SPLLEN R/W-1/1 R/W-1/1 R/W-1/1 IRCF<3:0> U-0 R/W-0/0 -- R/W-0/0 SCS<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 SPLLEN: Software PLL Enable bit If PLLEN in Configuration Words = 1: SPLLEN bit is ignored. 4x PLL is always enabled (subject to oscillator requirements) If PLLEN in Configuration Words = 0: 1 = 4x PLL Is enabled 0 = 4x PLL is disabled bit 6-3 IRCF<3:0>: Internal Oscillator Frequency Select bits 1111 =16 MHz HF 1110 =8 MHz HF 1101 =4 MHz HF 1100 =2 MHz HF 1011 =1 MHz HF 1010 =500 kHz HF(1) 1001 =250 kHz HF(1) 1000 =125 kHz HF(1) 0111 =500 kHz MF (default upon Reset) 0110 =250 kHz MF 0101 =125 kHz MF 0100 =62.5 kHz MF 0011 =31.25 kHz HF(1) 0010 =31.25 kHz MF 000x =31 kHz LF bit 2 Unimplemented: Read as `0' bit 1-0 SCS<1:0>: System Clock Select bits 1x = Internal oscillator block 01 = Reserved (defaults to internal oscillator block) 00 = Clock determined by FOSC<1:0> in Configuration Words. Note 1: Duplicate frequency derived from HFINTOSC. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 89 PIC16(L)F1615/9 REGISTER 5-2: OSCSTAT: OSCILLATOR STATUS REGISTER U-0 R-0/q U-0 R-0/q R-0/q R-q/q R-0/q R-0/q -- PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Conditional bit 7 Unimplemented: Read as `0' bit 6 PLLR: 4x PLL Ready bit 1 = 4x PLL is ready 0 = 4x PLL is not ready bit 5 OSTS: Oscillator Start-Up Timer Status bit 1 = Running from the clock defined by the FOSC<2:0> bits of the Configuration Words 0 = Running from an internal oscillator (FOSC<2:0> = 100) bit 4 HFIOFR: High-Frequency Internal Oscillator Ready bit 1 = HFINTOSC is ready 0 = HFINTOSC is not ready bit 3 HFIOFL: High-Frequency Internal Oscillator Locked bit 1 = HFINTOSC is at least 2% accurate 0 = HFINTOSC is not 2% accurate bit 2 MFIOFR: Medium-Frequency Internal Oscillator Ready bit 1 = MFINTOSC is ready 0 = MFINTOSC is not ready bit 1 LFIOFR: Low-Frequency Internal Oscillator Ready bit 1 = LFINTOSC is ready 0 = LFINTOSC is not ready bit 0 HFIOFS: High-Frequency Internal Oscillator Stable bit 1 = HFINTOSC is stable 0 = HFINTOSC is not stable DS40001770A-page 90 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 REGISTER 5-3: OSCTUNE: OSCILLATOR TUNING REGISTER U-0 U-0 -- -- R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 TUN<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 Unimplemented: Read as `0' bit 5-0 TUN<5:0>: Frequency Tuning bits 100000 = Minimum frequency * * * 111111 = 000000 = Oscillator module is running at the factory-calibrated frequency. 000001 = * * * 011110 = 011111 = Maximum frequency TABLE 5-3: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES Name Bit 7 Bit 6 OSCCON SPLLEN OSCSTAT -- PLLR OSCTUNE -- -- Bit 5 Bit 4 Bit 3 Bit 2 -- IRCF<3:0> OSTS HFIOFR HFIOFL MFIOFR Bit 1 Bit 0 SCS<1:0> LFIOFR Register on Page 89 HFIOFS TUN<5:0> 90 91 Legend: -- = unimplemented location, read as `0'. Shaded cells are not used by clock sources. TABLE 5-4: Name CONFIG1 SUMMARY OF CONFIGURATION WORD WITH CLOCK SOURCES Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 13:8 -- -- FCMEN IESO CLKOUTEN 7:0 CP MCLRE PWRTE -- -- Bit 10/2 Bit 9/1 Bit 8/0 BOREN<1:0> -- FOSC<2:0> Register on Page 69 Legend: -- = unimplemented location, read as `0'. Shaded cells are not used by clock sources. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 91 PIC16(L)F1615/9 6.0 RESETS There are multiple ways to reset this device: * * * * * * * * * Power-On Reset (POR) Brown-Out Reset (BOR) Low-Power Brown-Out Reset (LPBOR) MCLR Reset WDT Reset RESET instruction Stack Overflow Stack Underflow Programming mode exit To allow VDD to stabilize, an optional power-up timer can be enabled to extend the Reset time after a BOR or POR event. A simplified block diagram of the On-chip Reset Circuit is shown in Figure 6-1. FIGURE 6-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT Rev. 10-000 006D 1/22/201 4 ICSPTM Programming Mode Exit RESET Instruction Stack Underflow Stack Overflow VPP /MCLR MCLRE Sleep WDT Time-out Power-on Reset VDD BOR Active(1) R Brown-out Reset LFINTOSC LPBOR Reset Note 1: Device Reset WDT Window Violation Power-up Timer PWRTE See Table 6-1 for BOR active conditions. DS40001770A-page 92 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 6.1 Power-On Reset (POR) 6.2 Brown-Out Reset (BOR) The POR circuit holds the device in Reset until VDD has reached an acceptable level for minimum operation. Slow rising VDD, fast operating speeds or analog performance may require greater than minimum VDD. The PWRT, BOR or MCLR features can be used to extend the start-up period until all device operation conditions have been met. The BOR circuit holds the device in Reset when VDD reaches a selectable minimum level. Between the POR and BOR, complete voltage range coverage for execution protection can be implemented. 6.1.1 * * * * POWER-UP TIMER (PWRT) The Power-up Timer provides a nominal 64 ms timeout on POR or Brown-out Reset. The device is held in Reset as long as PWRT is active. The PWRT delay allows additional time for the VDD to rise to an acceptable level. The Power-up Timer is enabled by clearing the PWRTE bit in Configuration Words. The Power-up Timer starts after the release of the POR and BOR. For additional information, refer to Application Note AN607, "Power-up Trouble Shooting" (DS00607). TABLE 6-1: The Brown-out Reset module has four operating modes controlled by the BOREN<1:0> bits in Configuration Words. The four operating modes are: BOR is always on BOR is off when in Sleep BOR is controlled by software BOR is always off Refer to Table 6-1 for more information. The Brown-out Reset voltage level is selectable by configuring the BORV bit in Configuration Words. A VDD noise rejection filter prevents the BOR from triggering on small events. If VDD falls below VBOR for a duration greater than parameter TBORDC, the device will reset. See Figure 6-2 for more information. BOR OPERATING MODES Instruction Execution upon: Release of POR or Wake-up from Sleep BOREN<1:0> SBOREN Device Mode BOR Mode 11 X X Active Waits for BOR ready(1) (BORRDY = 1) Awake Active 10 X Sleep Disabled Waits for BOR ready (BORRDY = 1) Active Waits for BOR ready(1) (BORRDY = 1) X Disabled X Disabled Begins immediately (BORRDY = x) 1 X 0 X 01 00 Note 1: In these specific cases, "release of POR" and "wake-up from Sleep," there is no delay in start-up. The BOR ready flag, (BORRDY = 1), will be set before the CPU is ready to execute instructions because the BOR circuit is forced on by the BOREN<1:0> bits. 6.2.1 BOR IS ALWAYS ON When the BOREN bits of Configuration Words are programmed to `11', the BOR is always on. The device start-up will be delayed until the BOR is ready and VDD is higher than the BOR threshold. BOR protection is active during Sleep. The BOR does not delay wake-up from Sleep. 6.2.2 BOR IS OFF IN SLEEP When the BOREN bits of Configuration Words are programmed to `10', the BOR is on, except in Sleep. The device start-up will be delayed until the BOR is ready and VDD is higher than the BOR threshold. 2014 Microchip Technology Inc. BOR protection is not active during Sleep. The device wake-up will be delayed until the BOR is ready. 6.2.3 BOR CONTROLLED BY SOFTWARE When the BOREN bits of Configuration Words are programmed to `01', the BOR is controlled by the SBOREN bit of the BORCON register. The device start-up is not delayed by the BOR ready condition or the VDD level. BOR protection begins as soon as the BOR circuit is ready. The status of the BOR circuit is reflected in the BORRDY bit of the BORCON register. BOR protection is unchanged by Sleep. Preliminary DS40001770A-page 93 PIC16(L)F1615/9 FIGURE 6-2: BROWN-OUT SITUATIONS VDD VBOR Internal TPWRT(1) Reset VDD VBOR Internal < TPWRT TPWRT(1) Reset VDD VBOR Internal TPWRT(1) Reset Note 1: 6.3 TPWRT delay only if PWRTE bit is programmed to `0'. Register Definitions: BOR Control REGISTER 6-1: BORCON: BROWN-OUT RESET CONTROL REGISTER R/W-1/u R/W-0/u U-0 U-0 U-0 U-0 U-0 R-q/u SBOREN BORFS -- -- -- -- -- BORRDY bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7 SBOREN: Software Brown-Out Reset Enable bit If BOREN <1:0> in Configuration Words = 01: 1 = BOR Enabled 0 = BOR Disabled If BOREN <1:0> in Configuration Words 01: SBOREN is read/write, but has no effect on the BOR bit 6 BORFS: Brown-Out Reset Fast Start bit(1) If BOREN <1:0> = 10 (Disabled in Sleep) or BOREN<1:0> = 01 (Under software control): 1 = Band gap is forced on always (covers sleep/wake-up/operating cases) 0 = Band gap operates normally, and may turn off If BOREN<1:0> = 11 (Always on) or BOREN<1:0> = 00 (Always off) BORFS is Read/Write, but has no effect. bit 5-1 Unimplemented: Read as `0' bit 0 BORRDY: Brown-Out Reset Circuit Ready Status bit 1 = The Brown-out Reset circuit is active 0 = The Brown-out Reset circuit is inactive Note 1: BOREN<1:0> bits are located in Configuration Words. DS40001770A-page 94 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 6.4 Low-Power Brown-Out Reset (LPBOR) 6.6 The Low-Power Brown-Out Reset (LPBOR) operates like the BOR to detect low voltage conditions on the VDD pin. When too low of a voltage is detected, the device is held in Reset. When this occurs, a register bit (BOR) is changed to indicate that a BOR Reset has occurred. The BOR bit in PCON is used for both BOR and the LPBOR. Refer to Register 6-2. The LPBOR voltage threshold (VLPBOR) has a wider tolerance than the BOR (VBOR), but requires much less current (LPBOR current) to operate. The LPBOR is intended for use when the BOR is configured as disabled (BOREN = 00) or disabled in Sleep mode (BOREN = 10). Refer to Figure 6-1 to see how the LPBOR interacts with other modules. 6.4.1 MCLR The MCLR is an optional external input that can reset the device. The MCLR function is controlled by the MCLRE bit of Configuration Words and the LVP bit of Configuration Words (Table 6-2). TABLE 6-2: MCLR CONFIGURATION MCLRE LVP MCLR 0 0 Disabled 1 0 Enabled x 1 Enabled 6.5.1 A RESET instruction will cause a device Reset. The RI bit in the PCON register will be set to `0'. See Table 6-4 for default conditions after a RESET instruction has occurred. Stack Overflow/Underflow Reset The device can reset when the Stack Overflows or Underflows. The STKOVF or STKUNF bits of the PCON register indicate the Reset condition. These Resets are enabled by setting the STVREN bit in Configuration Words. See Section 3.4.2 "Overflow/Underflow Reset" for more information. 6.9 Programming Mode Exit Upon exit of Programming mode, the device will behave as if a POR had just occurred. Power-Up Timer The Power-up Timer is controlled by the PWRTE bit of Configuration Words. MCLR ENABLED A Reset does not drive the MCLR pin low. MCLR DISABLED When MCLR is disabled, the pin functions as a general purpose input and the internal weak pull-up is under software control. See Section 12.1 "PORTA Registers" for more information. 2014 Microchip Technology Inc. RESET Instruction The Power-up Timer optionally delays device execution after a BOR or POR event. This timer is typically used to allow VDD to stabilize before allowing the device to start running. The device has a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. 6.5.2 6.7 6.10 When MCLR is enabled and the pin is held low, the device is held in Reset. The MCLR pin is connected to VDD through an internal weak pull-up. Note: The Watchdog Timer generates a Reset if the firmware does not issue a CLRWDT instruction within the time-out period and the window is open. The TO and PD bits in the STATUS register are changed to indicate a WDT Reset caused by the timer overflowing, and WDTWV bit in the PCON register is changed to indicate a WDT Reset caused by a window violation. See Section 9.0 "Windowed Watchdog Timer (WDT)" for more information. 6.8 ENABLING LPBOR The LPBOR is controlled by the LPBOR bit of Configuration Words. When the device is erased, the LPBOR module defaults to disabled. 6.5 Watchdog Timer (WDT) Reset 6.11 Start-up Sequence Upon the release of a POR or BOR, the following must occur before the device will begin executing: 1. 2. Power-up Timer runs to completion (if enabled). MCLR must be released (if enabled). The total time-out will vary based on oscillator configuration and Power-up Timer configuration. See Section 5.0 "Oscillator Module" for more information. The Power-up Timer runs independently of MCLR Reset. If MCLR is kept low long enough, the Power-up Timer will expire. Upon bringing MCLR high, the device will begin execution after 10 FOSC cycles (see Figure 6-3). This is useful for testing purposes or to synchronize more than one device operating in parallel. Preliminary DS40001770A-page 95 PIC16(L)F1615/9 FIGURE 6-3: RESET START-UP SEQUENCE Rev. 10-000032A 7/30/2013 VDD Internal POR TPWRT Power-up Timer MCLR Internal RESET Int. Oscillator FOSC Begin Execution code execution (1) Internal Oscillator, PWRTEN = 0 code execution (1) Internal Oscillator, PWRTEN = 1 VDD Internal POR TPWRT Power-up Timer MCLR Internal RESET Ext. Clock (EC) FOSC Begin Execution code execution (1) External Clock (EC modes), PWRTEN = 0 code execution (1) External Clock (EC modes), PWRTEN = 1 VDD Internal POR TPWRT Power-up Timer MCLR Internal RESET Osc Start-Up Timer TOST TOST Ext. Oscillator FOSC Begin Execution code execution (1) External Oscillators , PWRTEN = 0, IESO = 0 code execution (1) External Oscillators , PWRTEN = 1, IESO = 0 VDD Internal POR TPWRT Power-up Timer MCLR Internal RESET Osc Start-Up Timer TOST TOST Ext. Oscillator Int. Oscillator FOSC Begin Execution code execution (1) External Oscillators , PWRTEN = 0, IESO = 1 Note 1: code execution (1) External Oscillators , PWRTEN = 1, IESO = 1 Code execution begins 10 FOSC cycles after the FOSC clock is released. DS40001770A-page 96 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 6.12 Determining the Cause of a Reset Upon any Reset, multiple bits in the STATUS and PCON registers are updated to indicate the cause of the Reset. Table 6-3 and Table 6-4 show the Reset conditions of these registers. TABLE 6-3: RESET STATUS BITS AND THEIR SIGNIFICANCE STKOVF STKUNF RWDT 0 0 1 RMCLR RI POR BOR TO PD 1 1 0 x 1 1 Condition Power-on Reset 0 0 1 1 1 0 x 0 x Illegal, TO is set on POR 0 0 1 1 1 0 x x 0 Illegal, PD is set on POR 0 0 u 1 1 u 0 1 1 Brown-out Reset u u 0 u u u u 0 u WDT Reset u u u u u u u 0 0 WDT Wake-up from Sleep u u u u u u u 1 0 Interrupt Wake-up from Sleep u u u 0 u u u u u MCLR Reset during normal operation u u u 0 u u u 1 0 MCLR Reset during Sleep u u u u 0 u u u u RESET Instruction Executed 1 u u u u u u u u Stack Overflow Reset (STVREN = 1) u 1 u u u u u u u Stack Underflow Reset (STVREN = 1) TABLE 6-4: RESET CONDITION FOR SPECIAL REGISTERS Program Counter STATUS Register PCON Register Power-on Reset 0000h ---1 1000 0011 110x MCLR Reset during normal operation 0000h ---u uuuu uuuu 0uuu MCLR Reset during Sleep 0000h ---1 0uuu uuuu 0uuu WDT Reset 0000h ---0 uuuu uuu0 uuuu WDT Wake-up from Sleep PC + 1 ---0 0uuu uuuu uuuu Brown-out Reset 0000h ---1 1uuu 00uu 11u0 Condition Interrupt Wake-up from Sleep PC + 1 (1) ---1 0uuu uuuu uuuu RESET Instruction Executed 0000h ---u uuuu uuuu u0uu Stack Overflow Reset (STVREN = 1) 0000h ---u uuuu 1uuu uuuu Stack Underflow Reset (STVREN = 1) 0000h ---u uuuu u1uu uuuu WDT Window Violation 0000h ---1 uuuu uu0u uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as `0'. Note 1:When the wake-up is due to an interrupt and the Global Interrupt Enable bit (GIE) is set, the return address is pushed on the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 97 PIC16(L)F1615/9 6.13 Power Control (PCON) Register The Power Control (PCON) register contains flag bits to differentiate between a: * * * * * * * Power-On Reset (POR) Brown-Out Reset (BOR) Reset Instruction Reset (RI) MCLR Reset (RMCLR) Watchdog Timer Reset (RWDT) Stack Underflow Reset (STKUNF) Stack Overflow Reset (STKOVF) The PCON register bits are shown in Register 6-2. 6.14 Register Definitions: Power Control REGISTER 6-2: PCON: POWER CONTROL REGISTER R/W/HS-0/q R/W/HS-0/q R/W/HC-1/q R/W/HC-1/q R/W/HC-1/q R/W/HC-1/q R/W/HC-q/u R/W/HC-q/u STKOVF STKUNF WDTWV RWDT RMCLR RI POR BOR bit 7 bit 0 Legend: HC = Bit is cleared by hardware HS = Bit is set by hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7 STKOVF: Stack Overflow Flag bit 1 = A Stack Overflow occurred 0 = A Stack Overflow has not occurred or cleared by firmware bit 6 STKUNF: Stack Underflow Flag bit 1 = A Stack Underflow occurred 0 = A Stack Underflow has not occurred or cleared by firmware bit 5 WDTWV: WDT Window Violation Flag bit 1 = A WDT Window Violation Reset has not occurred or set by firmware 0 = A WDT Window Violation Reset has occurred (a CLRWDT instruction was executed either without arming the window or outside the window (cleared by hardware) bit 4 RWDT: Watchdog Timer Reset Flag bit 1 = A Watchdog Timer Reset has not occurred or set by firmware 0 = A Watchdog Timer Reset has occurred (cleared by hardware) bit 3 RMCLR: MCLR Reset Flag bit 1 = A MCLR Reset has not occurred or set by firmware 0 = A MCLR Reset has occurred (cleared by hardware) bit 2 RI: RESET Instruction Flag bit 1 = A RESET instruction has not been executed or set by firmware 0 = A RESET instruction has been executed (cleared by hardware) bit 1 POR: Power-On Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-Out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset occurs) DS40001770A-page 98 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 TABLE 6-5: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page BORCON SBOREN BORFS -- -- -- -- -- BORRDY 94 PCON STKOVF STKUNF WDTWV RWDT RMCLR RI POR BOR 98 -- -- -- TO PD Z DC C 25 -- -- SEN 124 Name STATUS WDTCON0 Legend: Note 1: TABLE 6-6: Name CONFIG1 CONFIG2 Legend: WDTPS<4:0> -- = unimplemented bit, reads as `0'. Shaded cells are not used by Resets. Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. SUMMARY OF CONFIGURATION WORD WITH RESETS Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 13:8 -- -- FCMEN IESO CLKOUTEN 7:0 CP MCLRE PWRTE -- -- 13:8 -- -- LVP DEBUG LPBOR BORV 7:0 ZCD -- -- -- -- PPS1WAY Bit 9/1 BOREN<1:0> Bit 8/0 -- FOSC<2:0> STVREN PLLEN WRT<1:0> Register on Page 69 71 -- = unimplemented location, read as `0'. Shaded cells are not used by Resets. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 99 PIC16(L)F1615/9 7.0 INTERRUPTS The interrupt feature allows certain events to preempt normal program flow. Firmware is used to determine the source of the interrupt and act accordingly. Some interrupts can be configured to wake the MCU from Sleep mode. This chapter contains the following information for Interrupts: * * * * * Operation Interrupt Latency Interrupts During Sleep INT Pin Automatic Context Saving Many peripherals produce interrupts. Refer to the corresponding chapters for details. A block diagram of the interrupt logic is shown in Figure 7-1. FIGURE 7-1: Interrupt Logic Rev. 10-000010A 1/13/2014 TMR0IF TMR0IE Peripheral Interrupts (TMR1IF) PIR1<0> (TMR1IE) PIE1<0> Wake-up (If in Sleep mode) INTF INTE IOCIF IOCIE Interrupt to CPU PEIE PIRn<7> PIEn<7> DS40001770A-page 100 GIE Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 7.1 Operation 7.2 Interrupts are disabled upon any device Reset. They are enabled by setting the following bits: * GIE bit of the INTCON register * Interrupt Enable bit(s) for the specific interrupt event(s) * PEIE bit of the INTCON register (if the Interrupt Enable bit of the interrupt event is contained in the PIE1, PIE2 and PIE3 registers) Interrupt Latency Interrupt latency is defined as the time from when the interrupt event occurs to the time code execution at the interrupt vector begins. The latency for synchronous interrupts is three or four instruction cycles. For asynchronous interrupts, the latency is three to five instruction cycles, depending on when the interrupt occurs. See Figure 7-2 and Figure 7-3 for more details. The INTCON, PIR1, PIR2 and PIR3 registers record individual interrupts via interrupt flag bits. Interrupt flag bits will be set, regardless of the status of the GIE, PEIE and individual interrupt enable bits. The following events happen when an interrupt event occurs while the GIE bit is set: * Current prefetched instruction is flushed * GIE bit is cleared * Current Program Counter (PC) is pushed onto the stack * Critical registers are automatically saved to the shadow registers (See "Section 7.5 "Automatic Context Saving".") * PC is loaded with the interrupt vector 0004h The firmware within the Interrupt Service Routine (ISR) should determine the source of the interrupt by polling the interrupt flag bits. The interrupt flag bits must be cleared before exiting the ISR to avoid repeated interrupts. Because the GIE bit is cleared, any interrupt that occurs while executing the ISR will be recorded through its interrupt flag, but will not cause the processor to redirect to the interrupt vector. The RETFIE instruction exits the ISR by popping the previous address from the stack, restoring the saved context from the shadow registers and setting the GIE bit. For additional information on a specific interrupt's operation, refer to its peripheral chapter. Note 1: Individual interrupt flag bits are set, regardless of the state of any other enable bits. 2: All interrupts will be ignored while the GIE bit is cleared. Any interrupt occurring while the GIE bit is clear will be serviced when the GIE bit is set again. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 101 PIC16(L)F1615/9 FIGURE 7-2: INTERRUPT LATENCY Fosc Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CLKR Interrupt Sampled during Q1 Interrupt GIE PC Execute PC-1 PC 1-Cycle Instruction at PC PC+1 0004h 0005h NOP NOP Inst(0004h) PC+1/FSR ADDR New PC/ PC+1 0004h 0005h Inst(PC) NOP NOP Inst(0004h) FSR ADDR PC+1 PC+2 0004h 0005h INST(PC) NOP NOP NOP Inst(0004h) Inst(0005h) FSR ADDR PC+1 0004h 0005h INST(PC) NOP NOP Inst(0004h) Inst(PC) Interrupt GIE PC Execute PC-1 PC 2-Cycle Instruction at PC Interrupt GIE PC Execute PC-1 PC 3-Cycle Instruction at PC Interrupt GIE PC Execute PC-1 PC 3-Cycle Instruction at PC DS40001770A-page 102 Preliminary PC+2 NOP NOP 2014 Microchip Technology Inc. PIC16(L)F1615/9 FIGURE 7-3: INT PIN INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 FOSC CLKOUT (3) INT pin (1) (1) INTF Interrupt Latency (2) (4) GIE INSTRUCTION FLOW PC Instruction Fetched Instruction Executed Note 1: PC Inst (PC) Inst (PC - 1) PC + 1 Inst (PC + 1) Inst (PC) PC + 1 -- Forced NOP 0004h 0005h Inst (0004h) Inst (0005h) Forced NOP Inst (0004h) INTF flag is sampled here (every Q1). 2: Asynchronous interrupt latency = 3-5 TCY. Synchronous latency = 3-4 TCY, where TCY = instruction cycle time. Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction. 3: For minimum width of INT pulse, refer to AC specifications in Section 35.0 "Electrical Specifications". 4: INTF is enabled to be set any time during the Q4-Q1 cycles. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 103 PIC16(L)F1615/9 7.3 Interrupts During Sleep Some interrupts can be used to wake from Sleep. To wake from Sleep, the peripheral must be able to operate without the system clock. The interrupt source must have the appropriate Interrupt Enable bit(s) set prior to entering Sleep. On waking from Sleep, if the GIE bit is also set, the processor will branch to the interrupt vector. Otherwise, the processor will continue executing instructions after the SLEEP instruction. The instruction directly after the SLEEP instruction will always be executed before branching to the ISR. Refer to Section 8.0 "PowerDown Mode (Sleep)" for more details. 7.4 INT Pin The INT pin can be used to generate an asynchronous edge-triggered interrupt. This interrupt is enabled by setting the INTE bit of the INTCON register. The INTEDG bit of the OPTION_REG register determines on which edge the interrupt will occur. When the INTEDG bit is set, the rising edge will cause the interrupt. When the INTEDG bit is clear, the falling edge will cause the interrupt. The INTF bit of the INTCON register will be set when a valid edge appears on the INT pin. If the GIE and INTE bits are also set, the processor will redirect program execution to the interrupt vector. 7.5 Automatic Context Saving Upon entering an interrupt, the return PC address is saved on the stack. Additionally, the following registers are automatically saved in the shadow registers: * * * * * W register STATUS register (except for TO and PD) BSR register FSR registers PCLATH register Upon exiting the Interrupt Service Routine, these registers are automatically restored. Any modifications to these registers during the ISR will be lost. If modifications to any of these registers are desired, the corresponding shadow register should be modified and the value will be restored when exiting the ISR. The shadow registers are available in Bank 31 and are readable and writable. Depending on the user's application, other registers may also need to be saved. DS40001770A-page 104 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 7.6 Register Definitions: Interrupt Control REGISTER 7-1: INTCON: INTERRUPT CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0 GIE(1) PEIE(2) TMR0IE INTE IOCIE TMR0IF INTF IOCIF(3) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 GIE: Global Interrupt Enable bit(1) 1 = Enables all active interrupts 0 = Disables all interrupts bit 6 PEIE: Peripheral Interrupt Enable bit(2) 1 = Enables all active peripheral interrupts 0 = Disables all peripheral interrupts bit 5 TMR0IE: Timer0 Overflow Interrupt Enable bit 1 = Enables the Timer0 interrupt 0 = Disables the Timer0 interrupt bit 4 INTE: INT External Interrupt Enable bit 1 = Enables the INT external interrupt 0 = Disables the INT external interrupt bit 3 IOCIE: Interrupt-on-Change Enable bit 1 = Enables the interrupt-on-change 0 = Disables the interrupt-on-change bit 2 TMR0IF: Timer0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed 0 = TMR0 register did not overflow bit 1 INTF: INT External Interrupt Flag bit 1 = The INT external interrupt occurred 0 = The INT external interrupt did not occur bit 0 IOCIF: Interrupt-on-Change Interrupt Flag bit(3) 1 = When at least one of the interrupt-on-change pins changed state 0 = None of the interrupt-on-change pins have changed state Note 1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. 2: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. 3: The IOCIF Flag bit is read-only and cleared when all the interrupt-on-change flags in the IOCxF registers have been cleared by software. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 105 PIC16(L)F1615/9 REGISTER 7-2: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 TMR1GIE: Timer1 Gate Interrupt Enable bit 1 = Enables the Timer1 gate acquisition interrupt 0 = Disables the Timer1 gate acquisition interrupt bit 6 ADIE: Analog-to-Digital Converter (ADC) Interrupt Enable bit 1 = Enables the ADC interrupt 0 = Disables the ADC interrupt bit 5 RCIE: EUSART Receive Interrupt Enable bit 1 = Enables the EUSART receive interrupt 0 = Disables the EUSART receive interrupt bit 4 TXIE: EUSART Transmit Interrupt Enable bit 1 = Enables the EUSART transmit interrupt 0 = Disables the EUSART transmit interrupt bit 3 SSP1IE: Synchronous Serial Port (MSSP) Interrupt Enable bit 1 = Enables the MSSP interrupt 0 = Disables the MSSP interrupt bit 2 CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the Timer2 to PR2 match interrupt 0 = Disables the Timer2 to PR2 match interrupt bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit 1 = Enables the Timer1 overflow interrupt 0 = Disables the Timer1 overflow interrupt Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. DS40001770A-page 106 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 REGISTER 7-3: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 OSFIE C2IE C1IE -- BCL1IE TMR6IE TMR4IE CCP2IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 OSFIE: Oscillator Fail Interrupt Enable bit 1 = Enables the Oscillator Fail interrupt 0 = Disables the Oscillator Fail interrupt bit 6 C2IE: Comparator C2 Interrupt Enable bit 1 = Enables the Comparator C2 interrupt 0 = Disables the Comparator C2 interrupt bit 5 C1IE: Comparator C1 Interrupt Enable bit 1 = Enables the Comparator C1 interrupt 0 = Disables the Comparator C1 interrupt bit 4 Unimplemented: Read as `0' bit 3 BCL1IE: MSSP Bus Collision Interrupt Enable bit 1 = Enables the MSSP Bus Collision Interrupt 0 = Disables the MSSP Bus Collision Interrupt bit 2 TMR6IE: TMR6 to PR6 Match Interrupt Enable bit 1 = Enables the Timer6 to PR6 match interrupt 0 = Disables the Timer6 to PR6 match interrupt bit 1 TMR4IE: TMR4 to PR4 Match Interrupt Enable bit 1 = Enables the Timer4 to PR4 match interrupt 0 = Disables the Timer4 to PR4 match interrupt bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = The CCP2 interrupt is enabled 0 = The CCP2 interrupt is not enabled Note 1: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 107 PIC16(L)F1615/9 REGISTER 7-4: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 -- -- CWGIE ZCDIE CLC4IE CLC3IE CLC2IE CLC1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 Unimplemented: Read as `0' bit 5 CWGIE: Complementary Waveform Generator (CWG) Interrupt Enable bit 1 = Enables the CWG interrupt 0 = Disables the CWG interrupt bit 4 ZCDIE: Zero-Cross Detection (ZCD) Interrupt Enable bit 1 = Enables the ZCD interrupt 0 = Disables the ZCD interrupt bit 3 CLC4IE: Configurable Logic Block 4 Interrupt Enable bit 1 = Enables the CLC 4 interrupt 0 = Disables the CLC 4 interrupt bit 2 CLC3IE: Configurable Logic Block 3 Interrupt Enable bit 1 = Enables the CLC 3 interrupt 0 = Disables the CLC 3 interrupt bit 1 CLC2IE: Configurable Logic Block 2 Interrupt Enable bit 1 = Enables the CLC 2 interrupt 0 = Disables the CLC 2 interrupt bit 0 CLC1IE: Configurable Logic Block 1 Interrupt Enable bit 1 = Enables the CLC 1 interrupt 0 = Disables the CLC 1 interrupt Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. DS40001770A-page 108 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 REGISTER 7-5: PIE4: PERIPHERAL INTERRUPT ENABLE REGISTER 4 R/W-0/0 R/W-0/0 SCANIE CRCIE R/W-0/0 R/W-0/0 SMT2PWAIE SMT2PRAIE R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 SMT2IE SMT1PWAIE SMT1PRAIE SMT1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 SCANIE: Scanner Interrupt Enable bit 1 = Enables the scanner interrupt 0 = Disables the scanner interrupt bit 6 CRCIE: CRC Interrupt Enable bit 1 = Enables the CRC interrupt 0 = Disables the CRC interrupt bit 5 SMT2PWAIE: SMT2 Pulse Width Acquisition Interrupt Enable bit 1 = Enables the SMT acquisition interrupt 0 = Disables the SMT acquisition interrupt bit 4 SMT2PRAIE: SMT2 Period Acquisition Interrupt Enable bit 1 = Enables the SMT acquisition interrupt 0 = Disables the SMT acquisition interrupt bit 3 SMT2IE: SMT2 Match Interrupt Enable bit 1 = Enables the SMT period match interrupt 0 = Disables the SMT period match interrupt bit 2 SMT1PWAIE: SMT1 Pulse Width Acquisition Interrupt Enable bit 1 = Enables the SMT acquisition interrupt 0 = Disables the SMT acquisition interrupt bit 1 SMT1PRAIE: SMT1 Period Acquisition Interrupt Enable bit 1 = Enables the SMT acquisition interrupt 0 = Disables the SMT acquisition interrupt bit 0 SMT1IE: SMT1 Match Interrupt Enable bit 1 = Enables the SMT period match interrupt 0 = Disables the SMT period match interrupt Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 109 PIC16(L)F1615/9 REGISTER 7-6: PIE5: PERIPHERAL INTERRUPT ENABLE REGISTER 5 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 TMR3GIE TMR3IE TMR5GIE TMR5IE -- AT1IE PID1EIE PID1DIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 TMR3GIE: Timer3 Gate Interrupt Enable bit 1 = Enables the Timer3 Gate interrupt 0 = Disables the Timer3 Gate interrupt bit 6 TMR3IE: Timer3 Overflow Interrupt Enable bit 1 = Enables the Timer3 overflow interrupt 0 = Disables the Timer3 overflow interrupt bit 5 TMR5GIE: Timer5 Gate Interrupt Enable bit 1 = Enables the Timer5 Gate interrupt 0 = Disables the Timer5 Gate interrupt bit 4 TMR5IE: Timer5 Overflow Interrupt Enable bit 1 = Enables the Timer5 overflow interrupt 0 = Disables the Timer5 overflow interrupt bit 3 Unimplemented: Read as `0' bit 2 AT1IE: Angular Timer 1 Interrupt Enable bit 1 = Enables the Angular Timer 1 interrupt 0 = Disables the Angular Timer 1 interrupt bit 1 PID1EIE: PID Error Interrupt Enable bit 1 = Enables the PID error interrupt 0 = Disables the PID error interrupt bit 0 PID1DIE: PID Interrupt Enable bit 1 = Enables the PID interrupt 0 = Disables the PID interrupt Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. DS40001770A-page 110 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 REGISTER 7-7: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 TMR1GIE ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 TMR1GIF: Timer1 Gate Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 6 ADIF: ADC Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 5 RCIF: EUSART Receive Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 4 TXIF: EUSART Transmit Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 3 SSP1IF: Synchronous Serial Port (MSSP) Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 2 CCP1IF: CCP1 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 1 TMR2IF: Timer2 to PR2 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 111 PIC16(L)F1615/9 REGISTER 7-8: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 OSFIF C2IF C1IF -- BCL1IF TMR6IF TMR4IF CCP2IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 OSFIF: Oscillator Fail Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 6 C2IF: Comparator C2 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 5 C1IF: Comparator C1 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 4 Unimplemented: Read as `0' bit 3 BCL1IF: MSSP Bus Collision Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 2 TMR6IF: Timer6 to PR6 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 1 TMR4IF: Timer4 to PR4 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 0 CCP2IF: CCP2 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. DS40001770A-page 112 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 REGISTER 7-9: PIR3: PERIPHERAL INTERRUPT REQUEST REGISTER 3 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 -- -- CWGIF ZCDIF CLC4IF CLC3IF CLC2IF CLC1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 Unimplemented: Read as `0' bit 5 CWGIF: CWG Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 4 ZCDIF: ZCD Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 3 CLC4IF: Configurable Logic Block 4 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 2 CLC3IF: Configurable Logic Block 3 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 1 CLC2IF: Configurable Logic Block 2 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 0 CLC1IF: Configurable Logic Block 1 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 113 PIC16(L)F1615/9 REGISTER 7-10: PIR4: PERIPHERAL INTERRUPT REQUEST REGISTER 4 R/W-0/0 R/W-0/0 SCANIF CRCIF R/W-0/0 R/W-0/0 SMT2PWAIF SMT2PRAIF R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 SMT2IF SMT1PWAIF SMT1PRAIF SMT1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 SCANIF: Scanner Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 6 CRCIF: CRC Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 5 SMT2PWAIF: SMT2 Pulse Width Acquisition Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 4 SMT2PRAIF: SMT2 Period Acquisition Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 3 SMT2IF: SMT2 Match Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 2 SMT1PWAIF: SMT1 Pulse Width Acquisition Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 1 SMT1PRAIF: SMT1 Period Acquisition Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 0 SMT1IF: SMT1 Match Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. DS40001770A-page 114 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 REGISTER 7-11: R/W-0/0 PIR5: PERIPHERAL INTERRUPT REQUEST REGISTER 5 R/W-0/0 TMR3GIF R/W-0/0 TMR3IF TMR5GIF R/W-0/0 U-0 R/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 TMR5IF -- AT1IF PID1EIF PID1DIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 TMR3GIF: Timer3 Gate Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 6 TMR3IF: Timer3 Overflow Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 5 TMR5GIF: Timer5 Gate Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 4 TMR5IF: Timer5 Overflow Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 3 Unimplemented: Read as `0' bit 2 AT1IF: Angular Timer 1 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 1 PID1EIF: PID Error Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 0 PID1DIF: PID Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 115 PIC16(L)F1615/9 TABLE 7-1: Name INTCON SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 105 WPUEN INTEDG TMR0CS TMR0SE PSA PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 106 PIE2 OSFIE C2IE C1IE -- BCL1IE TMR6IE TMR4IE CCP2IE 107 PIE3 -- -- CWGIE ZCDIE CLC4IE CLC3IE CLC2IE CLC1IE 108 PIE4 SCANIE CRCIE SMT2PWAIE SMT2PRAIE SMT2IE SMT1IF 109 PIE5 TMR3GIE TMR3IE TMR5GIE TMR5IE -- AT1IE PID1EIE PID1DIE 110 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 111 PIR2 OSFIF C2IF C1IF -- BCL1IF TMR6IF TMR4IF CCP2IF 112 CLC3IF CLC2IF OPTION_REG PIR3 -- -- CWGIF ZCDIF CLC4IF PIR4 SCANIF CRCIF SMT2PWAIF SMT2PRAIF SMT2IF PIR5 TMR3GIF TMR3IF TMR5GIF TMR5IF -- Legend: PS<2:0> SMT1PWAIE SMT1PRAIE SMT1PWAIF SMT1PRAIF AT1IF PID1EIF 231 CLC1IF 113 SMT1IF 114 PID1DIF 115 -- = unimplemented location, read as `0'. Shaded cells are not used by interrupts. DS40001770A-page 116 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 8.0 POWER-DOWN MODE (SLEEP) The Power-Down mode is entered by executing a SLEEP instruction. Upon entering Sleep mode, the following conditions exist: 1. WDT will be cleared but keeps running, if enabled for operation during Sleep. PD bit of the STATUS register is cleared. TO bit of the STATUS register is set. CPU clock is disabled. 31 kHz LFINTOSC is unaffected and peripherals that operate from it may continue operation in Sleep. Timer1 and peripherals that operate from Timer1 continue operation in Sleep when the Timer1 clock source selected is: * LFINTOSC * T1CKI * Timer1 oscillator ADC is unaffected, if the dedicated FRC oscillator is selected. I/O ports maintain the status they had before SLEEP was executed (driving high, low or highimpedance). Resets other than WDT are not affected by Sleep mode. 2. 3. 4. 5. 6. 7. 8. 9. Refer to individual chapters for more details on peripheral operation during Sleep. To minimize current consumption, the following conditions should be considered: * * * * * * I/O pins should not be floating External circuitry sinking current from I/O pins Internal circuitry sourcing current from I/O pins Current draw from pins with internal weak pull-ups Modules using 31 kHz LFINTOSC CWG modules using HFINTOSC I/O pins that are high-impedance inputs should be pulled to VDD or VSS externally to avoid switching currents caused by floating inputs. Examples of internal circuitry that might be sourcing current include the FVR module. See Section 15.0 "Fixed Voltage Reference (FVR)" for more information on this module. 8.1 Wake-up from Sleep The device can wake-up from Sleep through one of the following events: 1. External Reset input on MCLR pin, if enabled 2. BOR Reset, if enabled 3. POR Reset 4. Watchdog Timer, if enabled 5. Any external interrupt 2014 Microchip Technology Inc. 6. Interrupts by peripherals capable of running during Sleep (see individual peripheral for more information) The first three events will cause a device Reset. The last three events are considered a continuation of program execution. To determine whether a device Reset or wake-up event occurred, refer to Section 6.12 "Determining the Cause of a Reset". When the SLEEP instruction is being executed, the next instruction (PC + 1) is prefetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be enabled. Wake-up will occur regardless of the state of the GIE bit. If the GIE bit is disabled, the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is enabled, the device executes the instruction after the SLEEP instruction, the device will then call the Interrupt Service Routine. In cases where the execution of the instruction following SLEEP is not desirable, the user should have a NOP after the SLEEP instruction. The WDT is cleared when the device wakes up from Sleep, regardless of the source of wake-up. 8.1.1 WAKE-UP USING INTERRUPTS When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: * If the interrupt occurs before the execution of a SLEEP instruction - SLEEP instruction will execute as a NOP - WDT and WDT prescaler will not be cleared - TO bit of the STATUS register will not be set - PD bit of the STATUS register will not be cleared * If the interrupt occurs during or after the execution of a SLEEP instruction - SLEEP instruction will be completely executed - Device will immediately wake-up from Sleep - WDT and WDT prescaler will be cleared - TO bit of the STATUS register will be set - PD bit of the STATUS register will be cleared Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. Preliminary DS40001770A-page 117 PIC16(L)F1615/9 FIGURE 8-1: WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CLKIN(1) T1OSC(3) CLKOUT(2) Interrupt flag Interrupt Latency (4) GIE bit (INTCON reg.) Instruction Flow PC Instruction Fetched Instruction Executed Note 8.2 1: 2: 3: 4: Processor in Sleep PC Inst(PC) = Sleep Inst(PC - 1) PC + 1 PC + 2 PC + 2 Inst(PC + 1) Inst(PC + 2) Sleep Inst(PC + 1) PC + 2 Forced NOP 0004h 0005h Inst(0004h) Inst(0005h) Forced NOP Inst(0004h) External clock. High, Medium, Low mode assumed. CLKOUT is shown here for timing reference. T1OSC; See Section 35.0 "Electrical Specifications". GIE = 1 assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line. 8.2.2 Low-Power Sleep Mode PERIPHERAL USAGE IN SLEEP This device contains an internal Low Dropout (LDO) voltage regulator, which allows the device I/O pins to operate at voltages up to 5.5V while the internal device logic operates at a lower voltage. The LDO and its associated reference circuitry must remain active when the device is in Sleep mode. Some peripherals that can operate in Sleep mode will not operate properly with the Low-Power Sleep mode selected. The LDO will remain in the Normal-Power mode when those peripherals are enabled. The LowPower Sleep mode is intended for use with these peripherals: Low-Power Sleep mode allows the user to optimize the operating current in Sleep. Low-Power Sleep mode can be selected by setting the VREGPM bit of the VREGCON register, putting the LDO and reference circuitry in a low-power state whenever the device is in Sleep. * * * * 8.2.1 SLEEP CURRENT VS. WAKE-UP TIME In the Default Operating mode, the LDO and reference circuitry remain in the normal configuration while in Sleep. The device is able to exit Sleep mode quickly since all circuits remain active. In Low-Power Sleep mode, when waking up from Sleep, an extra delay time is required for these circuits to return to the normal configuration and stabilize. The Low-Power Sleep mode is beneficial for applications that stay in Sleep mode for long periods of time. The Normal mode is beneficial for applications that need to wake from Sleep quickly and frequently. DS40001770A-page 118 Brown-Out Reset (BOR) Watchdog Timer (WDT) External interrupt pin/Interrupt-on-change pins Timer1 (with external clock source) The Complementary Waveform Generator (CWG) can utilize the HFINTOSC oscillator as either a clock source or as an input source. Under certain conditions, when the HFINTOSC is selected for use with the CWG modules, the HFINTOSC will remain active during Sleep. This will have a direct effect on the Sleep mode current. Please refer to sections Section 28.11 "Operation During Sleep" for more information. Note: Preliminary The PIC16LF1615/9 does not have a configurable Low-Power Sleep mode. PIC16LF1615/9 is an unregulated device and is always in the lowest power state when in Sleep, with no wake-up time penalty. This device has a lower maximum VDD and I/O voltage than the PIC16F1615/9. See Section 35.0 "Electrical Specifications" for more information. 2014 Microchip Technology Inc. PIC16(L)F1615/9 8.3 Register Definitions: Voltage Regulator Control VREGCON: VOLTAGE REGULATOR CONTROL REGISTER(1) REGISTER 8-1: U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-1/1 -- -- -- -- -- -- VREGPM Reserved bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-2 Unimplemented: Read as `0' bit 1 VREGPM: Voltage Regulator Power Mode Selection bit 1 = Low-Power Sleep mode enabled in Sleep(2) Draws lowest current in Sleep, slower wake-up 0 = Normal Power mode enabled in Sleep(2) Draws higher current in Sleep, faster wake-up bit 0 Reserved: Read as `1'. Maintain this bit set. Note 1: 2: PIC16F1615/9 only. See Section 35.0 "Electrical Specifications". TABLE 8-1: SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE Name Bit 7 Bit 6 Bit 5 INTCON Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 105 IOCAF -- -- IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 188 IOCAN -- -- IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 188 IOCAP -- -- IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 188 IOCCP IOCCP7(1) IOCCP6(1) IOCCP5 IOCCP4 IOCCP3 IOCCP2 IOCCP1 IOCCP0 188 IOCCN IOCCN7(1) IOCCN6(1) IOCCN5 IOCCN4 IOCCN3 IOCCN2 IOCCN1 IOCCN0 188 IOCCF IOCCF7(1) IOCCF6(1) IOCCF5 IOCCF4 IOCCF3 IOCCF2 IOCCF1 IOCCF0 188 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 106 PIE2 OSFIE C2IE C1IE -- BCL1IE TMR6IE TMR4IE CCP2IE 107 CLC3IE CLC2IE PIE3 -- -- CWGIE ZCDIE CLC4IE PIE4 SCANIE CRCIE SMT2PWAIE SMT2PRAIE SMT2IE PIE5 TMR3GIE TMR3IE TMR5GIE TMR5IE -- AT1IE PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF PIR2 OSFIF C2IF C1IF -- BCL1IF PIR3 -- -- CWGIF ZCDIF CLC4IF SMT2IF 108 109 PID1EIE PID1DIE 110 TMR2IF TMR1IF 111 TMR6IF TMR4IF CCP2IF 112 CLC3IF CLC2IF CLC1IF 113 PIR4 SCANIF CRCIF SMT1IF 114 PIR5 TMR3GIF TMR3IF TMR5GIF TMR5IF -- AT1IF PID1EIF PID1DIF 115 STATUS -- -- -- TO PD Z DC C 25 WDTCON0 -- -- SEN 124 Legend: Note 1: SMT2PWAIF SMT2PRAIF CLC1IE SMT1IF SMT1PWAIE SMT1PRAIE SMT1PWAIF SMT1PRAIF WDTPS<4:0> -- = unimplemented, read as `0'. Shaded cells are not used in Power-Down mode. PIC16(L)F1619 only. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 119 PIC16(L)F1615/9 9.0 WINDOWED WATCHDOG TIMER (WDT) The Watchdog Timer (WDT) is a system timer that generates a Reset if the firmware does not issue a CLRWDT instruction within the time-out period. The Watchdog Timer is typically used to recover the system from unexpected events. The Windowed Watchdog Timer (WDT) differs in that CLRWDT instructions are only accepted when they are performed within a specific window during the time-out period. The WDT has the following features: * Selectable clock source * Multiple operating modes - WDT is always on - WDT is off when in Sleep - WDT is controlled by software - WDT is always off * Configurable time-out period is from 1 ms to 256 seconds (nominal) * Configurable window size from 12.5 to 100 percent of the time-out period * Multiple Reset conditions * Operation during Sleep DS40001770A-page 120 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 FIGURE 9-1: WATCHDOG TIMER BLOCK DIAGRAM Rev. 10-000 162A 1/2/201 4 WWDT Armed WDT Window Violation Window Closed Window Sizes CLRWDT Comparator WINDOW RESET Reserved 111 Reserved 110 Reserved 101 Reserved 100 Reserved 011 Reserved 010 MFINTOSC/16 001 LFINTOSC 000 R 18-bit Prescale Counter E WDTCS WDTPS R 5-bit WDT Counter Overflow Latch WDT Time-out WDTE<1:0> = 01 SEN WDTE<1:0> = 11 WDTE<1:0> = 10 Sleep 2014 Microchip Technology Inc. Preliminary DS40001770A-page 121 PIC16(L)F1615/9 9.1 Independent Clock Source 9.4 Watchdog Window The WDT can derive its time base from either the 31 kHz LFINTOSC or 31.25 kHz MFINTOSC internal oscillators, depending on the value of either the WDTCCS<2:0> configuration bits or the WDTCS<2:0> bits of WDTCON1. Time intervals in this chapter are based on a minimum nominal interval of 1 ms. See Section 35.0 "Electrical Specifications" for LFINTOSC and MFINTOSC tolerances. The Watchdog Timer has an optional Windowed mode that is controlled by the WDTCWS<2:0> Configuration bits and WINDOW<2:0> bits of the WDTCON1 register. In the Windowed mode, the CLRWDT instruction must occur within the allowed window of the WDT period. Any CLRWDT instruction that occurs outside of this window will trigger a window violation and will cause a WDT Reset, similar to a WDT time out. See Figure 9-2 for an example. 9.2 The window size is controlled by the WDTCWS<2:0> Configuration bits, or the WINDOW<2:0> bits of WDTCON1, if WDTCWS<2:0> = 111. WDT Operating Modes The Watchdog Timer module has four operating modes controlled by the WDTE<1:0> bits in Configuration Words. See Table 9-1. 9.2.1 WDT IS ALWAYS ON When the WDTE bits of Configuration Words are set to `11', the WDT is always on. WDT protection is active during Sleep. 9.2.2 9.5 Clearing the WDT The WDT is cleared when any of the following conditions occur: WDT IS OFF IN SLEEP When the WDTE bits of Configuration Words are set to `10', the WDT is on, except in Sleep. WDT protection is not active during Sleep. 9.2.3 In the event of a window violation, a Reset will be generated and the WDTWV bit of the PCON register will be cleared. This bit is set by a POR or can be set in firmware. WDT CONTROLLED BY SOFTWARE When the WDTE bits of Configuration Words are set to `01', the WDT is controlled by the SEN bit of the WDTCON0 register. * * * * * * * Any Reset Valid CLRWDT instruction is executed Device enters Sleep Device wakes up from Sleep WDT is disabled Oscillator Start-up Timer (OST) is running Any write to the WDTCON0 or WDTCON1 registers WDT protection is unchanged by Sleep. See Table 9-1 for more details. 9.5.1 TABLE 9-1: When in Windowed mode, the WDT must be armed before a CLRWDT instruction will clear the timer. This is performed by reading the WDTCON0 register. Executing a CLRWDT instruction without performing such an arming action will trigger a window violation. WDT OPERATING MODES WDTE<1:0> SEN Device Mode WDT Mode 11 X X Active Awake Active Sleep Disabled 1 X Active 0 X Disabled X X Disabled 10 X 01 00 9.3 Time-Out Period The WDTPS bits of the WDTCON0 register set the time-out period from 1 ms to 256 seconds (nominal). After a Reset, the default time-out period is two seconds. DS40001770A-page 122 CLRWDT CONSIDERATIONS (WINDOWED MODE) See Table 9-2 for more information. 9.6 Operation During Sleep When the device enters Sleep, the WDT is cleared. If the WDT is enabled during Sleep, the WDT resumes counting. When the device exits Sleep, the WDT is cleared again. The WDT remains clear until the OST, if enabled, completes. See Section 5.0 "Oscillator Module" for more information on the OST. When a WDT time-out occurs while the device is in Sleep, no Reset is generated. Instead, the device wakes up and resumes operation. The TO and PD bits in the STATUS register are changed to indicate the event. The RWDT bit in the PCON register can also be used. See Section 3.0 "Memory Organization" for more information. Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 TABLE 9-2: WDT CLEARING CONDITIONS Conditions WDT WDTE<1:0> = 00 WDTE<1:0> = 01 and SEN = 0 WDTE<1:0> = 10 and enter Sleep Cleared CLRWDT Command Oscillator Fail Detected Exit Sleep + System Clock = T1OSC, EXTRC, INTOSC, EXTCLK Exit Sleep + System Clock = HS Cleared until the end of OST Change INTOSC divider (IRCF bits) FIGURE 9-2: Unaffected WINDOW PERIOD AND DELAY Rev. 10-000 163A 11/8/201 3 CLRWDT Instruction (or other WDT reset) Window Period Window Closed Window Open Window Delay (window violation can occur) 2014 Microchip Technology Inc. Preliminary Time-out Event DS40001770A-page 123 PIC16(L)F1615/9 9.7 Register Definitions: Windowed Watchdog Timer Control REGISTER 9-1: WDTCON0: WATCHDOG TIMER CONTROL REGISTER 0 U-0 U-0 -- -- R/W(3)-q/q(2) R/W(3)-q/q(2) R/W(3)-q/q(2) R/W(3)-q/q(2) R/W(3)-q/q(2) WDTPS<4:0> (1) R/W-0/0 SEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-6 Unimplemented: Read as `0' bit 5-1 WDTPS<4:0>: Watchdog Timer Prescale Select bits(1) Bit Value = Prescale Rate 11111 = Reserved. Results in minimum interval (1:32) * * * 10011 = Reserved. Results in minimum interval (1:32) 10010 10001 10000 01111 01110 01101 01100 01011 01010 01001 01000 00111 00110 00101 00100 00011 00010 00001 00000 bit 0 = = = = = = = = = = = = = = = = = = = 1:8388608 (223) (Interval 256s nominal) 1:4194304 (222) (Interval 128s nominal) 1:2097152 (221) (Interval 64s nominal) 1:1048576 (220) (Interval 32s nominal) 1:524288 (219) (Interval 16s nominal) 1:262144 (218) (Interval 8s nominal) 1:131072 (217) (Interval 4s nominal) 1:65536 (Interval 2s nominal) (Reset value) 1:32768 (Interval 1s nominal) 1:16384 (Interval 512 ms nominal) 1:8192 (Interval 256 ms nominal) 1:4096 (Interval 128 ms nominal) 1:2048 (Interval 64 ms nominal) 1:1024 (Interval 32 ms nominal) 1:512 (Interval 16 ms nominal) 1:256 (Interval 8 ms nominal) 1:128 (Interval 4 ms nominal) 1:64 (Interval 2 ms nominal) 1:32 (Interval 1 ms nominal) SEN: Software Enable/Disable for Watchdog Timer bit If WDTE<1:0> = 1x: This bit is ignored. If WDTE<1:0> = 01: 1 = WDT is turned on 0 = WDT is turned off If WDTE<1:0> = 00: This bit is ignored. Note 1: 2: 3: Times are approximate. WDT time is based on 31 kHz LFINTOSC. When WDTCPS <4:0> in CONFIG3 = 11111, the Reset value of WDTPS<4:0> is 01011. Otherwise, the Reset value of WDTPS<4:0> is equal to WDTCPS<4:0> in CONFIG3. When WDTCPS <4:0> in CONFIG3 11111, these bits are read-only. DS40001770A-page 124 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 REGISTER 9-2: WDTCON1: WATCHDOG TIMER CONTROL REGISTER 1 U-0 R/W(3)-q/q(1) R/W(3)-q/q(1) R/W(3)-q/q(1) U-0 -- WDTCS<2:0> -- R/W(4)-q/q(2) R/W(4)-q/q(2) R/W(4)-q/q(2) WINDOW<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7 Unimplemented: Read as `0' bit 6-4 WDTCS<2:0>: Watchdog Timer Clock Select bits 111 = Reserved * * * 010 = Reserved 001 = MFINTOSC 31.25 kHz 000 = LFINTOSC 31 kHz bit 3 Unimplemented: Read as `0' bit 2-0 WINDOW<2:0>: Watchdog Timer Window Select bits WINDOW<2:0> Note 1: 2: 3: 4: Window delay Percent of time Window opening Percent of time 111 N/A 100 110 12.5 87.5 101 25 75 100 37.5 62.5 011 50 50 010 62.5 37.5 001 75 25 000 87.5 12.5 If WDTCCS <2:0> in CONFIG3 = 111, the Reset value of WDTCS<2:0> is 000. The Reset value of WINDOW<2:0> is determined by the value of WDTCWS<2:0> in the CONFIG3 register. If WDTCCS<2:0> in CONFIG3 111, these bits are read-only. If WDTCWS<2:0> in CONFIG3 111, these bits are read-only. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 125 PIC16(L)F1615/9 REGISTER 9-3: R-0/0 WDTPSL: WDT PRESCALE SELECT LOW BYTE REGISTER (READ ONLY) R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 PSCNT<7:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared PSCNT<7:0>: Prescale Select Low Byte bits(1) bit 7-0 Note 1: The 18-bit WDT prescale value, PSCNT<17:0> includes the WDTPSL, WDTPSH and the lower bits of the WDTTMR registers. PSCNT<17:0> is intended for debug operations and should be read during normal operation. REGISTER 9-4: R-0/0 WDTPSH: WDT PRESCALE SELECT HIGH BYTE REGISTER (READ ONLY) R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 (1) PSCNT<15:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared PSCNT<15:8>: Prescale Select High Byte bits(1) bit 7-0 Note 1: The 18-bit WDT prescale value, PSCNT<17:0> includes the WDTPSL, WDTPSH and the lower bits of the WDTTMR registers. PSCNT<17:0> is intended for debug operations and should be read during normal operation. REGISTER 9-5: R-0/0 WDTTMR: WDT TIMER REGISTER (READ ONLY) R-0/0 R-0/0 R-0/0 R-0/0 WDTTMR<3:0> R-0/0 R-0/0 R-0/0 PSCNT<17:16>(1) STATE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-3 WDTTMR<4:0>: Watchdog Timer Value bit 2 STATE: WDT Armed Status bit 1 = WDT is armed 0 = WDT is not armed bit 1-0 PSCNT<17:16>: Prescale Select Upper Byte bits(1) Note 1: The 18-bit WDT prescale value, PSCNT<17:0> includes the WDTPSL, WDTPSH and the lower bits of the WDTTMR registers. PSCNT<17:0> is intended for debug operations and should be read during normal operation. DS40001770A-page 126 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 TABLE 9-3: Name SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 IRCF<3:0> Bit 2 Bit 1 Bit 0 Register on Page OSCCON SPLLEN PCON STKOVF STKUNF WDTWV RWDT RMCLR RI POR BOR STATUS -- -- -- TO PD Z DC C 25 WDTCON0 -- -- SEN 124 WDTCON1 -- 98 124 WINDOW<2:0> 124 PSCNT<15:8> WDTTMR<4:0> -- 124 STATE PSCNT<17:16> 124 x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by Watchdog Timer. TABLE 9-4: Legend: 89 PSCNT<7:0> WDTTMR CONFIG1 -- WDTCS<2:0> WDTPSH Name SCS<1:0> WDTPS<4:0> WDTPSL Legend: -- SUMMARY OF CONFIGURATION WORD WITH WATCHDOG TIMER Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 13:8 -- -- FCMEN IESO CLKOUTEN 7:0 CP MCLRE PWRTE -- -- Bit 10/2 Bit 9/1 Bit 8/0 BOREN<1:0> -- FOSC<2:0> Register on Page 69 -- = unimplemented location, read as `0'. Shaded cells are not used by Watchdog Timer. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 127 PIC16(L)F1615/9 10.0 FLASH PROGRAM MEMORY CONTROL The Flash program memory is readable and writable during normal operation over the full VDD range. Program memory is indirectly addressed using Special Function Registers (SFRs). The SFRs used to access program memory are: * * * * * * PMCON1 PMCON2 PMDATL PMDATH PMADRL PMADRH Control bits RD and WR initiate read and write, respectively. These bits cannot be cleared, only set, in software. They are cleared by hardware at completion of the read or write operation. The inability to clear the WR bit in software prevents the accidental, premature termination of a write operation. The WREN bit, when set, will allow a write operation to occur. On power-up, the WREN bit is clear. The WRERR bit is set when a write operation is interrupted by a Reset during normal operation. In these situations, following Reset, the user can check the WRERR bit and execute the appropriate error handling routine. The PMCON2 register is a write-only register. Attempting to read the PMCON2 register will return all `0's. When accessing the program memory, the PMDATH:PMDATL register pair forms a 2-byte word that holds the 14-bit data for read/write, and the PMADRH:PMADRL register pair forms a 2-byte word that holds the 15-bit address of the program memory location being read. The write time is controlled by an on-chip timer. The write/ erase voltages are generated by an on-chip charge pump rated to operate over the operating voltage range of the device. The Flash program memory can be protected in two ways; by code protection (CP bit in Configuration Words) and write protection (WRT<1:0> bits in Configuration Words). Code protection (CP = 0)(1), disables access, reading and writing, to the Flash program memory via external device programmers. Code protection does not affect the self-write and erase functionality. Code protection can only be reset by a device programmer performing a Bulk Erase to the device, clearing all Flash program memory, Configuration bits and User IDs. To enable writes to the program memory, a specific pattern (the unlock sequence), must be written to the PMCON2 register. The required unlock sequence prevents inadvertent writes to the program memory write latches and Flash program memory. 10.2 It is important to understand the Flash program memory structure for erase and programming operations. Flash program memory is arranged in rows. A row consists of a fixed number of 14-bit program memory words. A row is the minimum size that can be erased by user software. After a row has been erased, the user can reprogram all or a portion of this row. Data to be written into the program memory row is written to 14-bit wide data write latches. These write latches are not directly accessible to the user, but may be loaded via sequential writes to the PMDATH:PMDATL register pair. Note: Write protection prohibits self-write and erase to a portion or all of the Flash program memory, as defined by the bits WRT<1:0>. Write protection does not affect a device programmers ability to read, write or erase the device. Note 1: Code protection of the entire Flash program memory array is enabled by clearing the CP bit of Configuration Words. 10.1 PMADRL and PMADRH Registers The PMADRH:PMADRL register pair can address up to a maximum of 16K words of program memory. When selecting a program address value, the MSB of the address is written to the PMADRH register and the LSB is written to the PMADRL register. 10.1.1 PMCON1 AND PMCON2 REGISTERS If the user wants to modify only a portion of a previously programmed row, then the contents of the entire row must be read and saved in RAM prior to the erase. Then, new data and retained data can be written into the write latches to reprogram the row of Flash program memory. However, any unprogrammed locations can be written without first erasing the row. In this case, it is not necessary to save and rewrite the other previously programmed locations. See Table 10-1 for Erase Row size and the number of write latches for Flash program memory. TABLE 10-1: Device PIC16(L)F1615 PMCON1 is the control register for Flash program memory accesses. DS40001770A-page 128 Flash Program Memory Overview PIC16(L)F1619 Preliminary FLASH MEMORY ORGANIZATION BY DEVICE Row Erase (words) Write Latches (words) 32 32 2014 Microchip Technology Inc. PIC16(L)F1615/9 10.2.1 READING THE FLASH PROGRAM MEMORY FIGURE 10-1: To read a program memory location, the user must: 1. 2. 3. Write the desired address to the PMADRH:PMADRL register pair. Clear the CFGS bit of the PMCON1 register. Then, set control bit RD of the PMCON1 register. Once the read control bit is set, the program memory Flash controller will use the second instruction cycle to read the data. This causes the second instruction immediately following the "BSF PMCON1,RD" instruction to be ignored. The data is available in the very next cycle, in the PMDATH:PMDATL register pair; therefore, it can be read as two bytes in the following instructions. PMDATH:PMDATL register pair will hold this value until another read or until it is written to by the user. Note: The two instructions following a program memory read are required to be NOPs. This prevents the user from executing a 2cycle instruction on the next instruction after the RD bit is set. FLASH PROGRAM MEMORY READ FLOWCHART Rev. 10-000046A 7/30/2013 Start Read Operation Select Program or Configuration Memory (CFGS) Select Word Address (PMADRH:PMADRL) Initiate Read operation (RD = 1) Instruction fetched ignored NOP execution forced Instruction fetched ignored NOP execution forced Data read now in PMDATH:PMDATL End Read Operation 2014 Microchip Technology Inc. Preliminary DS40001770A-page 129 PIC16(L)F1615/9 FIGURE 10-2: FLASH PROGRAM MEMORY READ CYCLE EXECUTION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC Flash ADDR Flash Data PC + 1 INSTR (PC) INSTR(PC - 1) executed here PMADRH,PMADRL INSTR (PC + 1) BSF PMCON1,RD executed here PC +3 PC+3 PMDATH,PMDATL INSTR(PC + 1) instruction ignored Forced NOP executed here PC + 5 PC + 4 INSTR (PC + 3) INSTR(PC + 2) instruction ignored Forced NOP executed here INSTR (PC + 4) INSTR(PC + 3) executed here INSTR(PC + 4) executed here RD bit PMDATH PMDATL Register EXAMPLE 10-1: FLASH PROGRAM MEMORY READ * This code block will read 1 word of program * memory at the memory address: PROG_ADDR_HI: PROG_ADDR_LO * data will be returned in the variables; * PROG_DATA_HI, PROG_DATA_LO BANKSEL MOVLW MOVWF MOVLW MOVWF PMADRL PROG_ADDR_LO PMADRL PROG_ADDR_HI PMADRH ; Select Bank for PMCON registers ; ; Store LSB of address ; ; Store MSB of address BCF BSF NOP NOP PMCON1,CFGS PMCON1,RD ; ; ; ; Do not select Configuration Space Initiate read Ignored (Figure 10-2) Ignored (Figure 10-2) MOVF MOVWF MOVF MOVWF PMDATL,W PROG_DATA_LO PMDATH,W PROG_DATA_HI ; ; ; ; Get LSB of word Store in user location Get MSB of word Store in user location DS40001770A-page 130 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 10.2.2 FLASH MEMORY UNLOCK SEQUENCE FIGURE 10-3: The unlock sequence is a mechanism that protects the Flash program memory from unintended self-write programming or erasing. The sequence must be executed and completed without interruption to successfully complete any of the following operations: FLASH PROGRAM MEMORY UNLOCK SEQUENCE FLOWCHART Rev. 10-000047A 7/30/2013 Start Unlock Sequence * Row Erase * Load program memory write latches * Write of program memory write latches to program memory * Write of program memory write latches to User IDs Write 0x55 to PMCON2 The unlock sequence consists of the following steps: 1. Write 55h to PMCON2 Write 0xAA to PMCON2 2. Write AAh to PMCON2 3. Set the WR bit in PMCON1 4. NOP instruction 5. NOP instruction Once the WR bit is set, the processor will always force two NOP instructions. When an Erase Row or Program Row operation is being performed, the processor will stall internal operations (typical 2 ms), until the operation is complete and then resume with the next instruction. When the operation is loading the program memory write latches, the processor will always force the two NOP instructions and continue uninterrupted with the next instruction. Since the unlock sequence must not be interrupted, global interrupts should be disabled prior to the unlock sequence and re-enabled after the unlock sequence is completed. 2014 Microchip Technology Inc. Preliminary Initiate Write or Erase operation (WR = 1) Instruction fetched ignored NOP execution forced Instruction fetched ignored NOP execution forced End Unlock Sequence DS40001770A-page 131 PIC16(L)F1615/9 10.2.3 ERASING FLASH PROGRAM MEMORY FIGURE 10-4: While executing code, program memory can only be erased by rows. To erase a row: 1. 2. 3. 4. 5. Load the PMADRH:PMADRL register pair with any address within the row to be erased. Clear the CFGS bit of the PMCON1 register. Set the FREE and WREN bits of the PMCON1 register. Write 55h, then AAh, to PMCON2 (Flash programming unlock sequence). Set control bit WR of the PMCON1 register to begin the erase operation. See Example 10-2. After the "BSF PMCON1,WR" instruction, the processor requires two cycles to set up the erase operation. The user must place two NOP instructions immediately following the WR bit set instruction. The processor will halt internal operations for the typical 2 ms erase time. This is not Sleep mode as the clocks and peripherals will continue to run. After the erase cycle, the processor will resume operation with the third instruction after the PMCON1 write instruction. FLASH PROGRAM MEMORY ERASE FLOWCHART Rev. 10-000048A 7/30/2013 Start Erase Operation Disable Interrupts (GIE = 0) Select Program or Configuration Memory (CFGS) Select Row Address (PMADRH:PMADRL) Select Erase Operation (FREE = 1) Enable Write/Erase Operation (WREN = 1) Unlock Sequence (See Note 1) CPU stalls while Erase operation completes (2 ms typical) Disable Write/Erase Operation (WREN = 0) Re-enable Interrupts (GIE = 1) End Erase Operation Note 1: See Figure 10-3. DS40001770A-page 132 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 EXAMPLE 10-2: ERASING ONE ROW OF PROGRAM MEMORY Required Sequence ; This row erase routine assumes the following: ; 1. A valid address within the erase row is loaded in ADDRH:ADDRL ; 2. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM) BCF BANKSEL MOVF MOVWF MOVF MOVWF BCF BSF BSF INTCON,GIE PMADRL ADDRL,W PMADRL ADDRH,W PMADRH PMCON1,CFGS PMCON1,FREE PMCON1,WREN MOVLW MOVWF MOVLW MOVWF BSF NOP NOP 55h PMCON2 AAh PMCON2 PMCON1,WR BCF BSF PMCON1,WREN INTCON,GIE 2014 Microchip Technology Inc. ; Disable ints so required sequences will execute properly ; Load lower 8 bits of erase address boundary ; Load upper 6 bits of erase address boundary ; Not configuration space ; Specify an erase operation ; Enable writes ; ; ; ; ; ; ; ; ; ; Start of required sequence to initiate erase Write 55h Write AAh Set WR bit to begin erase NOP instructions are forced as processor starts row erase of program memory. The processor stalls until the erase process is complete after erase processor continues with 3rd instruction ; Disable writes ; Enable interrupts Preliminary DS40001770A-page 133 PIC16(L)F1615/9 10.2.4 WRITING TO FLASH PROGRAM MEMORY Program memory is programmed using the following steps: 1. 2. 3. 4. Load the address in PMADRH:PMADRL of the row to be programmed. Load each write latch with data. Initiate a programming operation. Repeat steps 1 through 3 until all data is written. The following steps should be completed to load the write latches and program a row of program memory. These steps are divided into two parts. First, each write latch is loaded with data from the PMDATH:PMDATL using the unlock sequence with LWLO = 1. When the last word to be loaded into the write latch is ready, the LWLO bit is cleared and the unlock sequence executed. This initiates the programming operation, writing all the latches into Flash program memory. Note: Before writing to program memory, the word(s) to be written must be erased or previously unwritten. Program memory can only be erased one row at a time. No automatic erase occurs upon the initiation of the write. Program memory can be written one or more words at a time. The maximum number of words written at one time is equal to the number of write latches. See Figure 10-5 (row writes to program memory with 32 write latches) for more details. The write latches are aligned to the Flash row address boundary defined by the upper 11 bits of PMADRH:PMADRL, (PMADRH<6:0>:PMADRL<7:4>) with the lower four bits of PMADRL, (PMADRL<3:0>) determining the write latch being loaded. Write operations do not cross these boundaries. At the completion of a program memory write operation, the data in the write latches is reset to contain 0x3FFF. The special unlock sequence is required to load a write latch with data or initiate a Flash programming operation. If the unlock sequence is interrupted, writing to the latches or program memory will not be initiated. 1. 2. 3. Set the WREN bit of the PMCON1 register. Clear the CFGS bit of the PMCON1 register. Set the LWLO bit of the PMCON1 register. When the LWLO bit of the PMCON1 register is `1', the write sequence will only load the write latches and will not initiate the write to Flash program memory. 4. Load the PMADRH:PMADRL register pair with the address of the location to be written. 5. Load the PMDATH:PMDATL register pair with the program memory data to be written. 6. Execute the unlock sequence (Section 10.2.2 "Flash Memory Unlock Sequence"). The write latch is now loaded. 7. Increment the PMADRH:PMADRL register pair to point to the next location. 8. Repeat steps 5 through 7 until all but the last write latch has been loaded. 9. Clear the LWLO bit of the PMCON1 register. When the LWLO bit of the PMCON1 register is `0', the write sequence will initiate the write to Flash program memory. 10. Load the PMDATH:PMDATL register pair with the program memory data to be written. 11. Execute the unlock sequence (Section 10.2.2 "Flash Memory Unlock Sequence"). The entire program memory latch content is now written to Flash program memory. Note: The program memory write latches are reset to the Blank state (0x3FFF) at the completion of every write or erase operation. As a result, it is not necessary to load all the program memory write latches. Unloaded latches will remain in the blank state. An example of the complete write sequence is shown in Example 10-3. The initial address is loaded into the PMADRH:PMADRL register pair; the data is loaded using indirect addressing. DS40001770A-page 134 Preliminary 2014 Microchip Technology Inc. 7 BLOCK WRITES TO FLASH PROGRAM MEMORY WITH 32 WRITE LATCHES 6 0 7 4 PMADRH - rA r9 r8 r7 r6 3 0 7 PMADRL r5 r4 r3 r2 r1 r0 c3 c2 c1 - 5 0 7 PMDATH - PMDATL 6 c0 Rev. 10-000004D 7/21/2014 0 8 14 11 Program Memory Write Latches 4 14 Write Latch #0 00h 14 14 14 Write Latch #30 1Eh Write Latch #1 01h Write Latch #31 1Fh PMADRL<3:0> Preliminary 14 CFGS = 0 2014 Microchip Technology Inc. PMADRH<6:0>: PMADRL<7:4> Row Address Decode 14 14 14 Row Addr Addr Addr Addr 000h 0000h 0001h 001Eh 001Fh 001h 0010h 0011h 003Eh 003Fh 002h 0020h 0021h 005Eh 005Fh 7FEh 7FE0h 7FE1h 7FDEh 7FDFh 7FFh 7FF0h 7FF1h 7FFEh 7FFFh Flash Program Memory 800h CFGS = 1 8000h - 8003h 8004h 8005h 8006h 8007h - 8009h 800Ah - 801Fh USER ID 0 - 3 reserved MASK/ REV ID DEVICE ID Configuration Words reserved Configuration Memory PIC16(L)F1615/9 DS40001770A-page 135 FIGURE 10-5: PIC16(L)F1615/9 FIGURE 10-6: FLASH PROGRAM MEMORY WRITE FLOWCHART Rev. 10-000049A 7/30/2013 Start Write Operation Determine number of words to be written into Program or Configuration Memory. The number of words cannot exceed the number of words per row (word_cnt) Enable Write/Erase Operation (WREN = 1) Load the value to write (PMDATH:PMDATL) Disable Interrupts (GIE = 0) Update the word counter (word_cnt--) Write Latches to Flash (LWLO = 0) Select Program or Config. Memory (CFGS) Last word to write ? Yes Unlock Sequence (See Note 1) Select Row Address (PMADRH:PMADRL) No Select Write Operation (FREE = 0) Load Write Latches Only (LWLO = 1) Unlock Sequence (See Note 1) No delay when writing to Program Memory Latches CPU stalls while Write operation completes (2 ms typical) Disable Write/Erase Operation (WREN = 0) Re-enable Interrupts (GIE = 1) Increment Address (PMADRH:PMADRL++) End Write Operation Note 1: See Figure 10-3. DS40001770A-page 136 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 EXAMPLE 10-3: ; ; ; ; ; ; ; WRITING TO FLASH PROGRAM MEMORY (32 WRITE LATCHES) This write routine assumes the following: 1. 64 bytes of data are loaded, starting at the address in DATA_ADDR 2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR, stored in little endian format 3. A valid starting address (the Least Significant bits = 00000) is loaded in ADDRH:ADDRL 4. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM) BCF BANKSEL MOVF MOVWF MOVF MOVWF MOVLW MOVWF MOVLW MOVWF BCF BSF BSF INTCON,GIE PMADRH ADDRH,W PMADRH ADDRL,W PMADRL LOW DATA_ADDR FSR0L HIGH DATA_ADDR FSR0H PMCON1,CFGS PMCON1,WREN PMCON1,LWLO ; ; ; ; ; ; ; ; ; ; ; ; ; Disable ints so required sequences will execute properly Bank 3 Load initial address MOVIW MOVWF MOVIW MOVWF FSR0++ PMDATL FSR0++ PMDATH ; Load first data byte into lower ; ; Load second data byte into upper ; MOVF XORLW ANDLW BTFSC GOTO PMADRL,W 0x1F 0x1F STATUS,Z START_WRITE ; Check if lower bits of address are '00000' ; Check if we're on the last of 32 addresses ; ; Exit if last of 32 words, ; MOVLW MOVWF MOVLW MOVWF BSF NOP 55h PMCON2 AAh PMCON2 PMCON1,WR ; ; ; ; ; ; ; ; PMADRL,F LOOP ; Still loading latches Increment address ; Write next latches PMCON1,LWLO ; No more loading latches - Actually start Flash program ; memory write 55h PMCON2 AAh PMCON2 PMCON1,WR ; ; ; ; ; ; ; ; ; ; ; ; ; Load initial data address Load initial data address Not configuration space Enable writes Only Load Write Latches Required Sequence LOOP NOP INCF GOTO Required Sequence START_WRITE BCF MOVLW MOVWF MOVLW MOVWF BSF NOP NOP BCF BSF PMCON1,WREN INTCON,GIE 2014 Microchip Technology Inc. Start of required write sequence: Write 55h Write AAh Set WR bit to begin write NOP instructions are forced as processor loads program memory write latches Start of required write sequence: Write 55h Write AAh Set WR bit to begin write NOP instructions are forced as processor writes all the program memory write latches simultaneously to program memory. After NOPs, the processor stalls until the self-write process in complete after write processor continues with 3rd instruction Disable writes Enable interrupts Preliminary DS40001770A-page 137 PIC16(L)F1615/9 10.3 Modifying Flash Program Memory FIGURE 10-7: When modifying existing data in a program memory row, and data within that row must be preserved, it must first be read and saved in a RAM image. Program memory is modified using the following steps: 1. 2. 3. 4. 5. 6. 7. Load the starting address of the row to be modified. Read the existing data from the row into a RAM image. Modify the RAM image to contain the new data to be written into program memory. Load the starting address of the row to be rewritten. Erase the program memory row. Load the write latches with data from the RAM image. Initiate a programming operation. FLASH PROGRAM MEMORY MODIFY FLOWCHART Rev. 10-000050A 7/30/2013 Start Modify Operation Read Operation (See Note 1) An image of the entire row read must be stored in RAM Modify Image The words to be modified are changed in the RAM image Erase Operation (See Note 2) Write Operation Use RAM image (See Note 3) End Modify Operation Note 1: See Figure 10-2. 2: See Figure 10-4. 3: See Figure 10-5. DS40001770A-page 138 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 10.4 User ID, Device ID and Configuration Word Access Instead of accessing program memory, the User ID's, Device ID/Revision ID and Configuration Words can be accessed when CFGS = 1 in the PMCON1 register. This is the region that would be pointed to by PC<15> = 1, but not all addresses are accessible. Different access may exist for reads and writes. Refer to Table 10-2. When read access is initiated on an address outside the parameters listed in Table 10-2, the PMDATH:PMDATL register pair is cleared, reading back `0's. TABLE 10-2: USER ID, DEVICE ID AND CONFIGURATION WORD ACCESS (CFGS = 1) Address Function 8000h-8003h 8006h/8005h 8007h-8009h EXAMPLE 10-4: User IDs Device ID/Revision ID Configuration Words 1, 2, and 3 Read Access Write Access Yes Yes Yes Yes No No CONFIGURATION WORD AND DEVICE ID ACCESS * This code block will read 1 word of program memory at the memory address: * PROG_ADDR_LO (must be 00h-08h) data will be returned in the variables; * PROG_DATA_HI, PROG_DATA_LO BANKSEL MOVLW MOVWF CLRF PMADRL PROG_ADDR_LO PMADRL PMADRH ; Select correct Bank ; ; Store LSB of address ; Clear MSB of address BSF BCF BSF NOP NOP BSF PMCON1,CFGS INTCON,GIE PMCON1,RD INTCON,GIE ; ; ; ; ; ; Select Configuration Space Disable interrupts Initiate read Executed (See Figure 10-2) Ignored (See Figure 10-2) Restore interrupts MOVF MOVWF MOVF MOVWF PMDATL,W PROG_DATA_LO PMDATH,W PROG_DATA_HI ; ; ; ; Get LSB of word Store in user location Get MSB of word Store in user location 2014 Microchip Technology Inc. Preliminary DS40001770A-page 139 PIC16(L)F1615/9 10.5 Write Verify It is considered good programming practice to verify that program memory writes agree with the intended value. Since program memory is stored as a full page then the stored program memory contents are compared with the intended data stored in RAM after the last write is complete. FIGURE 10-8: FLASH PROGRAM MEMORY VERIFY FLOWCHART Rev. 10-000051A 7/30/2013 Start Verify Operation This routine assumes that the last row of data written was from an image saved on RAM. This image will be used to verify the data currently stored in Flash Program Memory Read Operation (See Note 1) PMDAT = RAM image ? No Yes Fail Verify Operation No Last word ? Yes End Verify Operation Note 1: See Figure 10-2. DS40001770A-page 140 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 10.6 Register Definitions: Flash Program Memory Control REGISTER 10-1: R/W-x/u PMDATL: PROGRAM MEMORY DATA LOW BYTE REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u PMDAT<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 PMDAT<7:0>: Read/write value for Least Significant bits of program memory REGISTER 10-2: PMDATH: PROGRAM MEMORY DATA HIGH BYTE REGISTER U-0 U-0 -- -- R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u PMDAT<13:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 Unimplemented: Read as `0' bit 5-0 PMDAT<13:8>: Read/write value for Most Significant bits of program memory REGISTER 10-3: R/W-0/0 PMADRL: PROGRAM MEMORY ADDRESS LOW BYTE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PMADR<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 PMADR<7:0>: Specifies the Least Significant bits for program memory address REGISTER 10-4: U-1 PMADRH: PROGRAM MEMORY ADDRESS HIGH BYTE REGISTER R/W-0/0 R/W-0/0 --(1) R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PMADR<14:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 Unimplemented: Read as `1' bit 6-0 PMADR<14:8>: Specifies the Most Significant bits for program memory address Note 1: Unimplemented, read as `1'. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 141 PIC16(L)F1615/9 REGISTER 10-5: PMCON1: PROGRAM MEMORY CONTROL 1 REGISTER U-1 R/W-0/0 R/W-0/0 R/W/HC-0/0 R/W/HC-x/q(2) R/W-0/0 R/S/HC-0/0 R/S/HC-0/0 --(1) CFGS LWLO FREE WRERR WREN WR RD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared HC = Bit is cleared by hardware bit 7 Unimplemented: Read as `1' bit 6 CFGS: Configuration Select bit 1 = Access Configuration, User ID and Device ID Registers 0 = Access Flash program memory bit 5 LWLO: Load Write Latches Only bit(3) 1 = Only the addressed program memory write latch is loaded/updated on the next WR command 0 = The addressed program memory write latch is loaded/updated and a write of all program memory write latches will be initiated on the next WR command bit 4 FREE: Program Flash Erase Enable bit 1 = Performs an erase operation on the next WR command (hardware cleared upon completion) 0 = Performs a write operation on the next WR command bit 3 WRERR: Program/Erase Error Flag bit 1 = Condition indicates an improper program or erase sequence attempt or termination (bit is set automatically on any set attempt (write `1') of the WR bit) 0 = The program or erase operation completed normally bit 2 WREN: Program/Erase Enable bit 1 = Allows program/erase cycles 0 = Inhibits programming/erasing of program Flash bit 1 WR: Write Control bit 1 = Initiates a program Flash program/erase operation. The operation is self-timed and the bit is cleared by hardware once operation is complete. The WR bit can only be set (not cleared) in software. 0 = Program/erase operation to the Flash is complete and inactive bit 0 RD: Read Control bit 1 = Initiates a program Flash read. Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software. 0 = Does not initiate a program Flash read Note 1: 2: 3: Unimplemented bit, read as `1'. The WRERR bit is automatically set by hardware when a program memory write or erase operation is started (WR = 1). The LWLO bit is ignored during a program memory erase operation (FREE = 1). DS40001770A-page 142 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 REGISTER 10-6: W-0/0 PMCON2: PROGRAM MEMORY CONTROL 2 REGISTER W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 Program Memory Control Register 2 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 Flash Memory Unlock Pattern bits To unlock writes, a 55h must be written first, followed by an AAh, before setting the WR bit of the PMCON1 register. The value written to this register is used to unlock the writes. There are specific timing requirements on these writes. TABLE 10-3: Name SUMMARY OF REGISTERS ASSOCIATED WITH FLASH PROGRAM MEMORY Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 105 PMCON1 --(1) CFGS LWLO FREE WRERR WREN WR RD 142 PMCON2 Program Memory Control Register 2 143 PMADRL PMADRL<7:0> 141 -- PMADRH (1) PMADRH<6:0> PMDATL PMDATH Legend: Note 1: -- CONFIG1 CONFIG2 CONFIG3 Legend: -- 141 PMDATH<5:0> 141 -- = unimplemented location, read as `0'. Shaded cells are not used by Flash program memory. Unimplemented, read as `1'. TABLE 10-4: Name 141 PMDATL<7:0> SUMMARY OF CONFIGURATION WORD WITH FLASH PROGRAM MEMORY Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 13:8 -- -- FCMEN IESO CLKOUTEN 7:0 CP MCLRE PWRTE -- -- 13:8 -- -- LVP DEBUG LPBOR BORV 7:0 ZCD -- -- -- -- PPS1WAY 13:8 -- -- 7:0 -- WDTCCS<2:0> WDTE<1:0> Bit 10/2 Bit 9/1 Bit 8/0 BOREN<1:0> -- FOSC<2:0> STVREN PLLEN WRT<1:0> WDTCWS<2:0> WDTCPS<4:0> Register on Page 69 71 72 -- = unimplemented location, read as `0'. Shaded cells are not used by Flash program memory. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 143 PIC16(L)F1615/9 11.0 EXAMPLE 11-1: CYCLIC REDUNDANCY CHECK (CRC) MODULE Rev. 10-000206A 1/8/2014 CRC-16-ANSI The Cyclic Redundancy Check (CRC) module provides a software-configurable hardware-implemented CRC checksum generator. This module includes the following features: x16 + x15 + x2 + 1 (17 bits) Standard 16-bit representation = 0x8005 CRCXORH = 0b10000000 CRCXORL = 0b0000010- * * * * * Any standard CRC up to 16 bits can be used Configurable Polynomial Any seed value up to 16 bits can be used Standard and reversed bit order available Augmented zeros can be added automatically or by the user * Memory scanner for fast CRC calculations on program memory user data * Software loadable data registers for calculating CRC values not from the memory scanner 11.1 Data Sequence: 0x55, 0x66, 0x77, 0x88 DLEN = 0b0111 PLEN = 0b1111 Data entered into the CRC: SHIFTM = 0: 01010101 01100110 01110111 10001000 SHIFTM = 1: 10101010 01100110 11101110 00010001 Check Value (ACCM = 1): SHIFTM = 0: 0x32D6 CRCACCH = 0b00110010 CRCACCL = 0b11010110 CRC Module Overview The CRC module provides a means for calculating a check value of program memory. The CRC module is coupled with a memory scanner for faster CRC calculations. The memory scanner can automatically provide data to the CRC module. The CRC module can also be operated by directly writing data to SFRs, without using the scanner. 11.2 SHIFTM = 1: 0x6BA2 CRCACCH = 0b01101011 CRCACCL = 0b10100010 Note 1: Bit 0 is unimplemented. The LSb of any CRC polynomial is always `1' and will always be treated as a `1' by the CRC for calculating the CRC check value. This bit will be read in software as a `0'. CRC Functional Overview The CRC module can be used to detect bit errors in the Flash memory using the built-in memory scanner or through user input RAM memory. The CRC module can accept up to a 16-bit polynomial with up to a 16-bit seed value. A CRC calculated check value (or checksum) will then be generated into the CRCACC<15:0> registers for user storage. The CRC module uses an XOR shift register implementation to perform the polynomial division required for the CRC calculation. EXAMPLE 11-2: (1) 11.3 CRC Polynomial Implementation Any standard polynomial up to 17 bits can be used. The PLEN<3:0> bits are used to specify how long the polynomial used will be. For an xn polynomial, PLEN = n-2. In an n-bit polynomial the xn bit and the LSb will be used as a `1' in the CRC calculation because the MSb and LSb must always be a `1' for a CRC polynomial. For example, if using CRC-16-ANSI, the polynomial will look like 0x8005. This will be implemented into the CRCXOR<15:1> registers, as shown in Example 11-1. CRC LFSR EXAMPLE Rev. 10-000207A 5/27/2014 Linear Feedback Shift Register for CRC-16-ANSI x16 + x15 + x2 + 1 Data in Augmentation Mode ON b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 Data in Augmentation Mode OFF b15 b14 DS40001770A-page 144 b13 b12 b11 b10 b9 b8 b7 b6 Preliminary b0 b5 b4 b3 b2 b1 b0 2014 Microchip Technology Inc. PIC16(L)F1615/9 11.4 CRC Data Sources 11.6 Data can be input to the CRC module in two ways: - User data using the CRCDAT registers - Flash using the Program Memory Scanner To set the number of bits of data, up to 16 bits, the DLEN bits of CRCCON1 must be set accordingly. Only data bits in CRCDATA registers up to DLEN will be used, other data bits in CRCDATA registers will be ignored. CRC Interrupt The CRC will generate an interrupt when the BUSY bit transitions from 1 to 0. The CRCIF interrupt flag bit of the PIR4 register is set every time the BUSY bit transitions, regardless of whether or not the CRC interrupt is enabled. The CRCIF bit can only be cleared in software. The CRC interrupt enable is the CRCIE bit of the PIE4 register. Data is moved into the CRCSHIFT as an intermediate to calculate the check value located in the CRCACC registers. The SHIFTM bit is used to determine the bit order of the data being shifted into the accumulator. If SHIFTM is not set, the data will be shifted in MSb first. The value of DLEN will determine the MSb. If SHIFTM bit is set, the data will be shifted into the accumulator in reversed order, LSb first. The CRC module can be seeded with an initial value by setting the CRCACC<15:0> registers to the appropriate value before beginning the CRC. 11.4.1 CRC FROM USER DATA To use the CRC module on data input from the user, the user must write the data to the CRCDAT registers. The data from the CRCDAT registers will be latched into the shift registers on any write to the CRCDATL register. 11.4.2 CRC FROM FLASH To use the CRC module on data located in Flash memory, the user can initialize the Program Memory Scanner as defined in Section 11.8, Program Memory Scan Configuration. 11.5 CRC Check Value The CRC check value will be located in the CRCACC registers after the CRC calculation has finished. The check value will depend on two mode settings of the CRCCON: ACCM and SHIFTM. If the ACCM bit is set, the CRC module will augment the data with a number of zeros equal to the length of the polynomial to find the final check value. If the ACCM bit is not set, the CRC will stop at the end of the data. A number of zeros equal to the length of the polynomial can then be entered to find the same check value as augmented mode, alternatively the expected check value can be entered at this point to make the final result equal 0. A final XOR value may be needed with the check value to find the desired CRC result 2014 Microchip Technology Inc. Preliminary DS40001770A-page 145 PIC16(L)F1615/9 11.7 Configuring the CRC 11.8 The following steps illustrate how to properly configure the CRC. 1. Determine if the automatic Program Memory scan will be used with the Scanner or manual calculation through the SFR interface and perform the actions specified in Section 11.4 "CRC Data Sources", depending on which decision was made. 2. If desired, seed a starting CRC value into the CRCACCH/L registers. 3. Program the CRCXORH/L registers with the desired generator polynomial. 4. Program the DLEN<3:0> bits of the CRCCON1 register with the length of the data word - 1 (refer to Example 11-1). This determines how many times the shifter will shift into the accumulator for each data word. 5. Program the PLEN<3:0> bits of the CRCCON1 register with the length of the polynomial - 2 (refer to Example 11-1). 6. Determine whether shifting in trailing zeros is desired and set the ACCM bit of CRCCON0 register appropriately. 7. Likewise, determine whether the MSb or LSb should be shifted first and write the SHIFTM bit of CRCCON0 register appropriately. 8. Write the CRCGO bit of the CRCCON0 register to begin the shifting process. 9a. If manual SFR entry is used, monitor the FULL bit of CRCCON0 register. When FULL = 0, another word of data can be written to the CRCDATH/L registers, keeping in mind that CRCDATH should be written first if the data has >8 bits, as the shifter will begin upon the CRCDATL register being written. 9b. If the scanner is used, the scanner will automatically stuff words into the CRCDATH/L registers as needed, as long as the SCANGO bit is set. 10a.If using the Flash memory scanner, monitor the SCANIF (or the SCANGO bit) for the scanner to finish pushing information into the CRCDATA registers. After the scanner is completed, monitor the CRCIF (or the BUSY bit) to determine that the CRC has been completed and the check value can be read from the CRCACC registers. If both the interrupt flags are set (or both BUSY and SCANGO bits are cleared), the completed CRC calculation can be read from the CRCACCH/L registers. 10b.If manual entry is used, monitor the CRCIF (or BUSY bit) to determine when the CRCACC registers will hold the check value. DS40001770A-page 146 Program Memory Scan Configuration If desired, the Program Memory Scan module may be used in conjunction with the CRC module to perform a CRC calculation over a range of program memory addresses. In order to set up the Scanner to work with the CRC you need to perform the following steps: 1. 2. 3. 4. 5. Set the EN bit to enable the module. This can be performed at any point preceding the setting of the SCANGO bit, but if it gets disabled, all internal states of the Scanner are reset (registers are unaffected). Choose which memory access mode is to be used (see Section 11.10 "Scanning Modes") and set the MODE bits of the SCANCON0 register appropriately. Based on the memory access mode, set the INTM bits of the SCANCON0 register to the appropriate interrupt mode (see Section 11.10.5 "Interrupt Interaction") Set the SCANLADRL/H and SCANHADRL/H registers with the beginning and ending locations in memory that are to be scanned. Begin the scan by setting the SCANGO bit in the SCANCON0 register. The scanner will wait (CRCGO must be set) for the signal from the CRC that it is ready for the first Flash memory location, then begin loading data into the CRC. It will continue to do so until it either hits the configured end address or an address that is unimplemented on the device, at which point the SCANGO bit will clear, Scanner functions will cease, and the SCANIF interrupt will be triggered. Alternately, the SCANGO bit can be cleared in software if desired. 11.9 Scanner Interrupt The scanner will trigger an interrupt when the SCANGO bit transitions from 1 to 0. The SCANIF interrupt flag of PIR4 is set when the last memory location is reached and the data is entered into the CRCDATA registers. The SCANIF bit can only be cleared in software. The SCAN interrupt enable is the SCANIE bit of the PIE4 register. 11.10 Scanning Modes The memory scanner can scan in four modes: Burst, Peek, Concurrent, and Triggered. These modes are controlled by the MODE bits of the SCANCON0 register. The four modes are summarized in Table 11-1. 11.10.1 BURST MODE When MODE = 01, the scanner is in Burst mode. In Burst mode, CPU operation is stalled beginning with the operation after the one that sets the SCANGO bit, and the scan begins, using the instruction clock to execute. Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 The CPU is held until the scan stops. Note that because the CPU is not executing instructions, the SCANGO bit cannot be cleared in software, so the CPU will remain stalled until one of the hardware end-conditions occurs. Burst mode has the highest throughput for the scanner, but has the cost of stalling other execution while it occurs. 11.10.2 CONCURRENT MODE When MODE = 00, the scanner is in Concurrent mode. Concurrent mode, like Burst mode, stalls the CPU while performing accesses of memory. However, while Burst mode stalls until all accesses are complete, Concurrent mode allows the CPU to execute in between access cycles. 11.10.3 ately upon the SCANGO bit being set, it waits for a rising edge from a separate trigger clock, the source of which is determined by the SCANTRIG register. 11.10.4 PEEK MODE When MODE = 10, the scanner is in Peek mode. Peek mode waits for an instruction cycle in which the CPU does not need to access the NVM (such as a branch instruction) and uses that cycle to do its own NVM access. This results in the lowest throughput for the NVM access (and can take a much longer time to complete a scan than the other modes), but does so without any impact on execution times, unlike the other modes. TRIGGERED MODE When MODE = 11, the scanner is in Triggered mode. Triggered mode behaves identically to Concurrent mode, except instead of beginning the scan immedi- TABLE 11-1: SUMMARY OF SCANNER MODES Description MODE<1:0> First Scan Access CPU Operation 11 Triggered As soon as possible following a trigger Stalled during NVM access CPU resumes execution following each access 10 Peek At the first dead cycle Timing is unaffected CPU continues execution following each access 01 Burst 00 Concurrent As soon as possible 11.10.5 Stalled during NVM access CPU suspended until scan completes CPU resumes execution following each access INTERRUPT INTERACTION The INTM bit of the SCANCON0 register controls the scanner's response to interrupts depending on which mode the NVM scanner is in, as described in Table 112. TABLE 11-2: SCAN INTERRUPT MODES MODE<1:0> INTM MODE == Burst MODE != Burst 1 Interrupt overrides SCANGO to pause the burst Scanner suspended during interrupt response; and the interrupt handler executes at full speed; interrupt executes at full speed and scan Scanner Burst resumes when interrupt resumes when the interrupt is complete. completes. 0 Interrupts do not override SCANGO, and the scan (burst) operation will continue; interrupt response will be delayed until scan completes (latency will be increased). In general, if INTM = 0, the scanner will take precedence over the interrupt, resulting in decreased interrupt processing speed and/or increased interrupt 2014 Microchip Technology Inc. Scanner accesses NVM during interrupt response. If MODE != Peak the interrupt handler execution speed will be affected. response latency. If INTM = 1, the interrupt will take precedence and have a better speed, delaying the memory scan. Preliminary DS40001770A-page 147 PIC16(L)F1615/9 11.10.6 WDT INTERACTION 11.10.7 Operation of the WDT is not affected by scanner activity. Hence, it is possible that long scans, particularly in Burst mode, may exceed the WDT time-out period and result in an undesired device Reset. This should be considered when performing memory scans with an application that also utilizes WDT. IN-CIRCUIT DEBUG (ICD) INTERACTION The scanner freezes when an ICD halt occurs, and remains frozen until user-mode operation resumes. The debugger may inspect the SCANCON0 and SCANLADR registers to determine the state of the scan. The ICD interaction with each operating mode is summarized in Table 11-3. TABLE 11-3: ICD AND SCANNER INTERACTIONS Scanner Operating Mode ICD Halt Peek Concurrent Triggered If external halt is asserted during a scan cycle, the instruction (delayed by scan) may or may not execute before ICD entry, depending on external halt timing. External Halt Burst If external halt is asserted during the BSF(SCANCON.GO), ICD entry occurs, and the burst is delayed until ICD exit. Otherwise, the current NVM-access cycle will complete, and then the scanner will be interrupted for ICD entry. If external halt is asserted during the If external halt is asserted during the cycle immediately prior to the scan burst, the burst is suspended and will cycle, both scan and instruction resume with ICD exit. execution happen after the ICD exits. PC Breakpoint If Scanner would peek an instruction that is not executed (because of ICD entry), the peek will occur after ICD exit, when the instruction executes. Scan cycle occurs before ICD entry and instruction execution happens after the ICD exits. Data Breakpoint The instruction with the dataBP executes and ICD entry occurs immediately after. If scan is requested during that cycle, the scan cycle is postponed until the ICD exits. Single Step If a scan cycle is ready after the debug instruction is executed, the scan will read PFM and then the ICD is re-entered. SWBP and ICDINST DS40001770A-page 148 If scan would stall a SWBP, the scan cycle occurs and the ICD is entered. Preliminary If PCPB (or single step) is on BSF(SCANCON.GO), the ICD is entered before execution; execution of the burst will occur at ICD exit, and the burst will run to completion. Note that the burst can be interrupted by an external halt. If SWBP replaces BSF(SCANCON.GO), the ICD will be entered; instruction execution will occur at ICD exit (from ICDINSTR register), and the burst will run to completion. 2014 Microchip Technology Inc. PIC16(L)F1615/9 11.11 Register Definitions: CRC and Scanner Control REGISTER 11-1: CRCCON0: CRC CONTROL REGISTER 0 R/W-0/0 R/W-0/0 R-0 R/W-0/0 U-0 U-0 R/W-0/0 R-0 EN CRCGO BUSY ACCM -- -- SHIFTM FULL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 EN: CRC Enable bit 1 = CRC module is released from Reset 0 = CRC is disabled and consumes no operating current bit 6 CRCGO: CRC Start bit 1 = Start CRC serial shifter 0 = CRC serial shifter turned off bit 5 BUSY: CRC Busy bit 1 = Shifting in progress or pending 0 = All valid bits in shifter have been shifted into accumulator and EMPTY = 1 bit 4 ACCM: Accumulator Mode bit 1 = Data is augmented with zeros 0 = Data is not augmented with zeros bit 3-2 Unimplemented: Read as `0' bit 1 SHIFTM: Shift Mode bit 1 = Shift right (LSb) 0 = Shift left (MSb) bit 0 FULL: Data Path Full Indicator bit 1 = CRCDATH/L registers are full 0 = CRCDATH/L registers have shifted their data into the shifter REGISTER 11-2: R/W-0/0 CRCCON1: CRC CONTROL REGISTER 1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 DLEN<3:0> R/W-0/0 R/W-0/0 R/W-0/0 PLEN<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-4 DLEN<3:0>: Data Length bits Denotes the length of the data word -1 (See Example 11-1) bit 3-0 PLEN<3:0>: Polynomial Length bits Denotes the length of the polynomial -1 (See Example 11-1) 2014 Microchip Technology Inc. Preliminary DS40001770A-page 149 PIC16(L)F1615/9 REGISTER 11-3: R/W-xx CRCDATH: CRC DATA HIGH BYTE REGISTER R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x DAT<15:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 DAT<15:8>: CRC Input/Output Data bits REGISTER 11-4: R/W-xx CRCDATL: CRC DATA LOW BYTE REGISTER R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x DAT<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 DAT<7:0>: CRC Input/Output Data bits Writing to this register fills the shifter. REGISTER 11-5: R/W-0/0 CRCACCH: CRC ACCUMULATOR HIGH BYTE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ACC<15:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 ACC<15:8>: CRC Accumulator Register bits Writing to this register writes to the CRC accumulator register. Reading from this register reads the CRC accumulator. REGISTER 11-6: R/W-0/0 CRCACCL: CRC ACCUMULATOR LOW BYTE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ACC<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 ACC<7:0>: CRC Accumulator Register bits Writing to this register writes to the CRC accumulator register through the CRC write bus. Reading from this register reads the CRC accumulator. DS40001770A-page 150 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 REGISTER 11-7: R-0 CRCSHIFTH: CRC SHIFT HIGH BYTE REGISTER R-0 R-0 R-0 R-0 R-0 R-0 R-0 SHIFT<15:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 SHIFT<15:8>: CRC Shifter Register bits Reading from this register reads the CRC Shifter. REGISTER 11-8: R-0 CRCSHIFTL: CRC SHIFT LOW BYTE REGISTER R-0 R-0 R-0 R-0 R-0 R-0 R-0 SHIFT<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 SHIFT<7:0>: CRC Shifter Register bits Reading from this register reads the CRC Shifter. REGISTER 11-9: R/W CRCXORH: CRC XOR HIGH BYTE REGISTER R/W R/W R/W R/W R/W R/W R/W XOR<15:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 XOR<15:8>: XOR of Polynomial Term XN Enable bits REGISTER 11-10: CRCXORL: CRC XOR LOW BYTE REGISTER R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x U-0 -- XOR<7:1> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-1 XOR<7:1>: XOR of Polynomial Term XN Enable bits bit 0 Unimplemented: Read as `0' 2014 Microchip Technology Inc. Preliminary DS40001770A-page 151 PIC16(L)F1615/9 REGISTER 11-11: SCANCON0: SCANNER ACCESS CONTROL REGISTER 0 R/W-0/0 (1) R/W/HC-0/0 (2, 3) EN SCANGO R-0 (4) BUSY R-0 R/W-0/0 U-0 INVALID INTM -- R/W-0/0 R/W-0/0 MODE<1:0>(5) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared HC = Bit is cleared by hardware bit 7 EN: Scanner Enable bit(1) 1 = Scanner is enabled 0 = Scanner is disabled, internal states are reset bit 6 SCANGO: Scanner GO bit(2, 3) 1 = When the CRC sends a ready signal, NVM will be accessed according to MDx and data passed to the client peripheral. 0 = Scanner operations will not occur bit 5 BUSY: Scanner Busy Indicator bit(4) 1 = Scanner cycle is in process 0 = Scanner cycle is complete (or never started) bit 4 INVALID: Scanner Abort signal bit 1 = SCANLADRL/H has incremented or contains an invalid address(6) 0 = SCANLADRL/H points to a valid address bit 3 INTM: NVM Scanner Interrupt Management Mode Select bit If MODE = 10: This bit is ignored If MODE = 01 (CPU is stalled until all data is transferred): 1 = SCANGO is overridden (to zero) during interrupt operation; scanner resumes after returning from interrupt 0 = SCANGO is not affected by interrupts, the interrupt response will be affected If MODE = 00 or 11: 1 = SCANGO is overridden (to zero) during interrupt operation; scan operations resume after returning from interrupt 0 = Interrupts do not prevent NVM access bit 2 Unimplemented: Read as `0' bit 1-0 MODE<1:0>: Memory Access Mode bits(5) 11 = Triggered mode 10 = Peek mode 01 = Burst mode 00 = Concurrent mode Note 1: 2: 3: 4: 5: 6: Setting EN = 0 (SCANCON0 register) does not affect any other register content. This bit is cleared when LADR > HADR (and a data cycle is not occurring). If INTM = 1, this bit is overridden (to zero, but not cleared) during an interrupt response. BUSY = 1 when the NVM is being accessed, or when the CRC sends a ready signal. See Table 11-1 for more detailed information. An invalid address happens when the entire range of the PFM is scanned and completed, i.e., device memory is 0x4000 and SCANHADR = 0x3FFF, after the last scan SCANLADR increments to 0x4000, the address is invalid. DS40001770A-page 152 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 REGISTER 11-12: SCANLADRH: SCAN LOW ADDRESS HIGH BYTE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 LADR<15:8>(1, 2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared LADR<15:8>: Scan Start/Current Address bits(1, 2) Most Significant bits of the current address to be fetched from, value increments on each fetch of memory. bit 7-0 Note 1: 2: Registers SCANLADRH/L form a 16-bit value, but are not guarded for atomic or asynchronous access; registers should only be read or written while SCANGO = 0 (SCANCON0 register). While SCANGO = 1 (SCANCON0 register), writing to this register is ignored. REGISTER 11-13: SCANLADRL: SCAN LOW ADDRESS LOW BYTE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 LADR<7:0>(1, 2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared LADR<7:0>: Scan Start/Current Address bits(1, 2) Least Significant bits of the current address to be fetched from, value increments on each fetch of memory bit 7-0 Note 1: 2: Registers SCANLADRH/L form a 16-bit value, but are not guarded for atomic or asynchronous access; registers should only be read or written while SCANGO = 0 (SCANCON0 register). While SCANGO = 1 (SCANCON0 register), writing to this register is ignored. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 153 PIC16(L)F1615/9 REGISTER 11-14: SCANHADRH: SCAN HIGH ADDRESS HIGH BYTE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 (1, 2) HADR<15:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared HADR<15:8>: Scan End Address bits(1, 2) Most Significant bits of the address at the end of the designated scan bit 7-0 Note 1: 2: Registers SCANHADRH/L form a 16-bit value, but are not guarded for atomic or asynchronous access; registers should only be read or written while SCANGO = 0 (SCANCON0 register). While SCANGO = 1 (SCANCON0 register), writing to this register is ignored. REGISTER 11-15: SCANHADRL: SCAN HIGH ADDRESS LOW BYTE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 HADR<7:0> R/W-0/0 R/W-0/0 R/W-0/0 (1, 2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared HADR<7:0>: Scan End Address bits(1, 2) Least Significant bits of the address at the end of the designated scan bit 7-0 Note 1: 2: Registers SCANHADRH/L form a 16-bit value, but are not guarded for atomic or asynchronous access; registers should only be read or written while SCANGO = 0 (SCANCON0 register). While SCANGO = 1 (SCANCON0 register), writing to this register is ignored. DS40001770A-page 154 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 REGISTER 11-16: SCANTRIG: SCAN TRIGGER SELECTION REGISTER U-0 U-0 U-0 U-0 -- -- -- -- U-0 U-0 R/W-0/0 R/W-0/0 TSEL<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-4 Unimplemented: Read as `0' bit 3-0 TSEL<3:0>: Scanner Data Trigger Input Selection bits 1111-1010 = Reserved 1001 = SMT2_Match 1000 = SMT1_Match 0111 = TMR0_Overflow 0110 = TMR5_Overflow 0101 = TMR3_Overflow 0100 = TMR1_Overflow 0011 = TMR6_postscaled 0010 = TMR4_postscaled 0001 = TMR2_postscaled 0000 = LFINTOSC TABLE 11-4: Name SUMMARY OF REGISTERS ASSOCIATED WITH CRC Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page CRCACCH ACC<15:8> 150 CRCACCL ACC<7:0> 150 CRCCON0 EN CRCGO CRCCON1 BUSY ACCM -- -- DLEN<3:0> SHIFTM FULL PLEN<3:0> 149 149 CRCDATH DAT<15:8> 150 CRCDATL DAT<7:0> 150 CRCSHIFTH SHIFT<15:8> 151 CRCSHIFTL SHIFT<7:0> 151 CRCXORH XOR<15:8> CRCXORL 151 XOR<7:1> INTCON IOCIF 105 GIE PEIE TMR0IE INTE IOCIE SCANIF CRCIF SMT2PWAIF SMT2PRAIF SMT2IF SMT1PWAIF SMT1PRAIF SMT1IF 114 PIE4 SCANIE CRCIE SMT2PWAIE SMT2PRAIE SMT2IE SMT1PWAIE SMT1PRAIE SMT1IE 109 EN SCANGO BUSY INVALID INTM INTF 151 PIR4 SCANCON0 TMR0IF -- -- MODE<1:0> 152 SCANHADRH HADR<15:8> 154 SCANHADRL HADR<7:0> 154 SCANLADRH LADR<15:8> 153 SCANLADRL LADR<7:0> 153 TSEL<3:0> SCANTRIG Legend: * 155 -- = unimplemented location, read as `0'. Shaded cells are not used for the CRC module. Page provides register information. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 155 PIC16(L)F1615/9 12.0 I/O PORTS FIGURE 12-1: GENERIC I/O PORT OPERATION Each port has three standard registers for its operation. These registers are: * TRISx registers (data direction) * PORTx registers (reads the levels on the pins of the device) * LATx registers (output latch) * INLVLx (input level control) * ODCONx registers (open-drain) * SLRCONx registers (slew rate) Rev. 10-000052A 7/30/2013 Read LATx TRISx D Q Write LATx Write PORTx VDD CK Some ports may have one or more of the following additional registers. These registers are: Data Register Data bus * ANSELx (analog select) * WPUx (weak pull-up) I/O pin Read PORTx In general, when a peripheral is enabled on a port pin, that pin cannot be used as a general purpose output. However, the pin can still be read. To digital peripherals ANSELx To analog peripherals VSS Device PORTB PORTC PORT AVAILABILITY PER DEVICE PORTA TABLE 12-1: PIC16(L)F1619 PIC16(L)F1615 The Data Latch (LATx registers) is useful for readmodify-write operations on the value that the I/O pins are driving. A write operation to the LATx register has the same effect as a write to the corresponding PORTx register. A read of the LATx register reads of the values held in the I/O PORT latches, while a read of the PORTx register reads the actual I/O pin value. Ports that support analog inputs have an associated ANSELx register. When an ANSEL bit is set, the digital input buffer associated with that bit is disabled. Disabling the input buffer prevents analog signal levels on the pin between a logic high and low from causing excessive current in the logic input circuitry. A simplified model of a generic I/O port, without the interfaces to other peripherals, is shown in Figure 12-1. DS40001770A-page 156 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 12.1 12.1.1 12.1.5 PORTA Registers DATA REGISTER PORTA is a 6-bit wide, bidirectional port. The corresponding data direction register is TRISA (Register 12-2). Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., disable the output driver). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., enables output driver and puts the contents of the output latch on the selected pin). The exception is RA3, which is input-only and its TRIS bit will always read as `1'. Example 12-1 shows how to initialize an I/O port. Reading the PORTA register (Register 12-1) reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch (LATA). 12.1.2 DIRECTION CONTROL The TRISA register (Register 12-2) controls the PORTA pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISA register are maintained set when using them as analog inputs. I/O pins configured as analog input always read `0'. 12.1.3 OPEN-DRAIN CONTROL The ODCONA register (Register 12-6) controls the open-drain feature of the port. Open-drain operation is independently selected for each pin. When an ODCONA bit is set, the corresponding port output becomes an open-drain driver capable of sinking current only. When an ODCONA bit is cleared, the corresponding port output pin is the standard push-pull drive capable of sourcing and sinking current. 12.1.4 SLEW RATE CONTROL The SLRCONA register (Register 12-7) controls the slew rate option for each port pin. Slew rate control is independently selectable for each port pin. When an SLRCONA bit is set, the corresponding port pin drive is slew rate limited. When an SLRCONA bit is cleared, The corresponding port pin drive slews at the maximum rate possible. 2014 Microchip Technology Inc. INPUT THRESHOLD CONTROL The INLVLA register (Register 12-8) controls the input voltage threshold for each of the available PORTA input pins. A selection between the Schmitt Trigger CMOS or the TTL Compatible thresholds is available. The input threshold is important in determining the value of a read of the PORTA register and also the level at which an interrupt-on-change occurs, if that feature is enabled. See 35.3 "DC Characteristics" for more information on threshold levels. Note: 12.1.6 Changing the input threshold selection should be performed while all peripheral modules are disabled. Changing the threshold level during the time a module is active may inadvertently generate a transition associated with an input pin, regardless of the actual voltage level on that pin. ANALOG CONTROL The ANSELA register (Register 12-4) is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSELA bit high will cause all digital reads on the pin to be read as `0' and allow analog functions on the pin to operate correctly. The state of the ANSELA bits has no effect on digital output functions. A pin with TRIS clear and ANSEL set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port. Note: The ANSELA bits default to the Analog mode after Reset. To use any pins as digital general purpose or peripheral inputs, the corresponding ANSEL bits must be initialized to `0' by user software. EXAMPLE 12-1: BANKSEL CLRF BANKSEL CLRF BANKSEL CLRF BANKSEL MOVLW MOVWF Preliminary INITIALIZING PORTA PORTA ; PORTA ;Init PORTA LATA ;Data Latch LATA ; ANSELA ; ANSELA ;digital I/O TRISA ; B'00111000' ;Set RA<5:3> as inputs TRISA ;and set RA<2:0> as ;outputs DS40001770A-page 157 PIC16(L)F1615/9 12.1.7 PORTA FUNCTIONS AND OUTPUT PRIORITIES Each pin defaults to the PORT latch data after Reset. Other functions are selected with the peripheral pin select logic. See Section 13.0 "Peripheral Pin Select (PPS) Module" for more information. Analog input functions, such as ADC inputs, are not shown in the peripheral pin select lists. These inputs are active when the I/O pin is set for Analog mode using the ANSELA register. Digital output functions continue to may continue to control the pin when it is in Analog mode. DS40001770A-page 158 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 12.2 Register Definitions: PORTA REGISTER 12-1: PORTA: PORTA REGISTER U-0 U-0 R/W-x/x R/W-x/x R-x/x R/W-x/x R/W-x/x R/W-x/x -- -- RA5 RA4 RA3 RA2 RA1 RA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 Unimplemented: Read as `0' bit 5-0 RA<5:0>: PORTA I/O Value bits(1) 1 = Port pin is > VIH 0 = Port pin is < VIL Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return of actual I/O pin values. REGISTER 12-2: U-0 TRISA: PORTA TRI-STATE REGISTER U-0 -- -- R/W-1/1 TRISA5 R/W-1/1 U-1 R/W-1/1 R/W-1/1 R/W-1/1 TRISA4 --(1) TRISA2 TRISA1 TRISA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 Unimplemented: Read as `0' bit 5-4 TRISA<5:4>: PORTA Tri-State Control bit 1 = PORTA pin configured as an input (tri-stated) 0 = PORTA pin configured as an output bit 3 Unimplemented: Read as `1' bit 2-0 TRISA<2:0>: PORTA Tri-State Control bit 1 = PORTA pin configured as an input (tri-stated) 0 = PORTA pin configured as an output Note 1: Unimplemented, read as `1'. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 159 PIC16(L)F1615/9 REGISTER 12-3: LATA: PORTA DATA LATCH REGISTER U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u -- -- LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 Unimplemented: Read as `0' bit 5-0 LATA<5:0>: RA<5:0> Output Latch Value bits(1) Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return of actual I/O pin values. REGISTER 12-4: ANSELA: PORTA ANALOG SELECT REGISTER U-0 U-0 U-0 R/W-1/1 U-0 R/W-1/1 R/W-1/1 R/W-1/1 -- -- -- ANSA4 -- ANSA2 ANSA1 ANSA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-5 Unimplemented: Read as `0' bit 4 ANSA4: Analog Select between Analog or Digital Function on Pins RA4, respectively 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. 0 = Digital I/O. Pin is assigned to port or digital special function. bit 3 Unimplemented: Read as `0' bit 2-0 ANSA<2:0>: Analog Select between Analog or Digital Function on Pins RA<2:0>, respectively 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. 0 = Digital I/O. Pin is assigned to port or digital special function. Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. DS40001770A-page 160 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 REGISTER 12-5: WPUA: WEAK PULL-UP PORTA REGISTER U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 -- -- WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 Unimplemented: Read as `0' bit 5-0 WPUA<5:0>: Weak Pull-up Register bits(3) 1 = Pull-up enabled 0 = Pull-up disabled Note 1: 2: 3: Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled. The weak pull-up device is automatically disabled if the pin is configured as an output. For the WPUA3 bit, when MCLRE = 1, weak pull-up is internally enabled, but not reported here. REGISTER 12-6: ODCONA: PORTA OPEN-DRAIN CONTROL REGISTER U-0 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 -- -- ODA5 ODA4 -- ODA2 ODA1 ODA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 Unimplemented: Read as `0' bit 5-4 ODA<5:4>: PORTA Open-Drain Enable bits For RA<5:4> pins, respectively 1 = Port pin operates as open-drain drive (sink current only) 0 = Port pin operates as standard push-pull drive (source and sink current) bit 3 Unimplemented: Read as `0' bit 2-0 ODA<2:0>: PORTA Open-Drain Enable bits For RA<2:0> pins, respectively 1 = Port pin operates as open-drain drive (sink current only) 0 = Port pin operates as standard push-pull drive (source and sink current) 2014 Microchip Technology Inc. Preliminary DS40001770A-page 161 PIC16(L)F1615/9 REGISTER 12-7: SLRCONA: PORTA SLEW RATE CONTROL REGISTER U-0 U-0 R/W-1/1 R/W-1/1 U-0 R/W-1/1 R/W-1/1 R/W-1/1 -- -- SLRA5 SLRA4 -- SLRA2 SLRA1 SLRA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 Unimplemented: Read as `0' bit 5-4 SLRA<5:4>: PORTA Slew Rate Enable bits For RA<5:4> pins, respectively 1 = Port pin slew rate is limited 0 = Port pin slews at maximum rate bit 3 Unimplemented: Read as `0' bit 2-0 SLRA<2:0>: PORTA Slew Rate Enable bits For RA<2:0> pins, respectively 1 = Port pin slew rate is limited 0 = Port pin slews at maximum rate REGISTER 12-8: INLVLA: PORTA INPUT LEVEL CONTROL REGISTER U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 -- -- INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 Unimplemented: Read as `0' bit 5-0 INLVLA<5:0>: PORTA Input Level Select bits For RA<5:0> pins, respectively 1 = ST input used for PORT reads and interrupt-on-change 0 = TTL input used for PORT reads and interrupt-on-change DS40001770A-page 162 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 TABLE 12-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Name ANSELA Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page -- -- -- ANSA4 -- ANSA2 ANSA1 ANSA0 160 INLVLA -- -- INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 162 LATA -- -- LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 160 ODCONA -- -- ODA5 ODA4 -- ODA2 ODA1 ODA0 161 WPUEN INTEDG TMR0CS TMR0SE PSA -- -- RA5 RA4 RA3 RA0 159 OPTION_REG PORTA PS<2:0> RA2 231 RA1 SLRCONA -- -- SLRA5 SLRA4 -- SLRA2 SLRA1 SLRA0 162 TRISA -- -- TRISA5 TRISA4 --(1) TRISA2 TRISA1 TRISA0 159 -- -- WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 161 WPUA Legend: Note 1: x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by PORTA. Unimplemented, read as `1'. TABLE 12-3: Name CONFIG1 Legend: SUMMARY OF CONFIGURATION WORD WITH PORTA Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 13:8 -- -- FCMEN IESO CLKOUTEN 7:0 CP MCLRE PWRTE -- -- Bit 10/2 Bit 9/1 Bit 8/0 BOREN<1:0> -- FOSC<2:0> Register on Page 69 -- = unimplemented location, read as `0'. Shaded cells are not used by PORTA. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 163 PIC16(L)F1615/9 12.3 12.3.1 12.3.5 PORTB Registers (PIC16(L)F1619 Only) DATA REGISTER PORTB is a 4-bit wide, bidirectional port. The corresponding data direction register is TRISB (Register 12-10). Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., disable the output driver). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., enables output driver and puts the contents of the output latch on the selected pin). Example 12-1 shows how to initialize an I/O port. The INLVLA register (Register 12-8) controls the input voltage threshold for each of the available PORTA input pins. A selection between the Schmitt Trigger CMOS or the TTL Compatible thresholds is available. The input threshold is important in determining the value of a read of the PORTA register and also the level at which an interrupt-on-change occurs, if that feature is enabled. See 35.3 "DC Characteristics" for more information on threshold levels. Note: Reading the PORTB register (Register 12-9) reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch (LATB). 12.3.2 12.3.6 DIRECTION CONTROL The TRISB register (Register 12-10) controls the PORTB pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISB register are maintained set when using them as analog inputs. I/O pins configured as analog input always read `0'. 12.3.3 OPEN-DRAIN CONTROL The ODCONA register (Register 12-6) controls the open-drain feature of the port. Open-drain operation is independently selected for each pin. When an ODCONA bit is set, the corresponding port output becomes an open-drain driver capable of sinking current only. When an ODCONA bit is cleared, the corresponding port output pin is the standard push-pull drive capable of sourcing and sinking current. 12.3.4 INPUT THRESHOLD CONTROL Changing the input threshold selection should be performed while all peripheral modules are disabled. Changing the threshold level during the time a module is active may inadvertently generate a transition associated with an input pin, regardless of the actual voltage level on that pin. ANALOG CONTROL The ANSELB register (Register 12-12) is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSELB bit high will cause all digital reads on the pin to be read as `0' and allow analog functions on the pin to operate correctly. The state of the ANSELB bits has no effect on digital output functions. A pin with TRIS clear and ANSEL set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port. Note: The ANSELB bits default to the Analog mode after Reset. To use any pins as digital general purpose or peripheral inputs, the corresponding ANSEL bits must be initialized to `0' by user software. SLEW RATE CONTROL The SLRCONA register (Register 12-7) controls the slew rate option for each port pin. Slew rate control is independently selectable for each port pin. When an SLRCONA bit is set, the corresponding port pin drive is slew rate limited. When an SLRCONA bit is cleared, The corresponding port pin drive slews at the maximum rate possible. DS40001770A-page 164 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 12.3.7 PORTB FUNCTIONS AND OUTPUT PRIORITIES Each pin defaults to the PORT latch data after Reset. Other functions are selected with the peripheral pin select logic. See Section 13.0 "Peripheral Pin Select (PPS) Module" for more information. Analog input functions, such as ADC inputs, are not shown in the peripheral pin select lists. These inputs are active when the I/O pin is set for Analog mode using the ANSELB register. Digital output functions continue to may continue to control the pin when it is in Analog mode. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 165 PIC16(L)F1615/9 12.4 Register Definitions: PORTB REGISTER 12-9: PORTB: PORTB REGISTER R/W-x/x R/W-x/x R/W-x/x R/W-x/x U-0 U-0 U-0 U-0 RB7 RB6 RB5 RB4 -- -- -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-4 RB<7:4>: PORTB I/O Value bits(1) 1 = Port pin is > VIH 0 = Port pin is < VIL bit 3-0 Unimplemented: Read as `0' Note 1: Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is return of actual I/O pin values. REGISTER 12-10: TRISB: PORTB TRI-STATE REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 U-0 U-0 U-0 U-0 TRISB7 TRISB6 TRISB5 TRISB4 -- -- -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-4 TRISB<7:4>: PORTB Tri-State Control bits 1 = PORTB pin configured as an input (tri-stated) 0 = PORTB pin configured as an output bit 3-0 Unimplemented: Read as `0' DS40001770A-page 166 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 REGISTER 12-11: LATB: PORTB DATA LATCH REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u U-0 U-0 U-0 U-0 LATB7 LATB6 LATB5 LATB4 -- -- -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-4 LATB<7:4>: RB<7:4> Output Latch Value bits(1) bit 3-0 Unimplemented: Read as `0' Note 1: Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is return of actual I/O pin values. REGISTER 12-12: ANSELB: PORTB ANALOG SELECT REGISTER U-0 U-0 R/W-1/1 R/W-1/1 U-0 U-0 U-0 U-0 -- -- ANSB5 ANSB4 -- -- -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 Unimplemented: Read as `0' bit 5-4 ANSB<5:4>: Analog Select between Analog or Digital Function on Pins RB<5:4>, respectively 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. 0 = Digital I/O. Pin is assigned to port or digital special function. bit 3-0 Unimplemented: Read as `0' Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 167 PIC16(L)F1615/9 REGISTER 12-13: WPUB: WEAK PULL-UP PORTB REGISTER(1),(2) R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 U-0 U-0 U-0 U-0 WPUB7 WPUB6 WPUB5 WPUB4 -- -- -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-4 WPUB<7:4>: Weak Pull-up Register bits 1 = Pull-up enabled 0 = Pull-up disabled bit 3-0 Unimplemented: Read as `0' Note 1: 2: Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled. The weak pull-up device is automatically disabled if the pin is configured as an output. REGISTER 12-14: ODCONB: PORTB OPEN-DRAIN CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0 ODB7 ODB6 ODB5 ODB4 -- -- -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-4 ODB<7:4>: PORTB Open-Drain Enable bits For RB<7:4> pins, respectively 1 = Port pin operates as open-drain drive (sink current only) 0 = Port pin operates as standard push-pull drive (source and sink current) bit 3-0 Unimplemented: Read as `0' DS40001770A-page 168 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 REGISTER 12-15: SLRCONB: PORTB SLEW RATE CONTROL REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 U-0 U-0 U-0 U-0 SLRB7 SLRB6 SLRB5 SLRB4 -- -- -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-4 SLRB<7:4>: PORTA Slew Rate Enable bits For RB<7:4> pins, respectively 1 = Port pin slew rate is limited 0 = Port pin slews at maximum rate bit 3-0 Unimplemented: Read as `0' REGISTER 12-16: INLVLB: PORTB INPUT LEVEL CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0 INLVLB7 INLVLB6 INLVLB5 INLVLB4 -- -- -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-4 INLVLB<7:4>: PORTB Input Level Select bits For RB<7:4> pins, respectively 1 = ST input used for PORT reads and interrupt-on-change 0 = TTL input used for PORT reads and interrupt-on-change bit 3-0 Unimplemented: Read as `0' TABLE 12-4: Name SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page -- -- ANSB5 ANSB4 -- -- -- -- 167 INLVLB7 INLVLB6 INLVLB5 INLVLB4 -- -- -- -- 169 LATB LATB7 LATB6 LATB5 LATB4 -- -- -- -- 167 ODCONB ODB7 ODB6 ODB5 ODB4 -- -- -- -- 168 WPUEN INTEDG TMR0CS TMR0SE PSA RB7 RB6 RB5 RB4 -- -- ANSELB INLVLB OPTION_REG PORTB PS<2:0> -- 231 -- 166 SLRCONB SLRB7 SLRB6 SLRB5 SLRB4 -- -- -- -- 169 TRISB TRISB7 TRISB6 TRISB5 TRISB4 -- -- -- -- 166 WPUB7 WPUB6 WPUB5 WPUB4 -- -- -- -- 168 WPUB Legend: Note 1: x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by PORTB. Unimplemented, read as `1'. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 169 PIC16(L)F1615/9 TABLE 12-5: SUMMARY OF CONFIGURATION WORD WITH PORTB Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 CONFIG1 13:8 -- -- FCMEN IESO CLKOUTEN 7:0 CP MCLRE PWRTE Legend: Bit 10/2 WDTE<1:0> Bit 9/1 BOREN<1:0> Bit 8/0 Register on Page -- 38 FOSC<2:0> -- = unimplemented location, read as `0'. Shaded cells are not used by PORTB. DS40001770A-page 170 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 12.5 12.5.1 12.5.5 PORTC Registers DATA REGISTER PORTC is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISC (Register 12-18). Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., disable the output driver). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). Example 12-1 shows how to initialize an I/O port. The INLVLC register (Register 12-24) controls the input voltage threshold for each of the available PORTC input pins. A selection between the Schmitt Trigger CMOS or the TTL Compatible thresholds is available. The input threshold is important in determining the value of a read of the PORTC register and also the level at which an interrupt-on-change occurs, if that feature is enabled. See 35.3 "DC Characteristics" for more information on threshold levels. Note: Reading the PORTC register (Register 12-17) reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch (LATC). 12.5.2 12.5.6 DIRECTION CONTROL The TRISC register (Register 12-18) controls the PORTC pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISC register are maintained set when using them as analog inputs. I/O pins configured as analog input always read `0'. 12.5.3 OPEN-DRAIN CONTROL The ODCONC register (Register 12-22) controls the open-drain feature of the port. Open-drain operation is independently selected for each pin. When an ODCONC bit is set, the corresponding port output becomes an open-drain driver capable of sinking current only. When an ODCONC bit is cleared, the corresponding port output pin is the standard push-pull drive capable of sourcing and sinking current. 12.5.4 SLEW RATE CONTROL 2014 Microchip Technology Inc. Changing the input threshold selection should be performed while all peripheral modules are disabled. Changing the threshold level during the time a module is active may inadvertently generate a transition associated with an input pin, regardless of the actual voltage level on that pin. ANALOG CONTROL The ANSELC register (Register 12-20) is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSELC bit high will cause all digital reads on the pin to be read as `0' and allow analog functions on the pin to operate correctly. The state of the ANSELC bits has no effect on digital output functions. A pin with TRIS clear and ANSELC set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port. Note: 12.5.7 The SLRCONC register (Register 12-23) controls the slew rate option for each port pin. Slew rate control is independently selectable for each port pin. When an SLRCONC bit is set, the corresponding port pin drive is slew rate limited. When an SLRCONC bit is cleared, The corresponding port pin drive slews at the maximum rate possible. INPUT THRESHOLD CONTROL The ANSELC bits default to the Analog mode after Reset. To use any pins as digital general purpose or peripheral inputs, the corresponding ANSEL bits must be initialized to `0' by user software. HIGH DRIVE STRENGTH PINS The HIDRVC register (Register 12-25) controls the high drive options on the RC4 and RC5. When a HIDRVC bit is cleared, the pin has normal drive strengths. When a HIDRVC bit is set, it's respective pin can sink or source currents up to 100mA. Preliminary DS40001770A-page 171 PIC16(L)F1615/9 12.5.8 PORTC FUNCTIONS AND OUTPUT PRIORITIES Each pin defaults to the PORT latch data after Reset. Other functions are selected with the peripheral pin select logic. See Section 13.0 "Peripheral Pin Select (PPS) Module" for more information. Analog input functions, such as ADC inputs, are not shown in the peripheral pin select lists. These inputs are active when the I/O pin is set for Analog mode using the ANSELC register. Digital output functions continue to may continue to control the pin when it is in Analog mode. DS40001770A-page 172 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 12.6 Register Definitions: PORTC REGISTER 12-17: PORTC: PORTC REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u RC7(1) RC6(1) RC5 RC4 RC3 RC2 RC1 RC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared RC<7:0>: PORTC I/O Value bits(1, 2) 1 = Port pin is > VIH 0 = Port pin is < VIL bit 7-0 Note 1: 2: RC<7:6> on PIC16(L)F1619 only. Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is return of actual I/O pin values. REGISTER 12-18: TRISC: PORTC TRI-STATE REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 TRISC7(1) TRISC6(1) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 Note 1: TRISC<7:0>: PORTC Tri-State Control bits(1) 1 = PORTC pin configured as an input (tri-stated) 0 = PORTC pin configured as an output TRISC<7:6> on PIC16(L)F1619 only. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 173 PIC16(L)F1615/9 REGISTER 12-19: LATC: PORTC DATA LATCH REGISTER R/W-x/u R/W-x/u (1) (1) LATC7 LATC6 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared LATC<7:0>: RC<7:0> Output Latch Value bits(1) 1 = PORTC pin configured as an input (tri-stated) 0 = PORTC pin configured as an output bit 7-0 Note 1: 2: LATC<7:6> on PIC16(L)F1619 only. Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is return of actual I/O pin values. REGISTER 12-20: ANSELC: PORTC ANALOG SELECT REGISTER R/W-1/1 ANSC7 (1) R/W-1/1 U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 ANSC6(1) -- -- ANSC3 ANSC2 ANSC1 ANSC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 ANSC<7:6>: Analog Select between Analog or Digital Function on Pins RC<7:6>, respectively(1) 1 = Analog input. Pin is assigned as analog input(2). Digital input buffer disabled. 0 = Digital I/O. Pin is assigned to port or digital special function. bit 5-4 Unimplemented: Read as `0' bit 3-0 ANSC<3:0>: Analog Select between Analog or Digital Function on Pins RC<3:0>, respectively 1 = Analog input. Pin is assigned as analog input(2). Digital input buffer disabled. 0 = Digital I/O. Pin is assigned to port or digital special function. Note 1: 2: ANSC<7:6> on PIC16(L)F1619 only. When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. DS40001770A-page 174 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 REGISTER 12-21: WPUC: WEAK PULL-UP PORTC REGISTER(2),(3) R/W-1/1 (1) WPUC7 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 WPUC6(1) WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared WPUC<7:0>: Weak Pull-up Register bits(1) 1 = Pull-up enabled 0 = Pull-up disabled bit 7-0 Note 1: 2: 3: WPUC<7:6> on PIC16(L)F1619 only. Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled. The weak pull-up device is automatically disabled if the pin is configured as an output. REGISTER 12-22: ODCONC: PORTC OPEN-DRAIN CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ODC7(1) ODC6(1) ODC5 ODC4 ODC3 ODC2 ODC1 ODC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 Note 1: ODC<7:0>: PORTC Open-Drain Enable bits(1) For RC<7:0> pins, respectively 1 = Port pin operates as open-drain drive (sink current only) 0 = Port pin operates as standard push-pull drive (source and sink current) ODC<7:6> on PIC16(L)F1619 only. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 175 PIC16(L)F1615/9 REGISTER 12-23: SLRCONC: PORTC SLEW RATE CONTROL REGISTER R/W-1/1 SLRC7 R/W-1/1 (1) SLRC6 (1) R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 SLRC5 SLRC4 SLRC3 SLRC2 SLRC1 SLRC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared SLRC<7:0>: PORTC Slew Rate Enable bits(1) For RC<7:0> pins, respectively 1 = Port pin slew rate is limited 0 = Port pin slews at maximum rate bit 7-0 Note 1: SLRC<7:6> on PIC16(L)F1619 only. REGISTER 12-24: INLVLC: PORTC INPUT LEVEL CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 INLVLC7(1) INLVLC6(1) INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 Note 1: INLVLC<7:0>: PORTC Input Level Select bits(1) For RC<7:0> pins, respectively 1 = ST input used for PORT reads and interrupt-on-change 0 = TTL input used for PORT reads and interrupt-on-change INLVLC<7:6> on PIC16(L)F1619 only. DS40001770A-page 176 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 REGISTER 12-25: HIDRVC: PORTC HIGH DRIVE STRENGTH REGISTER U-0 U-0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0 -- -- HIDC5 HIDC4 -- -- -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 Unimplemented: Read as `0' bit 5 HIDC5: High Current Drive Enable on Port C5 1 = High Drive enabled 0 = High Drive disabled bit 4 HIDC4: High Current Drive Enable on Port C4 1 = High Drive enabled 0 = High Drive disabled bit 3-0 Unimplemented: Read as `0' TABLE 12-6: Name SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page -- -- ANSC3 ANSC2 ANSC1 ANSC0 174 HIDC5 HIDC4 -- -- -- -- 177 INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 176 LATC6(1) LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 174 ODC6(1) ODC5 ODC4 ODC3 ODC2 ODC1 ODC0 175 Bit 7 Bit 6 ANSELC ANSC7(1) ANSC6(1) HIDRVC -- -- INLVLC INLVLC7(1) INLVLC6(1) LATC7(1) (1) LATC ODCONC ODC7 Bit 5 RC7(1) RC6(1) RC5 RC4 RC3 RC2 RC1 RC0 173 SLRCONC SLRC7(1) SLRC6(1) SLRC5 SLRC4 SLRC3 SLRC2 SLRC1 SLRC0 176 TRISC TRISC7(1) TRISC6(1) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 173 WPUC WPUC7(1) WPUC6(1) WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 175 PORTC Legend: Note 1: x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by PORTC. PIC16(L)F1619 only 2014 Microchip Technology Inc. Preliminary DS40001770A-page 177 PIC16(L)F1615/9 13.0 PERIPHERAL PIN SELECT (PPS) MODULE 13.2 The Peripheral Pin Select (PPS) module connects peripheral inputs and outputs to the device I/O pins. Only digital signals are included in the selections. All analog inputs and outputs remain fixed to their assigned pins. Input and output selections are independent as shown in the simplified block diagram Figure 13-1. 13.1 PPS Inputs Each peripheral has a PPS register with which the inputs to the peripheral are selected. Inputs include the device pins. PPS Outputs Each I/O pin has a PPS register with which the pin output source is selected. With few exceptions, the port TRIS control associated with that pin retains control over the pin output driver. Peripherals that control the pin output driver as part of the peripheral operation will override the TRIS control as needed. These peripherals include: * EUSART (synchronous operation) * MSSP (I2C) * CWG (auto-shutdown) Although every pin has its own PPS peripheral selection register, the selections are identical for every pin as shown in Register 13-2. Multiple peripherals can operate from the same source simultaneously. Port reads always return the pin level regardless of peripheral PPS selection. If a pin also has associated analog functions, the ANSEL bit for that pin must be cleared to enable the digital input buffer. Note: The notation "Rxy" is a place holder for the pin identifier. For example, RA0PPS. Although every peripheral has its own PPS input selection register, the selections are identical for every peripheral as shown in Register 13-1. Note: The notation "xxx" in the register name is a place holder for the peripheral identifier. For example, CLC1PPS. FIGURE 13-1: SIMPLIFIED PPS BLOCK DIAGRAM PPS Outputs RA0PPS PPS Inputs abcPPS RA0 RA0 Peripheral abc RxyPPS Rxy Peripheral xyz RC7 xyzPPS DS40001770A-page 178 RC7PPS RC7 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 13.3 Bidirectional Pins 13.5 PPS selections for peripherals with bidirectional signals on a single pin must be made so that the PPS input and PPS output select the same pin. Peripherals that have bidirectional signals include: * EUSART (synchronous operation) * MSSP (I2C) Note: 13.4 The I2C default input pins are I2C and SMBus compatible and are the only pins on the device with this compatibility. The PPS can be permanently locked by setting the PPS1WAY Configuration bit. When this bit is set, the PPSLOCKED bit can only be cleared and set one time after a device Reset. This allows for clearing the PPSLOCKED bit so that the input and output selections can be made during initialization. When the PPSLOCKED bit is set after all selections have been made, it will remain set and cannot be cleared until after the next device Reset event. 13.6 Operation During Sleep PPS input and output selections are unaffected by Sleep. PPS Lock The PPS includes a mode in which all input and output selections can be locked to prevent inadvertent changes. PPS selections are locked by setting the PPSLOCKED bit of the PPSLOCK register. Setting and clearing this bit requires a special sequence as an extra precaution against inadvertent changes. Examples of setting and clearing the PPSLOCKED bit are shown in Example 13-1. EXAMPLE 13-1: PPS Permanent Lock 13.7 Effects of a Reset A device Power-On-Reset (POR) clears all PPS input and output selections to their default values. All other Resets leave the selections unchanged. Default input selections are shown in Table 13-1. PPS LOCK/UNLOCK SEQUENCE ; suspend interrupts bcf INTCON,GIE ; BANKSEL PPSLOCK ; set bank ; required sequence, next 5 instructions movlw 0x55 movwf PPSLOCK movlw 0xAA movwf PPSLOCK ; Set PPSLOCKED bit to disable writes or ; Clear PPSLOCKED bit to enable writes bsf PPSLOCK,PPSLOCKED ; restore interrupts bsf INTCON,GIE 2014 Microchip Technology Inc. Preliminary DS40001770A-page 179 PIC16(L)F1615/9 13.8 Register Definitions: PPS Input Selection REGISTER 13-1: xxxPPS: PERIPHERAL xxx INPUT SELECTION U-0 U-0 U-0 -- -- -- R/W-q/u R/W-q/u R/W-q/u R/W-q/u R/W-q/u xxxPPS<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = value depends on peripheral bit 7-5 Unimplemented: Read as `0' bit 4-3 xxxPPS<4:3>: Peripheral xxx Input PORT Selection bits 11 = Reserved. Do not use. 10 = Peripheral input is PORTC 01 = Peripheral input is PORTB (PIC16(L)F1619 only) 00 = Peripheral input is PORTA bit 2-0 xxxPPS<2:0>: Peripheral xxx Input Bit Selection bits (1) 111 = Peripheral input is from PORTx Bit 7 (Rx7) 110 = Peripheral input is from PORTx Bit 6 (Rx6) 101 = Peripheral input is from PORTx Bit 5 (Rx5) 100 = Peripheral input is from PORTx Bit 4 (Rx4) 011 = Peripheral input is from PORTx Bit 3 (Rx3) 010 = Peripheral input is from PORTx Bit 2 (Rx2) 001 = Peripheral input is from PORTx Bit 1 (Rx1) 000 = Peripheral input is from PORTx Bit 0 (Rx0) Note 1: See Table 13-1 for Reset values. REGISTER 13-2: RxyPPS: PIN Rxy OUTPUT SOURCE SELECTION REGISTER U-0 U-0 U-0 -- -- -- R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W-0/u RxyPPS<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-5 Unimplemented: Read as `0' bit 4-0 RxyPPS<4:0>: Pin Rxy Output Source Selection bits Selection code determines the output signal on the port pin. See Table 13-2 for the selection codes DS40001770A-page 180 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 REGISTER 13-3: PPSLOCK: PPS LOCK REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 -- -- -- -- -- -- -- PPSLOCKED bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-1 Unimplemented: Read as `0' bit 0 PPSLOCKED: PPS Locked bit 1 = PPS is locked. PPS selections can not be changed. 0 = PPS is not locked. PPS selections can be changed. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 181 PIC16(L)F1615/9 TABLE 13-1: PPS INPUT REGISTER RESET VALUES Peripheral xxxPPS Register Default Pin Selection PIC16(L)F1619 Reset Value (xxxPPS<4:0>) PIC16(L)F1615 PIC16(L)F1619 PIC16(L)F1615 Interrupt on change INTPPS RA2 RA2 00010 00010 Timer 0 clock T0CKIPPS RA2 RA2 00010 00010 Timer 1 clock T1CKIPPS RA5 RA5 00101 00101 Timer 1 gate T1GPPS RA4 RA4 00100 00100 Timer 2 clock T2CKIPPS RA5 RA5 0101 0101 Timer 3 clock T3CKIPPS RC5 RC5 10101 10101 Timer 3 gate T3GPPS RC4 RC4 10100 10100 Timer 4 clock T4CKIPPS RC1 RC1 10001 10001 Timer 5 clock T5CKIPPS RC0 RC0 10000 10000 Timer 5 gate T5GPPS RC3 RC3 10011 10011 Timer 6 clock T6CKIPPS RA3 RA3 00011 00011 CCP1 CCP1PPS RC5 RC5 10101 10101 CCP2 CCP2PPS RC3 RC3 10011 10011 CWG1 CWG1INPPS RA2 RA2 00010 00010 SPI and I2CTM clock SSPCLKPPS RB6 RC0 01110 10000 SPI and I2C data SSPDATPPS RB4 RC1 01100 10001 SPI slave select SSPSSPPS RC6 RC3 10110 10011 EUSART RX RXPPS RB5 RC5 01101 10101 EUSART CK CKPPS RB7 RC4 01111 10100 All CLCs CLCIN0PPS RC3 RC3 10011 10011 All CLCs CLCIN1PPS RC4 RC4 10100 10100 All CLCs CLCIN2PPS RC1 RC1 10001 10001 All CLCs CLCIN3PPS RA5 RA5 00101 00101 SMT1 Window Input SMTWIN1PPS RA5 RA5 00101 00101 SMT1 Signal Input SMTSIG1PPS RA4 RA4 00100 00100 SMT2 Window Input SMTWIN2PPS RA3 RA3 00101 00101 SMT2 Signal Input SMTSIG2PPS RC1 RC1 10001 10001 Angular Timer 1 Clock Input AT1INPPS RC5 RC5 10101 10101 Angular Timer 1 CC1 Input AT1CC1PPS RC3 RC3 10011 10011 Angular Timer 1 CC2 Input AT1CC2PPS RC4 RC4 10100 10100 Angular Timer 1 CC3 Input AT1CC3PPS RC5 RC5 10101 10101 Example: CCP1PPS = 0x13 selects RC3 as the CCP1 input. DS40001770A-page 182 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 TABLE 13-2: AVAILABLE PORTS FOR OUTPUT BY PERIPHERAL(2) PIC16(L)F1619 RxyPPS<4:0> PIC16(L)F1615 Output Signal PORTA PORTB PORTC PORTA PORTC 11xxx Reserved 10111 Reserved 10110 Reserved 10101 Reserved 10100 Reserved 10011 Reserved 10010 Reserved 10001 (1) SDO/SDA 10000 SCK/SCL(1) 01111 PWM4_out 01110 PWM3_out 01101 CCP2_out 01100 CCP1_out 01011 (1) CWG1OUTD 01010 CWG1OUTC(1) 01001 (1) CWG1OUTB 01000 CWG1OUTA(1) 00111 DT 00110 TX/CK 00101 LC2_out 00100 LC1_out 00011 ZCD1_out 00010 sync_C2OUT 00001 sync_C1OUT 00000 LATxy Note 1: 2: TRIS control is overridden by the peripheral as required. Unsupported peripherals will output a `0'. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 183 PIC16(L)F1615/9 TABLE 13-3: Name SUMMARY OF REGISTERS ASSOCIATED WITH THE PPS MODULE Bit 2 Bit 1 Bit 0 Register on page -- -- PPSLOCKED 181 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 PPSLOCK -- -- -- -- -- INTPPS -- -- -- INTPPS<4:0> 180 T0CKIPPS -- -- -- T0CKIPPS<4:0> 180 T1CKIPPS -- -- -- T1CKIPPS<4:0> 180 T1GPPS -- -- -- T1GPPS<4:0> 180 T2CKIPPS -- -- -- T2CKIPPS<4:0> 180 T3CKIPPS -- -- -- T3CKIPPS<4:0> 180 T3GPPS -- -- -- T3GPPS<4:0> 180 T4CKIPPS -- -- -- T4CKIPPS<4:0> 180 T5CKIPPS -- -- -- T5CKIPPS<4:0> 180 T5GPPS -- -- -- T5GPPS<4:0> 180 T6CKIPPS -- -- -- T6CKIPPS<4:0> 180 CCP1PPS -- -- -- CCP1PPS<4:0> 180 CCP2PPS -- -- -- CCP2PPS<4:0> 180 CWG1INPPS -- -- -- CWG1INPPS<4:0> 180 SSPCLKPPS -- -- -- SSPCLKPPS<4:0> 180 SSPDATPPS -- -- -- SSPDATPPS<4:0> 180 SSPSSPPS -- -- -- SSPSSPPS<4:0> 180 RXPPS -- -- -- RXPPS<4:0> 180 CKPPS -- -- -- CKPPS<4:0> 180 CLCIN0PPS -- -- -- CLCIN0PPS<4:0> 180 CLCIN1PPS -- -- -- CLCIN1PPS<4:0> 180 CLCIN2PPS -- -- -- CLCIN2PPS<4:0> 180 CLCIN3PPS -- -- -- CLCIN3PPS<4:0> 180 AT1INPPS -- -- -- AT1INPPS<4:0> 180 ATCC1PPS -- -- -- ATCC1PPS<4:0> 180 ATCC2PPS -- -- -- ATCC2PPS<4:0> 180 ATCC3PPS -- -- -- ATCC3PPS<4:0> 180 SMT1SIGPPS -- -- -- SMT1SIGPPS<4:0> 180 SMT1WINPPS -- -- -- SMT1WINPPS<4:0> 180 SMT2SIGPPS -- -- -- SMT2SIGPPS<4:0> 180 SMT2WINPPS -- -- -- SMT2WINPPS<4:0> 180 RA0PPS -- -- -- RA0PPS<4:0> 180 RA1PPS -- -- -- RA1PPS<4:0> 180 RA2PPS -- -- -- RA2PPS<4:0> 180 RA4PPS -- -- -- RA4PPS<4:0> 180 RA5PPS -- -- -- RA5PPS<4:0> 180 RB4PPS(1) -- -- -- RB4PPS<4:0> 180 RB5PPS(1) -- -- -- RB5PPS<4:0> 180 RB6PPS(1) -- -- -- RB6PPS<4:0> 180 RB7PPS(1) -- -- -- RB7PPS<4:0> 180 RC0PPS -- -- -- RC0PPS<4:0> 180 Note 1: PIC16(L)F1619 only. DS40001770A-page 184 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 TABLE 13-3: Name SUMMARY OF REGISTERS ASSOCIATED WITH THE PPS MODULE (CONTINUED) Bit 6 Bit 5 RC1PPS -- -- -- RC1PPS<4:0> 180 RC2PPS -- -- -- RC2PPS<4:0> 180 RC3PPS -- -- -- RC3PPS<4:0> 180 RC4PPS -- -- -- RC4PPS<4:0> 180 RC5PPS -- -- -- RC5PPS<4:0> 180 (1) -- -- -- RC6PPS<4:0> 180 RC7PPS(1) -- -- -- RC7PPS<4:0> 180 RC6PPS Note 1: Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page Bit 7 PIC16(L)F1619 only. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 185 PIC16(L)F1615/9 14.0 INTERRUPT-ON-CHANGE 14.3 The PORTA, PORTB(1) and PORTC pins can be configured to operate as Interrupt-On-Change (IOC) pins. An interrupt can be generated by detecting a signal that has either a rising edge or a falling edge. Any individual port pin, or combination of port pins, can be configured to generate an interrupt. The interrupt-onchange module has the following features: * * * * Interrupt-on-Change enable (Master Switch) Individual pin configuration Rising and falling edge detection Individual pin interrupt flags Note 1: PORTB available on PIC16(L)F1619 only. 14.1 The IOCAFx, IOCBFx and IOCCFx bits located in the IOCAF, IOCBF and IOCCF registers, respectively, are status flags that correspond to the interrupt-on-change pins of the associated port. If an expected edge is detected on an appropriately enabled pin, then the status flag for that pin will be set, and an interrupt will be generated if the IOCIE bit is set. The IOCIF bit of the INTCON register reflects the status of all IOCAFx, IOCBFx and IOCCFx bits. 14.4 Figure 14-1 is a block diagram of the IOC module. Enabling the Module To allow individual port pins to generate an interrupt, the IOCIE bit of the INTCON register must be set. If the IOCIE bit is disabled, the edge detection on the pin will still occur, but an interrupt will not be generated. Interrupt Flags Clearing Interrupt Flags The individual status flags, (IOCAFx, IOCBFx and IOCCFx bits), can be cleared by resetting them to zero. If another edge is detected during this clearing operation, the associated status flag will be set at the end of the sequence, regardless of the value actually being written. In order to ensure that no detected edge is lost while clearing flags, only AND operations masking out known changed bits should be performed. The following sequence is an example of what should be performed. EXAMPLE 14-1: 14.2 Individual Pin Configuration For each port pin, a rising edge detector and a falling edge detector are present. To enable a pin to detect a rising edge, the associated bit of the IOCxP register is set. To enable a pin to detect a falling edge, the associated bit of the IOCxN register is set. A pin can be configured to detect rising and falling edges simultaneously by setting both associated bits of the IOCxP and IOCxN registers, respectively. MOVLW XORWF ANDWF 14.5 CLEARING INTERRUPT FLAGS (PORTA EXAMPLE) 0xff IOCAF, W IOCAF, F Operation in Sleep The interrupt-on-change interrupt sequence will wake the device from Sleep mode, if the IOCIE bit is set. If an edge is detected while in Sleep mode, the IOCxF register will be updated prior to the first instruction executed out of Sleep. DS40001770A-page 186 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 FIGURE 14-1: INTERRUPT-ON-CHANGE BLOCK DIAGRAM (PORTA EXAMPLE) Rev. 10-000 037A 6/2/201 4 IOCANx D Q R Q4Q1 edge detect RAx IOCAPx D data bus = 0 or 1 Q D S to data bus IOCAFx Q write IOCAFx R IOCIE Q2 IOC interrupt to CPU core from all other IOCnFx individual pin detectors FOSC Q1 Q1 Q3 Q2 Q3 Q4 Q4Q1 Q1 Q2 Q2 Q3 Q4 Q4Q1 2014 Microchip Technology Inc. Q4 Q4Q1 Preliminary Q4Q1 DS40001770A-page 187 PIC16(L)F1615/9 14.6 Register Definitions: Interrupt-on-Change Control REGISTER 14-1: IOCAP: INTERRUPT-ON-CHANGE PORTA POSITIVE EDGE REGISTER U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 -- -- IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 Unimplemented: Read as `0' bit 5-0 IOCAP<5:0>: Interrupt-on-Change PORTA Positive Edge Enable bits 1 = Interrupt-on-Change enabled on the pin for a positive going edge. IOCAFx bit and IOCIF flag will be set upon detecting an edge. 0 = Interrupt-on-Change disabled for the associated pin. REGISTER 14-2: IOCAN: INTERRUPT-ON-CHANGE PORTA NEGATIVE EDGE REGISTER U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 -- -- IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 Unimplemented: Read as `0' bit 5-0 IOCAN<5:0>: Interrupt-on-Change PORTA Negative Edge Enable bits 1 = Interrupt-on-Change enabled on the pin for a negative going edge. IOCAFx bit and IOCIF flag will be set upon detecting an edge. 0 = Interrupt-on-Change disabled for the associated pin. REGISTER 14-3: IOCAF: INTERRUPT-ON-CHANGE PORTA FLAG REGISTER U-0 U-0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 -- -- IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared HS - Bit is set in hardware bit 7-6 Unimplemented: Read as `0' bit 5-0 IOCAF<5:0>: Interrupt-on-Change PORTA Flag bits 1 = An enabled change was detected on the associated pin. Set when IOCAPx = 1 and a rising edge was detected on RAx, or when IOCANx = 1 and a falling edge was detected on RAx. 0 = No change was detected, or the user cleared the detected change. DS40001770A-page 188 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 REGISTER 14-4: IOCBP: INTERRUPT-ON-CHANGE PORTB POSITIVE EDGE REGISTER(1) R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0 IOCBP7 IOCBP6 IOCBP5 IOCBP4 -- -- -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-4 IOCBP<7:4>: Interrupt-on-Change PORTB Positive Edge Enable bits 1 = Interrupt-on-Change enabled on the pin for a positive going edge. IOCBFx bit and IOCIF flag will be set upon detecting an edge. 0 = Interrupt-on-Change disabled for the associated pin. bit 3-0 Unimplemented: Read as `0' Note 1: PIC16(L)F1619 only. REGISTER 14-5: IOCBN: INTERRUPT-ON-CHANGE PORTB NEGATIVE EDGE REGISTER(1) R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0 IOCBN7 IOCBN6 IOCBN5 IOCBN4 -- -- -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-4 IOCBN<7:4>: Interrupt-on-Change PORTB Negative Edge Enable bits 1 = Interrupt-on-Change enabled on the pin for a negative going edge. IOCBFx bit and IOCIF flag will be set upon detecting an edge. 0 = Interrupt-on-Change disabled for the associated pin. bit 3-0 Unimplemented: Read as `0' Note 1: PIC16(L)F1619 only. REGISTER 14-6: IOCBF: INTERRUPT-ON-CHANGE PORTB FLAG REGISTER(1) R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 U-0 U-0 U-0 U-0 IOCBF7 IOCBF6 IOCBF5 IOCBF4 -- -- -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared HS - Bit is set in hardware bit 7-4 IOCBF<7:4>: Interrupt-on-Change PORTB Flag bits 1 = An enabled change was detected on the associated pin. Set when IOCBPx = 1 and a rising edge was detected on RBx, or when IOCBNx = 1 and a falling edge was detected on RBx. 0 = No change was detected, or the user cleared the detected change. bit 3-0 Unimplemented: Read as `0' Note 1: PIC16(L)F1619 only. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 189 PIC16(L)F1615/9 REGISTER 14-7: R/W-0/0 IOCCP7 IOCCP: INTERRUPT-ON-CHANGE PORTC POSITIVE EDGE REGISTER R/W-0/0 (1) IOCCP6 (1) R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 IOCCP5 IOCCP4 IOCCP3 IOCCP2 IOCCP1 IOCCP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared IOCCP<7:0>: Interrupt-on-Change PORTC Positive Edge Enable bits(1) 1 = Interrupt-on-Change enabled on the pin for a positive going edge. IOCCFx bit and IOCIF flag will be set upon detecting an edge. 0 = Interrupt-on-Change disabled for the associated pin. bit 7-0 Note 1: IOCCP<7:6> available on PIC16(L)F1619 only. IOCCN: INTERRUPT-ON-CHANGE PORTC NEGATIVE EDGE REGISTER(1) REGISTER 14-8: R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 IOCCN7(1) IOCCN6(1) IOCCN5 IOCCN4 IOCCN3 IOCCN2 IOCCN1 IOCCN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared IOCCN<7:0>: Interrupt-on-Change PORTC Negative Edge Enable bits(1) 1 = Interrupt-on-Change enabled on the pin for a negative going edge. IOCCFx bit and IOCIF flag will be set upon detecting an edge. 0 = Interrupt-on-Change disabled for the associated pin. bit 7-0 Note 1: IOCCN<7:6> available on PIC16(L)F1619 only. REGISTER 14-9: IOCCF: INTERRUPT-ON-CHANGE PORTC FLAG REGISTER(1) R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 IOCCF(1) IOCCF6(1) IOCCF5 IOCCF4 IOCCF3 IOCCF2 IOCCF1 IOCCF0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared HS - Bit is set in hardware IOCCF<7:0>: Interrupt-on-Change PORTC Flag bits(1) 1 = An enabled change was detected on the associated pin. Set when IOCCPx = 1 and a rising edge was detected on RCx, or when IOCCNx = 1 and a falling edge was detected on RCx. 0 = No change was detected, or the user cleared the detected change. bit 7-0 Note 1: IOCCF<7:6> available on PIC16(L)F1619 only. DS40001770A-page 190 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 TABLE 14-1: Name SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSELA -- -- -- ANSA4 -- ANSA2 ANSA1 ANSA0 160 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 105 IOCAF -- -- IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 188 IOCAN -- -- IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 188 IOCAP -- -- IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 188 IOCBF(2) IOCBF7 IOCBF6 IOCBF5 IOCBF4 -- -- -- -- 189 (2) IOCBN7 IOCBN6 IOCBN5 IOCBN4 -- -- -- -- 189 IOCBP(2) IOCBP7 IOCBP6 IOCBP5 IOCBP4 -- -- -- -- 189 IOCCF IOCCF7(2) IOCCF6(2) IOCCF5 IOCCF4 IOCCF3 IOCCF2 IOCCF1 IOCCF0 190 IOCCN IOCCN7(2) IOCCN6(2) IOCCN5 IOCCN4 IOCCN3 IOCCN2 IOCCN1 IOCCN0 190 190 IOCBN (2) IOCCP5 IOCCP4 IOCCP3 IOCCP2 IOCCP1 IOCCP0 TRISA -- -- TRISA5 TRISA4 --(1) TRISA2 TRISA1 TRISA0 159 TRISC TRISC7(2) TRISC7(2) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 173 IOCCP Legend: Note 1: 2: IOCCP7 IOCCP6 (2) -- = unimplemented location, read as `0'. Shaded cells are not used by interrupt-on-change. Unimplemented, read as `1'. PIC16(L)F1619 only. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 191 PIC16(L)F1615/9 15.0 The ADFVR<1:0> bits of the FVRCON register are used to enable and configure the gain amplifier settings for the reference supplied to the ADC module. Reference Section 16.0 "Analog-to-Digital Converter (ADC) Module" for additional information. FIXED VOLTAGE REFERENCE (FVR) The Fixed Voltage Reference (FVR) is a stable voltage reference, independent of VDD, with a nominal output level (VFVR) of 1.024V. The output of the FVR can be configured to supply a reference voltage to the following: The CDAFVR<1:0> bits of the FVRCON register are used to enable and configure the gain amplifier settings for the reference supplied to the comparator modules. Reference Section 18.0 "Comparator Module" for additional information. * ADC input channel * Comparator positive input * Comparator negative input To minimize current consumption when the FVR is disabled, the FVR buffers should be turned off by clearing the Buffer Gain Selection bits. The FVR can be enabled by setting the FVREN bit of the FVRCON register. 15.1 15.2 Independent Gain Amplifier When the Fixed Voltage Reference module is enabled, it requires time for the reference and amplifier circuits to stabilize. Once the circuits stabilize and are ready for use, the FVRRDY bit of the FVRCON register will be set. See Figure 29-19: FVR Stabilization Period. The output of the FVR supplied to the peripherals, (listed above), is routed through a programmable gain amplifier. Each amplifier can be programmed for a gain of 1x, 2x or 4x, to produce the three possible voltage levels. FIGURE 15-1: FVR Stabilization Period VOLTAGE REFERENCE BLOCK DIAGRAM Rev. 10-000 053C 12/9/201 3 ADFVR<1:0> CDAFVR<1:0> FVREN Note 1 2 1x 2x 4x FVR_buffer1 (To ADC Module) 1x 2x 4x FVR_buffer2 (To Comparators and DAC) 2 + _ FVRRDY Note 1: Any peripheral requiring the Fixed Reference (See Table 15-1) DS40001770A-page 192 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 TABLE 15-1: Peripheral HFINTOSC BOR LDO PERIPHERALS REQUIRING THE FIXED VOLTAGE REFERENCE (FVR) Conditions Description FOSC<2:0> = 010 and IRCF<3:0> = 000x INTOSC is active and device is not in Sleep. BOREN<1:0> = 11 BOR always enabled. BOREN<1:0> = 10 and BORFS = 1 BOR disabled in Sleep mode, BOR Fast Start enabled. BOREN<1:0> = 01 and BORFS = 1 BOR under software control, BOR Fast Start enabled. All PIC16F1615/9 devices, when VREGPM = 1 and not in Sleep The device runs off of the Low-Power Regulator when in Sleep mode. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 193 PIC16(L)F1615/9 15.3 Register Definitions: FVR Control REGISTER 15-1: R/W-0/0 FVREN(1) FVRCON: FIXED VOLTAGE REFERENCE CONTROL REGISTER R-q/q R/W-0/0 (2) FVRRDY TSEN (3) R/W-0/0 TSRNG R/W-0/0 (3) R/W-0/0 R/W-0/0 (1) R/W-0/0 ADFVR<1:0>(1) CDAFVR<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7 FVREN: Fixed Voltage Reference Enable bit(1) 1 = Fixed Voltage Reference is enabled 0 = Fixed Voltage Reference is disabled bit 6 FVRRDY: Fixed Voltage Reference Ready Flag bit(2) 1 = Fixed Voltage Reference output is ready for use 0 = Fixed Voltage Reference output is not ready or not enabled bit 5 TSEN: Temperature Indicator Enable bit(3) 1 = Temperature Indicator is enabled 0 = Temperature Indicator is disabled bit 4 TSRNG: Temperature Indicator Range Selection bit(3) 1 = VOUT = VDD - 4VT (High Range) 0 = VOUT = VDD - 2VT (Low Range) bit 3-2 CDAFVR<1:0>: Comparator FVR Buffer Gain Selection bits(1) 11 = Comparator FVR Buffer Gain is 4x, with output VCDAFVR = 4x VFVR(4) 10 = Comparator FVR Buffer Gain is 2x, with output VCDAFVR = 2x VFVR(4) 01 = Comparator FVR Buffer Gain is 1x, with output VCDAFVR = 1x VFVR 00 = Comparator FVR Buffer is off bit 1-0 ADFVR<1:0>: ADC FVR Buffer Gain Selection bit(1) 11 = ADC FVR Buffer Gain is 4x, with output VADFVR = 4x VFVR(4) 10 = ADC FVR Buffer Gain is 2x, with output VADFVR = 2x VFVR(4) 01 = ADC FVR Buffer Gain is 1x, with output VADFVR = 1x VFVR 00 = ADC FVR Buffer is off Note 1: 2: 3: 4: To minimize current consumption when the FVR is disabled, the FVR buffers should be turned off by clearing the Buffer Gain Selection bits. FVRRDY is always `1' for the PIC16F1615/9 devices. See Section 15.0 "Temperature Indicator Module" for additional information. Fixed Voltage Reference output cannot exceed VDD. TABLE 15-2: Name FVRCON Legend: SUMMARY OF REGISTERS ASSOCIATED WITH THE FIXED VOLTAGE REFERENCE Bit 7 Bit 6 Bit 5 Bit 4 FVREN FVRRDY TSEN TSRNG Bit 3 Bit 2 CDAFVR>1:0> Bit 1 Bit 0 ADFVR<1:0> Register on page 194 Shaded cells are unused by the Fixed Voltage Reference module. DS40001770A-page 194 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 16.0 TEMPERATURE INDICATOR MODULE FIGURE 16-1: This family of devices is equipped with a temperature circuit designed to measure the operating temperature of the silicon die. The circuit's range of operating temperature falls between -40C and +85C. The output is a voltage that is proportional to the device temperature. The output of the temperature indicator is internally connected to the device ADC. Rev. 10-000069A 7/31/2013 VDD TSEN The circuit may be used as a temperature threshold detector or a more accurate temperature indicator, depending on the level of calibration performed. A onepoint calibration allows the circuit to indicate a temperature closely surrounding that point. A two-point calibration allows the circuit to sense the entire range of temperature more accurately. Reference Application Note AN1333, "Use and Calibration of the Internal Temperature Indicator" (DS01333) for more details regarding the calibration process. 16.1 TEMPERATURE CIRCUIT DIAGRAM TSRNG VOUT Temp. Indicator To ADC Circuit Operation Figure 16-1 shows a simplified block diagram of the temperature circuit. The proportional voltage output is achieved by measuring the forward voltage drop across multiple silicon junctions. Equation 16-1 describes the output characteristics of the temperature indicator. EQUATION 16-1: VOUT RANGES High Range: VOUT = VDD - 4VT 16.2 Minimum Operating VDD When the temperature circuit is operated in low range, the device may be operated at any operating voltage that is within specifications. When the temperature circuit is operated in high range, the device operating voltage, VDD, must be high enough to ensure that the temperature circuit is correctly biased. Table 16-1 shows the recommended minimum VDD vs. range setting. Low Range: VOUT = VDD - 2VT TABLE 16-1: The temperature sense circuit is integrated with the Fixed Voltage Reference (FVR) module. See Section 15.0 "Fixed Voltage Reference (FVR)" for more information. The circuit is enabled by setting the TSEN bit of the FVRCON register. When disabled, the circuit draws no current. The circuit operates in either high or low range. The high range, selected by setting the TSRNG bit of the FVRCON register, provides a wider output voltage. This provides more resolution over the temperature range, but may be less consistent from part to part. This range requires a higher bias voltage to operate and thus, a higher VDD is needed. The low range is selected by clearing the TSRNG bit of the FVRCON register. The low range generates a lower voltage drop and thus, a lower bias voltage is needed to operate the circuit. The low range is provided for low voltage operation. 2014 Microchip Technology Inc. RECOMMENDED VDD VS. RANGE Min. VDD, TSRNG = 1 Min. VDD, TSRNG = 0 3.6V 1.8V 16.3 Temperature Output The output of the circuit is measured using the internal Analog-to-Digital Converter. A channel is reserved for the temperature circuit output. Refer to Section 17.0 "Analog-to-Digital Converter (ADC) Module" for detailed information. 16.4 ADC Acquisition Time To ensure accurate temperature measurements, the user must wait at least 200 s after the ADC input multiplexer is connected to the temperature indicator output before the conversion is performed. In addition, the user must wait 200 s between sequential conversions of the temperature indicator output. Preliminary DS40001770A-page 195 PIC16(L)F1615/9 TABLE 16-2: Name FVRCON Legend: SUMMARY OF REGISTERS ASSOCIATED WITH THE TEMPERATURE INDICATOR Bit 7 Bit 6 Bit 5 Bit 4 FVREN FVRRDY TSEN TSRNG Bit 3 Bit 2 CDAFVR<1:0> Bit 1 Bit 0 ADFVR<1:0> Register on page 118 Shaded cells are unused by the temperature indicator module. DS40001770A-page 196 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 17.0 The ADC voltage reference is software selectable to be either internally generated or externally supplied. ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE The ADC can generate an interrupt upon completion of a conversion. This interrupt can be used to wake-up the device from Sleep. The Analog-to-Digital Converter (ADC) allows conversion of an analog input signal to a 10-bit binary representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and hold circuit. The output of the sample and hold is connected to the input of the converter. The converter generates a 10-bit binary result via successive approximation and stores the conversion result into the ADC result registers (ADRESH:ADRESL register pair). Figure 17-1 shows the block diagram of the ADC. FIGURE 17-1: ADC BLOCK DIAGRAM Rev. 10-000033D 9/16/2014 VDD ADPREF Positive Reference Select VDD VREF+ pin External Channel Inputs ANa VRNEG VRPOS . . . ADC_clk sampled input ANz Internal Channel Inputs ADCS<2:0> VSS AN0 ADC Clock Select FOSC/n Fosc Divider FRC FOSC FRC Temp Indicator Reserved ADC CLOCK SOURCE FVR_buffer1 ADC Sample Circuit CHS<4:0> 10 set bit ADIF Write to bit GO/DONE ADFM GO/DONE Q1 Q4 16 start ADRESH Q2 TRIGSEL<4:0> 0=Left Justify 1=Right Justify complete ADRESL Enable Trigger Select ADON . . . Trigger Sources VDD AUTO CONVERSION TRIGGER 2014 Microchip Technology Inc. Preliminary DS40001770A-page 197 PIC16(L)F1615/9 17.1 17.1.4 ADC Configuration When configuring and using the ADC the following functions must be considered: * * * * * * Port configuration Channel selection ADC voltage reference selection ADC conversion clock source Interrupt control Result formatting 17.1.1 The ADC can be used to convert both analog and digital signals. When converting analog signals, the I/O pin should be configured for analog by setting the associated TRIS and ANSEL bits. Refer to Section 12.0 "I/O Ports" for more information. Note: 17.1.2 The source of the conversion clock is software selectable via the ADCS bits of the ADCON1 register. There are seven possible clock options: * * * * * * * PORT CONFIGURATION Analog voltages on any pin that is defined as a digital input may cause the input buffer to conduct excess current. FOSC/2 FOSC/4 FOSC/8 FOSC/16 FOSC/32 FOSC/64 FRC (internal RC oscillator) The time to complete one bit conversion is defined as TAD. One full 10-bit conversion requires 11.5 TAD periods as shown in Figure 17-2. For correct conversion, the appropriate TAD specification must be met. Refer to the ADC conversion requirements in 35.0 "Electrical Specifications" for more information. Table 17-1 gives examples of appropriate ADC clock selections. Note: CHANNEL SELECTION There are up to 15 channel selections available: * * * * * CONVERSION CLOCK AN<11:0> pins (PIC16(L)F1619 only) AN<7:0> pins (PIC16(L)F1615 only) Temperature Indicator DAC1_output FVR_buffer1 Unless using the FRC, any changes in the system clock frequency will change the ADC clock frequency, which may adversely affect the ADC result. The CHS bits of the ADCON0 register determine which channel is connected to the sample and hold circuit. When changing channels, a delay (TACQ) is required before starting the next conversion. Refer to 17.2.6 "ADC Conversion Procedure" for more information. 17.1.3 ADC VOLTAGE REFERENCE The ADC module uses a positive and a negative voltage reference. The positive reference is labeled ref+ and the negative reference is labeled ref-. The positive voltage reference (ref+) is selected by the ADPREF bits in the ADCON1 register. The positive voltage reference source can be: * VREF+ pin * VDD * FVR_buffer1 The negative voltage reference (ref-) source is: * VSS DS40001770A-page 198 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 TABLE 17-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES ADC Clock Period (TAD) ADC Clock Source Device Frequency (FOSC) ADCS<2:0 > 20 MHz 16 MHz 8 MHz 4 MHz 1 MHz Fosc/2 000 100 ns 125 ns 250 ns 500 ns 2.0 s Fosc/4 100 200 ns 250 ns 500 ns 1.0 s 4.0 s Fosc/8 001 400 ns 500 ns 1.0 s 2.0 s 8.0 s Fosc/16 101 800 ns 1.0 s 2.0 s 4.0 s 16.0 s Fosc/32 010 1.6 s 2.0 s 4.0 s 8.0 s 32.0 s Fosc/64 110 3.2 s 4.0 s 8.0 s 16.0 s 64.0 s FRC x11 1.0-6.0 s 1.0-6.0 s 1.0-6.0 s 1.0-6.0 s 1.0-6.0 s Legend: Shaded cells are outside of recommended range. Note 1: The FRC source has a typical TAD time of 1.7 ms. 2: When the device frequency is greater than 1 MHz, the FRC clock source is only recommended if the conversion will be performed during Sleep. 3: The TAD period when using the FRC clock source can fall within a specified range, (see TAD parameter). The TAD period when using the FOSC-based clock source can be configured for a more precise TAD period. However, the FRC clock source must be used when conversions are to be performed with the device in Sleep mode. FIGURE 17-2: ANALOG-TO-DIGITAL CONVERSION TAD CYCLES Rev. 10-000035A 7/30/2013 TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 THCD Conversion Starts TACQ Holding capacitor disconnected from analog input (THCD). Set GO bit On the following cycle: ADRESH:ADRESL is loaded, GO bit is cleared, ADIF bit is set, holding capacitor is reconnected to analog input. Enable ADC (ADON bit) and Select channel (ACS bits) 2014 Microchip Technology Inc. Preliminary DS40001770A-page 199 PIC16(L)F1615/9 17.1.5 INTERRUPTS 17.1.6 The ADC module allows for the ability to generate an interrupt upon completion of an Analog-to-Digital conversion. The ADC Interrupt Flag is the ADIF bit in the PIR1 register. The ADC Interrupt Enable is the ADIE bit in the PIE1 register. The ADIF bit must be cleared in software. RESULT FORMATTING The 10-bit ADC conversion result can be supplied in two formats, left justified or right justified. The ADFM bit of the ADCON1 register controls the output format. Figure 17-3 shows the two output formats. Note 1: The ADIF bit is set at the completion of every conversion, regardless of whether or not the ADC interrupt is enabled. 2: The ADC operates during Sleep only when the FRC oscillator is selected. This interrupt can be generated while the device is operating or while in Sleep. If the device is in Sleep, the interrupt will wake-up the device. Upon waking from Sleep, the next instruction following the SLEEP instruction is always executed. If the user is attempting to wake-up from Sleep and resume in-line code execution, the GIE and PEIE bits of the INTCON register must be disabled. If the GIE and PEIE bits of the INTCON register are enabled, execution will switch to the Interrupt Service Routine. FIGURE 17-3: 10-BIT ADC CONVERSION RESULT FORMAT Rev. 10-000054A 7/30/2013 ADRESH ADRESL (ADFM = 0) MSB LSB bit 7 bit 0 bit 7 10-bit ADC Result (ADFM = 1) bit 0 Unimplemented: Read as `0' MSB bit 7 LSB bit 0 bit 7 10-bit ADC Result Unimplemented: Read as `0' DS40001770A-page 200 bit 0 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 17.2 17.2.1 17.2.4 ADC Operation STARTING A CONVERSION To enable the ADC module, the ADON bit of the ADCON0 register must be set to a `1'. Setting the GO/ DONE bit of the ADCON0 register to a `1' will start the Analog-to-Digital conversion. Note: 17.2.2 The GO/DONE bit should not be set in the same instruction that turns on the ADC. Refer to 17.2.6 "ADC Conversion Procedure". COMPLETION OF A CONVERSION ADC OPERATION DURING SLEEP The ADC module can operate during Sleep. This requires the ADC clock source to be set to the FRC option. Performing the ADC conversion during Sleep can reduce system noise. If the ADC interrupt is enabled, the device will wake-up from Sleep when the conversion completes. If the ADC interrupt is disabled, the ADC module is turned off after the conversion completes, although the ADON bit remains set. When the ADC clock source is something other than FRC, a SLEEP instruction causes the present conversion to be aborted and the ADC module is turned off, although the ADON bit remains set. When the conversion is complete, the ADC module will: 17.2.5 * Clear the GO/DONE bit * Set the ADIF Interrupt Flag bit * Update the ADRESH and ADRESL registers with new conversion result The auto-conversion trigger allows periodic ADC measurements without software intervention. When a rising edge of the selected source occurs, the GO/DONE bit is set by hardware. 17.2.3 The auto-conversion trigger source is selected with the TRIGSEL<4:0> bits of the ADCON2 register. TERMINATING A CONVERSION If a conversion must be terminated before completion, the GO/DONE bit can be cleared in software. The ADRESH and ADRESL registers will be updated with the partially complete Analog-to-Digital conversion sample. Incomplete bits will match the last bit converted. Note: A device Reset forces all registers to their Reset state. Thus, the ADC module is turned off and any pending conversion is terminated. 2014 Microchip Technology Inc. AUTO-CONVERSION TRIGGER Using the auto-conversion trigger does not assure proper ADC timing. It is the user's responsibility to ensure that the ADC timing requirements are met. See Table 17-2 for auto-conversion sources. TABLE 17-2: AUTO-CONVERSION SOURCES Source Peripheral Signal Name Timer0 T0_overflow Timer1 T1_overflow Timer2 TMR2_postscaled Timer4 TMR4_postscaled Timer6 TMR6_postscaled Comparator C1 C1_OUT_sync Comparator C2 C2_OUT_sync SMT1 SMT1_CPW SMT1 SMT1_CPR SMT1 SMT1_PR SMT2 SMT2_CPW SMT2 SMT2_CPR SMT2 SMT2_PR CCP1 CCP1_out CCP2 CCP2_out Preliminary DS40001770A-page 201 PIC16(L)F1615/9 17.2.6 ADC CONVERSION PROCEDURE This is an example procedure for using the ADC to perform an Analog-to-Digital conversion: 1. 2. 3. 4. 5. 6. 7. 8. Configure Port: * Disable pin output driver (Refer to the TRIS register) * Configure pin as analog (Refer to the ANSEL register) Configure the ADC module: * Select ADC conversion clock * Configure voltage reference * Select ADC input channel * Turn on ADC module Configure ADC interrupt (optional): * Clear ADC interrupt flag * Enable ADC interrupt * Enable peripheral interrupt * Enable global interrupt(1) Wait the required acquisition time(2). Start conversion by setting the GO/DONE bit. Wait for ADC conversion to complete by one of the following: * Polling the GO/DONE bit * Waiting for the ADC interrupt (interrupts enabled) Read ADC Result. Clear the ADC interrupt flag (required if interrupt is enabled). EXAMPLE 17-1: ADC CONVERSION ;This code block configures the ADC ;for polling, Vdd and Vss references, FRC ;oscillator and AN0 input. ; ;Conversion start & polling for completion ; are included. ; BANKSEL ADCON1 ; MOVLW B'11110000' ;Right justify, FRC ;oscillator MOVWF ADCON1 ;Vdd and Vss Vref+ BANKSEL TRISA ; BSF TRISA,0 ;Set RA0 to input BANKSEL ANSEL ; BSF ANSEL,0 ;Set RA0 to analog BANKSEL ADCON0 ; MOVLW B'00000001' ;Select channel AN0 MOVWF ADCON0 ;Turn ADC On CALL SampleTime ;Acquisiton delay BSF ADCON0,ADGO ;Start conversion BTFSC ADCON0,ADGO ;Is conversion done? GOTO $-1 ;No, test again BANKSEL ADRESH ; MOVF ADRESH,W ;Read upper 2 bits MOVWF RESULTHI ;store in GPR space BANKSEL ADRESL ; MOVF ADRESL,W ;Read lower 8 bits MOVWF RESULTLO ;Store in GPR space Note 1: The global interrupt can be disabled if the user is attempting to wake-up from Sleep and resume in-line code execution. 2: Refer to 17.4 Requirements". DS40001770A-page 202 "ADC Acquisition Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 17.3 Register Definitions: ADC Control REGISTER 17-1: U-0 ADCON0: ADC CONTROL REGISTER 0 R/W-0/0 R/W-0/0 -- R/W-0/0 R/W-0/0 CHS<4:0> R/W-0/0 R/W-0/0 R/W-0/0 GO/DONE ADON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 Unimplemented: Read as `0' bit 6-2 CHS<4:0>: Analog Channel Select bits 11111 = FVR (Fixed Voltage Reference) Buffer 1 Output(3) 11110 = DAC (Digital-to-Analog Converter)(2) 11101 = Temperature Indicator(1) 11100 = Reserved. No channel connected. * * * 01100 = Reserved. No channel connected. 01011 = AN11(4) 01010 = AN10(4) 01001 = AN9(4) 01000 = AN8(4) 00111 = Reserved. No channel connected. 00110 = Reserved. No channel connected. 00101 = Reserved. No channel connected. 00100 = Reserved. No channel connected. 01000 = Reserved. No channel connected. 00111 = AN7(4) 00110 = AN6(4) 00101 = AN5(4) 00100 = AN4(4) 00011 = AN3 00010 = AN2 00001 = AN1 00000 = AN0 bit 1 GO/DONE: ADC Conversion Status bit 1 = ADC conversion cycle in progress. Setting this bit starts an ADC conversion cycle. This bit is automatically cleared by hardware when the ADC conversion has completed. 0 = ADC conversion completed/not in progress bit 0 ADON: ADC Enable bit 1 = ADC is enabled 0 = ADC is disabled and consumes no operating current Note 1: 2: 3: 4: See 16.0 "Temperature Indicator Module". See 18.0 "8-bit Digital-to-Analog Converter (DAC1) Module" for more information. See 15.0 "Fixed Voltage Reference (FVR)" for more information. AN<11:4> available on PIC16(L)F1619 only. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 203 PIC16(L)F1615/9 REGISTER 17-2: R/W-0/0 ADCON1: ADC CONTROL REGISTER 1 R/W-0/0 ADFM R/W-0/0 R/W-0/0 ADCS<2:0> U-0 U-0 -- -- R/W-0/0 R/W-0/0 ADPREF<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 ADFM: ADC Result Format Select bit 1 = Right justified. Six Most Significant bits of ADRESH are set to `0' when the conversion result is loaded. 0 = Left justified. Six Least Significant bits of ADRESL are set to `0' when the conversion result is loaded. bit 6-4 ADCS<2:0>: ADC Conversion Clock Select bits 111 = FRC (clock supplied from an internal RC oscillator) 110 = FOSC/64 101 = FOSC/16 100 = FOSC/4 011 = FRC (clock supplied from an internal RC oscillator) 010 = FOSC/32 001 = FOSC/8 000 = FOSC/2 bit 3-2 Unimplemented: Read as `0' bit 1-0 ADPREF<1:0>: ADC Positive Voltage Reference Configuration bits 11 = VRPOS is connected to internal Fixed Voltage Reference (FVR) 10 = VRPOS is connected to external VREF+ pin(1) 01 = Reserved 00 = VRPOS is connected to VDD Note 1: When selecting the VREF+ pin as the source of the positive reference, be aware that a minimum voltage specification exists. See TABLE 35-13: "Analog-to-Digital Converter (ADC) Characteristics(1,2,3)" for details. DS40001770A-page 204 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 REGISTER 17-3: R/W-0/0 ADCON2: ADC CONTROL REGISTER 2 R/W-0/0 R/W-0/0 TRIGSEL<4:0> R/W-0/0 R/W-0/0 (1) U-0 U-0 U-0 -- -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-3 TRIGSEL<4:0>: Auto-Conversion Trigger Selection bits(1) 11111 = Reserved * * * 10101 = Reserved 10100 = AT1_cmp3 10011 = AT1_cmp2 10010 = AT1_cmp1 10001 = CLC4OUT 10000 = CLC3OUT 01111 = CLC2OUT 01110 = CLC1OUT 01101 = TMR5_overflow 01100 = TMR3_overflow 01011 = SMT2_match 01010 =SMT1_match 01001 = TMR6_postscaled 01000 = TMR4_postscaled 00111 = C2_OUT_sync 00110 = C1_OUT_sync 00101 = TMR2_postscaled 00100 = T1_overflow(2) 00011 = T0_overflow(2) 00010 = CCP2_out 00001 = CCP1_out 00000 = No auto-conversion trigger selected bit 2-0 Unimplemented: Read as `0' Note 1: 2: This is a rising edge sensitive input for all sources. Signal also sets its corresponding interrupt flag. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 205 PIC16(L)F1615/9 REGISTER 17-4: R/W-x/u ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u ADRES<9:2> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 ADRES<9:2>: ADC Result Register bits Upper eight bits of 10-bit conversion result REGISTER 17-5: R/W-x/u ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0 R/W-x/u ADRES<1:0> R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u -- -- -- -- -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 ADRES<1:0>: ADC Result Register bits Lower two bits of 10-bit conversion result bit 5-0 Reserved: Do not use. DS40001770A-page 206 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 REGISTER 17-6: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u -- -- -- -- -- -- R/W-x/u R/W-x/u ADRES<9:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-2 Reserved: Do not use. bit 1-0 ADRES<9:8>: ADC Result Register bits Upper two bits of 10-bit conversion result REGISTER 17-7: R/W-x/u ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u ADRES<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 ADRES<7:0>: ADC Result Register bits Lower eight bits of 10-bit conversion result 2014 Microchip Technology Inc. Preliminary DS40001770A-page 207 PIC16(L)F1615/9 17.4 ADC Acquisition Requirements For the ADC to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The Analog Input model is shown in Figure 17-4. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), refer to Figure 17-4. The maximum recommended impedance for analog sources is 10 k. As the EQUATION 17-1: Assumptions: source impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (or changed), an ADC acquisition must be done before the conversion can be started. To calculate the minimum acquisition time, Equation 17-1 may be used. This equation assumes that 1/2 LSb error is used (1,024 steps for the ADC). The 1/2 LSb error is the maximum error allowed for the ADC to meet its specified resolution. ACQUISITION TIME EXAMPLE Temperature = 50C and external impedance of 10k 5.0V V DD T ACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient = T AMP + T C + T COFF = 2s + T C + Temperature - 25C 0.05s/C The value for TC can be approximated with the following equations: 1 = V CHOLD V AP P LI ED 1 - -------------------------n+1 2 -1 ;[1] VCHOLD charged to within 1/2 lsb -TC ---------- RC V AP P LI ED 1 - e = V CHOLD ;[2] VCHOLD charge response to VAPPLIED - Tc --------- 1 RC ;combining [1] and [2] V AP P LI ED 1 - e = V A PP LIE D 1 - -------------------------n+1 2 -1 Note: Where n = number of bits of the ADC. Solving for TC: T C = - C HOLD R IC + R SS + R S ln(1/2047) = - 12.5pF 1k + 7k + 10k ln(0.0004885) = 1.12 s Therefore: T A CQ = 2s + 1.12 s + 50C- 25C 0.05 s/C = 4.37s Note 1: The reference voltage (VRPOS) has no effect on the equation, since it cancels itself out. 2: The charge holding capacitor (CHOLD) is not discharged after each conversion. 3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin leakage specification. DS40001770A-page 208 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 FIGURE 17-4: ANALOG INPUT MODEL Rev. 10-000070A 8/2/2013 VDD RS Analog Input pin VT 0.6V RIC 1K Sampling switch SS RSS ILEAKAGE(1) VA Legend: CHOLD CPIN ILEAKAGE RIC RSS SS VT Note 1: FIGURE 17-5: CPIN 5pF CHOLD = 10 pF VT 0.6V Ref- = Sample/Hold Capacitance = Input Capacitance = Leakage Current at the pin due to varies injunctions = Interconnect Resistance = Resistance of Sampling switch = Sampling Switch = Threshold Voltage VDD 6V 5V 4V 3V 2V RSS 5 6 7 8 9 10 11 Sampling Switch (k ) Refer to Section 28.0 "Electrical Specifications". ADC TRANSFER FUNCTION Full-Scale Range 3FFh 3FEh ADC Output Code 3FDh 3FCh 3FBh 03h 02h 01h 00h Analog Input Voltage 0.5 LSB Ref- 2014 Microchip Technology Inc. 1.5 LSB Zero-Scale Transition Full-Scale Transition Preliminary Ref+ DS40001770A-page 209 PIC16(L)F1615/9 TABLE 17-3: Name SUMMARY OF REGISTERS ASSOCIATED WITH ADC Bit 7 Bit 6 ADCON0 -- ADCON1 ADFM Bit 5 Bit 3 Bit 2 -- -- ADPREF<1:0> -- -- CHS<4:0> ADCS<2:0> ADCON2 TRIGSEL<4:0> ADRESH ADC Result Register High ADRESL ADC Result Register Low ANSELA Bit 4 -- ANSELC ANSC7 INTCON GIE -- (2) ANSC6 Bit 0 GO/DONE ADON -- Register on Page 203 204 205 207, 208 207, 208 -- (2) Bit 1 ANSA4 -- ANSA2 ANSA1 ANSA0 132 -- -- ANSC3 ANSC2 ANSC1 ANSC0 139 PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 78 TXIE SSP1IE CCP1IE TMR2IE TMR1IE 79 CCP1IF TMR2IF TMR1IF 83 PIE1 TMR1GIE ADIE RCIE PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF -- -- TRISA5 TRISA4 --(1) TRISA2 TRISA1 TRISA0 131 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 138 TSEN TSRNG TRISA TRISC FVRCON Legend: Note 1: 2: TRISC7 (2) FVREN TRISC6 (2) FVRRDY CDAFVR<1:0> ADFVR<1:0> 148 x = unknown, u = unchanged, -- = unimplemented read as `0', q = value depends on condition. Shaded cells are not used for ADC module. Unimplemented, read as `1'. PIC16(L)F1619 only. DS40001770A-page 210 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 18.0 8-BIT DIGITAL-TO-ANALOG CONVERTER (DAC1) MODULE The Digital-to-Analog Converter supplies a variable voltage reference, ratiometric with the input source, with 256 selectable output levels. 18.1 Output Voltage Selection The DAC has 256 voltage level ranges. The 256 levels are set with the DAC1R<7:0> bits of the DAC1CON1 register. The DAC output voltage is determined by Equation 18-1: The input of the DAC can be connected to: * External VREF pins * VDD supply voltage * FVR (Fixed Voltage Reference) The output of the DAC can be configured to supply a reference voltage to the following: * Comparator positive input * ADC input channel * DACXOUT1 pin The Digital-to-Analog Converter (DAC) is enabled by setting the DAC1EN bit of the DAC1CON0 register. EQUATION 18-1: DAC OUTPUT VOLTAGE IF DAC1EN = 1 DAC1R 7:0 VOUT = VSOURCE+ - VSOURCE- -------------------------------- + VSOURCE8 2 VSOURCE+ = VDD, VREF, or FVR BUFFER 2 VSOURCE- = VSS 18.2 Ratiometric Output Level The DAC output value is derived using a resistor ladder with each end of the ladder tied to a positive and negative voltage reference input source. If the voltage of either input source fluctuates, a similar fluctuation will result in the DAC output value. The value of the individual resistors within the ladder can be found in Section 35.0 "Electrical Specifications". 18.3 DAC Voltage Reference Output The DAC voltage can be output to the DACxOUT1 pin by setting the DAC1OE1 pin of the DAC1CON0 register. Selecting the DAC reference voltage for output on the DACXOUT1 pin automatically overrides the digital output buffer and digital input threshold detector functions of that pin. Reading the DACXOUT1 pin when it has been configured for DAC reference voltage output will always return a `0'. Due to the limited current drive capability, a buffer must be used on the DAC voltage reference output for external connections to either DACXOUT1 pin. Figure 18-2 shows an example buffering technique. DS40001770A-page 212 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 FIGURE 18-1: DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM Rev. 10-000 026C 12/11/201 3 VDD 00 01 VREF+ FVR_buffer2 10 Reserved 11 VSOURCE+ DACR<7:0> 8 R DACPSS R DACEN R 32-to-1 MUX R 32 Steps DACx_output To Peripherals R DACxOUT1 (1) R DACOE1 R VSOURCE- VSS Note 1: The unbuffered DACx_output is provided on the DACxOUT pin(s). FIGURE 18-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE PIC(R) MCU DAC Module R Voltage Reference Output Impedance 2014 Microchip Technology Inc. DACXOUT1 Preliminary + - Buffered DAC Output DS40001770A-page 213 PIC16(L)F1615/9 18.4 Operation During Sleep When the device wakes up from Sleep through an interrupt or a Watchdog Timer time-out, the contents of the DAC1CON0 register are not affected. To minimize current consumption in Sleep mode, the voltage reference should be disabled. 18.5 Effects of a Reset A device Reset affects the following: * DAC is disabled. * DAC output voltage is removed from the DACXOUT1 pin. * The DAC1R<7:0> range select bits are cleared. DS40001770A-page 214 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 18.6 Register Definitions: DAC Control REGISTER 18-1: DAC1CON0: VOLTAGE REFERENCE CONTROL REGISTER 0 R/W-0/0 U-0 R/W-0/0 U-0 DAC1EN -- DAC1OE1 -- R/W-0/0 R/W-0/0 U-0 U-0 -- -- DAC1PSS<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 DAC1EN: DAC1 Enable bit 1 = DAC is enabled 0 = DAC is disabled bit 6 Unimplemented: Read as `0' bit 5 DAC1OE1: DAC1 Voltage Output 1 Enable bit 1 = DAC voltage level is also an output on the DACxOUT1 pin 0 = DAC voltage level is disconnected from the DACxOUT1 pin bit 4 Unimplemented: Read as `0' bit 3-2 DAC1PSS<1:0>: DAC1 Positive Source Select bits 11 = Reserved, do not use 10 = FVR Buffer2 output 01 = VREF+ pin 00 = VDD bit 1-0 Unimplemented: Read as `0' REGISTER 18-2: R/W-0/0 DAC1CON1: VOLTAGE REFERENCE CONTROL REGISTER 1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 DAC1R<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 DAC1R<7:0>: DAC1 Voltage Output Select bits TABLE 18-1: Name FVRCON DAC1CON0 SUMMARY OF REGISTERS ASSOCIATED WITH THE DAC1 MODULE Bit 7 Bit 6 Bit 5 Bit 4 FVREN DAC1EN FVRRDY TSEN TSRNG CDAFVR<1:0> -- DAC1OE1 -- DAC1PSS<1:0> DAC1CON1 Legend: Bit 3 Bit 2 Bit 1 Bit 0 ADFVR<1:0> -- DAC1R<7:0> -- Register on page 194 215 215 -- = Unimplemented location, read as `0'. Shaded cells are not used with the DAC module. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 215 PIC16(L)F1615/9 19.0 COMPARATOR MODULE FIGURE 19-1: Comparators are used to interface analog circuits to a digital circuit by comparing two analog voltages and providing a digital indication of their relative magnitudes. Comparators are very useful mixed signal building blocks because they provide analog functionality independent of program execution. The analog comparator module includes the following features: * * * * * * * * * Independent comparator control Programmable input selection Comparator output is available internally/externally Programmable output polarity Interrupt-on-change Wake-up from Sleep Programmable Speed/Power optimization PWM shutdown Programmable and fixed voltage reference 19.1 SINGLE COMPARATOR VIN+ + VIN- - Output VINVIN+ Output Note: Comparator Overview The black areas of the output of the comparator represents the uncertainty due to input offsets and response time. A single comparator is shown in Figure 19-1 along with the relationship between the analog input levels and the digital output. When the analog voltage at VIN+ is less than the analog voltage at VIN-, the output of the comparator is a digital low level. When the analog voltage at VIN+ is greater than the analog voltage at VIN-, the output of the comparator is a digital high level. The comparators available for this device are located in Table 19-1. TABLE 19-1: COMPARATOR AVAILABILITY PER DEVICE Device C1 C2 PIC16(L)F1619 PIC16(L)F1615 DS40001770A-page 216 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 FIGURE 19-2: COMPARATOR MODULE SIMPLIFIED BLOCK DIAGRAM Rev. 10-000027E 6/18/2014 CxNCH<2:0> 3 CxON(1) CxIN0- 000 CxIN1- 001 CxIN2- 010 CxIN3- 011 Reserved 100 Reserved 101 FVR_buffer2 110 CxON(1) CxVN Interrupt Rising Edge CxINTP Interrupt Falling Edge CxINTN set bit CxIF - D CxOUT Q MCxOUT Cx CxVP 111 + Q1 CxSP CxHYS CxPOL CxOUT_sync CxIN+ 00 DAC_output 01 FVR_buffer2 10 CxSYNC CxOE 0 Note 1: 2 TRIS bit CxOUT D 11 CxPCH<1:0> to peripherals CxON(1) Q 1 (From Timer1 Module) T1CLK When CxON = 0, all multiplexer inputs are disconnected and the Comparator will produce a `0' at the output. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 217 PIC16(L)F1615/9 19.2 19.2.3 Comparator Control Each comparator has two control registers: CMxCON0 and CMxCON1. The CMxCON0 registers (see Register 19-1) contain Control and Status bits for the following: * * * * * * Enable Output selection Output polarity Speed/Power selection Hysteresis enable Output synchronization Inverting the output of the comparator is functionally equivalent to swapping the comparator inputs. The polarity of the comparator output can be inverted by setting the CxPOL bit of the CMxCON0 register. Clearing the CxPOL bit results in a non-inverted output. Table 19-2 shows the output state versus input conditions, including polarity control. TABLE 19-2: Interrupt enable Interrupt edge polarity Positive input channel selection Negative input channel selection 19.2.1 CxPOL CxOUT CxVN > CxVP 0 0 CxVN < CxVP 0 1 CxVN > CxVP 1 1 CxVN < CxVP 1 0 19.2.4 COMPARATOR ENABLE Setting the CxON bit of the CMxCON0 register enables the comparator for operation. Clearing the CxON bit disables the comparator resulting in minimum current consumption. 19.2.2 COMPARATOR OUTPUT SELECTION COMPARATOR OUTPUT STATE VS. INPUT CONDITIONS Input Condition The CMxCON1 registers (see Register 19-2) contain Control bits for the following: * * * * COMPARATOR OUTPUT POLARITY COMPARATOR SPEED/POWER SELECTION The trade-off between speed or power can be optimized during program execution with the CxSP control bit. The default state for this bit is `1' which selects the Normal Speed mode. Device power consumption can be optimized at the cost of slower comparator propagation delay by clearing the CxSP bit to `0'. The output of the comparator can be monitored by reading either the CxOUT bit of the CMxCON0 register or the MCxOUT bit of the CMOUT register. In order to make the output available for an external connection, the following conditions must be true: * CxOE bit of the CMxCON0 register must be set * Corresponding TRIS bit must be cleared * CxON bit of the CMxCON0 register must be set Note 1: The CxOE bit of the CMxCON0 register overrides the PORT data latch. Setting the CxON bit of the CMxCON0 register has no impact on the port override. 2: The internal output of the comparator is latched with each instruction cycle. Unless otherwise specified, external outputs are not latched. DS40001770A-page 218 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 19.3 Comparator Hysteresis A selectable amount of separation voltage can be added to the input pins of each comparator to provide a hysteresis function to the overall operation. Hysteresis is enabled by setting the CxHYS bit of the CMxCON0 register. The associated interrupt flag bit, CxIF bit of the PIR2 register, must be cleared in software. If another edge is detected while this flag is being cleared, the flag will still be set at the end of the sequence. Note: See Section 35.0 "Electrical Specifications" for more information. 19.4 Timer1 Gate Operation The output resulting from a comparator operation can be used as a source for gate control of Timer1. See Section 22.5 "Timer1 Gate" for more information. This feature is useful for timing the duration or interval of an analog event. It is recommended that the comparator output be synchronized to Timer1. This ensures that Timer1 does not increment while a change in the comparator is occurring. 19.4.1 COMPARATOR OUTPUT SYNCHRONIZATION The output from a comparator can be synchronized with Timer1 by setting the CxSYNC bit of the CMxCON0 register. Once enabled, the comparator output is latched on the falling edge of the Timer1 source clock. If a prescaler is used with Timer1, the comparator output is latched after the prescaling function. To prevent a race condition, the comparator output is latched on the falling edge of the Timer1 clock source and Timer1 increments on the rising edge of its clock source. See the Comparator Block Diagram (Figure 19-2) and the Timer1 Block Diagram (Figure 22-1) for more information. 19.5 Comparator Interrupt An interrupt can be generated upon a change in the output value of the comparator for each comparator, a rising edge detector and a falling edge detector are present. When either edge detector is triggered and its associated enable bit is set (CxINTP and/or CxINTN bits of the CMxCON1 register), the Corresponding Interrupt Flag bit (CxIF bit of the PIR2 register) will be set. To enable the interrupt, you must set the following bits: * CxON, CxPOL and CxSP bits of the CMxCON0 register * CxIE bit of the PIE2 register * CxINTP bit of the CMxCON1 register (for a rising edge detection) * CxINTN bit of the CMxCON1 register (for a falling edge detection) * PEIE and GIE bits of the INTCON register 2014 Microchip Technology Inc. 19.6 Although a comparator is disabled, an interrupt can be generated by changing the output polarity with the CxPOL bit of the CMxCON0 register, or by switching the comparator on or off with the CxON bit of the CMxCON0 register. Comparator Positive Input Selection Configuring the CxPCH<2:0> bits of the CMxCON1 register directs an internal voltage reference or an analog pin to the non-inverting input of the comparator: * * * * CxIN+ analog pin DAC output FVR (Fixed Voltage Reference) VSS (Ground) See Section 15.0 "Fixed Voltage Reference (FVR)" for more information on the Fixed Voltage Reference module. See Section 18.0 "8-bit Digital-to-Analog Converter (DAC1) Module" for more information on the DAC input signal. Any time the comparator is disabled (CxON = 0), all comparator inputs are disabled. 19.7 Comparator Negative Input Selection The CxNCH<2:0> bits of the CMxCON1 register direct an analog input pin or analog ground to the inverting input of the comparator: * CxIN- pin * Analog Ground * FVR_buffer2 Some inverting input selections share a pin with the operational amplifier output function. Enabling both functions at the same time will direct the operational amplifier output to the comparator inverting input. Note: Preliminary To use CxINy+ and CxINy- pins as analog input, the appropriate bits must be set in the ANSEL register and the corresponding TRIS bits must also be set to disable the output drivers. DS40001770A-page 219 PIC16(L)F1615/9 19.8 Comparator Response Time The comparator output is indeterminate for a period of time after the change of an input source or the selection of a new reference voltage. This period is referred to as the response time. The response time of the comparator differs from the settling time of the voltage reference. Therefore, both of these times must be considered when determining the total response time to a comparator input change. See the Comparator and Voltage Reference Specifications in Section 35.0 "Electrical Specifications" for more details. 19.9 A maximum source impedance of 10 k is recommended for the analog sources. Also, any external component connected to an analog input pin, such as a capacitor or a Zener diode, should have very little leakage current to minimize inaccuracies introduced. Note 1: When reading a PORT register, all pins configured as analog inputs will read as a `0'. Pins configured as digital inputs will convert as an analog input, according to the input specification. 2: Analog levels on any pin defined as a digital input, may cause the input buffer to consume more current than is specified. Analog Input Connection Considerations A simplified circuit for an analog input is shown in Figure 19-3. Since the analog input pins share their connection with a digital input, they have reverse biased ESD protection diodes to VDD and VSS. The analog input, therefore, must be between VSS and VDD. If the input voltage deviates from this range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up may occur. FIGURE 19-3: ANALOG INPUT MODEL Rev. 10-000071A 8/2/2013 VDD RS < 10K Analog Input pin VT 0.6V RIC To Comparator ILEAKAGE(1) CPIN 5pF VA VT 0.6V VSS Legend: CPIN ILEAKAGE RIC RS VA VT Note 1: DS40001770A-page 220 = Input Capacitance = Leakage Current at the pin due to various junctions = Interconnect Resistance = Source Impedance = Analog Voltage = Threshold Voltage See Section 35.0 "Electrical Specifications". Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 19.10 Register Definitions: Comparator Control REGISTER 19-1: CMxCON0: COMPARATOR Cx CONTROL REGISTER 0 R/W-0/0 R-0/0 R/W-0/0 R/W-0/0 U-0 R/W-1/1 R/W-0/0 R/W-0/0 CxON CxOUT CxOE CxPOL -- CxSP CxHYS CxSYNC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 CxON: Comparator Enable bit 1 = Comparator is enabled 0 = Comparator is disabled and consumes no active power bit 6 CxOUT: Comparator Output bit If CxPOL = 1 (inverted polarity): 1 = CxVP < CxVN 0 = CxVP > CxVN If CxPOL = 0 (non-inverted polarity): 1 = CxVP > CxVN 0 = CxVP < CxVN bit 5 CxOE: Comparator Output Enable bit 1 = CxOUT is present on the CxOUT pin. Requires that the associated TRIS bit be cleared to actually drive the pin. Not affected by CxON. 0 = CxOUT is internal only bit 4 CxPOL: Comparator Output Polarity Select bit 1 = Comparator output is inverted 0 = Comparator output is not inverted bit 3 Unimplemented: Read as `0' bit 2 CxSP: Comparator Speed/Power Select bit 1 = Comparator operates in normal power, higher speed mode 0 = Comparator operates in Low-power, Low-speed mode bit 1 CxHYS: Comparator Hysteresis Enable bit 1 = Comparator hysteresis enabled 0 = Comparator hysteresis disabled bit 0 CxSYNC: Comparator Output Synchronous Mode bit 1 = Comparator output to Timer1 and I/O pin is synchronous to changes on Timer1 clock source. Output updated on the falling edge of Timer1 clock source. 0 = Comparator output to Timer1 and I/O pin is asynchronous 2014 Microchip Technology Inc. Preliminary DS40001770A-page 221 PIC16(L)F1615/9 REGISTER 19-2: CMxCON1: COMPARATOR Cx CONTROL REGISTER 1 R/W-0/0 R/W-0/0 CxINTP CxINTN R/W-0/0 R/W-0/0 CxPCH<1:0> R/W-0/0 R/W-0/0 -- R/W-0/0 R/W-0/0 CxNCH<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 CxINTP: Comparator Interrupt on Positive Going Edge Enable bits 1 = The CxIF interrupt flag will be set upon a positive going edge of the CxOUT bit 0 = No interrupt flag will be set on a positive going edge of the CxOUT bit bit 6 CxINTN: Comparator Interrupt on Negative Going Edge Enable bits 1 = The CxIF interrupt flag will be set upon a negative going edge of the CxOUT bit 0 = No interrupt flag will be set on a negative going edge of the CxOUT bit bit 5-4 CxPCH<1:0>: Comparator Positive Input Channel Select bits 11 = CxVP connects to AGND 10 = CxVP connects to FVR Buffer 2 01 = CxVP connects to VDAC 00 = CxVP connects to CxIN+ pin bit 3 Unimplemented: Read as `0' bit 2-0 CxNCH<2:0>: Comparator Negative Input Channel Select bits 111 = CxVN connects to AGND 110 = CxVN unconnected, input floating 101 = CxVN unconnected, input floating 100 = Reserved 011 = CxVN connects to CxIN3- pin(1) 010 = CxVN connects to CxIN2- pin(1) 001 = CxVN connects to CxIN1- pin 000 = CxVN connects to CxIN0- pin REGISTER 19-3: CMOUT: COMPARATOR OUTPUT REGISTER U-0 U-0 U-0 U-0 U-0 U-0 R-0/0 R-0/0 -- -- -- -- -- -- MC2OUT MC1OUT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-2 Unimplemented: Read as `0' bit 1 MC2OUT: Mirror Copy of C2OUT bit bit 0 MC1OUT: Mirror Copy of C1OUT bit DS40001770A-page 222 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 TABLE 19-3: Name ANSELA SUMMARY OF REGISTERS ASSOCIATED WITH COMPARATOR MODULE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page -- -- -- ANSA4 -- ANSA2 ANSA1 ANSA0 160 -- C1POL -- C1SP C1HYS C1SYNC 221 CM1CON0 C1ON C1OUT CM1CON1 C1INTP C1INTN CM2CON0 C2ON C2OUT CM2CON1 C2INTP C2INTN C1PCH<1:0> -- C2POL C2PCH<1:0> -- -- C1NCH<2:0> C2SP -- CMOUT -- -- -- -- FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> DAC1EN -- DAC1OE1 -- DAC1PSS<1:0> DAC1CON0 DAC1CON1 222 C2SYNC C2NCH<2:0> FVRCON -- C2HYS -- MC2OUT 222 MC1OUT ADFVR<1:0> -- 221 -- DAC1R<7:0> 222 194 215 215 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 105 PIE2 OSFIE C2IE C1IE -- BCL1IE TMR6IE TMR4IE CCP2IE 107 PIR2 OSFIF C2IF C1IF -- BCL1IF TMR6IF TMR4IF CCP2IF 112 -- -- TRISA5 TRISA4 --(1) TRISA2 TRISA1 TRISA0 159 TRISC7(2) TRISC6(2) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 173 INTCON TRISA TRISC(2) Legend: Note 1: 2: -- = unimplemented location, read as `0'. Shaded cells are unused by the comparator module. Unimplemented, read as `1'. PIC16F1619 only. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 223 PIC16(L)F1615/9 20.0 ZERO-CROSS DETECTION (ZCD) MODULE 20.1 The ZCD module detects when an A/C signal crosses through the ground potential. The actual zero crossing threshold is the zero crossing reference voltage, VCPINV, which is typically 0.75V above ground. The connection to the signal to be detected is through a series current limiting resistor. The module applies a current source or sink to the ZCD pin to maintain a constant voltage on the pin, thereby preventing the pin voltage from forward biasing the ESD protection diodes. When the applied voltage is greater than the reference voltage, the module sinks current. When the applied voltage is less than the reference voltage, the module sources current. The current source and sink action keeps the pin voltage constant over the full range of the applied voltage. The ZCD module is shown in the simplified block diagram Figure 20-2. External Resistor Selection The ZCD module requires a current limiting resistor in series with the external voltage source. The impedance and rating of this resistor depends on the external source peak voltage. Select a resistor value that will drop all of the peak voltage when the current through the resistor is nominally 300 A. Refer to Equation 20-1 and Figure 20-1. Make sure that the ZCD I/O pin internal weak pull-up is disabled so it does not interfere with the current source and sink. EQUATION 20-1: EXTERNAL RESISTOR V PEAK R SERIES = ----------------4 3 10 The ZCD module is useful when monitoring an A/C waveform for, but not limited to, the following purposes: * * * * A/C period measurement Accurate long term time measurement Dimmer phase delayed drive Low EMI cycle switching FIGURE 20-1: VPEAK EXTERNAL VOLTAGE VMAXPEAK VMINPEAK VCPINV DS40001770A-page 224 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 FIGURE 20-2: SIMPLIFIED ZCD BLOCK DIAGRAM VPULLUP Rev. 10-000194B 5/14/2014 optional VDD RPULLUP - Zcpinv ZCDxIN RSERIES RPULLDOWN + External voltage source optional ZCDx_output D Q ZCDxPOL ZCDxOUT bit Q1 Interrupt det ZCDxINTP ZCDxINTN Set ZCDIF flag Interrupt det 2014 Microchip Technology Inc. Preliminary DS40001770A-page 225 PIC16(L)F1615/9 20.2 ZCD Logic Output 20.5 The ZCD module includes a Status bit, which can be read to determine whether the current source or sink is active. The ZCDxOUT bit of the ZCDxCON register is set when the current sink is active, and cleared when the current source is active. The ZCDxOUT bit is affected by the polarity bit. 20.3 ZCD Logic Polarity The ZCDxPOL bit of the ZCDxCON register inverts the ZCDxOUT bit relative to the current source and sink output. When the ZCDxPOL bit is set, a ZCDxOUT high indicates that the current source is active, and a low output indicates that the current sink is active. The ZCDxPOL bit affects the ZCD interrupts. See Section 20.4 "ZCD Interrupts". Correcting for VCPINV offset The actual voltage at which the ZCD switches is the reference voltage at the non-inverting input of the ZCD op amp. For external voltage source waveforms other than square waves, this voltage offset from zero causes the zero-cross event to occur either too early or too late. When the waveform is varying relative to VSS, then the zero cross is detected too early as the waveform falls and too late as the waveform rises. When the waveform is varying relative to VDD, then the zero cross is detected too late as the waveform rises and too early as the waveform falls. The actual offset time can be determined for sinusoidal waveforms with the corresponding equations shown in Equation 20-2. EQUATION 20-2: ZCD EVENT OFFSET When External Voltage Source is relative to Vss: 20.4 ZCD Interrupts An interrupt will be generated upon a change in the ZCD logic output when the appropriate interrupt enables are set. A rising edge detector and a falling edge detector are present in the ZCD for this purpose. The ZCDIF bit of the PIR3 register will be set when either edge detector is triggered and its associated enable bit is set. The ZCDxINTP enables rising edge interrupts and the ZCDxINTN bit enables falling edge interrupts. Both are located in the ZCDxCON register. T OFFSET When External Voltage Source is relative to VDD: T OFFSET To fully enable the interrupt, the following bits must be set: * ZCDIE bit of the PIE3 register * ZCDxINTP bit of the ZCDxCON register (for a rising edge detection) * ZCDxINTN bit of the ZCDxCON register (for a falling edge detection) * PEIE and GIE bits of the INTCON register Changing the ZCDxPOL bit will cause an interrupt, regardless of the level of the ZCDxEN bit. The ZCDIF bit of the PIR3 register must be cleared in software as part of the interrupt service. If another edge is detected while this flag is being cleared, the flag will still be set at the end of the sequence. Vcpinv asin ------------------ V PEAK = ---------------------------------2 Freq V DD - Vcpinv asin -------------------------------- V PEAK = ------------------------------------------------2 Freq This offset time can be compensated for by adding a pull-up or pull-down biasing resistor to the ZCD pin. A pull-up resistor is used when the external voltage source is varying relative to VSS. A pull-down resistor is used when the voltage is varying relative to VDD. The resistor adds a bias to the ZCD pin so that the target external voltage source must go to zero to pull the pin voltage to the VCPINV switching voltage. The pull-up or pull-down value can be determined with the equations shown in Equation 20-3 or Equation 20-4. EQUATION 20-3: ZCD PULL-UP/DOWN When External Signal is relative to Vss: R SERIE S V PULLUP - V cpinv R PULLUP = -----------------------------------------------------------------------V cpinv When External Signal is relative to VDD: R SERIES V cpinv R PULLDOWN = ------------------------------------------- V DD - V cpinv DS40001770A-page 226 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 The pull-up and pull-down resistor values are significantly affected by small variations of VCPINV. Measuring VCPINV can be difficult, especially when the waveform is relative to VDD. However, by combining Equations 20-2 and 20-3, the resistor value can be determined from the time difference between the ZCDx_output high and low periods. Note that the time difference, T, is 4*TOFFSET. The equation for determining the pull-up and pull-down resistor values from the high and low ZCDx_output periods is shown in Equation 20-4. The ZCDx_output signal can be directly observed on the ZCDxOUT pin by setting the ZCDxOE bit. EQUATION 20-4: 20.6 Handling VPEAK variations If the peak amplitude of the external voltage is expected to vary, the series resistor must be selected to keep the ZCD current source and sink below the design maximum range of 600 A and above a reasonable minimum range. A general rule of thumb is that the maximum peak voltage can be no more than six times the minimum peak voltage. To ensure that the maximum current does not exceed 600 A and the minimum is at least 100 A, compute the series resistance as shown in Equation 20-5. The compensating pull-up for this series resistance can be determined with Equation 20-3 because the pull-up value is independent from the peak voltage. EQUATION 20-5: V BI A S R = R SERIES ---------------------------------------------------------------- - 1 T V PE AK sin Freq ---------- 2 SERIES R FOR V RANGE V MAXPEAK + V MINPEAK R SERIES = ---------------------------------------------------------4 7 10 R is pull-up or pull-down resistor. VBIAS is VPULLUP when R is pull-up or VDD when R is pull-down. T is the ZCDxOUT high and low period difference. 20.7 Operation During Sleep The ZCD current sources and interrupts are unaffected by Sleep. 20.8 Effects of a Reset The ZCD circuit can be configured to default to the active or inactive state on Power-On-Reset (POR). When the ZCD Configuration bit is cleared, the ZCD circuit will be active at POR. When the ZCD Configuration bit is set, the ZCDxEN bit of the ZCDxCON register must be set to enable the ZCD module. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 227 PIC16(L)F1615/9 20.9 Register Definitions: ZCD Control REGISTER 20-1: ZCDxCON: ZERO CROSS DETECTION CONTROL REGISTER R/W-q/q U-0 R-x/x R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0 ZCDxEN -- ZCDxOUT ZCDxPOL -- -- ZCDxINTP ZCDxINTN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = value depends on configuration bits bit 7 ZCDxEN: Zero-Cross Detection Enable bit 1 = Zero-cross detect is enabled. ZCD pin is forced to output to source and sink current. 0 = Zero-cross detect is disabled. ZCD pin operates according to PPS and TRIS controls. bit 6 Unimplemented: Read as `0' bit 5 ZCDxOUT: Zero-Cross Detection Logic Level bit ZCDxPOL bit = 0: 1 = ZCD pin is sinking current 0 = ZCD pin is sourcing current ZCDxPOL bit = 1: 1 = ZCD pin is sourcing current 0 = ZCD pin is sinking current bit 4 ZCDxPOL: Zero-Cross Detection Logic Output Polarity bit 1 = ZCD logic output is inverted 0 = ZCD logic output is not inverted bit 3-2 Unimplemented: Read as `0' bit 1 ZCDxINTP: Zero-Cross Positive Edge Interrupt Enable bit 1 = ZCDIF bit is set on low-to-high ZCDx_output transition 0 = ZCDIF bit is unaffected by low-to-high ZCDx_output transition bit 0 ZCDxINTN: Zero-Cross Negative Edge Interrupt Enable bit 1 = ZCDIF bit is set on high-to-low ZCDx_output transition 0 = ZCDIF bit is unaffected by high-to-low ZCDx_output transition TABLE 20-1: SUMMARY OF REGISTERS ASSOCIATED WITH THE ZCD MODULE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page -- -- CWGIE ZCDIE CLC4IE CLC3IE CLC2IE CLC1IE 108 -- -- CWGIF ZCDIF CLC4IF CLC3IF CLC2IF CLC1IF ZCD1EN -- ZCD1OUT ZCD1POL -- -- Name PIE3 PIR3 ZCD1CON Legend: CONFIG2 Legend: 113 228 -- = unimplemented, read as `0'. Shaded cells are unused by the ZCD module. TABLE 20-2: Name ZCD1INTP ZCD1INTN Bits SUMMARY OF CONFIGURATION WORD WITH THE ZCD MODULE Bit 10/2 Bit 9/1 Bit 8/0 Register on Page LPBOR BORV STVREN PLLEN 71 -- PPS1WAY Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 13:8 -- -- LVP DEBUG 7:0 ZCD -- -- -- WRT<1:0> -- = unimplemented location, read as `0'. Shaded cells are not used by the ZCD module. DS40001770A-page 228 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 21.0 21.1.2 TIMER0 MODULE 8-BIT COUNTER MODE The Timer0 module is an 8-bit timer/counter with the following features: In 8-Bit Counter mode, the Timer0 module will increment on every rising or falling edge of the T0CKI pin. * * * * * * 8-Bit Counter mode using the T0CKI pin is selected by setting the TMR0CS bit in the OPTION_REG register to `1'. 8-bit timer/counter register (TMR0) 3-bit prescaler (independent of Watchdog Timer) Programmable internal or external clock source Programmable external clock edge selection Interrupt on overflow TMR0 can be used to gate Timer1 The rising or falling transition of the incrementing edge for either input source is determined by the TMR0SE bit in the OPTION_REG register. Figure 21-1 is a block diagram of the Timer0 module. 21.1 Timer0 Operation The Timer0 module can be used as either an 8-bit timer or an 8-bit counter. 21.1.1 8-BIT TIMER MODE The Timer0 module will increment every instruction cycle, if used without a prescaler. 8-bit Timer mode is selected by clearing the TMR0CS bit of the OPTION_REG register. When TMR0 is written, the increment is inhibited for two instruction cycles immediately following the write. Note: The value written to the TMR0 register can be adjusted, in order to account for the two instruction cycle delay when TMR0 is written. FIGURE 21-1: TIMER0 BLOCK DIAGRAM Rev. 10-000017A 8/5/2013 TMR0CS Fosc/4 T0CKI(1) PSA 0 1 TMR0SE 1 write to TMR0 Prescaler R 0 FOSC/2 T0CKI Sync Circuit T0_overflow TMR0 Q1 set bit TMR0IF PS<2:0> Note 1: The T0CKI prescale output frequency should not exceed FOSC/8. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 229 PIC16(L)F1615/9 21.1.3 SOFTWARE PROGRAMMABLE PRESCALER A software programmable prescaler is available for exclusive use with Timer0. The prescaler is enabled by clearing the PSA bit of the OPTION_REG register. Note: The Watchdog Timer (WDT) uses its own independent prescaler. There are eight prescaler options for the Timer0 module ranging from 1:2 to 1:256. The prescale values are selectable via the PS<2:0> bits of the OPTION_REG register. In order to have a 1:1 prescaler value for the Timer0 module, the prescaler must be disabled by setting the PSA bit of the OPTION_REG register. The prescaler is not readable or writable. All instructions writing to the TMR0 register will clear the prescaler. 21.1.4 TIMER0 INTERRUPT Timer0 will generate an interrupt when the TMR0 register overflows from FFh to 00h. The TMR0IF interrupt flag bit of the INTCON register is set every time the TMR0 register overflows, regardless of whether or not the Timer0 interrupt is enabled. The TMR0IF bit can only be cleared in software. The Timer0 interrupt enable is the TMR0IE bit of the INTCON register. Note: 21.1.5 The Timer0 interrupt cannot wake the processor from Sleep since the timer is frozen during Sleep. 8-BIT COUNTER MODE SYNCHRONIZATION When in 8-Bit Counter mode, the incrementing edge on the T0CKI pin must be synchronized to the instruction clock. Synchronization can be accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the instruction clock. The high and low periods of the external clocking source must meet the timing requirements as shown in Section 35.0 "Electrical Specifications". 21.1.6 OPERATION DURING SLEEP Timer0 cannot operate while the processor is in Sleep mode. The contents of the TMR0 register will remain unchanged while the processor is in Sleep mode. DS40001770A-page 230 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 21.2 Register Definitions: Option Register REGISTER 21-1: OPTION_REG: OPTION REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 WPUEN INTEDG TMR0CS TMR0SE PSA R/W-1/1 R/W-1/1 R/W-1/1 PS<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 WPUEN: Weak Pull-Up Enable bit 1 = All weak pull-ups are disabled (except MCLR, if it is enabled) 0 = Weak pull-ups are enabled by individual WPUx latch values bit 6 INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of INT pin 0 = Interrupt on falling edge of INT pin bit 5 TMR0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (FOSC/4) bit 4 TMR0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Prescaler Assignment bit 1 = Prescaler is not assigned to the Timer0 module 0 = Prescaler is assigned to the Timer0 module bit 2-0 PS<2:0>: Prescaler Rate Select bits Bit Value 001 1:2 1:4 010 1:8 011 1 : 16 100 1 : 32 101 110 1 : 64 111 1 : 256 000 TABLE 21-1: Name Bit 7 Bit 6 OPTION_REG Legend: * Note 1: Bit 5 Bit 4 Bit 3 TRIGSEL<4:0> INTCON TRISA 1 : 128 SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0 ADCON2 TMR0 Timer0 Rate GIE PEIE TMR0IE INTE IOCIE WPUEN INTEDG TMR0CS TMR0SE PSA Bit 2 Bit 1 Bit 0 Register on Page -- -- -- 205 INTF IOCIF 105 TMR0IF PS<2:0> 231 Holding Register for the 8-bit Timer0 Count -- -- TRISA5 TRISA4 229* --(1) TRISA2 TRISA1 TRISA0 159 -- = Unimplemented location, read as `0'. Shaded cells are not used by the Timer0 module. Page provides register information. Unimplemented, read as `1'. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 231 PIC16(L)F1615/9 22.0 * Wake-up on overflow (external clock, Asynchronous mode only) * ADC Auto-Conversion Trigger(s) * Selectable Gate Source Polarity * Gate Toggle mode * Gate Single-Pulse mode * Gate Value Status * Gate Event Interrupt TIMER1 MODULE WITH GATE CONTROL The Timer1 module is a 16-bit timer/counter with the following features: * * * * * * 16-bit timer/counter register pair (TMR1H:TMR1L) Programmable internal or external clock source 2-bit prescaler Optionally synchronized comparator out Multiple Timer1 gate (count enable) sources Interrupt on overflow FIGURE 22-1: Figure 22-1 is a block diagram of the Timer1 module. TIMER1 BLOCK DIAGRAM T1GSS<1:0> Rev. 10-000018H 9/22/2014 T1GPPS PPS 00 T0_overflow 01 C1OUT_sync 10 C2OUT_sync 11 T1GSPM 0 1 D 1 Single Pulse Acq. Control D 0 Q T1GVAL Q1 Q T1GGO/DONE T1GPOL CK Q Interrupt TMR1ON R set bit TMR1GIF det T1GTM TMR1GE set flag bit TMR1IF TMR1ON EN T1_overflow TMR1 TMR1H (2) TMR1L Q Synchronized Clock Input 0 D 1 T1CLK T1SYNC TMR1CS<1:0> LFINTOSC (1) 11 10 T1CKI Fosc Internal Clock 01 00 Fosc/4 Internal Clock Prescaler 1,2,4,8 Synchronize(3) det 2 T1CKPS<1:0> Fosc/2 Internal Clock Sleep Input Note 1: ST Buffer is high speed type when using T1CKI. 2: Timer1 register increments on rising edge. 3: Synchronize does not operate while in Sleep. DS40001770A-page 232 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 22.1 Timer1 Operation 22.2 The Timer1 module is a 16-bit incrementing counter which is accessed through the TMR1H:TMR1L register pair. Writes to TMR1H or TMR1L directly update the counter. When used with an internal clock source, the module is a timer and increments on every instruction cycle. When used with an external clock source, the module can be used as either a timer or counter and increments on every selected edge of the external source. Timer1 is enabled by configuring the TMR1ON and TMR1GE bits in the T1CON and T1GCON registers, respectively. Table 22-1 displays the Timer1 enable selections. TABLE 22-1: TIMER1 ENABLE SELECTIONS Clock Source Selection The TMR1CS<1:0> bits of the T1CON register are used to select the clock source for Timer1. Table 22-2 displays the clock source selections. 22.2.1 INTERNAL CLOCK SOURCE When the internal clock source is selected, the TMR1H:TMR1L register pair will increment on multiples of FOSC as determined by the Timer1 prescaler. When the FOSC internal clock source is selected, the Timer1 register value will increment by four counts every instruction clock cycle. Due to this condition, a 2 LSB error in resolution will occur when reading the Timer1 value. To utilize the full resolution of Timer1, an asynchronous input signal must be used to gate the Timer1 clock input. The following asynchronous sources may be used: * Asynchronous event on the T1G pin to Timer1 gate * C1 or C2 comparator input to Timer1 gate Timer1 Operation TMR1ON TMR1GE 0 0 Off 0 1 Off 22.2.2 1 0 Always On 1 1 Count Enabled When the external clock source is selected, the Timer1 module may work as a timer or a counter. EXTERNAL CLOCK SOURCE When enabled to count, Timer1 is incremented on the rising edge of the external clock input T1CKI. The external clock source can be synchronized to the microcontroller system clock or it can run asynchronously. Note: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge after any one or more of the following conditions: *Timer1 enabled after POR *Write to TMR1H or TMR1L *Timer1 is disabled *Timer1 is disabled (TMR1ON = 0) when T1CKI is high then Timer1 is enabled (TMR1ON=1) when T1CKI is low. TABLE 22-2: CLOCK SOURCE SELECTIONS TMR1CS<1:0> Clock Source 11 LFINTOSC 10 External Clocking on T1CKI Pin 01 System Clock (FOSC) 00 Instruction Clock (FOSC/4) 2014 Microchip Technology Inc. Preliminary DS40001770A-page 233 PIC16(L)F1615/9 22.3 Timer1 Prescaler Timer1 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. The T1CKPS bits of the T1CON register control the prescale counter. The prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to TMR1H or TMR1L. 22.4 22.4.1 When switching from synchronous to asynchronous operation, it is possible to skip an increment. When switching from asynchronous to synchronous operation, it is possible to produce an additional increment. READING AND WRITING TIMER1 IN ASYNCHRONOUS COUNTER MODE Reading TMR1H or TMR1L while the timer is running from an external asynchronous clock will ensure a valid read (taken care of in hardware). However, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself, poses certain problems, since the timer may overflow between the reads. TABLE 22-4: T1GSS Timer1 Gate Timer1 gate can also be driven by multiple selectable sources. 22.5.1 TIMER1 GATE ENABLE The Timer1 Gate Enable mode is enabled by setting the TMR1GE bit of the T1GCON register. The polarity of the Timer1 Gate Enable mode is configured using the T1GPOL bit of the T1GCON register. When Timer1 Gate Enable mode is enabled, Timer1 will increment on the rising edge of the Timer1 clock source. When Timer1 Gate Enable mode is disabled, no incrementing will occur and Timer1 will hold the current count. See Figure 22-3 for timing details. TABLE 22-3: TIMER1 GATE ENABLE SELECTIONS T1CLK T1GPOL T1G 0 0 Counts 0 1 Holds Count 1 0 Holds Count 1 1 Counts 22.5.2 Timer1 Operation TIMER1 GATE SOURCE SELECTION Timer1 gate source selections are shown in Table 22-4. Source selection is controlled by the T1GSS<1:0> bits of the T1GCON register. The polarity for each available source is also selectable. Polarity selection is controlled by the T1GPOL bit of the T1GCON register. TIMER1 GATE SOURCES Timer1 Gate Source 00 Timer1 Gate pin (T1G) 01 Overflow of Timer0 (T0_overflow) (TMR0 increments from FFh to 00h) 10 Comparator 1 Output (C1_OUT_sync)(1) 11 Comparator 2 Output (C2_OUT_sync)(1) Note 1: 22.5 Timer1 can be configured to count freely or the count can be enabled and disabled using Timer1 gate circuitry. This is also referred to as Timer1 Gate Enable. Timer1 Operation in Asynchronous Counter Mode If control bit T1SYNC of the T1CON register is set, the external clock input is not synchronized. The timer increments asynchronously to the internal phase clocks. If the external clock source is selected then the timer will continue to run during Sleep and can generate an interrupt on overflow, which will wake-up the processor. However, special precautions in software are needed to read/write the timer (see Section 22.4.1 "Reading and Writing Timer1 in Asynchronous Counter Mode"). Note: For writes, it is recommended that the user simply stop the timer and write the desired values. A write contention may occur by writing to the timer registers, while the register is incrementing. This may produce an unpredictable value in the TMR1H:TMR1L register pair. Optionally synchronized comparator output. DS40001770A-page 234 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 22.5.2.1 T1G Pin Gate Operation 22.5.5 The T1G pin is one source for Timer1 gate control. It can be used to supply an external source to the Timer1 gate circuitry. 22.5.2.2 Timer0 Overflow Gate Operation When Timer0 increments from FFh to 00h, a low-tohigh pulse will automatically be generated and internally supplied to the Timer1 gate circuitry. 22.5.3 TIMER1 GATE TOGGLE MODE When Timer1 Gate Toggle mode is enabled, it is possible to measure the full-cycle length of a Timer1 gate signal, as opposed to the duration of a single level pulse. The Timer1 gate source is routed through a flip-flop that changes state on every incrementing edge of the signal. See Figure 22-4 for timing details. TIMER1 GATE VALUE STATUS When Timer1 Gate Value Status is utilized, it is possible to read the most current level of the gate control value. The value is stored in the T1GVAL bit in the T1GCON register. The T1GVAL bit is valid even when the Timer1 gate is not enabled (TMR1GE bit is cleared). 22.5.6 TIMER1 GATE EVENT INTERRUPT When Timer1 Gate Event Interrupt is enabled, it is possible to generate an interrupt upon the completion of a gate event. When the falling edge of T1GVAL occurs, the TMR1GIF flag bit in the PIR1 register will be set. If the TMR1GIE bit in the PIE1 register is set, then an interrupt will be recognized. The TMR1GIF flag bit operates even when the Timer1 gate is not enabled (TMR1GE bit is cleared). Timer1 Gate Toggle mode is enabled by setting the T1GTM bit of the T1GCON register. When the T1GTM bit is cleared, the flip-flop is cleared and held clear. This is necessary in order to control which edge is measured. Note: 22.5.4 Enabling Toggle mode at the same time as changing the gate polarity may result in indeterminate operation. TIMER1 GATE SINGLE-PULSE MODE When Timer1 Gate Single-Pulse mode is enabled, it is possible to capture a single pulse gate event. Timer1 Gate Single-Pulse mode is first enabled by setting the T1GSPM bit in the T1GCON register. Next, the T1GGO/ DONE bit in the T1GCON register must be set. The Timer1 will be fully enabled on the next incrementing edge. On the next trailing edge of the pulse, the T1GGO/ DONE bit will automatically be cleared. No other gate events will be allowed to increment Timer1 until the T1GGO/DONE bit is once again set in software. See Figure 22-5 for timing details. If the Single Pulse Gate mode is disabled by clearing the T1GSPM bit in the T1GCON register, the T1GGO/DONE bit should also be cleared. Enabling the Toggle mode and the Single-Pulse mode simultaneously will permit both sections to work together. This allows the cycle times on the Timer1 gate source to be measured. See Figure 22-6 for timing details. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 235 PIC16(L)F1615/9 22.6 Timer1 Interrupt The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls over, the Timer1 interrupt flag bit of the PIR1 register is set. To enable the interrupt on rollover, you must set these bits: * * * * Timer1 oscillator will continue to operate in Sleep regardless of the T1SYNC bit setting. TMR1ON bit of the T1CON register TMR1IE bit of the PIE1 register PEIE bit of the INTCON register GIE bit of the INTCON register The interrupt is cleared by clearing the TMR1IF bit in the Interrupt Service Routine. The TMR1H:TMR1L register pair and the TMR1IF bit should be cleared before enabling interrupts. Note: 22.7 Timer1 Operation During Sleep Timer1 can only operate during Sleep when setup in Asynchronous Counter mode. In this mode, an external crystal or clock source can be used to increment the counter. To set up the timer to wake the device: * * * * * TMR1ON bit of the T1CON register must be set TMR1IE bit of the PIE1 register must be set PEIE bit of the INTCON register must be set T1SYNC bit of the T1CON register must be set TMR1CS bits of the T1CON register must be configured The device will wake-up on an overflow and execute the next instructions. If the GIE bit of the INTCON register is set, the device will call the Interrupt Service Routine. FIGURE 22-2: TIMER1 INCREMENTING EDGE T1CKI = 1 when TMR1 Enabled T1CKI = 0 when TMR1 Enabled Note 1: 2: Arrows indicate counter increments. In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. DS40001770A-page 236 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 FIGURE 22-3: TIMER1 GATE ENABLE MODE TMR1GE T1GPOL T1G_in T1CKI T1GVAL Timer1 N FIGURE 22-4: N+1 N+2 N+3 N+4 TIMER1 GATE TOGGLE MODE TMR1GE T1GPOL T1GTM T1G_in T1CKI T1GVAL Timer1 N 2014 Microchip Technology Inc. N+1 N+2 N+3 N+4 Preliminary N+5 N+6 N+7 N+8 DS40001770A-page 237 PIC16(L)F1615/9 FIGURE 22-5: TIMER1 GATE SINGLE-PULSE MODE TMR1GE T1GPOL T1GSPM T1GGO/ Cleared by hardware on falling edge of T1GVAL Set by software DONE Counting enabled on rising edge of T1G T1G_in T1CKI T1GVAL Timer1 TMR1GIF DS40001770A-page 238 N N+1 N+2 Set by hardware on falling edge of T1GVAL Cleared by software Preliminary Cleared by software 2014 Microchip Technology Inc. PIC16(L)F1615/9 FIGURE 22-6: TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE TMR1GE T1GPOL T1GSPM T1GTM T1GGO/ Cleared by hardware on falling edge of T1GVAL Set by software DONE Counting enabled on rising edge of T1G T1G_in T1CKI T1GVAL Timer1 TMR1GIF N Cleared by software 2014 Microchip Technology Inc. N+1 N+2 N+3 Set by hardware on falling edge of T1GVAL Preliminary N+4 Cleared by software DS40001770A-page 239 PIC16(L)F1615/9 22.8 Register Definitions: Timer1 Control REGISTER 22-1: R/W-0/u T1CON: TIMER1 CONTROL REGISTER R/W-0/u TMR1CS<1:0> R/W-0/u R/W-0/u U-0 R/W-0/u U-0 R/W-0/u -- T1SYNC -- TMR1ON T1CKPS<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 TMR1CS<1:0>: Timer1 Clock Source Select bits 11 =LFINTOSC 10 =Timer1 Clock source is T1CKI 01 =FOSC 00 =FOSC/4 bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits 11 =1:8 Prescale value 10 =1:4 Prescale value 01 =1:2 Prescale value 00 =1:1 Prescale value bit 3 Unimplemented: Read as `0' bit 2 T1SYNC: Timer1 Synchronization Control bit 1 = Do not synchronize asynchronous clock input 0 = Synchronize asynchronous clock input with system clock (FOSC) bit 1 Unimplemented: Read as `0' bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 and clears Timer1 gate flip-flop DS40001770A-page 240 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 REGISTER 22-2: T1GCON: TIMER1 GATE CONTROL REGISTER R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W/HC-0/u R-x/x TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ DONE T1GVAL R/W-0/u R/W-0/u T1GSS<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared HC = Bit is cleared by hardware bit 7 TMR1GE: Timer1 Gate Enable bit If TMR1ON = 0: This bit is ignored If TMR1ON = 1: 1 = Timer1 counting is controlled by the Timer1 gate function 0 = Timer1 counts regardless of Timer1 gate function bit 6 T1GPOL: Timer1 Gate Polarity bit 1 = Timer1 gate is active-high (Timer1 counts when gate is high) 0 = Timer1 gate is active-low (Timer1 counts when gate is low) bit 5 T1GTM: Timer1 Gate Toggle Mode bit 1 = Timer1 Gate Toggle mode is enabled 0 = Timer1 Gate Toggle mode is disabled and toggle flip-flop is cleared Timer1 gate flip-flop toggles on every rising edge. bit 4 T1GSPM: Timer1 Gate Single-Pulse Mode bit 1 = Timer1 gate Single-Pulse mode is enabled and is controlling Timer1 gate 0 = Timer1 gate Single-Pulse mode is disabled bit 3 T1GGO/DONE: Timer1 Gate Single-Pulse Acquisition Status bit 1 = Timer1 gate single-pulse acquisition is ready, waiting for an edge 0 = Timer1 gate single-pulse acquisition has completed or has not been started bit 2 T1GVAL: Timer1 Gate Value Status bit Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L. Unaffected by Timer1 Gate Enable (TMR1GE). bit 0 T1GSS<1:0>: Timer1 Gate Source Select bits 11 =Comparator 2 optionally synchronized output (C2_OUT_sync) 10 =Comparator 1 optionally synchronized output (C1_OUT_sync) 01 =Timer0 overflow output (T0_overflow) 00 =Timer1 gate pin (T1G) 2014 Microchip Technology Inc. Preliminary DS40001770A-page 241 PIC16(L)F1615/9 TABLE 22-5: Name SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSELA -- -- -- ANSA4 -- ANSA2 ANSA1 ANSA0 160 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 105 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 106 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF PIE1 PIR1 TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Count TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Count TRISA -- T1CON TMR1CS<1:0> T1GCON Legend: * Note 1: TMR1GE -- T1GPOL TRISA5 TRISA4 T1CKPS<1:0> T1GTM T1GSPM 111 236* 236* --(1) TRISA2 TRISA1 TRISA0 159 -- T1SYNC -- TMR1ON 240 T1GGO/ DONE T1GVAL T1GSS<1:0> 241 -- = unimplemented location, read as `0'. Shaded cells are not used by the Timer1 module. Page provides register information. Unimplemented, read as `1'. DS40001770A-page 242 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 23.0 TIMER2/4/6 MODULE The Timer2/4/6 modules are 8-bit incorporate the following features: timers that * 8-bit Timer and Period registers (TMR2 and PR2, respectively) * Readable and writable (both registers) * Software programmable prescaler (1:1 to 1:128) * Software programmable postscaler (1:1 to 1:16) * Interrupt on TMR2 match with PR2 * One-shot operation * Full asynchronous operation * Includes Hardware Limit Timer (HLT) extension * Alternate clock sources * External Timer Reset signal sources * Configurable Timer Reset operation See Figure 23-1 for Timer2 clock sources. See Figure 23-2 for a block diagram of Timer2 with HLT. Note: Three identical Timer2 modules are implemented on this device. The timers are named Timer2, Timer4, and Timer6. All references to Timer2 apply as well to Timer4 and Timer6. All references to PR2 apply as well to PR4 and PR6. FIGURE 23-1: TIMER2 CLOCK SOURCE BLOCK DIAGRAM Notes: TxCLKCON Rev. 10-000 169B 5/29/201 4 TXINPPS TXIN PPS TMR2_clk 2014 Microchip Technology Inc. Preliminary DS40001770A-page 243 PIC16(L)F1615/9 FIGURE 23-2: TIMER2 WITH HARDWARE LIMIT TIMER (HLT) BLOCK DIAGRAM RSEL TxINPPS TxIN PPS Rev. 10-000 168B 5/29/201 4 MODE<4:0> TMRx_ers Edg e Detecto r Level Dete ctor Mode Control (2 clock Sync) MODE<3> reset CCP_pset MODE<4:3>=01 enable D MODE<4:1>=1011 Q Clear ON CKPOL 0 Pre scaler TMRx_clk TMRx 3 CKPS<2:0> Sync 1 Fosc/4 PSYNC R Set flag bi t TMRxIF Comparator Postscaler TMRx_postscaled 4 ON Sync (2 Clocks) 1 PRx OUTPS<3:0> 0 CKSYNC Note 1: 2: Signal to the CCP to trigger the PWM pulse See Section 22.5 for description of CCP interaction in the different TMR modes DS40001770A-page 244 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 23.1 Timer2 Operation The 7-bit counter/prescaler on the clock input allows for several prescaler options, from direct input to divideby-128. These options are selected by the prescaler control bits CKPS<2:0> of the TxCON register. The value of TMR2 is compared to that of the Period register, PR2, on each clock cycle. When the two values match, the comparator resets the value of TMR2 to 00h on the next cycle and drives the output counter/ postscaler (see Section 23.2 "Timer2 Interrupt"). In addition, the Timer can be reset through the use of an external Reset signal as outlined in Section 23.4 "External Reset Sources". The TMR2 and PR2 registers are both directly readable and writable. The TMR2 register is cleared on any device Reset, whereas the PR2 register initializes to FFh. Both the prescaler and postscaler counters are cleared on the following events: * a write to the TMR2 register * a write to the T2CON register * Power-on Reset (POR) FIGURE 23-3: * * * * * * * Brown-out Reset (BOR) MCLR Reset Watchdog Timer (WDT) Reset Stack Overflow Reset Stack Underflow Reset RESET Instruction External Reset Source events, which resets the timer. Note: 23.2 TMR2 is not cleared when T2CON is written. Timer2 Interrupt Timer2 can also generate a device interrupt. The interrupt is generated when the postscaler counter matches one of 16 postscale options (from 1:1 through 1:16), which is selected with the postscaler control bits, OUTPS<3:0> of the T2CON register. The interrupt is enabled by setting the TMR2 Interrupt Enable bit, TMR2IE, of the PIE1 register. The interrupt timing is illustrated in Figure 23-3. TIMER2 PRESCALER, POSTSCALER, AND INTERRUPT TIMING DIAGRAM 0b010 CKPS PRx 1 OUTPS 2 TMRx_clk TMRx 0 1 0 1 0 1 0 TMRx_postscaled (1) TMRxIF Note 1: Setting the interrupt flag is synchronized with the instruction clock. Synchronization may take as many as 2 instruction cycles 2014 Microchip Technology Inc. Preliminary DS40001770A-page 245 PIC16(L)F1615/9 23.3 Timer2 Output 23.5 The Timer2 module's primary output is TMR2_postscaled, which pulses for a single TMR2_clk period upon each match of the postscaler counter and the OUTPS TMR2xCON. The PR2 postscaler is incremented each time the TMR2 value matches the PR2 value. this signal can be selected as an input to several other input modules: * The CRC memory scanner, as a trigger for Triggered mode * The ADC module, as an auto-conversion trigger * Both SMT modules, as both a window and/or a signal input * CWG, as an auto-shutdown source In addition, the Timer2 is also used by the CCP module for pulse generation in PWM mode. Both the actual TMR2 value as well as other internal signals are sent to the CCP module to properly clock both the period and pulse width of the PWM signal. See Section 26.4 "CCP/PWM Clock Selection" for more details on setting up Timer2 for use with the CCP, as well as the timing diagrams in Section 23.5 "Operation Examples" for examples of how the varying Timer2 modes affect CCP PWM output. 23.4 Operation Examples Unless otherwise specified, the following notes apply to the following timing diagrams: - Both the prescaler and postscaler are set to 1:1 (both the CKPS and OUTPS bits in the TxCON register are cleared). - The diagrams illustrate any clock except FOSC/4 and show clock-sync delays of at least two full cycles for both ON and Timer2_ers. When using FOSC/4, the clocksync delay is at least one instruction period for Timer2_ers; ON applies in the next instruction period. - ON and Timer2_ers are somewhat generalized, and clock-sync delays may produce results that are slightly different than illustrated. - The PWM Duty Cycle and PWM output are illustrated assuming that the timer is used for the PWM function of the CCP module as described in Section 26.4 "CCP/PWM Clock Selection". The signals are not a part of the Timer2 module. External Reset Sources In addition to the clock source, the Timer2 also takes in an external Reset source. This external Reset source is selected for Timer2, Timer4, and Timer6 with the T2RST, T4RST, and T6RST registers, respectively. This source can control starting and stopping of the timer, as well as resetting the timer, depending on which mode the timer is in. The mode of the timer is controlled by the MODE<4:0> bits of the TMRxHLT register. 23.4.1 ONE-SHOT MODE The MODE<3> bit of the TMRxHLT register controls whether the timer is in either the One-Shot mode or the original Normal Period mode. When this bit is set, the timer acts in the One-Shot mode, meaning that upon the timer register matching the PRx period register, the timer will stop incrementing until the timer is manually started again. DS40001770A-page 246 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 23.5.1 SOFTWARE GATE MODE The Software Gate mode corresponds to legacy Timer2 operation. The timer increments with each clock input when ON = 1 and does not increment when ON = 0. When the TMRx count equals the PRx period count the timer resets on the next clock and continues counting from 0. Operation with the ON bit software controlled is illustrated in Figure 23-4. With PRx = 5, the counter advances until TMRx = 5, and goes to zero with the next clock. FIGURE 23-4: SOFTWARE GATE MODE TIMING DIAGRAM Rev. 10-000195B 5/30/2014 0b00000 MODE TMRx_clk Instruction(1) BSF BCF BSF ON PRx TMRx 5 0 1 2 3 4 5 0 1 2 3 4 5 0 1 2 3 4 5 0 1 TMRx_postscaled PWM Duty Cycle 3 PWM Output Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 247 PIC16(L)F1615/9 23.5.2 HARDWARE GATE MODE The Hardware Gate modes operate the same as the software gate mode except the TMRx_ers external signal can also gate the timer. When used with the CCP the gating extends the PWM period. If the timer is stopped when the PWM output is high then the duty cycle is also extended. When MODE<4:0> = 00001 then the timer is stopped when the external signal is high. When MODE<4:0> = 00010, the timer is stopped when the external signal is low. Figure 23-5 illustrates the hardware gating mode for MODE<4:0> = 00001 in which a high input level stops the counter. FIGURE 23-5: HARDWARE GATE MODE TIMING DIAGRAM Rev. 10-000 196B 5/30/201 4 0b00001 MODE TMRx_clk TMRx_ers PRx TMRx 5 0 1 2 3 4 5 0 1 2 3 4 5 0 1 TMRx_postscaled PWM Duty Cycle 3 PWM Output DS40001770A-page 248 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 23.5.3 EDGE-TRIGGERED HARDWARE LIMIT MODE In Edge-Triggered Hardware Limit mode, the timer can be reset by the TMRx_ers external signal before the timer reaches the period count. Three types of Resets are possible: * Reset on rising or falling edge (MODE<4:0> = 00011) * Reset on rising edge (MODE<4:0> = 00100) * Reset on falling edge (MODE<4:0> = 00101) When the timer is used in conjunction with the CCP in PWM mode then an early Reset shortens the period and restarts the PWM pulse after a two clock delay. Refer to Figure 23-6. FIGURE 23-6: EDGE-TRIGGERED HARDWARE LIMIT MODE TIMING DIAGRAM Rev. 10-000 197B 5/30/201 4 0b00100 MODE TMRx_clk PRx 5 Instruction(1) BSF BCF BSF ON TMRx_ers TMRx 0 1 2 0 1 2 3 4 5 0 1 2 3 4 5 0 1 TMRx_postscaled PWM Duty Cycle 3 PWM Output Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 249 PIC16(L)F1615/9 23.5.4 LEVEL-TRIGGERED HARDWARE LIMIT MODE In the Level-Triggered Hardware Limit Timer modes, the counter is reset by high or low levels of the external signal TMRx_ers, as shown in Figure 23-7. Selecting MODE<4:0> = 00110 will cause the timer to reset on a low level external signal. Selecting MODE<4:0> = 00111 will cause the timer to reset on a high level external signal. In the example, the counter is reset while TMRx_ers = 1. ON is controlled by BSF and BCF instructions. When ON = 0 the external signal is ignored. When the CCP uses the timer as the PWM time base then an external signal Reset will set the PWM output high after a two clock synchronization delay or the timer matches the PRx period value. The PWM output will remain high until the external signal is released and the timer counts up to match the CCPRx pulse width value. FIGURE 23-7: LEVEL-TRIGGERED HARDWARE LIMIT TIMING DIAGRAM Rev. 10-000198B 5/30/2014 0b00111 MODE TMRx_clk 5 PRx Instruction(1) BSF BCF BSF ON TMRx_ers 0 TMRx 1 2 0 1 2 3 4 5 0 0 1 2 3 4 5 0 TMRx_postscaled PWM Duty Cycle 3 PWM Output Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input. DS40001770A-page 250 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 23.5.5 ONE-SHOT MODE When One-Shot mode is used in conjunction with the CCP PWM operation the PWM pulse drive starts concurrent with setting the ON bit. Clearing the ON bit while the PWM drive is active will extend the PWM drive. The PWM drive will terminate when the timer value matches the CCPRx pulse width value. The PWM drive will remain off until software sets the ON bit to start another cycle. If software clears the ON bit after the CCPRx match but before the PRx match then the PWM drive will be extended by the length of time the ON bit remains cleared. Another timing cycle can only be initiated by setting the ON bit after it has been cleared by a PRx period count match. In One-Shot mode, the timer resets and the ON bit is cleared when the timer value matches the PRx period value. The ON bit must be set by software to start another timer cycle. Setting MODE<4:0> = 01000 selects One-Shot mode which is illustrated in Figure 23-8. In the example, ON is controlled by BSF and BCF instructions. In the first case, a BSF instruction sets ON and the counter runs to completion and clears ON. In the second case, a BSF instruction starts the cycle, BCF/BSF instructions turn the counter off and on during the cycle, and then it runs to completion. FIGURE 23-8: ONE-SHOT MODE TIMING DIAGRAM Rev. 10-000199B 5/30/2014 0b01000 MODE TMRx_clk 5 PRx Instruction(1) BSF BSF BCF BSF ON TMRx 0 1 2 3 4 5 0 1 2 3 4 5 0 TMRx_postscaled PWM Duty Cycle 3 PWM Output Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 251 PIC16(L)F1615/9 23.5.6 EDGE-TRIGGERED ONE-SHOT MODE The Edge-Triggered One-Shot modes start the timer on an edge from the external signal input, after the ON bit is set, and clear the ON bit when the timer matches the PRx period value. The following edges will start the timer: * Rising edge (MODE<4:0> = 01001) * Falling edge (MODE<4:0>= 01010) * Rising or Falling edge (MODE<4:0> = 01011) FIGURE 23-9: If the timer is halted by clearing the ON bit then another TMRx_ers edge is required after the ON bit is set to resume counting. Figure 23-9 illustrates operation in the rising edge One-Shot mode. When this mode is used in conjunction with the CCP then the edge-trigger will activate the PWM drive and the PWM drive will deactivate when the timer matches the CCPRx pulse width value and stay deactivated when the timer halts at the PRx period count match. EDGE-TRIGGERED ONE-SHOT MODE TIMING DIAGRAM Rev. 10-000200B 5/30/2014 0b01001 MODE TMRx_clk 5 PRx Instruction(1) BSF BSF BCF ON TMRx_ers TMRx 0 1 2 3 4 5 0 1 2 TMRx_out TMRx_postscaled PWM Duty Cycle 3 PWM Output Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input. DS40001770A-page 252 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 23.5.7 EDGE-TRIGGERED HARDWARE LIMIT ONE-SHOT MODE In Edge-Triggered Hardware Limit One-Shot modes the timer starts on the first external signal edge after the ON bit is set and resets on all subsequent edges. Only the first edge after the ON bit is set is needed to start the timer. The counter will resume counting automatically two clocks after all subsequent external Reset edges. Edge triggers are as follows: * Rising edge start and reset (MODE<4:0> = 01100) * Falling edge start and reset (MODE<4:0> = 01101) The timer resets and clears the ON bit when the timer value matches the PRx period value. External signal edges will have no effect until after software sets the ON bit. Figure 23-10 illustrates the rising edge hardware limit one-shot operation. When this mode is used in conjunction with the CCP then the first starting edge trigger, and all subsequent Reset edges, will activate the PWM drive. The PWM drive will deactivate when the timer matches the CCPRx pulse width value and stay deactivated until the timer halts at the PRx period match unless an external signal edge resets the timer before the match occurs. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 253 EDGE-TRIGGERED HARDWARE LIMIT ONE-SHOT TIMING DIAGRAM Rev. 10-000 201B 5/30/201 4 MODE 0b01100 TMRx_clk 5 PRx Instruction(1) BSF BSF ON TMRx_ers 0 TMRx 1 2 3 4 5 0 1 2 0 1 2 3 4 Preliminary TMRx_postscaled PWM Duty Cycle 3 PWM Output Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input. 5 0 PIC16(L)F1615/9 DS40001770A-page 254 FIGURE 23-10: 2014 Microchip Technology Inc. PIC16(L)F1615/9 23.5.8 LEVEL TRIGGERED HARDWARE LIMIT ONE-SHOT MODES In Level Triggered One-Shot mode the timer count is reset on the external signal level and starts counting when the external signal level relinquishes the Reset. Reset levels are selected as follows: * High Reset level (MODE<4:0> = 01110) * Low Reset level (MODE<4:0> = 01111) When the timer count matches the PRx period count then the timer is reset and the ON bit is cleared. When the ON bit is cleared by either a PRx match or by software control a new external signal edge is required after the ON bit is set to start the counter. When Level Triggered Reset One-Shot mode is used in conjunction with the CCP PWM operation the PWM drive goes active with the external signal edge that starts the timer. The PWM drive goes inactive when the timer count equals the CCPRx pulse width count. The PWM drive does not go active when the timer count clears at the PRx period count match. 23.6 Timer2 Operation During Sleep When PSYNC = 1, Timer2 cannot be operated while the processor is in Sleep mode. The contents of the TMR2 and PR2 registers will remain unchanged while processor is in Sleep mode. When PSYNC = 0, Timer2 will operate in Sleep as long as the clock source selected is also still running. Selecting the LFINTOSC, MFINTOSC, or HFINTOSC oscillator as the timer clock source will keep the selected oscillator running during Sleep. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 255 TLEVEL-TRIGGERED HARDWARE LIMIT ONE-SHOT MODE TIMING DIAGRAM Rev. 10-000 202A 12/20/201 3 MODE 0b1110 TMRx_clk 5 PRx Instruction(1) BS F BS F ON TMRx_ers TMRx 0 1 2 3 4 5 0 1 0 1 2 3 TMRx_postscaled PWM Duty Cycle 3 Preliminary PWM Output Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input. 4 5 0 PIC16(L)F1615/9 DS40001770A-page 256 FIGURE 23-11: 2014 Microchip Technology Inc. PIC16(L)F1615/9 23.7 Register Definitions: Timer2/4/6 Control Long bit name prefixes for the Timer2/4/6 peripherals are shown in Table 23-1. Refer to Section 1.1 "Register and Bit Naming Conventions" for more information. TABLE 23-1: Peripheral Bit Name Prefix TMR2 TMR2 TMR4 TMR4 TMR6 TMR6 REGISTER 23-1: TxCLKCON: TIMERx CLOCK SELECTION REGISTER U-0 U-0 U-0 U-0 -- -- -- -- R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 TxCS<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-4 Unimplemented: Read as `0' bit 3-0 TxCS: Timerx Clock Selection bits 1111 = Reserved. No channel connected. * * * 1100 = Reserved. No channel connected. 1011 = AT1_perclk 1010 = LC4_out 1001 = LC3_out 1000 = LC2_out 1100 = LC1_out 0110 = TxIN 0101 = MFINTOSC 31.25 kHz 0100 = ZCD_output 0011 = LFINTOSC 0010 = HFINTOSC 16 MHz 0001 = FOSC 0000 = FOSC/4 2014 Microchip Technology Inc. Preliminary DS40001770A-page 257 PIC16(L)F1615/9 REGISTER 23-2: R/W/HC-0/0 TxCON: TIMERx CONTROL REGISTER R/W-0/0 (1) ON R/W-0/0 R/W-0/0 R/W-0/0 CKPS<2:0> R/W-0/0 R/W-0/0 R/W-0/0 OUTPS<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared HC = Bit is cleared by hardware bit 7 ON: Timerx On bit 1 = Timerx is on 0 = Timerx is off: all counters and state machines are reset bit 6-4 CKPS<2:0>: Timer2-type Clock Prescale Select bits 111 =1:128 Prescaler 110 =1:64 Prescaler 101 =1:32 Prescaler 100 =1:16 Prescaler 011 =1:8 Prescaler 010 =1:4 Prescaler 001 =1:2 Prescaler 000 =1:1 Prescaler bit 3-0 OUTPS<3:0>: Timerx Output Postscaler Select bits 1111 =1:16 Postscaler 1110 =1:15 Postscaler 1101 =1:14 Postscaler 1100 =1:13 Postscaler 1011 =1:12 Postscaler 1010 =1:11 Postscaler 1001 =1:10 Postscaler 1000 =1:9 Postscaler 0111 =1:8 Postscaler 0110 =1:7 Postscaler 0101 =1:6 Postscaler 0100 =1:5 Postscaler 0011 =1:4 Postscaler 0010 =1:3 Postscaler 0001 =1:2 Postscaler 0000 =1:1 Postscaler Note 1: In certain modes, the ON bit will be auto-cleared by hardware. See Section 23.4.1 "One-Shot Mode". DS40001770A-page 258 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 REGISTER 23-3: TxHLT: TIMERx CLOCK SELECTION REGISTER R/W-0/0 R/W-0/0 R/W-0/0 PSYNC(1, 2) CKPOL(3) CKSYNC(4, 5) R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 MODE<4:0>(6, 7, 8) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 PSYNC: Timerx Prescaler Synchronization Enable bit(1, 2) 1 = TMRx Prescaler Output is synchronized to Fosc/4 0 = TMRx Prescaler Output is not synchronized to Fosc/4 bit 6 CKPOL: Timerx Clock Polarity Selection bit(3) 1 = Falling edge of input clock clocks timer/prescaler 0 = Rising edge of input clock clocks timer/prescaler bit 5 CKSYNC: Timerx Clock Synchronization Enable bit(4, 5) 1 = ON register bit is synchronized to TMR2_clk input 0 = ON register bit is not synchronized to TMR2_clk input bit 4-0 MODE<4:0>: Timerx Control Mode Selection bits(6, 7, 8) All modes with MODE<4> = 01 are "One Shot" (ON bit is cleared, clock is stopped, and TMRx is cleared immediately following TMRx = PRx). ON bit must be set by software to enable next one-shot. ON bit is not affected by TMRx_ers. 11111 * * * 11000 10111 10110 = Reserved. No channel connected. = Reserved. No channel connected. = Timer starts on TMRx_ers = 0 = Timer starts on TMRx_ers = 0 All modes from 10011 through 10001 are Monostable (Clock is stopped and TMRx is cleared immediately following TMRx = PRx). The ON bit must be initially set, but is not cleared upon the TMRx = PRx, and the timer will start upon an TMRx_ers start event following TMRx = PRx. 01111 01110 01101 01100 01011 01010 01001 01000 = = = = = = = = Timer starts when a falling edge is detected on the TMRx_ers, resets upon TMRx_ers = 1 Timer starts when a rising edge is detected on the TMRx_ers, resets upon TMRx_ers = 0 Timer starts upon first TMRx_ers falling edge and restarts on all subsequent TMRx_ers falling edges Timer starts upon first TMRx_ers rising edge and resets on all subsequent TMRx_ers rising edges Timer starts when either a rising or falling edge is detected on TMRx_ers Timer starts when a falling edge is detected on the TMRx_ers Timer starts when a rising edge is detected on the TMRx_ers Timer starts immediately upon ON = 1 (Software Control) All modes with MODE<4> = 00 are Roll-over Pulse (clear TMRx upon TMRx = PRx, then continue running). ON bit must be set and is not affected by Resets 00111 00110 00101 00100 00011 00010 00001 00000 = = = = = = = = Timer resets upon TMRx_ers = 1 Timer resets upon TMRx_ers = 0 Timer resets upon falling edge of TMRx_ers Timer resets upon rising edge of TMRx_ers Timer resets upon rising or falling edge of TMRx_ers Timer starts when ON = 1 and TMRx_ers = 0. Stops when TMRx_ers = 1 Timer starts when ON = 1 and TMRx_ers = 1. Stops when TMRx_ers = 0 Timer starts immediately upon ON = 1 (Software Control) 2014 Microchip Technology Inc. Preliminary DS40001770A-page 259 PIC16(L)F1615/9 REGISTER 23-3: Note 1: TxHLT: TIMERx CLOCK SELECTION REGISTER (CONTINUED) Setting this bit ensures that reading TMRx will return a valid data value. 2: When this bit is `1', Timer2 cannot operate in Sleep mode. 3: CKPOL should not be changed while ON = 1. 4: Setting this bit ensures glitch-free operation when the ON is enabled or disabled. 5: Setting this bit will "consume" two TMRx input clock to enable Timer. 6: Unless otherwise indicated, all modes start upon ON = 1 and stop upon ON = 0 (stops occur without affecting the value of TMRx). 7: When TMRx = PRx, the next clock clears TMRx, regardless of the operating mode. 8: In edge-triggered "One-Shot" modes, the triggered-start mechanism is reset and rearmed when ON = 0; the counter will not restart until an input edge occurs. DS40001770A-page 260 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 REGISTER 23-4: T2RST: TIMER2 EXTERNAL RESET SIGNAL SELECTION REGISTER U-0 U-0 U-0 U-0 -- -- -- -- R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 RSEL<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-4 Unimplemented: Read as `0' bit 3-0 RSEL<3:0>: Timer2 External Reset Signal Source Selection bits 1111 = Reserved 1110 = PWM4_out 1101 = PWM3_out 1100 = LC4_out 1011 = LC3_out 1010 = LC2_out 1001 = LC1_out 1000 = ZCD1_output 0111 = TMR6_postscaled 0110 = TMR4_postscaled 0101 = Reserved 0100 = CCP2_out 0011 = CCP1_out 0010 = C2_OUT_sync 0001 = C1_OUT_sync 0000 = T2IN 2014 Microchip Technology Inc. Preliminary DS40001770A-page 261 PIC16(L)F1615/9 REGISTER 23-5: T4RST: TIMER4 EXTERNAL RESET SIGNAL SELECTION REGISTER U-0 U-0 U-0 U-0 -- -- -- -- R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 RSEL<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-4 Unimplemented: Read as `0' bit 3-0 RSEL<3:0>: Timer4 External Reset Signal Source Selection bits 1111 = Reserved 1110 = PWM4_out 1101 = PWM3_out 1100 = LC4_out 1011 = LC3_out 1010 = LC2_out 1001 = LC1_out 1000 = ZCD1_output 0111 = TMR6_postscaled 0110 = Reserved 0101 = TMR4_postscaled 0100 = CCP2_out 0011 = CCP1_out 0010 = C2_OUT_sync 0001 = C1_OUT_sync 0000 = T4IN DS40001770A-page 262 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 REGISTER 23-6: T6RST: TIMER6 EXTERNAL RESET SIGNAL SELECTION REGISTER U-0 U-0 U-0 U-0 -- -- -- -- R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 RSEL<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-4 Unimplemented: Read as `0' bit 3-0 RSEL<3:0>: Timer6 External Reset Signal Source Selection bits 1111 = Reserved 1110 = PWM4_out 1101 = PWM3_out 1100 = LC4_out 1011 = LC3_out 1010 = LC2_out 1001 = LC1_out 1000 = ZCD1_output 0111 = Reserved 0110 = TMR4_postscaled 0101 = TMR2_postscaled 0100 = CCP2_out 0011 = CCP1_out 0010 = C2_OUT_sync 0001 = C1_OUT_sync 0000 = T6IN 2014 Microchip Technology Inc. Preliminary DS40001770A-page 263 PIC16(L)F1615/9 TABLE 23-2: Name CCP1CON SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2 Bit 7 Bit 6 Bit 5 Bit 4 EN OE OUT FMT Bit 3 Bit 2 Bit 1 Bit 0 MODE<3:0> Register on Page 359 CCP2CON EN OE OUT FMT INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 105 TMR1GIE ADIE -- -- -- CCP1IE TMR2IE TMR1IE 106 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF PIE1 PIR1 PR2 Timer2 Module Period Register TMR2 Holding Register for the 8-bit TMR2 Register T2CON ON T2CLKCON -- MODE<3:0> 111 245* 245* CKPS<2:0> -- 359 -- -- -- T2RST -- -- -- T2HLT PSYNC CKPOL CKSYNC OUTPS<3:0> 258 CS<3:0> 257 RSEL<3:0> 261 MODE<4:0> PR4 Timer4 Module Period Register TMR4 Holding Register for the 8-bit TMR4 Register 259 245* T4CON ON T4CLKCON -- -- -- T4RST -- -- -- T4HLT PSYNC CKPOL CKSYNC 245* CKPS<2:0> OUTPS<3:0> 258 -- CS<3:0> 257 -- RSEL<3:0> 262 MODE<4:0> 259 PR6 Timer6 Module Period Register 245* TMR6 Holding Register for the 8-bit TMR6 Register 245* T6CON ON T6CLKCON -- -- -- -- T6RST -- -- -- -- T6HLT PSYNC CKPOL CKSYNC Legend: * CKPS<2:0> OUTPS<3:0> -- T6CS<2:0> RSEL<3:0> MODE<4:0> 258 257 263 259 -- = unimplemented location, read as `0'. Shaded cells are not used for Timer2 module. Page provides register information. DS40001770A-page 264 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 24.0 MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE 24.1 MSSP Module Overview The Master Synchronous Serial Port (MSSP) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc. The MSSP module can operate in one of two modes: * Serial Peripheral Interface (SPI) * Inter-Integrated Circuit (I2CTM) The SPI interface supports the following modes and features: * * * * * Master mode Slave mode Clock Parity Slave Select Synchronization (Slave mode only) Daisy-chain connection of slave devices Figure 24-1 is a block diagram of the SPI interface module. FIGURE 24-1: MSSP BLOCK DIAGRAM (SPI MODE) Data Bus Read Write SSPxBUF Reg SSPDATPPS SDI PPS SSPSR Reg Shift Clock bit 0 SDO PPS RxyPPS SS SS Control Enable PPS SSPSSPPS Edge Select SSPCLKPPS(2) SCK SSPM<3:0> 4 PPS PPS TRIS bit 2 (CKP, CKE) Clock Select Edge Select RxyPPS(1) ( T2_match 2 ) Prescaler TOSC 4, 16, 64 Baud Rate Generator (SSPxADD) Note 1: Output selection for master mode 2: Input selection for slave mode 2014 Microchip Technology Inc. Preliminary DS40001770A-page 265 PIC16(L)F1615/9 The I2C interface supports the following modes and features: * * * * * * * * * * * * * Master mode Slave mode Byte NACKing (Slave mode) Limited multi-master support 7-bit and 10-bit addressing Start and Stop interrupts Interrupt masking Clock stretching Bus collision detection General call address matching Address masking Address Hold and Data Hold modes Selectable SDA hold times Figure 24-2 is a block diagram of the I2C interface module in Master mode. Figure 24-3 is a diagram of the I2C interface module in Slave mode. MSSP BLOCK DIAGRAM (I2CTM MASTER MODE) FIGURE 24-2: Internal data bus SSPDATPPS(1) Read [SSPM<3:0>] Write SDA SDA in PPS SSPxBUF Baud Rate Generator (SSPxADD) SSPCLKPPS SCL PPS LSb Start bit, Stop bit, Acknowledge Generate (SSPxCON2) (Hold off clock source) (2) Receive Enable (RCEN) MSb Clock Cntl SSPSR PPS Clock arbitrate/BCOL detect Shift Clock RxyPPS(1) PPS RxyPPS(2) SCL in Bus Collision Start bit detect, Stop bit detect Write collision detect Clock arbitration State counter for end of XMIT/RCV Address Match detect Set/Reset: S, P, SSPxSTAT, WCOL, SSPOV Reset SEN, PEN (SSPxCON2) Set SSP1IF, BCL1IF Note 1: SDA pin selections must be the same for input and output 2: SCL pin selections must be the same for input and output DS40001770A-page 266 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 FIGURE 24-3: MSSP BLOCK DIAGRAM (I2CTM SLAVE MODE) Internal Data Bus Read Write SSPCLKPPS(2) SCL PPS PPS Clock Stretching RxyPPS(2) SSPxBUF Reg Shift Clock SSPSR Reg LSb MSb SSPxMSK Reg SSPDATPPS(1) SDA Match Detect Addr Match PPS SSPxADD Reg PPS RxyPPS(1) Start and Stop bit Detect Set, Reset S, P bits (SSPxSTAT Reg) Note 1: SDA pin selections must be the same for input and output 2: SCL pin selections must be the same for input and output 2014 Microchip Technology Inc. Preliminary DS40001770A-page 267 PIC16(L)F1615/9 24.2 SPI Mode Overview The Serial Peripheral Interface (SPI) bus is a synchronous serial data communication bus that operates in Full-Duplex mode. Devices communicate in a master/slave environment where the master device initiates the communication. A slave device is controlled through a Chip Select known as Slave Select. The SPI bus specifies four signal connections: * * * * Serial Clock (SCK) Serial Data Out (SDO) Serial Data In (SDI) Slave Select (SS) During each SPI clock cycle, a full-duplex data transmission occurs. This means that while the master device is sending out the MSb from its shift register (on its SDO pin) and the slave device is reading this bit and saving it as the LSb of its shift register, that the slave device is also sending out the MSb from its shift register (on its SDO pin) and the master device is reading this bit and saving it as the LSb of its shift register. After eight bits have been shifted out, the master and slave have exchanged register values. If there is more data to exchange, the shift registers are loaded with new data and the process repeats itself. Figure 24-1 shows the block diagram of the MSSP module when operating in SPI mode. The SPI bus operates with a single master device and one or more slave devices. When multiple slave devices are used, an independent Slave Select connection is required from the master device to each slave device. Figure 24-4 shows a typical connection between a master device and multiple slave devices. The master selects only one slave at a time. Most slave devices have tri-state outputs so their output signal appears disconnected from the bus when they are not selected. Transmissions involve two shift registers, eight bits in size, one in the master and one in the slave. With either the master or the slave device, data is always shifted out one bit at a time, with the Most Significant bit (MSb) shifted out first. At the same time, a new Least Significant bit (LSb) is shifted into the same register. Whether the data is meaningful or not (dummy data), depends on the application software. This leads to three scenarios for data transmission: * Master sends useful data and slave sends dummy data. * Master sends useful data and slave sends useful data. * Master sends dummy data and slave sends useful data. Transmissions may involve any number of clock cycles. When there is no more data to be transmitted, the master stops sending the clock signal and it deselects the slave. Every slave device connected to the bus that has not been selected through its slave select line must disregard the clock and transmission signals and must not transmit out any data of its own. Figure 24-5 shows a typical connection between two processors configured as master and slave devices. Data is shifted out of both shift registers on the programmed clock edge and latched on the opposite edge of the clock. The master device transmits information out on its SDO output pin which is connected to, and received by, the slave's SDI input pin. The slave device transmits information out on its SDO output pin, which is connected to, and received by, the master's SDI input pin. To begin communication, the master device first sends out the clock signal. Both the master and the slave devices should be configured for the same clock polarity. The master device starts a transmission by sending out the MSb from its shift register. The slave device reads this bit from that same line and saves it into the LSb position of its shift register. DS40001770A-page 268 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 FIGURE 24-4: SPI MASTER AND MULTIPLE SLAVE CONNECTION SPI Master SCK SCK SDO SDI SDI General I/O SDO SPI Slave #1 SS General I/O General I/O SCK SDI SDO SPI Slave #2 SS SCK SDI SDO SPI Slave #3 SS 24.2.1 24.2.2 SPI MODE REGISTERS The MSSP module has five registers for SPI mode operation. These are: * * * * * * MSSP STATUS register (SSPxSTAT) MSSP Control register 1 (SSPxCON1) MSSP Control register 3 (SSPxCON3) MSSP Data Buffer register (SSPxBUF) MSSP Address register (SSPxADD) MSSP Shift register (SSPSR) (Not directly accessible) SSPxCON1 and SSPxSTAT are the control STATUS registers in SPI mode operation. SSPxCON1 register is readable and writable. lower six bits of the SSPxSTAT are read-only. upper two bits of the SSPxSTAT are read/write. SPI MODE OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPxCON1<5:0> and SSPxSTAT<7:6>). These control bits allow the following to be specified: * * * * and The The The In one SPI master mode, SSPxADD can be loaded with a value used in the Baud Rate Generator. More information on the Baud Rate Generator is available in Section 24.7 "Baud Rate Generator". SSPSR is the shift register used for shifting data in and out. SSPxBUF provides indirect access to the SSPSR register. SSPxBUF is the buffer register to which data bytes are written, and from which data bytes are read. In receive operations, SSPSR and SSPxBUF together create a buffered receiver. When SSPSR receives a complete byte, it is transferred to SSPxBUF and the SSPxIF interrupt is set. During transmission, the SSPxBUF is not buffered. A write to SSPxBUF will write to both SSPxBUF and SSPSR. Master mode (SCK is the clock output) Slave mode (SCK is the clock input) Clock Polarity (Idle state of SCK) Data Input Sample Phase (middle or end of data output time) * Clock Edge (output data on rising/falling edge of SCK) * Clock Rate (Master mode only) * Slave Select mode (Slave mode only) To enable the serial port, SSP Enable bit, SSPEN of the SSPxCON1 register, must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, re-initialize the SSPxCONx registers and then set the SSPEN bit. This configures the SDI, SDO, SCK and SS pins as serial port pins. For the pins to behave as the serial port function, some must have their data direction bits (in the TRIS register) appropriately programmed as follows: * SDI must have corresponding TRIS bit set * SDO must have corresponding TRIS bit cleared * SCK (Master mode) must have corresponding TRIS bit cleared * SCK (Slave mode) must have corresponding TRIS bit set * SS must have corresponding TRIS bit set Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRIS) register to the opposite value. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 269 PIC16(L)F1615/9 The MSSP consists of a transmit/receive shift register (SSPSR) and a buffer register (SSPxBUF). The SSPSR shifts the data in and out of the device, MSb first. The SSPxBUF holds the data that was written to the SSPSR until the received data is ready. Once the eight bits of data have been received, that byte is moved to the SSPxBUF register. Then, the Buffer Full Detect bit, BF of the SSPxSTAT register, and the interrupt flag bit, SSPxIF, are set. This double-buffering of the received data (SSPxBUF) allows the next byte to start reception before reading the data that was just received. Any write to the SSPxBUF register during transmission/reception of data will be ignored and the write collision detect bit WCOL of the SSPxCON1 register, will be set. User software must clear the WCOL bit to allow the following write(s) to the SSPxBUF register to complete successfully. FIGURE 24-5: When the application software is expecting to receive valid data, the SSPxBUF should be read before the next byte of data to transfer is written to the SSPxBUF. The Buffer Full bit, BF of the SSPxSTAT register, indicates when SSPxBUF has been loaded with the received data (transmission is complete). When the SSPxBUF is read, the BF bit is cleared. This data may be irrelevant if the SPI is only a transmitter. Generally, the MSSP interrupt is used to determine when the transmission/reception has completed. If the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur. The SSPSR is not directly readable or writable and can only be accessed by addressing the SSPxBUF register. Additionally, the SSPxSTAT register indicates the various Status conditions. SPI MASTER/SLAVE CONNECTION SPI Master SSPM<3:0> = 00xx = 1010 SPI Slave SSPM<3:0> = 010x SDO SDI Serial Input Buffer (BUF) SDI Shift Register (SSPSR) MSb Serial Input Buffer (SSPxBUF) LSb SCK General I/O Processor 1 DS40001770A-page 270 SDO Serial Clock Slave Select (optional) Preliminary Shift Register (SSPSR) MSb LSb SCK SS Processor 2 2014 Microchip Technology Inc. PIC16(L)F1615/9 24.2.3 SPI MASTER MODE The master can initiate the data transfer at any time because it controls the SCK line. The master determines when the slave (Processor 2, Figure 24-5) is to broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPxBUF register is written to. If the SPI is only going to receive, the SDO output could be disabled (programmed as an input). The SSPSR register will continue to shift in the signal present on the SDI pin at the programmed clock rate. As each byte is received, it will be loaded into the SSPxBUF register as if a normal received byte (interrupts and Status bits appropriately set). The clock polarity is selected by appropriately programming the CKP bit of the SSPxCON1 register and the CKE bit of the SSPxSTAT register. This then, would give waveforms for SPI communication as shown in Figure 24-6, Figure 24-8, Figure 24-9 and Figure 24-10, where the MSB is transmitted first. In Master mode, the SPI clock rate (bit rate) is user programmable to be one of the following: * * * * * FOSC/4 (or TCY) FOSC/16 (or 4 * TCY) FOSC/64 (or 16 * TCY) Timer2 output/2 FOSC/(4 * (SSPxADD + 1)) Figure 24-6 shows the waveforms for Master mode. When the CKE bit is set, the SDO data is valid before there is a clock edge on SCK. The change of the input sample is shown based on the state of the SMP bit. The time when the SSPxBUF is loaded with the received data is shown. Note: 2014 Microchip Technology Inc. Preliminary In Master mode the clock signal output to the SCK pin is also the clock signal input to the peripheral. The pin selected for output with the RxyPPS register must also be selected as the peripheral input with the SSPCLKPPS register. DS40001770A-page 271 PIC16(L)F1615/9 FIGURE 24-6: SPI MODE WAVEFORM (MASTER MODE) Write to SSPxBUF SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) 4 Clock Modes SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) SDO (CKE = 0) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDO (CKE = 1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI (SMP = 0) bit 0 bit 7 Input Sample (SMP = 0) SDI (SMP = 1) bit 0 bit 7 Input Sample (SMP = 1) SSPxIF SSPSR to SSPxBUF 24.2.4 24.2.4.1 SPI SLAVE MODE In Slave mode, the data is transmitted and received as external clock pulses appear on SCK. When the last bit is latched, the SSPxIF interrupt flag bit is set. Before enabling the module in SPI Slave mode, the clock line must match the proper Idle state. The clock line can be observed by reading the SCK pin. The Idle state is determined by the CKP bit of the SSPxCON1 register. While in Slave mode, the external clock is supplied by the external clock source on the SCK pin. This external clock must meet the minimum high and low times as specified in the electrical specifications. While in Sleep mode, the slave can transmit/receive data. The shift register is clocked from the SCK pin input and when a byte is received, the device will generate an interrupt. If enabled, the device will wakeup from Sleep. DS40001770A-page 272 Daisy-Chain Configuration The SPI bus can sometimes be connected in a daisychain configuration. The first slave output is connected to the second slave input, the second slave output is connected to the third slave input, and so on. The final slave output is connected to the master input. Each slave sends out, during a second group of clock pulses, an exact copy of what was received during the first group of clock pulses. The whole chain acts as one large communication shift register. The daisychain feature only requires a single Slave Select line from the master device. Figure 24-7 shows the block diagram of a typical daisy-chain connection when operating in SPI mode. In a daisy-chain configuration, only the most recent byte on the bus is required by the slave. Setting the BOEN bit of the SSPxCON3 register will enable writes to the SSPxBUF register, even if the previous byte has not been read. This allows the software to ignore data that may not apply to it. Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 24.2.5 SLAVE SELECT SYNCHRONIZATION When the SS pin is low, transmission and reception are enabled and the SDO pin is driven. The Slave Select can also be used to synchronize communication. The Slave Select line is held high until the master device is ready to communicate. When the Slave Select line is pulled low, the slave knows that a new transmission is starting. If the slave fails to receive the communication properly, it will be reset at the end of the transmission, when the Slave Select line returns to a high state. The slave is then ready to receive a new transmission when the Slave Select line is pulled low again. If the Slave Select line is not used, there is a risk that the slave will eventually become out of sync with the master. If the slave misses a bit, it will always be one bit off in future transmissions. Use of the Slave Select line allows the slave and master to align themselves at the beginning of each transmission. The SS pin allows a Synchronous Slave mode. The SPI must be in Slave mode with SS pin control enabled (SSPxCON1<3:0> = 0100). FIGURE 24-7: When the SS pin goes high, the SDO pin is no longer driven, even if in the middle of a transmitted byte and becomes a floating output. External pull-up/pull-down resistors may be desirable depending on the application. Note 1: When the SPI is in Slave mode with SS pin control enabled (SSPxCON1<3:0> = 0100), the SPI module will reset if the SS pin is set to VDD. 2: When the SPI is used in Slave mode with CKE set; the user must enable SS pin control. 3: While operated in SPI Slave mode the SMP bit of the SSPxSTAT register must remain clear. When the SPI module resets, the bit counter is forced to `0'. This can be done by either forcing the SS pin to a high level or clearing the SSPEN bit. SPI DAISY-CHAIN CONNECTION SPI Master SCK SCK SDO SDI SDI SDO General I/O SPI Slave #1 SS SCK SDI SDO SPI Slave #2 SS SCK SDI SDO SPI Slave #3 SS 2014 Microchip Technology Inc. Preliminary DS40001770A-page 273 PIC16(L)F1615/9 FIGURE 24-8: SLAVE SELECT SYNCHRONOUS WAVEFORM SS SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPxBUF Shift register SSPSR and bit count are reset SSPxBUF to SSPSR SDO bit 7 bit 6 bit 7 SDI bit 6 bit 0 bit 0 bit 7 bit 7 Input Sample SSPxIF Interrupt Flag SSPSR to SSPxBUF DS40001770A-page 274 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 FIGURE 24-9: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPxBUF Valid SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI bit 0 bit 7 Input Sample SSPxIF Interrupt Flag SSPSR to SSPxBUF Write Collision detection active FIGURE 24-10: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPxBUF Valid SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI bit 0 bit 7 Input Sample SSPxIF Interrupt Flag SSPSR to SSPxBUF Write Collision detection active 2014 Microchip Technology Inc. Preliminary DS40001770A-page 275 PIC16(L)F1615/9 24.2.6 SPI OPERATION IN SLEEP MODE In SPI Master mode, module clocks may be operating at a different speed than when in Full-Power mode; in the case of the Sleep mode, all clocks are halted. Special care must be taken by the user when the MSSP clock is much faster than the system clock. In Slave mode, when MSSP interrupts are enabled, after the master completes sending data, an MSSP interrupt will wake the controller from Sleep. If an exit from Sleep mode is not desired, MSSP interrupts should be disabled. TABLE 24-1: Name Bit 6 -- -- (2) ANSELC In SPI Slave mode, the SPI Transmit/Receive Shift register operates asynchronously to the device. This allows the device to be placed in Sleep mode and data to be shifted into the SPI Transmit/Receive Shift register. When all eight bits have been received, the MSSP interrupt flag bit will be set and if enabled, will wake the device. SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION Bit 7 ANSELA In SPI Master mode, when the Sleep mode is selected, all module clocks are halted and the transmission/ reception will remain in that state until the device wakes. After the device returns to Run mode, the module will resume transmitting and receiving data. ANSC7 (2) Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page -- ANSA4 -- ANSA2 ANSA1 ANSA0 160 -- -- ANSC3 ANSC2 ANSC1 ANSC0 174 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 105 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 106 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF RxyPPS -- -- -- SSPCLKPPS -- -- SSPDATPPS -- -- -- -- INTCON SSPSSPPS SSP1BUF ANSC6 Bit 5 111 RxyPPS<4:0> 180 -- SSPCLKPPS<4:0> 182, 180 -- SSPDATPPS<4:0> 182, 180 -- SSPSSPPS<4:0> 182, 180 Synchronous Serial Port Receive Buffer/Transmit Register 269* SSP1CON1 WCOL SSPOV SSPEN CKP SSP1CON3 ACKTIM PCIE SCIE BOEN SSP1STAT SMP CKE D/A P S R/W UA BF 313 -- -- TRISA5 TRISA4 --(1) TRISA2 TRISA1 TRISA0 159 TRISA TRISB(2) TRISC Legend: * Note 1: 2: SSPM<3:0> SDAHT SBCDE AHEN 314 DHEN 313 TRISB7 TRISB6 TRISB5 TRISB4 -- -- -- -- 166 TRISC7(2) TRISC6(2) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 173 -- = Unimplemented location, read as `0'. Shaded cells are not used by the MSSP in SPI mode. Page provides register information. Unimplemented, read as `1'. PIC16(L)F1619 only. DS40001770A-page 276 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 24.3 I2C MODE OVERVIEW FIGURE 24-11: The Inter-Integrated Circuit (I2C) bus is a multi-master serial data communication bus. Devices communicate in a master/slave environment where the master devices initiate the communication. A slave device is controlled through addressing. VDD SCL The I2C bus specifies two signal connections: * Serial Clock (SCL) * Serial Data (SDA) Figure 24-11 shows a typical connection between two processors configured as master and slave devices. The I2C bus can operate with one or more master devices and one or more slave devices. There are four potential modes of operation for a given device: * Master Transmit mode (master is transmitting data to a slave) * Master Receive mode (master is receiving data from a slave) * Slave Transmit mode (slave is transmitting data to a master) * Slave Receive mode (slave is receiving data from the master) SDA The Acknowledge bit (ACK) is an active-low signal, which holds the SDA line low to indicate to the transmitter that the slave device has received the transmitted data and is ready to receive more. The transition of a data bit is always performed while the SCL line is held low. Transitions that occur while the SCL line is held high are used to indicate Start and Stop bits. If the master intends to write to the slave, then it repeatedly sends out a byte of data, with the slave responding after each byte with an ACK bit. In this example, the master device is in Master Transmit mode and the slave is in Slave Receive mode. If the master intends to read from the slave, then it repeatedly receives a byte of data from the slave, and responds after each byte with an ACK bit. In this example, the master device is in Master Receive mode and the slave is Slave Transmit mode. To begin communication, a master device starts out in Master Transmit mode. The master device sends out a Start bit followed by the address byte of the slave it intends to communicate with. This is followed by a single Read/Write bit, which determines whether the master intends to transmit to or receive data from the slave device. If the requested slave exists on the bus, it will respond with an Acknowledge bit, otherwise known as an ACK. The master then continues in either Transmit mode or Receive mode and the slave continues in the complement, either in Receive mode or Transmit mode, respectively. A Start bit is indicated by a high-to-low transition of the SDA line while the SCL line is held high. Address and data bytes are sent out, Most Significant bit (MSb) first. The Read/Write bit is sent out as a logical one when the master intends to read data from the slave, and is sent out as a logical zero when it intends to write data to the slave. 2014 Microchip Technology Inc. Slave SDA Figure 24-11 shows the block diagram of the MSSP module when operating in I2C mode. SCL VDD Master Both the SCL and SDA connections are bidirectional open-drain lines, each requiring pull-up resistors for the supply voltage. Pulling the line to ground is considered a logical zero and letting the line float is considered a logical one. I2C MASTER/ SLAVE CONNECTION On the last byte of data communicated, the master device may end the transmission by sending a Stop bit. If the master device is in Receive mode, it sends the Stop bit in place of the last ACK bit. A Stop bit is indicated by a low-to-high transition of the SDA line while the SCL line is held high. In some cases, the master may want to maintain control of the bus and re-initiate another transmission. If so, the master device may send another Start bit in place of the Stop bit or last ACK bit when it is in receive mode. The I2C bus specifies three message protocols; * Single message where a master writes data to a slave. * Single message where a master reads data from a slave. * Combined message where a master initiates a minimum of two writes, or two reads, or a combination of writes and reads, to one or more slaves. Preliminary DS40001770A-page 277 PIC16(L)F1615/9 When one device is transmitting a logical one, or letting the line float, and a second device is transmitting a logical zero, or holding the line low, the first device can detect that the line is not a logical one. This detection, when used on the SCL line, is called clock stretching. Clock stretching gives slave devices a mechanism to control the flow of data. When this detection is used on the SDA line, it is called arbitration. Arbitration ensures that there is only one master device communicating at any single time. 24.3.1 CLOCK STRETCHING When a slave device has not completed processing data, it can delay the transfer of more data through the process of clock stretching. An addressed slave device may hold the SCL clock line low after receiving or sending a bit, indicating that it is not yet ready to continue. The master that is communicating with the slave will attempt to raise the SCL line in order to transfer the next bit, but will detect that the clock line has not yet been released. Because the SCL connection is opendrain, the slave has the ability to hold that line low until it is ready to continue communicating. Clock stretching allows receivers that cannot keep up with a transmitter to control the flow of incoming data. 24.3.2 ARBITRATION Each master device must monitor the bus for Start and Stop bits. If the device detects that the bus is busy, it cannot begin a new message until the bus returns to an Idle state. However, two master devices may try to initiate a transmission on or about the same time. When this occurs, the process of arbitration begins. Each transmitter checks the level of the SDA data line and compares it to the level that it expects to find. The first transmitter to observe that the two levels do not match, loses arbitration, and must stop transmitting on the SDA line. For example, if one transmitter holds the SDA line to a logical one (lets it float) and a second transmitter holds it to a logical zero (pulls it low), the result is that the SDA line will be low. The first transmitter then observes that the level of the line is different than expected and concludes that another transmitter is communicating. The first transmitter to notice this difference is the one that loses arbitration and must stop driving the SDA line. If this transmitter is also a master device, it also must stop driving the SCL line. It then can monitor the lines for a Stop condition before trying to reissue its transmission. In the meantime, the other device that has not noticed any difference between the expected and actual levels on the SDA line continues with its original transmission. It can do so without any complications, because so far, the transmission appears exactly as expected with no other transmitter disturbing the message. Slave Transmit mode can also be arbitrated, when a master addresses multiple slaves, but this is less common. If two master devices are sending a message to two different slave devices at the address stage, the master sending the lower slave address always wins arbitration. When two master devices send messages to the same slave address, and addresses can sometimes refer to multiple slaves, the arbitration process must continue into the data stage. Arbitration usually occurs very rarely, but it is a necessary process for proper multi-master support. DS40001770A-page 278 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 24.4 I2C MODE OPERATION TABLE 24-2: All MSSP I2C communication is byte oriented and shifted out MSb first. Six SFR registers and two interrupt flags interface the module with the PIC(R) microcontroller and user software. Two pins, SDA and SCL, are exercised by the module to communicate with other external I2C devices. 24.4.1 BYTE FORMAT All communication in I2C is done in 9-bit segments. A byte is sent from a master to a slave or vice-versa, followed by an Acknowledge bit sent back. After the eighth falling edge of the SCL line, the device outputting data on the SDA changes that pin to an input and reads in an acknowledge value on the next clock pulse. The clock signal, SCL, is provided by the master. Data is valid to change while the SCL signal is low, and sampled on the rising edge of the clock. Changes on the SDA line while the SCL line is high define special conditions on the bus, explained below. 24.4.2 DEFINITION OF I2C TERMINOLOGY There is language and terminology in the description of I2C communication that have definitions specific to I2C. That word usage is defined below and may be used in the rest of this document without explanation. This table was adapted from the Philips I2CTM specification. 24.4.3 SDA AND SCL PINS Selection of any I2C mode with the SSPEN bit set, forces the SCL and SDA pins to be open-drain. These pins should be set by the user to inputs by setting the appropriate TRIS bits. Note 1: Data is tied to output zero when an I2C mode is enabled. 2: Any device pin can be selected for SDA and SCL functions with the PPS peripheral. These functions are bidirectional. The SDA input is selected with the SSPDATPPS registers. The SCL input is selected with the SSPCLKPPS registers. Outputs are selected with the RxyPPS registers. It is the user's responsibility to make the selections so that both the input and the output for each function is on the same pin. 24.4.4 TERM I2C BUS TERMS Description Transmitter The device which shifts data out onto the bus. Receiver The device which shifts data in from the bus. Master The device that initiates a transfer, generates clock signals and terminates a transfer. Slave The device addressed by the master. Multi-master A bus with more than one device that can initiate data transfers. Arbitration Procedure to ensure that only one master at a time controls the bus. Winning arbitration ensures that the message is not corrupted. Synchronization Procedure to synchronize the clocks of two or more devices on the bus. Idle No master is controlling the bus, and both SDA and SCL lines are high. Active Any time one or more master devices are controlling the bus. Addressed Slave device that has received a Slave matching address and is actively being clocked by a master. Matching Address byte that is clocked into a Address slave that matches the value stored in SSPxADD. Write Request Slave receives a matching address with R/W bit clear, and is ready to clock in data. Read Request Master sends an address byte with the R/W bit set, indicating that it wishes to clock data out of the Slave. This data is the next and all following bytes until a Restart or Stop. Clock Stretching When a device on the bus holds SCL low to stall communication. Bus Collision Any time the SDA line is sampled low by the module while it is outputting and expected high state. SDA HOLD TIME The hold time of the SDA pin is selected by the SDAHT bit of the SSPxCON3 register. Hold time is the time SDA is held valid after the falling edge of SCL. Setting the SDAHT bit selects a longer 300 ns minimum hold time and may help on buses with large capacitance. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 279 PIC16(L)F1615/9 24.4.5 START CONDITION 24.4.7 2 The I C specification defines a Start condition as a transition of SDA from a high to a low state while SCL line is high. A Start condition is always generated by the master and signifies the transition of the bus from an Idle to an Active state. Figure 24-12 shows wave forms for Start and Stop conditions. A Restart is valid any time that a Stop would be valid. A master can issue a Restart if it wishes to hold the bus after terminating the current transfer. A Restart has the same effect on the slave that a Start would, resetting all slave logic and preparing it to clock in an address. The master may want to address the same or another slave. Figure 24-13 shows the wave form for a Restart condition. A bus collision can occur on a Start condition if the module samples the SDA line low before asserting it low. This does not conform to the I2C Specification that states no bus collision can occur on a Start. 24.4.6 RESTART CONDITION In 10-bit Addressing Slave mode a Restart is required for the master to clock data out of the addressed slave. Once a slave has been fully addressed, matching both high and low address bytes, the master can issue a Restart and the high address byte with the R/W bit set. The slave logic will then hold the clock and prepare to clock out data. STOP CONDITION A Stop condition is a transition of the SDA line from low-to-high state while the SCL line is high. Note: At least one SCL low time must appear before a Stop is valid, therefore, if the SDA line goes low then high again while the SCL line stays high, only the Start condition is detected. After a full match with R/W clear in 10-bit mode, a prior match flag is set and maintained until a Stop condition, a high address with R/W clear, or high address match fails. 24.4.8 START/STOP CONDITION INTERRUPT MASKING The SCIE and PCIE bits of the SSPxCON3 register can enable the generation of an interrupt in Slave modes that do not typically support this function. Slave modes where interrupt on Start and Stop detect are already enabled, these bits will have no effect. I2C START AND STOP CONDITIONS FIGURE 24-12: SDA SCL S Start P Change of Change of Data Allowed Data Allowed Condition FIGURE 24-13: Stop Condition I2C RESTART CONDITION Sr Change of Change of Data Allowed Restart Data Allowed Condition DS40001770A-page 280 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 24.4.9 ACKNOWLEDGE SEQUENCE 24.5 The 9th SCL pulse for any transferred byte in I2C is dedicated as an Acknowledge. It allows receiving devices to respond back to the transmitter by pulling the SDA line low. The transmitter must release control of the line during this time to shift in the response. The Acknowledge (ACK) is an active-low signal, pulling the SDA line low indicates to the transmitter that the device has received the transmitted data and is ready to receive more. The result of an ACK is placed in the ACKSTAT bit of the SSPxCON2 register. Slave software, when the AHEN and DHEN bits are set, allow the user to set the ACK value sent back to the transmitter. The ACKDT bit of the SSPxCON2 register is set/cleared to determine the response. Slave hardware will generate an ACK response if the AHEN and DHEN bits of the SSPxCON3 register are clear. There are certain conditions where an ACK will not be sent by the slave. If the BF bit of the SSPxSTAT register or the SSPOV bit of the SSPxCON1 register are set when a byte is received. When the module is addressed, after the eighth falling edge of SCL on the bus, the ACKTIM bit of the SSPxCON3 register is set. The ACKTIM bit indicates the acknowledge time of the active bus. The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is enabled. I2C SLAVE MODE OPERATION The MSSP Slave mode operates in one of four modes selected by the SSPM bits of SSPxCON1 register. The modes can be divided into 7-bit and 10-bit Addressing mode. 10-bit Addressing modes operate the same as 7-bit with some additional overhead for handling the larger addresses. Modes with Start and Stop bit interrupts operate the same as the other modes with SSPxIF additionally getting set upon detection of a Start, Restart, or Stop condition. 24.5.1 SLAVE MODE ADDRESSES The SSPxADD register (Register 24-6) contains the Slave mode address. The first byte received after a Start or Restart condition is compared against the value stored in this register. If the byte matches, the value is loaded into the SSPxBUF register and an interrupt is generated. If the value does not match, the module goes idle and no indication is given to the software that anything happened. The SSP Mask register (Register 24-5) affects the address matching process. See Section 24.5.8 "SSP Mask Register" for more information. 24.5.1.1 I2C Slave 7-bit Addressing Mode In 7-bit Addressing mode, the LSb of the received data byte is ignored when determining if there is an address match. 24.5.1.2 I2C Slave 10-bit Addressing Mode In 10-bit Addressing mode, the first received byte is compared to the binary value of `1 1 1 1 0 A9 A8 0'. A9 and A8 are the two MSb's of the 10-bit address and stored in bits 2 and 1 of the SSPxADD register. After the acknowledge of the high byte the UA bit is set and SCL is held low until the user updates SSPxADD with the low address. The low address byte is clocked in and all eight bits are compared to the low address value in SSPxADD. Even if there is not an address match; SSPxIF and UA are set, and SCL is held low until SSPxADD is updated to receive a high byte again. When SSPxADD is updated the UA bit is cleared. This ensures the module is ready to receive the high address byte on the next communication. A high and low address match as a write request is required at the start of all 10-bit addressing communication. A transmission can be initiated by issuing a Restart once the slave is addressed, and clocking in the high address with the R/W bit set. The slave hardware will then acknowledge the read request and prepare to clock out data. This is only valid for a slave after it has received a complete high and low address byte match. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 281 PIC16(L)F1615/9 24.5.2 SLAVE RECEPTION 24.5.2.2 When the R/W bit of a matching received address byte is clear, the R/W bit of the SSPxSTAT register is cleared. The received address is loaded into the SSPxBUF register and acknowledged. When the overflow condition exists for a received address, then not Acknowledge is given. An overflow condition is defined as either bit BF of the SSPxSTAT register is set, or bit SSPOV of the SSPxCON1 register is set. The BOEN bit of the SSPxCON3 register modifies this operation. For more information see Register 24-4. An MSSP interrupt is generated for each transferred data byte. Flag bit, SSPxIF, must be cleared by software. When the SEN bit of the SSPxCON2 register is set, SCL will be held low (clock stretch) following each received byte. The clock must be released by setting the CKP bit of the SSPxCON1 register, except sometimes in 10-bit mode. See Section 24.5.6.2 "10bit Addressing Mode" for more detail. 24.5.2.1 7-bit Addressing Reception This section describes a standard sequence of events for the MSSP module configured as an I2C slave in 7-bit Addressing mode. Figure 24-14 and Figure 24-15 is used as a visual reference for this description. This is a step by step process of what typically must be done to accomplish I2C communication. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. Start bit detected. S bit of SSPxSTAT is set; SSPxIF is set if interrupt on Start detect is enabled. Matching address with R/W bit clear is received. The slave pulls SDA low sending an ACK to the master, and sets SSPxIF bit. Software clears the SSPxIF bit. Software reads received address from SSPxBUF clearing the BF flag. If SEN = 1; Slave software sets CKP bit to release the SCL line. The master clocks out a data byte. Slave drives SDA low sending an ACK to the master, and sets SSPxIF bit. Software clears SSPxIF. Software reads the received byte from SSPxBUF clearing BF. Steps 8-12 are repeated for all received bytes from the master. Master sends Stop condition, setting P bit of SSPxSTAT, and the bus goes idle. DS40001770A-page 282 7-bit Reception with AHEN and DHEN Slave device reception with AHEN and DHEN set operate the same as without these options with extra interrupts and clock stretching added after the eighth falling edge of SCL. These additional interrupts allow the slave software to decide whether it wants to ACK the receive address or data byte, rather than the hardware. This functionality adds support for PMBusTM that was not present on previous versions of this module. This list describes the steps that need to be taken by slave software to use these options for I2C communication. Figure 24-16 displays a module using both address and data holding. Figure 24-17 includes the operation with the SEN bit of the SSPxCON2 register set. 1. S bit of SSPxSTAT is set; SSPxIF is set if interrupt on Start detect is enabled. 2. Matching address with R/W bit clear is clocked in. SSPxIF is set and CKP cleared after the eighth falling edge of SCL. 3. Slave clears the SSPxIF. 4. Slave can look at the ACKTIM bit of the SSPxCON3 register to determine if the SSPxIF was after or before the ACK. 5. Slave reads the address value from SSPxBUF, clearing the BF flag. 6. Slave sets ACK value clocked out to the master by setting ACKDT. 7. Slave releases the clock by setting CKP. 8. SSPxIF is set after an ACK, not after a NACK. 9. If SEN = 1 the slave hardware will stretch the clock after the ACK. 10. Slave clears SSPxIF. Note: SSPxIF is still set after the 9th falling edge of SCL even if there is no clock stretching and BF has been cleared. Only if NACK is sent to master is SSPxIF not set 11. SSPxIF set and CKP cleared after eighth falling edge of SCL for a received data byte. 12. Slave looks at ACKTIM bit of SSPxCON3 to determine the source of the interrupt. 13. Slave reads the received data from SSPxBUF clearing BF. 14. Steps 7-14 are the same for each received data byte. 15. Communication is ended by either the slave sending an ACK = 1, or the master sending a Stop condition. If a Stop is sent and Interrupt on Stop Detect is disabled, the slave will only know by polling the P bit of the SSTSTAT register. Preliminary 2014 Microchip Technology Inc. 2014 Microchip Technology Inc. Preliminary SSPOV BF SSPxIF S 1 A7 2 A6 3 A5 4 A4 5 A3 Receiving Address 6 A2 7 A1 8 9 ACK 1 D7 2 D6 4 5 D3 6 D2 7 D1 SSPxBUF is read Cleared by software 3 D4 Receiving Data D5 8 9 2 D6 First byte of data is available in SSPxBUF 1 D0 ACK D7 4 5 D3 6 D2 7 D1 SSPOV set because SSPxBUF is still full. ACK is not sent. Cleared by software 3 D4 Receiving Data D5 8 D0 9 P SSPxIF set on 9th falling edge of SCL ACK = 1 FIGURE 24-14: SCL SDA From Slave to Master Bus Master sends Stop condition PIC16(L)F1615/9 I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 0, DHEN = 0) DS40001770A-page 283 DS40001770A-page 284 Preliminary CKP SSPOV BF SSPxIF 1 SCL S A7 2 A6 3 A5 4 A4 5 A3 6 A2 7 A1 8 9 R/W=0 ACK SEN 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 CKP is written to `1' in software, releasing SCL SSPxBUF is read Cleared by software Clock is held low until CKP is set to `1' 1 D7 Receive Data 9 ACK SEN 3 D5 4 D4 5 D3 First byte of data is available in SSPxBUF 6 D2 7 D1 SSPOV set because SSPxBUF is still full. ACK is not sent. Cleared by software 2 D6 CKP is written to `1' in software, releasing SCL 1 D7 Receive Data 8 D0 9 ACK SCL is not held low because ACK= 1 SSPxIF set on 9th falling edge of SCL P FIGURE 24-15: SDA Receive Address Bus Master sends Stop condition PIC16(L)F1615/9 I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0) 2014 Microchip Technology Inc. 2014 Microchip Technology Inc. Preliminary P S ACKTIM CKP ACKDT BF SSPxIF S Receiving Address 1 3 5 6 7 8 ACK the received byte Slave software clears ACKDT to Address is read from SSBUF If AHEN = 1: SSPxIF is set 4 ACKTIM set by hardware on 8th falling edge of SCL When AHEN=1: CKP is cleared by hardware and SCL is stretched 2 A7 A6 A5 A4 A3 A2 A1 Receiving Data 9 2 3 4 5 6 7 ACKTIM cleared by hardware in 9th rising edge of SCL When DHEN=1: CKP is cleared by hardware on 8th falling edge of SCL SSPxIF is set on 9th falling edge of SCL, after ACK 1 8 ACK D7 D6 D5 D4 D3 D2 D1 D0 Received Data 1 2 4 5 6 ACKTIM set by hardware on 8th falling edge of SCL CKP set by software, SCL is released 8 Slave software sets ACKDT to not ACK 7 Cleared by software 3 D7 D6 D5 D4 D3 D2 D1 D0 Data is read from SSPxBUF 9 ACK 9 P No interrupt after not ACK from Slave ACK=1 Master sends Stop condition FIGURE 24-16: SCL SDA Master Releases SDA to slave for ACK sequence PIC16(L)F1615/9 I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 1) DS40001770A-page 285 DS40001770A-page 286 Preliminary P S ACKTIM CKP ACKDT BF SSPxIF S Receiving Address 4 5 6 7 8 When AHEN = 1; on the 8th falling edge of SCL of an address byte, CKP is cleared Slave software clears ACKDT to ACK the received byte Received address is loaded into SSPxBUF 2 3 ACKTIM is set by hardware on 8th falling edge of SCL 1 A7 A6 A5 A4 A3 A2 A1 9 ACK Receive Data 2 3 4 5 6 7 8 ACKTIM is cleared by hardware on 9th rising edge of SCL When DHEN = 1; on the 8th falling edge of SCL of a received data byte, CKP is cleared Received data is available on SSPxBUF Cleared by software 1 D7 D6 D5 D4 D3 D2 D1 D0 9 ACK Receive Data 1 3 4 5 6 7 8 Set by software, release SCL Slave sends not ACK SSPxBUF can be read any time before next byte is loaded 2 D7 D6 D5 D4 D3 D2 D1 D0 9 ACK CKP is not cleared if not ACK No interrupt after if not ACK from Slave P Master sends Stop condition FIGURE 24-17: SCL SDA R/W = 0 Master releases SDA to slave for ACK sequence PIC16(L)F1615/9 I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 1, DHEN = 1) 2014 Microchip Technology Inc. PIC16(L)F1615/9 24.5.3 24.5.3.2 SLAVE TRANSMISSION 7-bit Transmission When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPxSTAT register is set. The received address is loaded into the SSPxBUF register, and an ACK pulse is sent by the slave on the ninth bit. A master device can transmit a read request to a slave, and then clock data out of the slave. The list below outlines what software for a slave will need to do to accomplish a standard transmission. Figure 24-18 can be used as a reference to this list. Following the ACK, slave hardware clears the CKP bit and the SCL pin is held low (see Section 24.5.6 "Clock Stretching" for more detail). By stretching the clock, the master will be unable to assert another clock pulse until the slave is done preparing the transmit data. 1. The transmit data must be loaded into the SSPxBUF register which also loads the SSPSR register. Then the SCL pin should be released by setting the CKP bit of the SSPxCON1 register. The eight data bits are shifted out on the falling edge of the SCL input. This ensures that the SDA signal is valid during the SCL high time. The ACK pulse from the master-receiver is latched on the rising edge of the ninth SCL input pulse. This ACK value is copied to the ACKSTAT bit of the SSPxCON2 register. If ACKSTAT is set (not ACK), then the data transfer is complete. In this case, when the not ACK is latched by the slave, the slave goes idle and waits for another occurrence of the Start bit. If the SDA line was low (ACK), the next transmit data must be loaded into the SSPxBUF register. Again, the SCL pin must be released by setting bit CKP. An MSSP interrupt is generated for each data transfer byte. The SSPxIF bit must be cleared by software and the SSPxSTAT register is used to determine the status of the byte. The SSPxIF bit is set on the falling edge of the ninth clock pulse. 24.5.3.1 Master sends a Start condition on SDA and SCL. 2. S bit of SSPxSTAT is set; SSPxIF is set if interrupt on Start detect is enabled. 3. Matching address with R/W bit set is received by the Slave setting SSPxIF bit. 4. Slave hardware generates an ACK and sets SSPxIF. 5. SSPxIF bit is cleared by user. 6. Software reads the received address from SSPxBUF, clearing BF. 7. R/W is set so CKP was automatically cleared after the ACK. 8. The slave software loads the transmit data into SSPxBUF. 9. CKP bit is set releasing SCL, allowing the master to clock the data out of the slave. 10. SSPxIF is set after the ACK response from the master is loaded into the ACKSTAT register. 11. SSPxIF bit is cleared. 12. The slave software checks the ACKSTAT bit to see if the master wants to clock out more data. Note 1: If the master ACKs the clock will be stretched. 2: ACKSTAT is the only bit updated on the rising edge of SCL (9th) rather than the falling. Slave Mode Bus Collision A slave receives a Read request and begins shifting data out on the SDA line. If a bus collision is detected and the SBCDE bit of the SSPxCON3 register is set, the BCL1IF bit of the PIR2 register is set. Once a bus collision is detected, the slave goes idle and waits to be addressed again. User software can use the BCL1IF bit to handle a slave bus collision. 2014 Microchip Technology Inc. 13. Steps 9-13 are repeated for each transmitted byte. 14. If the master sends a not ACK; the clock is not held, but SSPxIF is still set. 15. The master sends a Restart condition or a Stop. 16. The slave is no longer addressed. Preliminary DS40001770A-page 287 DS40001770A-page 288 Preliminary P S D/A R/W ACKSTAT CKP BF SSPxIF S 1 2 5 6 7 8 Received address is read from SSPxBUF 4 Indicates an address has been received R/W is copied from the matching address byte When R/W is set SCL is always held low after 9th SCL falling edge 3 9 Automatic 2 3 4 5 Set by software Data to transmit is loaded into SSPxBUF Cleared by software 1 6 7 8 9 D7 D6 D5 D4 D3 D2 D1 D0 ACK Transmitting Data 2 3 4 5 7 8 CKP is not held for not ACK 6 Masters not ACK is copied to ACKSTAT BF is automatically cleared after 8th falling edge of SCL 1 D7 D6 D5 D4 D3 D2 D1 D0 Transmitting Data 9 ACK P FIGURE 24-18: SCL SDA R/W = 1 Automatic A7 A6 A5 A4 A3 A2 A1 ACK Receiving Address Master sends Stop condition PIC16(L)F1615/9 I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 0) 2014 Microchip Technology Inc. PIC16(L)F1615/9 24.5.3.3 7-bit Transmission with Address Hold Enabled Setting the AHEN bit of the SSPxCON3 register enables additional clock stretching and interrupt generation after the eighth falling edge of a received matching address. Once a matching address has been clocked in, CKP is cleared and the SSPxIF interrupt is set. Figure 24-19 displays a standard waveform of a 7-bit address slave transmission with AHEN enabled. 1. 2. Bus starts Idle. Master sends Start condition; the S bit of SSPxSTAT is set; SSPxIF is set if interrupt on Start detect is enabled. 3. Master sends matching address with R/W bit set. After the eighth falling edge of the SCL line the CKP bit is cleared and SSPxIF interrupt is generated. 4. Slave software clears SSPxIF. 5. Slave software reads ACKTIM bit of SSPxCON3 register, and R/W and D/A of the SSPxSTAT register to determine the source of the interrupt. 6. Slave reads the address value from the SSPxBUF register clearing the BF bit. 7. Slave software decides from this information if it wishes to ACK or not ACK and sets the ACKDT bit of the SSPxCON2 register accordingly. 8. Slave sets the CKP bit releasing SCL. 9. Master clocks in the ACK value from the slave. 10. Slave hardware automatically clears the CKP bit and sets SSPxIF after the ACK if the R/W bit is set. 11. Slave software clears SSPxIF. 12. Slave loads value to transmit to the master into SSPxBUF setting the BF bit. Note: SSPxBUF cannot be loaded until after the ACK. 13. Slave sets the CKP bit releasing the clock. 14. Master clocks out the data from the slave and sends an ACK value on the 9th SCL pulse. 15. Slave hardware copies the ACK value into the ACKSTAT bit of the SSPxCON2 register. 16. Steps 10-15 are repeated for each byte transmitted to the master from the slave. 17. If the master sends a not ACK the slave releases the bus allowing the master to send a Stop and end the communication. Note: Master must send a not ACK on the last byte to ensure that the slave releases the SCL line to receive a Stop. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 289 DS40001770A-page 290 Preliminary D/A R/W ACKTIM CKP ACKSTAT ACKDT BF SSPxIF S Receiving Address 2 4 5 6 7 8 Slave clears ACKDT to ACK address ACKTIM is set on 8th falling edge of SCL 9 ACK When R/W = 1; CKP is always cleared after ACK R/W = 1 Received address is read from SSPxBUF 3 When AHEN = 1; CKP is cleared by hardware after receiving matching address. 1 A7 A6 A5 A4 A3 A2 A1 3 4 5 6 Cleared by software 2 Set by software, releases SCL Data to transmit is loaded into SSPxBUF 1 7 8 9 Transmitting Data Automatic D7 D6 D5 D4 D3 D2 D1 D0 ACK ACKTIM is cleared on 9th rising edge of SCL Automatic Transmitting Data 1 3 4 5 6 7 after not ACK CKP not cleared Master's ACK response is copied to SSPxSTAT BF is automatically cleared after 8th falling edge of SCL 2 8 D7 D6 D5 D4 D3 D2 D1 D0 9 ACK P Master sends Stop condition FIGURE 24-19: SCL SDA Master releases SDA to slave for ACK sequence PIC16(L)F1615/9 I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 1) 2014 Microchip Technology Inc. PIC16(L)F1615/9 24.5.4 SLAVE MODE 10-BIT ADDRESS RECEPTION 24.5.5 This section describes a standard sequence of events for the MSSP module configured as an I2C slave in 10-bit Addressing mode. Figure 24-20 is used as a visual reference for this description. This is a step by step process of what must be done by slave software to accomplish I2C communication. 1. 2. 3. 4. 5. 6. 7. 8. Bus starts Idle. Master sends Start condition; S bit of SSPxSTAT is set; SSPxIF is set if interrupt on Start detect is enabled. Master sends matching high address with R/W bit clear; UA bit of the SSPxSTAT register is set. Slave sends ACK and SSPxIF is set. Software clears the SSPxIF bit. Software reads received address from SSPxBUF clearing the BF flag. Slave loads low address into SSPxADD, releasing SCL. Master sends matching low address byte to the slave; UA bit is set. 10-BIT ADDRESSING WITH ADDRESS OR DATA HOLD Reception using 10-bit addressing with AHEN or DHEN set is the same as with 7-bit modes. The only difference is the need to update the SSPxADD register using the UA bit. All functionality, specifically when the CKP bit is cleared and SCL line is held low are the same. Figure 24-21 can be used as a reference of a slave in 10-bit addressing with AHEN set. Figure 24-22 shows a standard waveform for a slave transmitter in 10-bit Addressing mode. Note: Updates to the SSPxADD register are not allowed until after the ACK sequence. 9. Slave sends ACK and SSPxIF is set. Note: If the low address does not match, SSPxIF and UA are still set so that the slave software can set SSPxADD back to the high address. BF is not set because there is no match. CKP is unaffected. 10. Slave clears SSPxIF. 11. Slave reads the received matching address from SSPxBUF clearing BF. 12. Slave loads high address into SSPxADD. 13. Master clocks a data byte to the slave and clocks out the slaves ACK on the 9th SCL pulse; SSPxIF is set. 14. If SEN bit of SSPxCON2 is set, CKP is cleared by hardware and the clock is stretched. 15. Slave clears SSPxIF. 16. Slave reads the received byte from SSPxBUF clearing BF. 17. If SEN is set the slave sets CKP to release the SCL. 18. Steps 13-17 repeat for each received byte. 19. Master sends Stop to end the transmission. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 291 DS40001770A-page 292 Preliminary CKP UA BF SSPxIF S 1 1 2 1 5 6 7 0 A9 A8 8 Set by hardware on 9th falling edge 4 1 When UA = 1; SCL is held low 9 ACK If address matches SSPxADD it is loaded into SSPxBUF 3 1 Receive First Address Byte 1 3 4 5 6 7 8 Software updates SSPxADD and releases SCL 2 9 A7 A6 A5 A4 A3 A2 A1 A0 ACK Receive Second Address Byte 1 3 4 5 6 7 8 9 1 3 4 5 6 7 Data is read from SSPxBUF SCL is held low while CKP = 0 2 8 9 D7 D6 D5 D4 D3 D2 D1 D0 ACK Receive Data Set by software, When SEN = 1; releasing SCL CKP is cleared after 9th falling edge of received byte Receive address is read from SSPxBUF Cleared by software 2 D7 D6 D5 D4 D3 D2 D1 D0 ACK Receive Data P FIGURE 24-20: SCL SDA Master sends Stop condition PIC16(L)F1615/9 I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0) 2014 Microchip Technology Inc. 2014 Microchip Technology Inc. Preliminary ACKTIM CKP UA ACKDT BF 2 1 5 0 6 A9 7 A8 Set by hardware on 9th falling edge 4 1 8 R/W = 0 ACKTIM is set by hardware on 8th falling edge of SCL If when AHEN = 1; on the 8th falling edge of SCL of an address byte, CKP is cleared Slave software clears ACKDT to ACK the received byte 3 1 Receive First Address Byte 9 ACK UA 2 3 A5 4 A4 6 A2 7 A1 Update to SSPxADD is not allowed until 9th falling edge of SCL SSPxBUF can be read anytime before the next received byte 5 A3 Receive Second Address Byte A6 Cleared by software 1 A7 8 A0 9 ACK UA 2 D6 3 D5 4 D4 6 D2 Set CKP with software releases SCL 7 D1 Update of SSPxADD, clears UA and releases SCL 5 D3 Receive Data Cleared by software 1 D7 8 9 2 Received data is read from SSPxBUF 1 D6 D5 Receive Data D0 ACK D7 FIGURE 24-21: SSPxIF 1 SCL S 1 SDA PIC16(L)F1615/9 I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 0) DS40001770A-page 293 DS40001770A-page 294 Preliminary D/A R/W ACKSTAT CKP UA BF SSPxIF 4 5 6 7 Set by hardware 3 Indicates an address has been received UA indicates SSPxADD must be updated SSPxBUF loaded with received address 2 8 9 1 SCL S Receiving Address R/W = 0 1 1 1 1 0 A9 A8 ACK 1 3 4 5 6 7 8 After SSPxADD is updated, UA is cleared and SCL is released Cleared by software 2 9 A7 A6 A5 A4 A3 A2 A1 A0 ACK Receiving Second Address Byte 1 4 5 6 7 8 Set by hardware 2 3 R/W is copied from the matching address byte When R/W = 1; CKP is cleared on 9th falling edge of SCL High address is loaded back into SSPxADD Received address is read from SSPxBUF Sr 1 1 1 1 0 A9 A8 Receive First Address Byte 9 ACK 2 3 4 5 6 7 8 Masters not ACK is copied Set by software releases SCL Data to transmit is loaded into SSPxBUF 1 D7 D6 D5 D4 D3 D2 D1 D0 Transmitting Data Byte 9 P Master sends Stop condition ACK = 1 Master sends not ACK FIGURE 24-22: SDA Master sends Restart event PIC16(L)F1615/9 I2C SLAVE, 10-BIT ADDRESS, TRANSMISSION (SEN = 0, AHEN = 0, DHEN = 0) 2014 Microchip Technology Inc. PIC16(L)F1615/9 24.5.6 CLOCK STRETCHING 24.5.6.2 Clock stretching occurs when a device on the bus holds the SCL line low, effectively pausing communication. The slave may stretch the clock to allow more time to handle data or prepare a response for the master device. A master device is not concerned with stretching as anytime it is active on the bus and not transferring data it is stretching. Any stretching done by a slave is invisible to the master software and handled by the hardware that generates SCL. The CKP bit of the SSPxCON1 register is used to control stretching in software. Any time the CKP bit is cleared, the module will wait for the SCL line to go low and then hold it. Setting CKP will release SCL and allow more communication. 24.5.6.1 Normal Clock Stretching Following an ACK if the R/W bit of SSPxSTAT is set, a read request, the slave hardware will clear CKP. This allows the slave time to update SSPxBUF with data to transfer to the master. If the SEN bit of SSPxCON2 is set, the slave hardware will always stretch the clock after the ACK sequence. Once the slave is ready; CKP is set by software and communication resumes. Note 1:The BF bit has no effect on if the clock will be stretched or not. This is different than previous versions of the module that would not stretch the clock, clear CKP, if SSPxBUF was read before the 9th falling edge of SCL. 2: Previous versions of the module did not stretch the clock for a transmission if SSPxBUF was loaded before the 9th falling edge of SCL. It is now always cleared for read requests. FIGURE 24-23: 10-bit Addressing Mode In 10-bit Addressing mode, when the UA bit is set the clock is always stretched. This is the only time the SCL is stretched without CKP being cleared. SCL is released immediately after a write to SSPxADD. Note: Previous versions of the module did not stretch the clock if the second address byte did not match. 24.5.6.3 Byte NACKing When the AHEN bit of SSPxCON3 is set; CKP is cleared by hardware after the eighth falling edge of SCL for a received matching address byte. When the DHEN bit of SSPxCON3 is set; CKP is cleared after the eighth falling edge of SCL for received data. Stretching after the eighth falling edge of SCL allows the slave to look at the received address or data and decide if it wants to ACK the received data. 24.5.6.4 Clock Synchronization and the CKP Bit Any time the CKP bit is cleared, the module will wait for the SCL line to go low and then hold it. However, clearing the CKP bit will not assert the SCL output low until the SCL output is already sampled low. Therefore, the CKP bit will not assert the SCL line until an external I2C master device has already asserted the SCL line. The SCL output will remain low until the CKP bit is set and all other devices on the I2C bus have released SCL. This ensures that a write to the CKP bit will not violate the minimum high time requirement for SCL (see Figure 24-23). CLOCK SYNCHRONIZATION TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 SDA DX - 1 DX SCL CKP Master device asserts clock Master device releases clock WR SSPxCON1 2014 Microchip Technology Inc. Preliminary DS40001770A-page 295 PIC16(L)F1615/9 24.5.7 GENERAL CALL ADDRESS SUPPORT R/W bit clear, an interrupt is generated and slave software can read SSPxBUF and respond. Figure 24-24 shows a general call reception sequence. The addressing procedure for the I2C bus is such that the first byte after the Start condition usually determines which device will be the slave addressed by the master device. The exception is the general call address which can address all devices. When this address is used, all devices should, in theory, respond with an acknowledge. In 10-bit Address mode, the UA bit will not be set on the reception of the general call address. The slave will prepare to receive the second byte as data, just as it would in 7-bit mode. If the AHEN bit of the SSPxCON3 register is set, just as with any other address reception, the slave hardware will stretch the clock after the eighth falling edge of SCL. The slave must then set its ACKDT value and release the clock with communication progressing as it would normally. The general call address is a reserved address in the I2C protocol, defined as address 0x00. When the GCEN bit of the SSPxCON2 register is set, the slave module will automatically ACK the reception of this address regardless of the value stored in SSPxADD. After the slave clocks in an address of all zeros with the FIGURE 24-24: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE Address is compared to General Call Address after ACK, set interrupt R/W = 0 ACK D7 General Call Address SDA SCL S 1 2 3 4 5 6 7 8 9 1 Receiving Data ACK D6 D5 D4 D3 D2 D1 D0 2 3 4 5 6 7 8 9 SSPxIF BF (SSPxSTAT<0>) Cleared by software SSPxBUF is read GCEN (SSPxCON2<7>) '1' 24.5.8 SSP MASK REGISTER An SSP Mask (SSPxMSK) register (Register 24-5) is available in I2C Slave mode as a mask for the value held in the SSPSR register during an address comparison operation. A zero (`0') bit in the SSPxMSK register has the effect of making the corresponding bit of the received address a "don't care". This register is reset to all `1's upon any Reset condition and, therefore, has no effect on standard SSP operation until written with a mask value. The SSP Mask register is active during: * 7-bit Address mode: address compare of A<7:1>. * 10-bit Address mode: address compare of A<7:0> only. The SSP mask has no effect during the reception of the first (high) byte of the address. DS40001770A-page 296 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 24.6 I2C Master Mode 24.6.1 I2C MASTER MODE OPERATION Master mode is enabled by setting and clearing the appropriate SSPM bits in the SSPxCON1 register and by setting the SSPEN bit. In Master mode, the SDA and SCK pins must be configured as inputs. The MSSP peripheral hardware will override the output driver TRIS controls when necessary to drive the pins low. The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with a Stop condition or with a Repeated Start condition. Since the Repeated Start condition is also the beginning of the next serial transfer, the I2C bus will not be released. Master mode of operation is supported by interrupt generation on the detection of the Start and Stop conditions. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP module is disabled. Control of the I 2C bus may be taken when the P bit is set, or the bus is Idle. In Master Transmitter mode, serial data is output through SDA, while SCL outputs the serial clock. The first byte transmitted contains the slave address of the receiving device (7 bits) and the Read/Write (R/W) bit. In this case, the R/W bit will be logic `0'. Serial data is transmitted eight bits at a time. After each byte is transmitted, an Acknowledge bit is received. Start and Stop conditions are output to indicate the beginning and the end of a serial transfer. In Firmware Controlled Master mode, user code conducts all I 2C bus operations based on Start and Stop bit condition detection. Start and Stop condition detection is the only active circuitry in this mode. All other communication is done by the user software directly manipulating the SDA and SCL lines. The following events will cause the SSP Interrupt Flag bit, SSPxIF, to be set (SSP interrupt, if enabled): * * * * * Start condition detected Stop condition detected Data transfer byte transmitted/received Acknowledge transmitted/received Repeated Start generated Note 1:The MSSP module, when configured in I2C Master mode, does not allow queuing of events. For instance, the user is not allowed to initiate a Start condition and immediately write the SSPxBUF register to initiate transmission before the Start condition is complete. In this case, the SSPxBUF will not be written to and the WCOL bit will be set, indicating that a write to the SSPxBUF did not occur In Master Receive mode, the first byte transmitted contains the slave address of the transmitting device (7 bits) and the R/W bit. In this case, the R/W bit will be logic `1'. Thus, the first byte transmitted is a 7-bit slave address followed by a `1' to indicate the receive bit. Serial data is received via SDA, while SCL outputs the serial clock. Serial data is received eight bits at a time. After each byte is received, an Acknowledge bit is transmitted. Start and Stop conditions indicate the beginning and end of transmission. A Baud Rate Generator is used to set the clock frequency output on SCL. See Section 24.7 "Baud Rate Generator" for more detail. 2: When in Master mode, Start/Stop detection is masked and an interrupt is generated when the SEN/PEN bit is cleared and the generation is complete. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 297 PIC16(L)F1615/9 24.6.2 CLOCK ARBITRATION Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, releases the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the SCL pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD<7:0> and begins counting. This ensures that the SCL high time will always be at least one BRG rollover count in the event that the clock is held low by an external device (Figure 24-25). FIGURE 24-25: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION SDA DX - 1 DX SCL deasserted but slave holds SCL low (clock arbitration) SCL allowed to transition high SCL BRG decrements on Q2 and Q4 cycles BRG Value 03h 02h 01h 00h (hold off) 03h 02h SCL is sampled high, reload takes place and BRG starts its count BRG Reload 24.6.3 WCOL STATUS FLAG If the user writes the SSPxBUF when a Start, Restart, Stop, Receive or Transmit sequence is in progress, the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur). Any time the WCOL bit is set it indicates that an action on SSPxBUF was attempted while the module was not idle. Note: Because queuing of events is not allowed, writing to the lower five bits of SSPxCON2 is disabled until the Start condition is complete. DS40001770A-page 298 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 24.6.4 I2C MASTER MODE START CONDITION TIMING by hardware; the Baud Rate Generator is suspended, leaving the SDA line held low and the Start condition is complete. To initiate a Start condition (Figure 24-26), the user sets the Start Enable bit, SEN bit of the SSPxCON2 register. If the SDA and SCL pins are sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD<7:0> and starts its count. If SCL and SDA are both sampled high when the Baud Rate Generator times out (TBRG), the SDA pin is driven low. The action of the SDA being driven low while SCL is high is the Start condition and causes the S bit of the SSPxSTAT1 register to be set. Following this, the Baud Rate Generator is reloaded with the contents of SSPxADD<7:0> and resumes its count. When the Baud Rate Generator times out (TBRG), the SEN bit of the SSPxCON2 register will be automatically cleared FIGURE 24-26: Note 1: If at the beginning of the Start condition, the SDA and SCL pins are already sampled low, or if during the Start condition, the SCL line is sampled low before the SDA line is driven low, a bus collision occurs, the Bus Collision Interrupt Flag, BCL1IF, is set, the Start condition is aborted and the I2C module is reset into its Idle state. 2: The Philips I2CTM specification states that a bus collision cannot occur on a Start. FIRST START BIT TIMING Set S bit (SSPxSTAT<3>) Write to SEN bit occurs here At completion of Start bit, hardware clears SEN bit and sets SSPxIF bit SDA = 1, SCL = 1 TBRG TBRG Write to SSPxBUF occurs here SDA 1st bit 2nd bit TBRG SCL S 2014 Microchip Technology Inc. Preliminary TBRG DS40001770A-page 299 PIC16(L)F1615/9 24.6.5 I2C MASTER MODE REPEATED START CONDITION TIMING cally cleared and the Baud Rate Generator will not be reloaded, leaving the SDA pin held low. As soon as a Start condition is detected on the SDA and SCL pins, the S bit of the SSPxSTAT register will be set. The SSPxIF bit will not be set until the Baud Rate Generator has timed out. A Repeated Start condition (Figure 24-27) occurs when the RSEN bit of the SSPxCON2 register is programmed high and the master state machine is no longer active. When the RSEN bit is set, the SCL pin is asserted low. When the SCL pin is sampled low, the Baud Rate Generator is loaded and begins counting. The SDA pin is released (brought high) for one Baud Rate Generator count (TBRG). When the Baud Rate Generator times out, if SDA is sampled high, the SCL pin will be deasserted (brought high). When SCL is sampled high, the Baud Rate Generator is reloaded and begins counting. SDA and SCL must be sampled high for one TBRG. This action is then followed by assertion of the SDA pin (SDA = 0) for one TBRG while SCL is high. SCL is asserted low. Following this, the RSEN bit of the SSPxCON2 register will be automati- FIGURE 24-27: Note 1: If RSEN is programmed while any other event is in progress, it will not take effect. 2: A bus collision during the Repeated Start condition occurs if: *SDA is sampled low when SCL goes from low-to-high. *SCL goes low before SDA is asserted low. This may indicate that another master is attempting to transmit a data `1'. REPEATED START CONDITION WAVEFORM S bit set by hardware Write to SSPxCON2 occurs here SDA = 1, SCL (no change) At completion of Start bit, hardware clears RSEN bit and sets SSPxIF SDA = 1, SCL = 1 TBRG TBRG TBRG 1st bit SDA Write to SSPxBUF occurs here TBRG SCL Sr TBRG Repeated Start DS40001770A-page 300 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 24.6.6 I2C MASTER MODE TRANSMISSION 24.6.6.3 Transmission of a data byte, a 7-bit address or the other half of a 10-bit address is accomplished by simply writing a value to the SSPxBUF register. This action will set the Buffer Full flag bit, BF, and allow the Baud Rate Generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDA pin after the falling edge of SCL is asserted. SCL is held low for one Baud Rate Generator rollover count (TBRG). Data should be valid before SCL is released high. When the SCL pin is released high, it is held that way for TBRG. The data on the SDA pin must remain stable for that duration and some hold time after the next falling edge of SCL. After the eighth bit is shifted out (the falling edge of the eighth clock), the BF flag is cleared and the master releases SDA. This allows the slave device being addressed to respond with an ACK bit during the ninth bit time if an address match occurred, or if data was received properly. The status of ACK is written into the ACKSTAT bit on the rising edge of the ninth clock. If the master receives an Acknowledge, the Acknowledge Status bit, ACKSTAT, is cleared. If not, the bit is set. After the ninth clock, the SSPxIF bit is set and the master clock (Baud Rate Generator) is suspended until the next data byte is loaded into the SSPxBUF, leaving SCL low and SDA unchanged (Figure 24-28). After the write to the SSPxBUF, each bit of the address will be shifted out on the falling edge of SCL until all seven address bits and the R/W bit are completed. On the falling edge of the eighth clock, the master will release the SDA pin, allowing the slave to respond with an Acknowledge. On the falling edge of the ninth clock, the master will sample the SDA pin to see if the address was recognized by a slave. The status of the ACK bit is loaded into the ACKSTAT Status bit of the SSPxCON2 register. Following the falling edge of the ninth clock transmission of the address, the SSPxIF is set, the BF flag is cleared and the Baud Rate Generator is turned off until another write to the SSPxBUF takes place, holding SCL low and allowing SDA to float. 24.6.6.1 ACKSTAT Status Flag In Transmit mode, the ACKSTAT bit of the SSPxCON2 register is cleared when the slave has sent an Acknowledge (ACK = 0) and is set when the slave does not Acknowledge (ACK = 1). A slave sends an Acknowledge when it has recognized its address (including a general call), or when the slave has properly received its data. 24.6.6.4 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. BF Status Flag Typical Transmit Sequence: The user generates a Start condition by setting the SEN bit of the SSPxCON2 register. SSPxIF is set by hardware on completion of the Start. SSPxIF is cleared by software. The MSSP module will wait the required start time before any other operation takes place. The user loads the SSPxBUF with the slave address to transmit. Address is shifted out the SDA pin until all eight bits are transmitted. Transmission begins as soon as SSPxBUF is written to. The MSSP module shifts in the ACK bit from the slave device and writes its value into the ACKSTAT bit of the SSPxCON2 register. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPxIF bit. The user loads the SSPxBUF with eight bits of data. Data is shifted out the SDA pin until all eight bits are transmitted. The MSSP module shifts in the ACK bit from the slave device and writes its value into the ACKSTAT bit of the SSPxCON2 register. Steps 8-11 are repeated for all transmitted data bytes. The user generates a Stop or Restart condition by setting the PEN or RSEN bits of the SSPxCON2 register. Interrupt is generated once the Stop/Restart condition is complete. In Transmit mode, the BF bit of the SSPxSTAT register is set when the CPU writes to SSPxBUF and is cleared when all eight bits are shifted out. 24.6.6.2 WCOL Status Flag If the user writes the SSPxBUF when a transmit is already in progress (i.e., SSPSR is still shifting out a data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur). WCOL must be cleared by software before the next transmission. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 301 DS40001770A-page 302 S Preliminary R/W PEN SEN BF (SSPxSTAT<0>) SSPxIF SCL SDA A6 A5 A4 A3 A2 A1 3 4 5 Cleared by software 2 6 7 8 9 After Start condition, SEN cleared by hardware SSPxBUF written 1 D7 1 SCL held low while CPU responds to SSPxIF ACK = 0 R/W = 0 SSPxBUF written with 7-bit address and R/W start transmit A7 Transmit Address to Slave 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 SSPxBUF is written by software Cleared by software service routine from SSP interrupt 2 D6 Transmitting Data or Second Half of 10-bit Address P Cleared by software 9 ACK From slave, clear ACKSTAT bit SSPxCON2<6> ACKSTAT in SSPxCON2 = 1 FIGURE 24-28: SEN = 0 Write SSPxCON2<0> SEN = 1 Start condition begins PIC16(L)F1615/9 I2C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS) 2014 Microchip Technology Inc. PIC16(L)F1615/9 24.6.7 I2C MASTER MODE RECEPTION 24.6.7.4 Master mode reception (Figure 24-29) is enabled by programming the Receive Enable bit, RCEN bit of the SSPxCON2 register. Note: The MSSP module must be in an Idle state before the RCEN bit is set or the RCEN bit will be disregarded. The Baud Rate Generator begins counting and on each rollover, the state of the SCL pin changes (high-to-low/ low-to-high) and data is shifted into the SSPSR. After the falling edge of the eighth clock, the receive enable flag is automatically cleared, the contents of the SSPSR are loaded into the SSPxBUF, the BF flag bit is set, the SSPxIF flag bit is set and the Baud Rate Generator is suspended from counting, holding SCL low. The MSSP is now in Idle state awaiting the next command. When the buffer is read by the CPU, the BF flag bit is automatically cleared. The user can then send an Acknowledge bit at the end of reception by setting the Acknowledge Sequence Enable, ACKEN bit of the SSPxCON2 register. 24.6.7.1 2. 3. 4. 5. 6. 7. 8. 9. 10. BF Status Flag In receive operation, the BF bit is set when an address or data byte is loaded into SSPxBUF from SSPSR. It is cleared when the SSPxBUF register is read. 24.6.7.2 1. 11. 12. SSPOV Status Flag In receive operation, the SSPOV bit is set when eight bits are received into the SSPSR and the BF flag bit is already set from a previous reception. 13. 14. 24.6.7.3 15. WCOL Status Flag If the user writes the SSPxBUF when a receive is already in progress (i.e., SSPSR is still shifting in a data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur). 2014 Microchip Technology Inc. Preliminary Typical Receive Sequence: The user generates a Start condition by setting the SEN bit of the SSPxCON2 register. SSPxIF is set by hardware on completion of the Start. SSPxIF is cleared by software. User writes SSPxBUF with the slave address to transmit and the R/W bit set. Address is shifted out the SDA pin until all eight bits are transmitted. Transmission begins as soon as SSPxBUF is written to. The MSSP module shifts in the ACK bit from the slave device and writes its value into the ACKSTAT bit of the SSPxCON2 register. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPxIF bit. User sets the RCEN bit of the SSPxCON2 register and the master clocks in a byte from the slave. After the eighth falling edge of SCL, SSPxIF and BF are set. Master clears SSPxIF and reads the received byte from SSPxBUF, clears BF. Master sets ACK value sent to slave in ACKDT bit of the SSPxCON2 register and initiates the ACK by setting the ACKEN bit. Master's ACK is clocked out to the slave and SSPxIF is set. User clears SSPxIF. Steps 8-13 are repeated for each received byte from the slave. Master sends a not ACK or Stop to end communication. DS40001770A-page 303 DS40001770A-page 304 Preliminary RCEN ACKEN SSPOV BF (SSPxSTAT<0>) SDA = 0, SCL = 1 while CPU responds to SSPxIF SSPxIF S 1 A7 2 4 5 6 Cleared by software 3 A6 A5 A4 A3 A2 Transmit Address to Slave 7 8 9 ACK Receiving Data from Slave 2 3 5 6 7 8 D0 9 ACK Receiving Data from Slave 2 3 4 RCEN cleared automatically 5 6 7 Cleared by software Set SSPxIF interrupt at end of Acknowledge sequence Data shifted in on falling edge of CLK 1 ACK from Master SDA = ACKDT = 0 Cleared in software Set SSPxIF at end of receive 9 ACK is not sent ACK RCEN cleared automatically P Set SSPxIF interrupt at end of Acknowledge sequence Bus master terminates transfer Set P bit (SSPxSTAT<4>) and SSPxIF PEN bit = 1 written here SSPOV is set because SSPxBUF is still full 8 D0 RCEN cleared automatically Set ACKEN, start Acknowledge sequence SDA = ACKDT = 1 D7 D6 D5 D4 D3 D2 D1 Last bit is shifted into SSPSR and contents are unloaded into SSPxBUF Cleared by software Set SSPxIF interrupt at end of receive 4 Cleared by software 1 D7 D6 D5 D4 D3 D2 D1 Master configured as a receiver by programming SSPxCON2<3> (RCEN = 1) A1 R/W RCEN = 1, start next receive ACK from Master SDA = ACKDT = 0 FIGURE 24-29: SCL SDA Master configured as a receiver by programming SSPxCON2<3> (RCEN = 1) SEN = 0 Write to SSPxBUF occurs here, RCEN cleared ACK from Slave automatically start XMIT Write to SSPxCON2<0>(SEN = 1), begin Start condition Write to SSPxCON2<4> to start Acknowledge sequence SDA = ACKDT (SSPxCON2<5>) = 0 PIC16(L)F1615/9 I2C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) 2014 Microchip Technology Inc. PIC16(L)F1615/9 24.6.8 ACKNOWLEDGE SEQUENCE TIMING 24.6.9 A Stop bit is asserted on the SDA pin at the end of a receive/transmit by setting the Stop Sequence Enable bit, PEN bit of the SSPxCON2 register. At the end of a receive/transmit, the SCL line is held low after the falling edge of the ninth clock. When the PEN bit is set, the master will assert the SDA line low. When the SDA line is sampled low, the Baud Rate Generator is reloaded and counts down to `0'. When the Baud Rate Generator times out, the SCL pin will be brought high and one TBRG (Baud Rate Generator rollover count) later, the SDA pin will be deasserted. When the SDA pin is sampled high while SCL is high, the P bit of the SSPxSTAT register is set. A TBRG later, the PEN bit is cleared and the SSPxIF bit is set (Figure 24-31). An Acknowledge sequence is enabled by setting the Acknowledge Sequence Enable bit, ACKEN bit of the SSPxCON2 register. When this bit is set, the SCL pin is pulled low and the contents of the Acknowledge data bit are presented on the SDA pin. If the user wishes to generate an Acknowledge, then the ACKDT bit should be cleared. If not, the user should set the ACKDT bit before starting an Acknowledge sequence. The Baud Rate Generator then counts for one rollover period (TBRG) and the SCL pin is deasserted (pulled high). When the SCL pin is sampled high (clock arbitration), the Baud Rate Generator counts for TBRG. The SCL pin is then pulled low. Following this, the ACKEN bit is automatically cleared, the Baud Rate Generator is turned off and the MSSP module then goes into Idle mode (Figure 24-30). 24.6.8.1 24.6.9.1 WCOL Status Flag If the user writes the SSPxBUF when a Stop sequence is in progress, then the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur). WCOL Status Flag If the user writes the SSPxBUF when an Acknowledge sequence is in progress, then WCOL bit is set and the contents of the buffer are unchanged (the write does not occur). FIGURE 24-30: STOP CONDITION TIMING ACKNOWLEDGE SEQUENCE WAVEFORM Acknowledge sequence starts here, write to SSPxCON2 ACKEN = 1, ACKDT = 0 ACKEN automatically cleared TBRG TBRG SDA ACK D0 SCL 8 9 SSPxIF SSPxIF set at the end of receive Cleared in software SSPxIF set at the end of Acknowledge sequence Cleared in software Note: TBRG = one Baud Rate Generator period. FIGURE 24-31: STOP CONDITION RECEIVE OR TRANSMIT MODE SCL = 1 for TBRG, followed by SDA = 1 for TBRG after SDA sampled high. P bit (SSPxSTAT<4>) is set. Write to SSPxCON2, set PEN PEN bit (SSPxCON2<2>) is cleared by hardware and the SSPxIF bit is set Falling edge of 9th clock TBRG SCL SDA ACK P TBRG TBRG TBRG SCL brought high after TBRG SDA asserted low before rising edge of clock to setup Stop condition Note: TBRG = one Baud Rate Generator period. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 305 PIC16(L)F1615/9 24.6.10 SLEEP OPERATION 24.6.13 2 While in Sleep mode, the I C slave module can receive addresses or data and when an address match or complete byte transfer occurs, wake the processor from Sleep (if the MSSP interrupt is enabled). 24.6.11 EFFECTS OF A RESET A Reset disables the MSSP module and terminates the current transfer. 24.6.12 MULTI-MASTER MODE In Multi-Master mode, the interrupt generation on the detection of the Start and Stop conditions allows the determination of when the bus is free. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP module is disabled. Control of the I 2C bus may be taken when the P bit of the SSPxSTAT register is set, or the bus is Idle, with both the S and P bits clear. When the bus is busy, enabling the SSP interrupt will generate the interrupt when the Stop condition occurs. In multi-master operation, the SDA line must be monitored for arbitration to see if the signal level is the expected output level. This check is performed by hardware with the result placed in the BCL1IF bit. The states where arbitration can be lost are: * * * * * Address Transfer Data Transfer A Start Condition A Repeated Start Condition An Acknowledge Condition MULTI -MASTER COMMUNICATION, BUS COLLISION AND BUS ARBITRATION Multi-Master mode support is achieved by bus arbitration. When the master outputs address/data bits onto the SDA pin, arbitration takes place when the master outputs a `1' on SDA, by letting SDA float high and another master asserts a `0'. When the SCL pin floats high, data should be stable. If the expected data on SDA is a `1' and the data sampled on the SDA pin is `0', then a bus collision has taken place. The master will set the Bus Collision Interrupt Flag, BCL1IF and reset the I2C port to its Idle state (Figure 24-32). If a transmit was in progress when the bus collision occurred, the transmission is halted, the BF flag is cleared, the SDA and SCL lines are deasserted and the SSPxBUF can be written to. When the user services the bus collision Interrupt Service Routine and if the I2C bus is free, the user can resume communication by asserting a Start condition. If a Start, Repeated Start, Stop or Acknowledge condition was in progress when the bus collision occurred, the condition is aborted, the SDA and SCL lines are deasserted and the respective control bits in the SSPxCON2 register are cleared. When the user services the bus collision Interrupt Service Routine and if the I2C bus is free, the user can resume communication by asserting a Start condition. The master will continue to monitor the SDA and SCL pins. If a Stop condition occurs, the SSPxIF bit will be set. A write to the SSPxBUF will start the transmission of data at the first data bit, regardless of where the transmitter left off when the bus collision occurred. In Multi-Master mode, the interrupt generation on the detection of Start and Stop conditions allows the determination of when the bus is free. Control of the I2C bus can be taken when the P bit is set in the SSPxSTAT register, or the bus is Idle and the S and P bits are cleared. FIGURE 24-32: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Data changes while SCL = 0 SDA line pulled low by another source SDA released by master Sample SDA. While SCL is high, data does not match what is driven by the master. Bus collision has occurred. SDA SCL Set bus collision interrupt (BCL1IF) BCL1IF DS40001770A-page 306 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 24.6.13.1 Bus Collision During a Start Condition During a Start condition, a bus collision occurs if: a) b) SDA or SCL are sampled low at the beginning of the Start condition (Figure 24-33). SCL is sampled low before SDA is asserted low (Figure 24-34). During a Start condition, both the SDA and the SCL pins are monitored. If the SDA pin is sampled low during this count, the BRG is reset and the SDA line is asserted early (Figure 24-35). If, however, a `1' is sampled on the SDA pin, the SDA pin is asserted low at the end of the BRG count. The Baud Rate Generator is then reloaded and counts down to zero; if the SCL pin is sampled as `0' during this time, a bus collision does not occur. At the end of the BRG count, the SCL pin is asserted low. Note: If the SDA pin is already low, or the SCL pin is already low, then all of the following occur: * the Start condition is aborted, * the BCL1IF flag is set and * the MSSP module is reset to its Idle state (Figure 24-33). The Start condition begins with the SDA and SCL pins deasserted. When the SDA pin is sampled high, the Baud Rate Generator is loaded and counts down. If the SCL pin is sampled low while SDA is high, a bus collision occurs because it is assumed that another master is attempting to drive a data `1' during the Start condition. FIGURE 24-33: The reason that bus collision is not a factor during a Start condition is that no two bus masters can assert a Start condition at the exact same time. Therefore, one master will always assert SDA before the other. This condition does not cause a bus collision because the two masters must be allowed to arbitrate the first address following the Start condition. If the address is the same, arbitration must be allowed to continue into the data portion, Repeated Start or Stop conditions. BUS COLLISION DURING START CONDITION (SDA ONLY) SDA goes low before the SEN bit is set. Set BCL1IF, S bit and SSPxIF set because SDA = 0, SCL = 1. SDA SCL Set SEN, enable Start condition if SDA = 1, SCL = 1 SEN cleared automatically because of bus collision. SSP module reset into Idle state. SEN BCL1IF SDA sampled low before Start condition. Set BCL1IF. S bit and SSPxIF set because SDA = 0, SCL = 1. SSPxIF and BCL1IF are cleared by software S SSPxIF SSPxIF and BCL1IF are cleared by software 2014 Microchip Technology Inc. Preliminary DS40001770A-page 307 PIC16(L)F1615/9 FIGURE 24-34: BUS COLLISION DURING START CONDITION (SCL = 0) SDA = 0, SCL = 1 TBRG TBRG SDA Set SEN, enable Start sequence if SDA = 1, SCL = 1 SCL SCL = 0 before SDA = 0, bus collision occurs. Set BCL1IF. SEN SCL = 0 before BRG time-out, bus collision occurs. Set BCL1IF. BCL1IF Interrupt cleared by software S '0' '0' SSPxIF '0' '0' FIGURE 24-35: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION SDA = 0, SCL = 1 Set S Less than TBRG SDA SCL TBRG SDA pulled low by other master. Reset BRG and assert SDA. S SCL pulled low after BRG time-out SEN BCL1IF Set SSPxIF Set SEN, enable Start sequence if SDA = 1, SCL = 1 '0' S SSPxIF SDA = 0, SCL = 1, set SSPxIF DS40001770A-page 308 Preliminary Interrupts cleared by software 2014 Microchip Technology Inc. PIC16(L)F1615/9 24.6.13.2 If SDA is low, a bus collision has occurred (i.e., another master is attempting to transmit a data `0', Figure 24-36). If SDA is sampled high, the BRG is reloaded and begins counting. If SDA goes from high-to-low before the BRG times out, no bus collision occurs because no two masters can assert SDA at exactly the same time. Bus Collision During a Repeated Start Condition During a Repeated Start condition, a bus collision occurs if: a) b) A low level is sampled on SDA when SCL goes from low level to high level (Case 1). SCL goes low before SDA is asserted low, indicating that another master is attempting to transmit a data `1' (Case 2). If SCL goes from high-to-low before the BRG times out and SDA has not already been asserted, a bus collision occurs. In this case, another master is attempting to transmit a data `1' during the Repeated Start condition, see Figure 24-37. When the user releases SDA and the pin is allowed to float high, the BRG is loaded with SSPxADD and counts down to zero. The SCL pin is then deasserted and when sampled high, the SDA pin is sampled. FIGURE 24-36: If, at the end of the BRG time-out, both SCL and SDA are still high, the SDA pin is driven low and the BRG is reloaded and begins counting. At the end of the count, regardless of the status of the SCL pin, the SCL pin is driven low and the Repeated Start condition is complete. BUS COLLISION DURING A REPEATED START CONDITION (CASE 1) SDA SCL Sample SDA when SCL goes high. If SDA = 0, set BCL1IF and release SDA and SCL. RSEN BCL IF Cleared by software S '0' SSPxIF '0' FIGURE 24-37: BUS COLLISION DURING REPEATED START CONDITION (CASE 2) TBRG TBRG SDA SCL BCL1IF SCL goes low before SDA, set BCL1IF. Release SDA and SCL. Interrupt cleared by software RSEN '0' S SSPxIF 2014 Microchip Technology Inc. Preliminary DS40001770A-page 309 PIC16(L)F1615/9 24.6.13.3 The Stop condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPxADD and counts down to zero. After the BRG times out, SDA is sampled. If SDA is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data `0' (Figure 24-38). If the SCL pin is sampled low before SDA is allowed to float high, a bus collision occurs. This is another case of another master attempting to drive a data `0' (Figure 24-39). Bus Collision During a Stop Condition Bus collision occurs during a Stop condition if: a) b) After the SDA pin has been deasserted and allowed to float high, SDA is sampled low after the BRG has timed out (Case 1). After the SCL pin is deasserted, SCL is sampled low before SDA goes high (Case 2). FIGURE 24-38: BUS COLLISION DURING A STOP CONDITION (CASE 1) TBRG TBRG SDA sampled low after TBRG, set BCL1IF TBRG SDA SDA asserted low SCL PEN BCL1IF P '0' SSPxIF '0' FIGURE 24-39: BUS COLLISION DURING A STOP CONDITION (CASE 2) TBRG TBRG TBRG SDA SCL goes low before SDA goes high, set BCL1IF Assert SDA SCL PEN BCL1IF P '0' SSPxIF '0' DS40001770A-page 310 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 TABLE 24-3: Name SUMMARY OF REGISTERS ASSOCIATED WITH I2CTM OPERATION Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: -- -- ANSA4 -- ANSA2 ANSA1 ANSA0 160 -- ANSB5 ANSB4 -- -- -- -- 167 ANSC6(1) -- -- ANSC3 ANSC2 ANSC1 ANSC0 174 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 105 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 106 Bit 7 Bit 6 ANSELA -- ANSELB(1) -- ANSC7(1) ANSELC INTCON PIE1 PIE2 OSFIE C2IE C1IE -- BCL1IE TMR6IE TMR4IE CCP2IE 107 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 111 PIR2 -- BCL1IF TMR6IF TMR4IF CCP2IF OSFIF C2IF C1IF RxyPPS -- -- -- RxyPPS<4:0> SSPCLKPPS -- -- -- SSPCLKPPS<4:0> 182, 180 SSPDATPPS -- -- -- SSPDATPPS<4:0> 182, 180 SSPSSPPS -- -- -- SSPSSPPS<4:0> 182, 180 SSP1ADD SSP1BUF SSP1CON1 112 180 ADD<7:0> 317 Synchronous Serial Port Receive Buffer/Transmit Register 269* WCOL SSPOV SSPEN CKP SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 315 SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 316 SMP CKE D/A P S R/W UA BF 313 -- -- TRISA5 TRISA4 --(2) TRISA2 TRISA1 TRISA0 159 SSP1MSK SSP1STAT TRISA TRISB(1) TRISC Legend: * Note 1: 2: SSPM<3:0> 314 MSK<7:0> 317 TRISB7 TRISB6 TRISB5 TRISB4 -- -- -- -- 166 TRISC7(1) TRISC6(1) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 173 -- = unimplemented location, read as `0'. Shaded cells are not used by the MSSP module in I2CTM mode. Page provides register information. PIC16(L)F1619 only. Unimplemented, read as `1'. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 311 PIC16(L)F1615/9 24.7 BAUD RATE GENERATOR The MSSP module has a Baud Rate Generator available for clock generation in both I2C and SPI Master modes. The Baud Rate Generator (BRG) reload value is placed in the SSPxADD register (Register 24-6). When a write occurs to SSPxBUF, the Baud Rate Generator will automatically begin counting down. Once the given operation is complete, the internal clock will automatically stop counting and the clock pin will remain in its last state. module clock line. The logic dictating when the reload signal is asserted depends on the mode the MSSP is being operated in. Table 24-4 demonstrates clock rates based on instruction cycles and the BRG value loaded into SSPxADD. EQUATION 24-1: FOSC FCLOCK = ------------------------------------------------ SSPxADD + 1 4 An internal signal "Reload" in Figure 24-40 triggers the value from SSPxADD to be loaded into the BRG counter. This occurs twice for each oscillation of the FIGURE 24-40: BAUD RATE GENERATOR BLOCK DIAGRAM SSPM<3:0> SSPM<3:0> Reload SSPxADD<7:0> Reload Control SCL SSPCLK BRG Down Counter FOSC/2 Note: Values of 0x00, 0x01 and 0x02 are not valid for SSPxADD when used as a Baud Rate Generator for I2C. This is an implementation limitation. TABLE 24-4: Note: MSSP CLOCK RATE W/BRG FOSC FCY BRG Value FCLOCK (2 Rollovers of BRG) 32 MHz 8 MHz 13h 400 kHz 32 MHz 8 MHz 19h 308 kHz 32 MHz 8 MHz 4Fh 100 kHz 16 MHz 4 MHz 09h 400 kHz 16 MHz 4 MHz 0Ch 308 kHz 16 MHz 4 MHz 27h 100 kHz 4 MHz 1 MHz 09h 100 kHz Refer to the I/O port electrical specifications in Table 35-4 to ensure the system is designed to support IOL requirements. DS40001770A-page 312 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 24.8 Register Definitions: MSSP Control REGISTER 24-1: SSP1STAT: SSP STATUS REGISTER R/W-0/0 R/W-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 SMP: SPI Data Input Sample bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave mode: SMP must be cleared when SPI is used in Slave mode In I2 C Master or Slave mode: 1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz) 0 = Slew rate control enabled for High-Speed mode (400 kHz) bit 6 CKE: SPI Clock Edge Select bit (SPI mode only) In SPI Master or Slave mode: 1 = Transmit occurs on transition from active to Idle clock state 0 = Transmit occurs on transition from Idle to active clock state In I2 CTM mode only: 1 = Enable input logic so that thresholds are compliant with SMBus specification 0 = Disable SMBus specific inputs bit 5 D/A: Data/Address bit (I2C mode only) 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address bit 4 P: Stop bit (I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.) 1 = Indicates that a Stop bit has been detected last (this bit is `0' on Reset) 0 = Stop bit was not detected last bit 3 S: Start bit (I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.) 1 = Indicates that a Start bit has been detected last (this bit is `0' on Reset) 0 = Start bit was not detected last bit 2 R/W: Read/Write bit information (I2C mode only) This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit, or not ACK bit. In I2 C Slave mode: 1 = Read 0 = Write In I2 C Master mode: 1 = Transmit is in progress 0 = Transmit is not in progress OR-ing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Idle mode. bit 1 UA: Update Address bit (10-bit I2C mode only) 1 = Indicates that the user needs to update the address in the SSP1ADD register 0 = Address does not need to be updated bit 0 BF: Buffer Full Status bit Receive (SPI and I2 C modes): 1 = Receive complete, SSP1BUF is full 0 = Receive not complete, SSP1BUF is empty Transmit (I2 C mode only): 1 = Data transmit in progress (does not include the ACK and Stop bits), SSP1BUF is full 0 = Data transmit complete (does not include the ACK and Stop bits), SSP1BUF is empty 2014 Microchip Technology Inc. Preliminary DS40001770A-page 313 PIC16(L)F1615/9 REGISTER 24-2: SSP1CON1: SSP CONTROL REGISTER 1 R/C/HS-0/0 R/C/HS-0/0 R/W-0/0 R/W-0/0 WCOL SSPOV(1) SSPEN CKP R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 SSPM<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared HS = Bit is set by hardware C = User cleared bit 7 WCOL: Write Collision Detect bit Master mode: 1 = A write to the SSP1BUF register was attempted while the I2C conditions were not valid for a transmission to be started 0 = No collision Slave mode: 1 = The SSP1BUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6 SSPOV: Receive Overflow Indicator bit(1) In SPI mode: 1 = A new byte is received while the SSP1BUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. In Slave mode, the user must read the SSP1BUF, even if only transmitting data, to avoid setting overflow. In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSP1BUF register (must be cleared in software). 0 = No overflow 2 C mode: In I 1 = A byte is received while the SSP1BUF register is still holding the previous byte. SSPOV is a "don't care" in Transmit mode (must be cleared in software). 0 = No overflow bit 5 SSPEN: Synchronous Serial Port Enable bit In both modes, when enabled, these pins must be properly configured as input or output In SPI mode: 1 = Enables serial port and configures SCK, SDO, SDI and SS as the source of the serial port pins(2) 0 = Disables serial port and configures these pins as I/O port pins In I2C mode: 1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins(3) 0 = Disables serial port and configures these pins as I/O port pins bit 4 CKP: Clock Polarity Select bit In SPI mode: 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level In I2C Slave mode: SCL release control 1 = Enable clock 0 = Holds clock low (clock stretch). (Used to ensure data setup time.) In I2C Master mode: Unused in this mode bit 3-0 SSPM<3:0>: Synchronous Serial Port Mode Select bits 1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled 1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled 1101 = Reserved 1100 = Reserved 1011 = I2C firmware controlled Master mode (slave idle) 1010 = SPI Master mode, clock = FOSC/(4 * (SSP1ADD+1))(5) 1001 = Reserved 1000 = I2C Master mode, clock = FOSC / (4 * (SSP1ADD+1))(4) 0111 = I2C Slave mode, 10-bit address 0110 = I2C Slave mode, 7-bit address 0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin 0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled 0011 = SPI Master mode, clock = T2_match/2 0010 = SPI Master mode, clock = FOSC/64 0001 = SPI Master mode, clock = FOSC/16 0000 = SPI Master mode, clock = FOSC/4 Note 1: 2: 3: 4: 5: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSP1BUF register. When enabled, these pins must be properly configured as input or output. Use SSPSSPPS, SSPCLKPPS, SSPDATPPS, and RxyPPS to select the pins. When enabled, the SDA and SCL pins must be configured as inputs. Use SSPCLKPPS, SSPDATPPS, and RxyPPS to select the pins. SSP1ADD values of 0, 1 or 2 are not supported for I2C mode. SSP1ADD value of `0' is not supported. Use SSPM = 0000 instead. DS40001770A-page 314 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 SSP1CON2: SSP CONTROL REGISTER 2(1) REGISTER 24-3: R/W-0/0 R-0/0 R/W-0/0 R/S/HS-0/0 R/S/HS-0/0 R/S/HS-0/0 R/S/HS-0/0 R/W/HS-0/0 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared HC = Cleared by hardware S = User set bit 7 GCEN: General Call Enable bit (in I2C Slave mode only) 1 = Enable interrupt when a general call address (0x00 or 00h) is received in the SSPSR 0 = General call address disabled bit 6 ACKSTAT: Acknowledge Status bit (in I2C mode only) 1 = Acknowledge was not received 0 = Acknowledge was received bit 5 ACKDT: Acknowledge Data bit (in I2C mode only) In Receive mode: Value transmitted when the user initiates an Acknowledge sequence at the end of a receive 1 = Not Acknowledge 0 = Acknowledge bit 4 ACKEN: Acknowledge Sequence Enable bit (in I2C Master mode only) In Master Receive mode: 1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit. Automatically cleared by hardware. 0 = Acknowledge sequence idle bit 3 RCEN: Receive Enable bit (in I2C Master mode only) 1 = Enables Receive mode for I2C 0 = Receive idle bit 2 PEN: Stop Condition Enable bit (in I2C Master mode only) SCKMSSP Release Control: 1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Stop condition Idle bit 1 RSEN: Repeated Start Condition Enable bit (in I2C Master mode only) 1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Repeated Start condition Idle bit 0 SEN: Start Condition Enable/Stretch Enable bit In Master mode: 1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Start condition Idle In Slave mode: 1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled) 0 = Clock stretching is disabled Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, this bit may not be set (no spooling) and the SSP1BUF may not be written (or writes to the SSP1BUF are disabled). 2014 Microchip Technology Inc. Preliminary DS40001770A-page 315 PIC16(L)F1615/9 REGISTER 24-4: SSP1CON3: SSP CONTROL REGISTER 3 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ACKTIM(3) PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 ACKTIM: Acknowledge Time Status bit (I2C mode only)(3) 1 = Indicates the I2C bus is in an Acknowledge sequence, set on eighth falling edge of SCL clock 0 = Not an Acknowledge sequence, cleared on 9th rising edge of SCL clock bit 6 PCIE: Stop Condition Interrupt Enable bit (I2C mode only) 1 = Enable interrupt on detection of Stop condition 0 = Stop detection interrupts are disabled(2) bit 5 SCIE: Start Condition Interrupt Enable bit (I2C mode only) 1 = Enable interrupt on detection of Start or Restart conditions 0 = Start detection interrupts are disabled(2) bit 4 BOEN: Buffer Overwrite Enable bit In SPI Slave mode:(1) 1 = SSP1BUF updates every time that a new data byte is shifted in ignoring the BF bit 0 = If new byte is received with BF bit of the SSP1STAT register already set, SSPOV bit of the SSP1CON1 register is set, and the buffer is not updated In I2C Master mode and SPI Master mode: This bit is ignored. In I2C Slave mode: 1 = SSP1BUF is updated and ACK is generated for a received address/data byte, ignoring the state of the SSPOV bit only if the BF bit = 0. 0 = SSP1BUF is only updated when SSPOV is clear bit 3 SDAHT: SDA Hold Time Selection bit (I2C mode only) 1 = Minimum of 300 ns hold time on SDA after the falling edge of SCL 0 = Minimum of 100 ns hold time on SDA after the falling edge of SCL bit 2 SBCDE: Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only) If, on the rising edge of SCL, SDA is sampled low when the module is outputting a high state, the BCL1IF bit of the PIR2 register is set, and bus goes idle 1 = Enable slave bus collision interrupts 0 = Slave bus collision interrupts are disabled bit 1 AHEN: Address Hold Enable bit (I2C Slave mode only) 1 = Following the eighth falling edge of SCL for a matching received address byte; CKP bit of the SSP1CON1 register will be cleared and the SCL will be held low. 0 = Address holding is disabled bit 0 DHEN: Data Hold Enable bit (I2C Slave mode only) 1 = Following the eighth falling edge of SCL for a received data byte; slave hardware clears the CKP bit of the SSP1CON1 register and SCL is held low. 0 = Data holding is disabled Note 1: 2: 3: For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPOV is still set when a new byte is received and BF = 1, but hardware continues to write the most recent byte to SSP1BUF. This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled. The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is set. DS40001770A-page 316 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 REGISTER 24-5: R/W-1/1 SSP1MSK: SSP MASK REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 MSK<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-1 MSK<7:1>: Mask bits 1 = The received address bit n is compared to SSP1ADD<n> to detect I2C address match 0 = The received address bit n is not used to detect I2C address match bit 0 MSK<0>: Mask bit for I2C Slave mode, 10-bit Address I2C Slave mode, 10-bit address (SSPM<3:0> = 0111 or 1111): 1 = The received address bit 0 is compared to SSP1ADD<0> to detect I2C address match 0 = The received address bit 0 is not used to detect I2C address match I2C Slave mode, 7-bit address, the bit is ignored REGISTER 24-6: R/W-0/0 SSP1ADD: MSSP ADDRESS AND BAUD RATE REGISTER (I2C MODE) R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ADD<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared Master mode: bit 7-0 ADD<7:0>: Baud Rate Clock Divider bits SCL pin clock period = ((ADD<7:0> + 1) *4)/FOSC 10-Bit Slave mode - Most Significant Address Byte: bit 7-3 Not used: Unused for Most Significant Address Byte. Bit state of this register is a "don't care". Bit pattern sent by master is fixed by I2C specification and must be equal to `11110'. However, those bits are compared by hardware and are not affected by the value in this register. bit 2-1 ADD<2:1>: Two Most Significant bits of 10-bit address bit 0 Not used: Unused in this mode. Bit state is a "don't care". 10-Bit Slave mode - Least Significant Address Byte: bit 7-0 ADD<7:0>: Eight Least Significant bits of 10-bit address 7-Bit Slave mode: bit 7-1 ADD<7:1>: 7-bit address bit 0 Not used: Unused in this mode. Bit state is a "don't care". 2014 Microchip Technology Inc. Preliminary DS40001770A-page 317 PIC16(L)F1615/9 25.0 * * * * * * * * * Two-character input buffer One-character output buffer Programmable 8-bit or 9-bit character length Address detection in 9-bit mode Input buffer overrun error detection Received character framing error detection Half-duplex synchronous master Half-duplex synchronous slave Programmable clock polarity in synchronous modes * Sleep operation ENHANCED UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (EUSART) The Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) module is a serial I/O communications peripheral. It contains all the clock generators, shift registers and data buffers necessary to perform an input or output serial data transfer independent of device program execution. The EUSART, also known as a Serial Communications Interface (SCI), can be configured as a full-duplex asynchronous system or half-duplex synchronous system. Full-Duplex mode is useful for communications with peripheral systems, such as CRT terminals and personal computers. Half-Duplex Synchronous mode is intended for communications with peripheral devices, such as A/D or D/A integrated circuits, serial EEPROMs or other microcontrollers. These devices typically do not have internal clocks for baud rate generation and require the external clock signal provided by a master synchronous device. The EUSART module implements the following additional features, making it ideally suited for use in Local Interconnect Network (LIN) bus systems: * Automatic detection and calibration of the baud rate * Wake-up on Break reception * 13-bit Break character transmit Block diagrams of the EUSART transmitter and receiver are shown in Figure 25-1 and Figure 25-2. The EUSART transmit output (TX_out) is available to the TX/CK pin and internally to the following peripherals: The EUSART module includes the following capabilities: * Configurable Logic Cell (CLC) * Data signal modulator (DSM) * Full-duplex asynchronous transmit and receive FIGURE 25-1: EUSART TRANSMIT BLOCK DIAGRAM Data Bus SYNC CSRC 8 TXEN LSb (8) 0 * * * CKPPS TRMT Multiplier SYNC TX9 x4 x16 x64 1 X 0 0 TX9D TX/CK pin 0 BRGH X 1 1 0 0 BRG16 X 1 0 1 0 0 PPS 1 RxyPPS In Synchronous mode the DT output and RX input PPS selections should enable the same pin. DS40001770A-page 318 TX_out /n n BRG16 SPxBRGH SPxBRGL RX/DT pin PPS SYNC FOSC +1 Pin Buffer and Control Transmit Shift Register (TSR) 0 Note 1: RxyPPS(1) MSb 1 Baud Rate Generator Interrupt TXIF TXxREG Register CK pin PPS TXIE Preliminary SYNC CSRC 2014 Microchip Technology Inc. PIC16(L)F1615/9 FIGURE 25-2: EUSART RECEIVE BLOCK DIAGRAM SPEN RX/DT pin CREN RXPPS(1) RSR Register MSb Pin Buffer and Control PPS Baud Rate Generator Data Recovery FOSC +1 SPxBRGH SPxBRGL Multiplier x4 x16 x64 SYNC 1 X 0 0 0 BRGH X 1 1 0 0 BRG16 X 1 0 1 0 Stop (8) *** 7 1 LSb 0 Start RX9 /n BRG16 n FERR RX9D RCxREG Register 8 Note 1: RCIDL OERR In Synchronous mode the DT output and RX input PPS selections should enable the same pin. FIFO Data Bus RCIF RCIE Interrupt The operation of the EUSART module is controlled through three registers: * Transmit Status and Control (TXxSTA) * Receive Status and Control (RCxSTA) * Baud Rate Control (BAUDxCON) These registers are detailed in Register 25-1, Register 25-2 and Register 25-3, respectively. The RX and CK input pins are selected with the RXPPS and CKPPS registers, respectively. TX, CK, and DT output pins are selected with each pin's RxyPPS register. Since the RX input is coupled with the DT output in Synchronous mode, it is the user's responsibility to select the same pin for both of these functions when operating in Synchronous mode. The EUSART control logic will control the data direction drivers automatically. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 319 PIC16(L)F1615/9 25.1 25.1.1.2 EUSART Asynchronous Mode The EUSART transmits and receives data using the standard non-return-to-zero (NRZ) format. NRZ is implemented with two levels: a VOH Mark state which represents a `1' data bit, and a VOL Space state which represents a `0' data bit. NRZ refers to the fact that consecutively transmitted data bits of the same value stay at the output level of that bit without returning to a neutral level between each bit transmission. An NRZ transmission port idles in the Mark state. Each character transmission consists of one Start bit followed by eight or nine data bits and is always terminated by one or more Stop bits. The Start bit is always a space and the Stop bits are always marks. The most common data format is eight bits. Each transmitted bit persists for a period of 1/(Baud Rate). An on-chip dedicated 8-bit/16bit Baud Rate Generator is used to derive standard baud rate frequencies from the system oscillator. See Table 25-5 for examples of baud rate configurations. The EUSART transmits and receives the LSb first. The EUSART's transmitter and receiver are functionally independent, but share the same data format and baud rate. Parity is not supported by the hardware, but can be implemented in software and stored as the ninth data bit. 25.1.1 EUSART ASYNCHRONOUS TRANSMITTER 25.1.1.1 Enabling the Transmitter The EUSART transmitter is enabled for asynchronous operations by configuring the following three control bits: * TXEN = 1 * SYNC = 0 * SPEN = 1 All other EUSART control bits are assumed to be in their default state. Setting the TXEN bit of the TXxSTA register enables the transmitter circuitry of the EUSART. Clearing the SYNC bit of the TXxSTA register configures the EUSART for asynchronous operation. Setting the SPEN bit of the RCxSTA register enables the EUSART and automatically configures the TX/CK I/O pin as an output. If the TX/CK pin is shared with an analog peripheral, the analog I/O function must be disabled by clearing the corresponding ANSEL bit. Note: A transmission is initiated by writing a character to the TXxREG register. If this is the first character, or the previous character has been completely flushed from the TSR, the data in the TXxREG is immediately transferred to the TSR register. If the TSR still contains all or part of a previous character, the new character data is held in the TXxREG until the Stop bit of the previous character has been transmitted. The pending character in the TXxREG is then transferred to the TSR in one TCY immediately following the Stop bit transmission. The transmission of the Start bit, data bits and Stop bit sequence commences immediately following the transfer of the data to the TSR from the TXxREG. 25.1.1.3 Transmit Data Polarity The polarity of the transmit data can be controlled with the SCKP bit of the BAUDxCON register. The default state of this bit is `0' which selects high true transmit idle and data bits. Setting the SCKP bit to `1' will invert the transmit data resulting in low true idle and data bits. The SCKP bit controls transmit data polarity in Asynchronous mode only. In Synchronous mode, the SCKP bit has a different function. See Section 25.5.1.2 "Clock Polarity". 25.1.1.4 The EUSART transmitter block diagram is shown in Figure 25-1. The heart of the transmitter is the serial Transmit Shift Register (TSR), which is not directly accessible by software. The TSR obtains its data from the transmit buffer, which is the TXxREG register. Transmitting Data Transmit Interrupt Flag The TXIF interrupt flag bit of the PIR1 register is set whenever the EUSART transmitter is enabled and no character is being held for transmission in the TXxREG. In other words, the TXIF bit is only clear when the TSR is busy with a character and a new character has been queued for transmission in the TXxREG. The TXIF flag bit is not cleared immediately upon writing TXxREG. TXIF becomes valid in the second instruction cycle following the write execution. Polling TXIF immediately following the TXxREG write will return invalid results. The TXIF bit is read-only, it cannot be set or cleared by software. The TXIF interrupt can be enabled by setting the TXIE interrupt enable bit of the PIE1 register. However, the TXIF flag bit will be set whenever the TXxREG is empty, regardless of the state of TXIE enable bit. To use interrupts when transmitting data, set the TXIE bit only when there is more data to send. Clear the TXIE interrupt enable bit upon writing the last character of the transmission to the TXxREG. The TXIF Transmitter Interrupt flag is set when the TXEN enable bit is set. DS40001770A-page 320 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 25.1.1.5 TSR Status 25.1.1.7 The TRMT bit of the TXxSTA register indicates the status of the TSR register. This is a read-only bit. The TRMT bit is set when the TSR register is empty and is cleared when a character is transferred to the TSR register from the TXxREG. The TRMT bit remains clear until all bits have been shifted out of the TSR register. No interrupt logic is tied to this bit, so the user has to poll this bit to determine the TSR status. Note: 25.1.1.6 1. 2. 3. The TSR register is not mapped in data memory, so it is not available to the user. Transmitting 9-Bit Characters The EUSART supports 9-bit character transmissions. When the TX9 bit of the TXxSTA register is set, the EUSART will shift nine bits out for each character transmitted. The TX9D bit of the TXxSTA register is the ninth, and Most Significant data bit. When transmitting 9-bit data, the TX9D data bit must be written before writing the eight Least Significant bits into the TXxREG. All nine bits of data will be transferred to the TSR shift register immediately after the TXxREG is written. A special 9-bit Address mode is available for use with multiple receivers. See Section 25.1.2.7 "Address Detection" for more information on the Address mode. FIGURE 25-3: Write to TXxREG BRG Output (Shift Clock) 7. 8. Word 1 Start bit bit 0 bit 1 bit 7/8 Stop bit Word 1 TXIF bit (Transmit Buffer Reg. Empty Flag) FIGURE 25-4: 6. Initialize the SPxBRGH, SPxBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 25.4 "EUSART Baud Rate Generator (BRG)"). Enable the asynchronous serial port by clearing the SYNC bit and setting the SPEN bit. If 9-bit transmission is desired, set the TX9 control bit. A set ninth data bit will indicate that the eight Least Significant data bits are an address when the receiver is set for address detection. Set SCKP bit if inverted transmit is desired. Enable the transmission by setting the TXEN control bit. This will cause the TXIF interrupt bit to be set. If interrupts are desired, set the TXIE interrupt enable bit of the PIE1 register. An interrupt will occur immediately provided that the GIE and PEIE bits of the INTCON register are also set. If 9-bit transmission is selected, the ninth bit should be loaded into the TX9D data bit. Load 8-bit data into the TXxREG register. This will start the transmission. ASYNCHRONOUS TRANSMISSION TX/CK pin TRMT bit (Transmit Shift Reg. Empty Flag) 4. 5. Asynchronous Transmission Set-up: 1 TCY Word 1 Transmit Shift Reg. ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK) Write to TXxREG BRG Output (Shift Clock) Word 1 TX/CK pin TXIF bit (Transmit Buffer Reg. Empty Flag) TRMT bit (Transmit Shift Reg. Empty Flag) Note: Word 2 Start bit bit 0 1 TCY bit 1 Word 1 bit 7/8 Stop bit Start bit Word 2 bit 0 1 TCY Word 1 Transmit Shift Reg. Word 2 Transmit Shift Reg. This timing diagram shows two consecutive transmissions. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 321 PIC16(L)F1615/9 TABLE 25-1: Name ANSELA (1) SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page -- -- -- ANSA4 -- ANSA2 ANSA1 ANSA0 160 167 ANSELB -- -- ANSB5 ANSB4 -- -- -- -- ANSELC ANSC7(1) ANSC6(1) -- -- ANSC3 ANSC2 ANSC1 ANSC0 174 BAUD1CON ABDOVF RCIDL -- SCKP BRG16 -- WUE ABDEN 330 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 105 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 106 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 111 RC1STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D RxyPPS -- -- -- INTCON SP1BRGL TRISB(1) TRISC TX1REG TX1STA Legend: * Note 1: 2: 331* BRG<15:8> -- -- TRISA5 TRISA4 329 180 BRG<7:0> SP1BRGH TRISA RxyPPS<4:0> --(2) 331* TRISA2 TRISA1 TRISA0 159 TRISB7 TRISB6 TRISB5 TRISB4 -- -- -- -- 166 TRISC7(1) TRISC6(1) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 173 SYNC SENDB BRGH TRMT TX9D EUSART Transmit Data Register CSRC TX9 TXEN 320* 328 -- = unimplemented location, read as `0'. Shaded cells are not used for asynchronous transmission. Page provides register information. PIC16(L)F1619 only. Unimplemented, read as `1'. DS40001770A-page 322 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 25.1.2 EUSART ASYNCHRONOUS RECEIVER 25.1.2.2 The Asynchronous mode is typically used in RS-232 systems. The receiver block diagram is shown in Figure 25-2. The data is received on the RX/DT pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at 16 times the baud rate, whereas the serial Receive Shift Register (RSR) operates at the bit rate. When all eight or nine bits of the character have been shifted in, they are immediately transferred to a two character First-InFirst-Out (FIFO) memory. The FIFO buffering allows reception of two complete characters and the start of a third character before software must start servicing the EUSART receiver. The FIFO and RSR registers are not directly accessible by software. Access to the received data is via the RCxREG register. 25.1.2.1 Enabling the Receiver The EUSART receiver is enabled for asynchronous operation by configuring the following three control bits: * CREN = 1 * SYNC = 0 * SPEN = 1 All other EUSART control bits are assumed to be in their default state. Setting the CREN bit of the RCxSTA register enables the receiver circuitry of the EUSART. Clearing the SYNC bit of the TXxSTA register configures the EUSART for asynchronous operation. Setting the SPEN bit of the RCxSTA register enables the EUSART. The programmer must set the corresponding TRIS bit to configure the RX/DT I/O pin as an input. Note: If the RX/DT function is on an analog pin, the corresponding ANSEL bit must be cleared for the receiver to function. Receiving Data The receiver data recovery circuit initiates character reception on the falling edge of the first bit. The first bit, also known as the Start bit, is always a zero. The data recovery circuit counts one-half bit time to the center of the Start bit and verifies that the bit is still a zero. If it is not a zero then the data recovery circuit aborts character reception, without generating an error, and resumes looking for the falling edge of the Start bit. If the Start bit zero verification succeeds then the data recovery circuit counts a full bit time to the center of the next bit. The bit is then sampled by a majority detect circuit and the resulting `0' or `1' is shifted into the RSR. This repeats until all data bits have been sampled and shifted into the RSR. One final bit time is measured and the level sampled. This is the Stop bit, which is always a `1'. If the data recovery circuit samples a `0' in the Stop bit position then a framing error is set for this character, otherwise the framing error is cleared for this character. See Section 25.1.2.4 "Receive Framing Error" for more information on framing errors. Immediately after all data bits and the Stop bit have been received, the character in the RSR is transferred to the EUSART receive FIFO and the RCIF interrupt flag bit of the PIR1 register is set. The top character in the FIFO is transferred out of the FIFO by reading the RCxREG register. Note: 25.1.2.3 If the receive FIFO is overrun, no additional characters will be received until the overrun condition is cleared. See Section 25.1.2.5 "Receive Overrun Error" for more information on overrun errors. Receive Interrupts The RCIF interrupt flag bit of the PIR1 register is set whenever the EUSART receiver is enabled and there is an unread character in the receive FIFO. The RCIF interrupt flag bit is read-only, it cannot be set or cleared by software. RCIF interrupts are enabled by setting all of the following bits: * RCIE, Interrupt Enable bit of the PIE1 register * PEIE, Peripheral Interrupt Enable bit of the INTCON register * GIE, Global Interrupt Enable bit of the INTCON register The RCIF interrupt flag bit will be set when there is an unread character in the FIFO, regardless of the state of interrupt enable bits. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 323 PIC16(L)F1615/9 25.1.2.4 Receive Framing Error 25.1.2.7 Each character in the receive FIFO buffer has a corresponding framing error Status bit. A framing error indicates that a Stop bit was not seen at the expected time. The framing error status is accessed via the FERR bit of the RCxSTA register. The FERR bit represents the status of the top unread character in the receive FIFO. Therefore, the FERR bit must be read before reading the RCxREG. The FERR bit is read-only and only applies to the top unread character in the receive FIFO. A framing error (FERR = 1) does not preclude reception of additional characters. It is not necessary to clear the FERR bit. Reading the next character from the FIFO buffer will advance the FIFO to the next character and the next corresponding framing error. The FERR bit can be forced clear by clearing the SPEN bit of the RCxSTA register which resets the EUSART. Clearing the CREN bit of the RCxSTA register does not affect the FERR bit. A framing error by itself does not generate an interrupt. Note: 25.1.2.5 Address Detection A special Address Detection mode is available for use when multiple receivers share the same transmission line, such as in RS-485 systems. Address detection is enabled by setting the ADDEN bit of the RCxSTA register. Address detection requires 9-bit character reception. When address detection is enabled, only characters with the ninth data bit set will be transferred to the receive FIFO buffer, thereby setting the RCIF interrupt bit. All other characters will be ignored. Upon receiving an address character, user software determines if the address matches its own. Upon address match, user software must disable address detection by clearing the ADDEN bit before the next Stop bit occurs. When user software detects the end of the message, determined by the message protocol used, software places the receiver back into the Address Detection mode by setting the ADDEN bit. If all receive characters in the receive FIFO have framing errors, repeated reads of the RCxREG will not clear the FERR bit. Receive Overrun Error The receive FIFO buffer can hold two characters. An overrun error will be generated if a third character, in its entirety, is received before the FIFO is accessed. When this happens the OERR bit of the RCxSTA register is set. The characters already in the FIFO buffer can be read but no additional characters will be received until the error is cleared. The error must be cleared by either clearing the CREN bit of the RCxSTA register or by resetting the EUSART by clearing the SPEN bit of the RCxSTA register. 25.1.2.6 Receiving 9-Bit Characters The EUSART supports 9-bit character reception. When the RX9 bit of the RCxSTA register is set, the EUSART will shift nine bits into the RSR for each character received. The RX9D bit of the RCxSTA register is the ninth and Most Significant data bit of the top unread character in the receive FIFO. When reading 9-bit data from the receive FIFO buffer, the RX9D data bit must be read before reading the eight Least Significant bits from the RCxREG. DS40001770A-page 324 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 25.1.2.8 Asynchronous Reception Set-up 25.1.2.9 1. Initialize the SPxBRGH, SPxBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 25.4 "EUSART Baud Rate Generator (BRG)"). 2. Clear the ANSEL bit for the RX pin (if applicable). 3. Enable the serial port by setting the SPEN bit. The SYNC bit must be clear for asynchronous operation. 4. If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. 5. If 9-bit reception is desired, set the RX9 bit. 6. Enable reception by setting the CREN bit. 7. The RCIF interrupt flag bit will be set when a character is transferred from the RSR to the receive buffer. An interrupt will be generated if the RCIE interrupt enable bit was also set. 8. Read the RCxSTA register to get the error flags and, if 9-bit data reception is enabled, the ninth data bit. 9. Get the received eight Least Significant data bits from the receive buffer by reading the RCxREG register. 10. If an overrun occurred, clear the OERR flag by clearing the CREN receiver enable bit. FIGURE 25-5: This mode would typically be used in RS-485 systems. To set up an Asynchronous Reception with Address Detect Enable: 1. Initialize the SPxBRGH, SPxBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 25.4 "EUSART Baud Rate Generator (BRG)"). 2. Clear the ANSEL bit for the RX pin (if applicable). 3. Enable the serial port by setting the SPEN bit. The SYNC bit must be clear for asynchronous operation. 4. If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. 5. Enable 9-bit reception by setting the RX9 bit. 6. Enable address detection by setting the ADDEN bit. 7. Enable reception by setting the CREN bit. 8. The RCIF interrupt flag bit will be set when a character with the ninth bit set is transferred from the RSR to the receive buffer. An interrupt will be generated if the RCIE interrupt enable bit was also set. 9. Read the RCxSTA register to get the error flags. The ninth data bit will always be set. 10. Get the received eight Least Significant data bits from the receive buffer by reading the RCxREG register. Software determines if this is the device's address. 11. If an overrun occurred, clear the OERR flag by clearing the CREN receiver enable bit. 12. If the device has been addressed, clear the ADDEN bit to allow all received data into the receive buffer and generate interrupts. ASYNCHRONOUS RECEPTION Start bit bit 0 RX/DT pin 9-bit Address Detection Mode Set-up Rcv Shift Reg Rcv Buffer Reg. RCIDL bit 1 bit 7/8 Stop bit Start bit bit 0 Word 1 RCxREG bit 7/8 Stop bit Start bit bit 7/8 Stop bit Word 2 RCxREG Read Rcv Buffer Reg. RCxREG RCIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RX input. The RCxREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 325 PIC16(L)F1615/9 TABLE 25-2: Name ANSELA (1) SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page -- -- -- ANSA4 -- ANSA2 ANSA1 ANSA0 160 167 ANSELB -- -- ANSB5 ANSB4 -- -- -- -- ANSELC ANSC7(1) ANSC6(1) -- -- ANSC3 ANSC2 ANSC1 ANSC0 174 BAUD1CON ABDOVF RCIDL -- SCKP BRG16 -- WUE ABDEN 330 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 105 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 105 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 111 RC1STA SPEN RX9 SREN OERR RX9D RxyPPS -- -- -- INTCON RC1REG EUSART Receive Data Register CREN ADDEN 323* FERR RxyPPS<4:0> 329 180 SP1BRGL BRG<7:0> 331 SP1BRGH BRG<15:8> 331 TRISA TRISB(1) TRISC TX1STA Legend: * Note 1: 2: -- -- TRISA5 TRISA4 --(2) TRISA2 TRISA1 TRISA0 159 TRISB7 TRISB6 TRISB5 TRISB4 -- -- -- -- 166 TRISC7(1) TRISC6(1) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 173 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 328 -- = unimplemented location, read as `0'. Shaded cells are not used for asynchronous reception. Page provides register information. PIC16(L)F1619 only. Unimplemented, read as `1'. DS40001770A-page 326 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 25.2 Clock Accuracy with Asynchronous Operation The factory calibrates the internal oscillator block output (INTOSC). However, the INTOSC frequency may drift as VDD or temperature changes, and this directly affects the asynchronous baud rate. Two methods may be used to adjust the baud rate clock, but both require a reference clock source of some kind. The first (preferred) method uses the OSCTUNE register to adjust the INTOSC output. Adjusting the value in the OSCTUNE register allows for fine resolution changes to the system clock source. See Section 5.2.2.3 "Internal Oscillator Frequency Adjustment" for more information. The other method adjusts the value in the Baud Rate Generator. This can be done automatically with the Auto-Baud Detect feature (see Section 25.4.1 "AutoBaud Detect"). There may not be fine enough resolution when adjusting the Baud Rate Generator to compensate for a gradual change in the peripheral clock frequency. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 327 PIC16(L)F1615/9 25.3 Register Definitions: EUSART Control REGISTER 25-1: R/W-/0 CSRC TX1STA: TRANSMIT STATUS AND CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-1/1 R/W-0/0 TX9 TXEN(1) SYNC SENDB BRGH TRMT TX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don't care Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) bit 6 TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission bit 5 TXEN: Transmit Enable bit(1) 1 = Transmit enabled 0 = Transmit disabled bit 4 SYNC: EUSART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode bit 3 SENDB: Send Break Character bit Asynchronous mode: 1 = Send Sync Break on next transmission (cleared by hardware upon completion) 0 = Sync Break transmission completed Synchronous mode: Don't care bit 2 BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode bit 1 TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full bit 0 TX9D: Ninth bit of Transmit Data Can be address/data bit or a parity bit. Note 1: SREN/CREN overrides TXEN in Sync mode. DS40001770A-page 328 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 REGISTER 25-2: RC1STA: RECEIVE STATUS AND CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0 R-0/0 R-0/0 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled 0 = Serial port disabled (held in Reset) bit 6 RX9: 9-Bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode: Don't care Synchronous mode - Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode - Slave Don't care bit 4 CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables receiver 0 = Disables receiver Synchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive bit 3 ADDEN: Address Detect Enable bit Asynchronous mode 9-bit (RX9 = 1): 1 = Enables address detection, enable interrupt and load the receive buffer when RSR<8> is set 0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit Asynchronous mode 8-bit (RX9 = 0): Don't care bit 2 FERR: Framing Error bit 1 = Framing error (can be updated by reading RCxREG register and receive next valid byte) 0 = No framing error bit 1 OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN) 0 = No overrun error bit 0 RX9D: Ninth bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 329 PIC16(L)F1615/9 REGISTER 25-3: BAUD1CON: BAUD RATE CONTROL REGISTER R-0/0 R-1/1 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 ABDOVF RCIDL -- SCKP BRG16 -- WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 ABDOVF: Auto-Baud Detect Overflow bit Asynchronous mode: 1 = Auto-baud timer overflowed 0 = Auto-baud timer did not overflow Synchronous mode: Don't care bit 6 RCIDL: Receive Idle Flag bit Asynchronous mode: 1 = Receiver is Idle 0 = Start bit has been received and the receiver is receiving Synchronous mode: Don't care bit 5 Unimplemented: Read as `0' bit 4 SCKP: Synchronous Clock Polarity Select bit Asynchronous mode: 1 = Transmit inverted data to the TX/CK pin 0 = Transmit non-inverted data to the TX/CK pin Synchronous mode: 1 = Data is clocked on rising edge of the clock 0 = Data is clocked on falling edge of the clock bit 3 BRG16: 16-bit Baud Rate Generator bit 1 = 16-bit Baud Rate Generator is used 0 = 8-bit Baud Rate Generator is used bit 2 Unimplemented: Read as `0' bit 1 WUE: Wake-up Enable bit Asynchronous mode: 1 = Receiver is waiting for a falling edge. No character will be received, byte RCIF will be set. WUE will automatically clear after RCIF is set. 0 = Receiver is operating normally Synchronous mode: Don't care bit 0 ABDEN: Auto-Baud Detect Enable bit Asynchronous mode: 1 = Auto-Baud Detect mode is enabled (clears when auto-baud is complete) 0 = Auto-Baud Detect mode is disabled Synchronous mode: Don't care DS40001770A-page 330 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 25.4 EUSART Baud Rate Generator (BRG) EXAMPLE 25-1: The Baud Rate Generator (BRG) is an 8-bit or 16-bit timer that is dedicated to the support of both the asynchronous and synchronous EUSART operation. By default, the BRG operates in 8-bit mode. Setting the BRG16 bit of the BAUDxCON register selects 16-bit mode. For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG: F OS C Desired Baud Rate = -----------------------------------------------------------------------64 [SPBRGH:SPBRGL] + 1 Solving for SPxBRGH:SPxBRGL: FOSC --------------------------------------------Desired Baud Rate X = --------------------------------------------- - 1 64 The SPxBRGH, SPxBRGL register pair determines the period of the free running baud rate timer. In Asynchronous mode the multiplier of the baud rate period is determined by both the BRGH bit of the TXxSTA register and the BRG16 bit of the BAUDxCON register. In Synchronous mode, the BRGH bit is ignored. Table 25-3 contains the formulas for determining the baud rate. Example 25-1 provides a sample calculation for determining the baud rate and baud rate error. CALCULATING BAUD RATE ERROR 16000000 -----------------------9600 = ------------------------ - 1 64 = 25.042 = 25 16000000 Calculated Baud Rate = --------------------------64 25 + 1 Typical baud rates and error values for various Asynchronous modes have been computed for your convenience and are shown in Table 25-5. It may be advantageous to use the high baud rate (BRGH = 1), or the 16-bit BRG (BRG16 = 1) to reduce the baud rate error. The 16-bit BRG mode is used to achieve slow baud rates for fast oscillator frequencies. = 9615 Calc. Baud Rate - Desired Baud Rate Error = -------------------------------------------------------------------------------------------Desired Baud Rate 9615 - 9600 = ---------------------------------- = 0.16% 9600 Writing a new value to the SPxBRGH, SPxBRGL register pair causes the BRG timer to be reset (or cleared). This ensures that the BRG does not wait for a timer overflow before outputting the new baud rate. If the system clock is changed during an active receive operation, a receive error or data loss may result. To avoid this problem, check the status of the RCIDL bit to make sure that the receive operation is idle before changing the system clock. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 331 PIC16(L)F1615/9 TABLE 25-3: BAUD RATE FORMULAS Configuration Bits BRG/EUSART Mode Baud Rate Formula 8-bit/Asynchronous FOSC/[64 (n+1)] SYNC BRG16 BRGH 0 0 0 0 0 1 8-bit/Asynchronous 0 1 0 16-bit/Asynchronous 0 1 1 16-bit/Asynchronous 1 0 x 8-bit/Synchronous 1 x 16-bit/Synchronous 1 Legend: FOSC/[16 (n+1)] FOSC/[4 (n+1)] x = Don't care, n = value of SPxBRGH, SPxBRGL register pair. TABLE 25-4: Name SUMMARY OF REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR Bit 7 BAUD1CON ABDOVF RC1STA SPEN Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page RCIDL -- SCKP BRG16 -- WUE ABDEN 330 RX9 SREN CREN ADDEN FERR OERR RX9D 329 SP1BRGL BRG<7:0> 331 SP1BRGH BRG<15:8> 331 TX1STA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 328 Legend: -- = unimplemented location, read as `0'. Shaded cells are not used for the Baud Rate Generator. * Page provides register information. DS40001770A-page 332 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 TABLE 25-5: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 16.000 MHz FOSC = 11.0592 MHz Actual Rate % Error SPBRG value (decimal) 300 1200 -- 1221 -- 1.73 -- 255 -- 1200 -- 0.00 -- 239 -- 1202 -- 0.16 -- 207 -- 1200 -- 0.00 -- 143 2400 2404 0.16 129 2400 0.00 119 2404 0.16 103 2400 0.00 71 9600 9470 -1.36 32 9600 0.00 29 9615 0.16 25 9600 0.00 17 10417 10417 0.00 29 10286 -1.26 27 10417 0.00 23 10165 -2.42 16 19.2k 19.53k 1.73 15 19.20k 0.00 14 19.23k 0.16 12 19.20k 0.00 8 57.6k -- -- -- -- -- -- 57.60k -- 0.00 7 -- -- -- -- -- -- 57.60k -- 0.00 2 -- -- -- 115.2k Actual Rate % Error SPBRG value (decimal) Actual Rate -- % Error SPBRG value (decimal) Actual Rate % Error SPBRG value (decimal) SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz Actual Rate % Error SPBRG value (decimal) 300 1200 -- 1202 -- 0.16 -- 103 300 1202 0.16 0.16 207 51 300 1200 0.00 191 47 300 1202 0.16 0.16 51 12 2400 2404 0.16 51 2404 0.16 25 2400 0.00 23 -- -- -- 9600 9615 0.16 12 -- -- -- 9600 0.00 5 -- -- -- 10417 10417 0.00 11 10417 0.00 5 -- -- -- -- -- -- 19.2k -- -- -- -- -- -- 19.20k 0.00 2 -- -- -- 57.6k -- -- -- -- -- -- 57.60k 0.00 0 -- -- -- 115.2k -- -- -- -- -- -- -- -- -- -- -- -- Actual Rate % Error SPBRG value (decimal) Actual Rate % Error 0.00 SPBRG value (decimal) Actual Rate % Error SPBRG value (decimal) SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE FOSC = 20.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 18.432 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 16.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 11.0592 MHz Actual Rate % Error SPBRG value (decimal) 300 -- -- -- -- -- -- -- -- -- -- -- -- 1200 -- -- -- -- -- -- -- -- -- -- -- -- 2400 -- -- -- -- -- -- -- -- -- -- -- -- 9600 9615 0.16 129 9600 0.00 119 9615 0.16 103 9600 0.00 71 10417 10417 0.00 119 10378 -0.37 110 10417 0.00 95 10473 0.53 65 19.2k 19.23k 0.16 64 19.20k 0.00 59 19.23k 0.16 51 19.20k 0.00 35 57.6k 56.82k -1.36 21 57.60k 0.00 19 58.82k 2.12 16 57.60k 0.00 11 115.2k 113.64k -1.36 10 115.2k 0.00 9 111.1k -3.55 8 115.2k 0.00 5 2014 Microchip Technology Inc. Preliminary DS40001770A-page 333 PIC16(L)F1615/9 TABLE 25-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE FOSC = 8.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 4.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 3.6864 MHz Actual Rate % Error FOSC = 1.000 MHz SPBRG value (decimal) Actual Rate % Error SPBRG value (decimal) 207 300 -- -- -- -- -- -- -- -- -- 300 0.16 1200 -- -- -- 1202 0.16 207 1200 0.00 191 1202 0.16 51 2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25 9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 -- -- -- 10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5 19.2k 19231 0.16 25 19.23k 0.16 12 19.2k 0.00 11 -- -- -- 57.6k 55556 -3.55 8 -- -- -- 57.60k 0.00 3 -- -- -- 115.2k -- -- -- -- -- -- 115.2k 0.00 1 -- -- -- SYNC = 0, BRGH = 0, BRG16 = 1 BAUD RATE FOSC = 20.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 18.432 MHz Actual Rate FOSC = 16.000 MHz % Error SPBRG value (decimal) Actual Rate FOSC = 11.0592 MHz % Error SPBRG value (decimal) Actual Rate % Error SPBRG value (decimal) 2303 300 300.0 -0.01 4166 300.0 0.00 3839 300.03 0.01 3332 300.0 0.00 1200 1200 -0.03 1041 1200 0.00 959 1200.5 0.04 832 1200 0.00 575 2400 2399 -0.03 520 2400 0.00 479 2398 -0.08 416 2400 0.00 287 71 9600 9615 0.16 129 9600 0.00 119 9615 0.16 103 9600 0.00 10417 10417 0.00 119 10378 -0.37 110 10417 0.00 95 10473 0.53 65 19.2k 19.23k 0.16 64 19.20k 0.00 59 19.23k 0.16 51 19.20k 0.00 35 57.6k 56.818 -1.36 21 57.60k 0.00 19 58.82k 2.12 16 57.60k 0.00 11 115.2k 113.636 -1.36 10 115.2k 0.00 9 111.11k -3.55 8 115.2k 0.00 5 SYNC = 0, BRGH = 0, BRG16 = 1 BAUD RATE FOSC = 8.000 MHz SPBRG Actual % value Rate Error (decimal) FOSC = 4.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 3.6864 MHz Actual Rate FOSC = 1.000 MHz % Error SPBRG value (decimal) Actual Rate % Error SPBRG value (decimal) 300 1200 299.9 1199 -0.02 -0.08 1666 416 300.1 1202 0.04 0.16 832 207 300.0 1200 0.00 0.00 767 191 300.5 1202 0.16 0.16 207 51 2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25 -- 9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 -- -- 10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5 19.2k 19.23k 0.16 25 19.23k 0.16 12 19.20k 0.00 11 -- -- -- 57.6k 55556 -3.55 8 -- -- -- 57.60k 0.00 3 -- -- -- 115.2k -- -- -- -- -- -- 115.2k 0.00 1 -- -- -- DS40001770A-page 334 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 TABLE 25-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD RATE FOSC = 20.000 MHz Actual Rate FOSC = 18.432 MHz % Error SPBRG value (decimal) Actual Rate % Error SPBRG value (decimal) FOSC = 16.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 11.0592 MHz Actual Rate % Error SPBRG value (decimal) 300 300.0 0.00 16665 300.0 0.00 15359 300.0 0.00 13332 300.0 0.00 9215 1200 1200 -0.01 4166 1200 0.00 3839 1200.1 0.01 3332 1200 0.00 2303 2400 2400 0.02 2082 2400 0.00 1919 2399.5 -0.02 1666 2400 0.00 1151 9600 9597 -0.03 520 9600 0.00 479 9592 -0.08 416 9600 0.00 287 10417 10417 0.00 479 10425 0.08 441 10417 0.00 383 10433 0.16 264 19.2k 19.23k 0.16 259 19.20k 0.00 239 19.23k 0.16 207 19.20k 0.00 143 57.6k 57.47k -0.22 86 57.60k 0.00 79 57.97k 0.64 68 57.60k 0.00 47 115.2k 116.3k 0.94 42 115.2k 0.00 39 114.29k -0.79 34 115.2k 0.00 23 BAUD RATE FOSC = 8.000 MHz SPBRG Actual % value Rate Error (decimal) SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 FOSC = 4.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 3.6864 MHz Actual Rate FOSC = 1.000 MHz % Error SPBRG value (decimal) Actual Rate % Error SPBRG value (decimal) 300 1200 300.0 1200 0.00 -0.02 6666 1666 300.0 1200 0.01 0.04 3332 832 300.0 1200 0.00 0.00 3071 767 300.1 1202 0.04 0.16 832 207 2400 2401 0.04 832 2398 0.08 416 2400 0.00 383 2404 0.16 103 9600 9615 0.16 207 9615 0.16 103 9600 0.00 95 9615 0.16 25 10417 10417 0 191 10417 0.00 95 10473 0.53 87 10417 0.00 23 19.2k 19.23k 0.16 103 19.23k 0.16 51 19.20k 0.00 47 19.23k 0.16 12 57.6k 57.14k -0.79 34 58.82k 2.12 16 57.60k 0.00 15 -- -- -- 115.2k 117.6k 2.12 16 111.1k -3.55 8 115.2k 0.00 7 -- -- -- 2014 Microchip Technology Inc. Preliminary DS40001770A-page 335 PIC16(L)F1615/9 25.4.1 AUTO-BAUD DETECT The EUSART module supports automatic detection and calibration of the baud rate. In the Auto-Baud Detect (ABD) mode, the clock to the BRG is reversed. Rather than the BRG clocking the incoming RX signal, the RX signal is timing the BRG. The Baud Rate Generator is used to time the period of a received 55h (ASCII "U") which is the Sync character for the LIN bus. The unique feature of this character is that it has five rising edges including the Stop bit edge. Setting the ABDEN bit of the BAUDxCON register starts the auto-baud calibration sequence. While the ABD sequence takes place, the EUSART state machine is held in Idle. On the first rising edge of the receive line, after the Start bit, the SPxBRG begins counting up using the BRG counter clock as shown in Figure 25-6. The fifth rising edge will occur on the RX pin at the end of the eighth bit period. At that time, an accumulated value totaling the proper BRG period is left in the SPxBRGH, SPxBRGL register pair, the ABDEN bit is automatically cleared and the RCIF interrupt flag is set. The value in the RCxREG needs to be read to clear the RCIF interrupt. RCxREG content should be discarded. When calibrating for modes that do not use the SPxBRGH register the user can verify that the SPxBRGL register did not overflow by checking for 00h in the SPxBRGH register. TABLE 25-6: BRGH BRG Base Clock BRG ABD Clock 0 0 FOSC/64 FOSC/512 0 1 FOSC/16 FOSC/128 1 0 FOSC/16 FOSC/128 1 FOSC/4 FOSC/32 1 Note 1: If the WUE bit is set with the ABDEN bit, auto-baud detection will occur on the byte following the Break character (see Section 25.4.3 "Auto-Wake-up on Break"). 2: It is up to the user to determine that the incoming character baud rate is within the range of the selected BRG clock source. Some combinations of oscillator frequency and EUSART baud rates are not possible. 3: During the auto-baud process, the autobaud counter starts counting at one. Upon completion of the auto-baud sequence, to achieve maximum accuracy, subtract 1 from the SPxBRGH:SPxBRGL register pair. BRG COUNTER CLOCK RATES BRG16 Note: The BRG auto-baud clock is determined by the BRG16 and BRGH bits as shown in Table 25-6. During ABD, both the SPxBRGH and SPxBRGL registers are used as a 16-bit counter, independent of the BRG16 bit setting. While calibrating the baud rate period, the SPxBRGH and SPxBRGL registers are clocked at 1/ 8th the BRG base clock rate. The resulting byte measurement is the average bit time when clocked at full speed. During the ABD sequence, SPxBRGL and SPxBRGH registers are both used as a 16bit counter, independent of the BRG16 setting. DS40001770A-page 336 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 FIGURE 25-6: AUTOMATIC BAUD RATE CALIBRATION XXXXh BRG Value RX pin 0000h 001Ch Start Edge #1 bit 1 bit 0 Edge #2 bit 3 bit 2 Edge #3 bit 5 bit 4 Edge #4 bit 7 bit 6 Edge #5 Stop bit BRG Clock Auto Cleared Set by User ABDEN bit RCIDL RCIF bit (Interrupt) Read RCxREG SPxBRGL XXh 1Ch SPxBRGH XXh 00h Note 1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 337 PIC16(L)F1615/9 25.4.2 AUTO-BAUD OVERFLOW 25.4.3.1 During the course of automatic baud detection, the ABDOVF bit of the BAUDxCON register will be set if the baud rate counter overflows before the fifth rising edge is detected on the RX pin. The ABDOVF bit indicates that the counter has exceeded the maximum count that can fit in the 16 bits of the SPxBRGH:SPxBRGL register pair. After the ABDOVF bit has been set, the counter continues to count until the fifth rising edge is detected on the RX pin. Upon detecting the fifth RX edge, the hardware will set the RCIF interrupt flag and clear the ABDEN bit of the BAUDxCON register. The RCIF flag can be subsequently cleared by reading the RCxREG register. The ABDOVF flag of the BAUDxCON register can be cleared by software directly. To terminate the auto-baud process before the RCIF flag is set, clear the ABDEN bit then clear the ABDOVF bit of the BAUDxCON register. The ABDOVF bit will remain set if the ABDEN bit is not cleared first. 25.4.3 AUTO-WAKE-UP ON BREAK During Sleep mode, all clocks to the EUSART are suspended. Because of this, the Baud Rate Generator is inactive and a proper character reception cannot be performed. The Auto-Wake-up feature allows the controller to wake-up due to activity on the RX/DT line. This feature is available only in Asynchronous mode. The Auto-Wake-up feature is enabled by setting the WUE bit of the BAUDxCON register. Once set, the normal receive sequence on RX/DT is disabled, and the EUSART remains in an Idle state, monitoring for a wakeup event independent of the CPU mode. A wake-up event consists of a high-to-low transition on the RX/DT line. (This coincides with the start of a Sync Break or a wake-up signal character for the LIN protocol.) The EUSART module generates an RCIF interrupt coincident with the wake-up event. The interrupt is generated synchronously to the Q clocks in normal CPU operating modes (Figure 25-7), and asynchronously if the device is in Sleep mode (Figure 25-8). The interrupt condition is cleared by reading the RCxREG register. Special Considerations Break Character To avoid character errors or character fragments during a wake-up event, the wake-up character must be all zeros. When the wake-up is enabled the function works independent of the low time on the data stream. If the WUE bit is set and a valid non-zero character is received, the low time from the Start bit to the first rising edge will be interpreted as the wake-up event. The remaining bits in the character will be received as a fragmented character and subsequent characters can result in framing or overrun errors. Therefore, the initial character in the transmission must be all `0's. This must be ten or more bit times, 13-bit times recommended for LIN bus, or any number of bit times for standard RS-232 devices. Oscillator Start-up Time Oscillator start-up time must be considered, especially in applications using oscillators with longer start-up intervals (i.e., HS/PLL mode). The Sync Break (or wake-up signal) character must be of sufficient length, and be followed by a sufficient interval, to allow enough time for the selected oscillator to start and provide proper initialization of the EUSART. WUE Bit The wake-up event causes a receive interrupt by setting the RCIF bit. The WUE bit is cleared in hardware by a rising edge on RX/DT. The interrupt condition is then cleared in software by reading the RCxREG register and discarding its contents. To ensure that no actual data is lost, check the RCIDL bit to verify that a receive operation is not in process before setting the WUE bit. If a receive operation is not occurring, the WUE bit may then be set just prior to entering the Sleep mode. The WUE bit is automatically cleared by the low-to-high transition on the RX line at the end of the Break. This signals to the user that the Break event is over. At this point, the EUSART module is in Idle mode waiting to receive the next character. DS40001770A-page 338 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 FIGURE 25-7: AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Auto Cleared Bit set by user WUE bit RX/DT Line RCIF Note 1: Cleared due to User Read of RCxREG The EUSART remains in Idle while the WUE bit is set. FIGURE 25-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 OSC1 Auto Cleared Bit Set by User WUE bit RX/DT Line Note 1 RCIF Sleep Command Executed Note 1: 2: Sleep Ends Cleared due to User Read of RCxREG If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal is still active. This sequence should not depend on the presence of Q clocks. The EUSART remains in Idle while the WUE bit is set. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 339 PIC16(L)F1615/9 25.4.4 BREAK CHARACTER SEQUENCE The EUSART module has the capability of sending the special Break character sequences that are required by the LIN bus standard. A Break character consists of a Start bit, followed by 12 `0' bits and a Stop bit. To send a Break character, set the SENDB and TXEN bits of the TXxSTA register. The Break character transmission is then initiated by a write to the TXxREG. The value of data written to TXxREG will be ignored and all `0's will be transmitted. The SENDB bit is automatically reset by hardware after the corresponding Stop bit is sent. This allows the user to preload the transmit FIFO with the next transmit byte following the Break character (typically, the Sync character in the LIN specification). The TRMT bit of the TXxSTA register indicates when the transmit operation is active or idle, just as it does during normal transmission. See Figure 25-9 for the timing of the Break character sequence. 25.4.4.1 Break and Sync Transmit Sequence The following sequence will start a message frame header made up of a Break, followed by an auto-baud Sync byte. This sequence is typical of a LIN bus master. 1. 2. 3. 4. 5. 25.4.5 RECEIVING A BREAK CHARACTER The Enhanced EUSART module can receive a Break character in two ways. The first method to detect a Break character uses the FERR bit of the RCxSTA register and the received data as indicated by RCxREG. The Baud Rate Generator is assumed to have been initialized to the expected baud rate. A Break character has been received when; * RCIF bit is set * FERR bit is set * RCxREG = 00h The second method uses the Auto-Wake-up feature described in Section 25.4.3 "Auto-Wake-up on Break". By enabling this feature, the EUSART will sample the next two transitions on RX/DT, cause an RCIF interrupt, and receive the next data byte followed by another interrupt. Note that following a Break character, the user will typically want to enable the Auto-Baud Detect feature. For both methods, the user can set the ABDEN bit of the BAUDxCON register before placing the EUSART in Sleep mode. Configure the EUSART for the desired mode. Set the TXEN and SENDB bits to enable the Break sequence. Load the TXxREG with a dummy character to initiate transmission (the value is ignored). Write `55h' to TXxREG to load the Sync character into the transmit FIFO buffer. After the Break has been sent, the SENDB bit is reset by hardware and the Sync character is then transmitted. When the TXxREG becomes empty, as indicated by the TXIF, the next data byte can be written to TXxREG. FIGURE 25-9: Write to TXxREG SEND BREAK CHARACTER SEQUENCE Dummy Write BRG Output (Shift Clock) TX (pin) Start bit bit 0 bit 1 bit 11 Stop bit Break TXIF bit (Transmit Interrupt Flag) TRMT bit (Transmit Shift Empty Flag) SENDB (send Break control bit) DS40001770A-page 340 SENDB Sampled Here Preliminary Auto Cleared 2014 Microchip Technology Inc. PIC16(L)F1615/9 25.5 EUSART Synchronous Mode Synchronous serial communications are typically used in systems with a single master and one or more slaves. The master device contains the necessary circuitry for baud rate generation and supplies the clock for all devices in the system. Slave devices can take advantage of the master clock by eliminating the internal clock generation circuitry. There are two signal lines in Synchronous mode: a bidirectional data line and a clock line. Slaves use the external clock supplied by the master to shift the serial data into and out of their respective receive and transmit shift registers. Since the data line is bidirectional, synchronous operation is half-duplex only. Half-duplex refers to the fact that master and slave devices can receive and transmit data but not both simultaneously. The EUSART can operate as either a master or slave device. Start and Stop bits are not used in synchronous transmissions. 25.5.1 SYNCHRONOUS MASTER MODE Clearing the SCKP bit sets the Idle state as low. When the SCKP bit is cleared, the data changes on the rising edge of each clock. 25.5.1.3 Data is transferred out of the device on the RX/DT pin. The RX/DT and TX/CK pin output drivers are automatically enabled when the EUSART is configured for synchronous master transmit operation. A transmission is initiated by writing a character to the TXxREG register. If the TSR still contains all or part of a previous character, the new character data is held in the TXxREG until the last bit of the previous character has been transmitted. If this is the first character, or the previous character has been completely flushed from the TSR, the data in the TXxREG is immediately transferred to the TSR. The transmission of the character commences immediately following the transfer of the data to the TSR from the TXxREG. Each data bit changes on the leading edge of the master clock and remains valid until the subsequent leading clock edge. Note: The TSR register is not mapped in data memory, so it is not available to the user. 25.5.1.4 Synchronous Master Transmission Set-up: The following bits are used to configure the EUSART for synchronous master operation: * * * * * SYNC = 1 CSRC = 1 SREN = 0 (for transmit); SREN = 1 (for receive) CREN = 0 (for transmit); CREN = 1 (for receive) SPEN = 1 1. Setting the SYNC bit of the TXxSTA register configures the device for synchronous operation. Setting the CSRC bit of the TXxSTA register configures the device as a master. Clearing the SREN and CREN bits of the RCxSTA register ensures that the device is in the Transmit mode, otherwise the device will be configured to receive. Setting the SPEN bit of the RCxSTA register enables the EUSART. 25.5.1.1 25.5.1.2 2. 3. 4. 5. 6. Master Clock Synchronous data transfers use a separate clock line, which is synchronous with the data. A device configured as a master transmits the clock on the TX/CK line. The TX/CK pin output driver is automatically enabled when the EUSART is configured for synchronous transmit or receive operation. Serial data bits change on the leading edge to ensure they are valid at the trailing edge of each clock. One clock cycle is generated for each data bit. Only as many clock cycles are generated as there are data bits. Synchronous Master Transmission 7. 8. Initialize the SPxBRGH, SPxBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 25.4 "EUSART Baud Rate Generator (BRG)"). Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. Disable Receive mode by clearing bits SREN and CREN. Enable Transmit mode by setting the TXEN bit. If 9-bit transmission is desired, set the TX9 bit. If interrupts are desired, set the TXIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. If 9-bit transmission is selected, the ninth bit should be loaded in the TX9D bit. Start transmission by loading data to the TXxREG register. Clock Polarity A clock polarity option is provided for Microwire compatibility. Clock polarity is selected with the SCKP bit of the BAUDxCON register. Setting the SCKP bit sets the clock Idle state as high. When the SCKP bit is set, the data changes on the falling edge of each clock. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 341 PIC16(L)F1615/9 FIGURE 25-10: SYNCHRONOUS TRANSMISSION RX/DT pin bit 0 bit 1 Word 1 bit 2 bit 7 bit 0 bit 1 Word 2 bit 7 TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to TXxREG Reg Write Word 1 Write Word 2 TXIF bit (Interrupt Flag) TRMT bit TXEN bit Note: `1' `1' Sync Master mode, SPxBRGL = 0, continuous transmission of two 8-bit words. FIGURE 25-11: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RX/DT pin bit 0 bit 1 bit 2 bit 6 bit 7 TX/CK pin Write to TXxREG reg TXIF bit TRMT bit TXEN bit DS40001770A-page 342 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 TABLE 25-7: Name ANSELA ANSELB(1) SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page -- -- -- ANSA4 -- ANSA2 ANSA1 ANSA0 160 167 -- -- ANSB5 ANSB4 -- -- -- -- ANSELC ANSC7(1) ANSC6(1) -- -- ANSC3 ANSC2 ANSC1 ANSC0 174 BAUD1CON ABDOVF RCIDL -- SCKP BRG16 -- WUE ABDEN 330 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 105 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 106 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 111 RC1STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D RxyPPS -- -- -- RxyPPS<4:0> SP1BRGL BRG<7:0> SP1BRGH TRISA TRISB(1) TRISC Legend: * Note 1: 2: 331 BRG<15:8> 331 -- -- TRISA5 TRISA4 --(2) TRISA2 TRISA1 TRISA0 159 TRISB7 TRISB6 TRISB5 TRISB4 -- -- -- -- 166 TRISC7(1) TRISC6(1) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 TX1REG TX1STA 329 180 EUSART Transmit Data Register CSRC TX9 TXEN SYNC SENDB 173 320* BRGH TRMT TX9D 328 -- = unimplemented location, read as `0'. Shaded cells are not used for synchronous master transmission. Page provides register information. PIC16(L)F1619 only. Unimplemented, read as `1'. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 343 PIC16(L)F1615/9 25.5.1.5 Synchronous Master Reception 25.5.1.7 Data is received at the RX/DT pin. The RX/DT pin output driver is automatically disabled when the EUSART is configured for synchronous master receive operation. In Synchronous mode, reception is enabled by setting either the Single Receive Enable bit (SREN of the RCxSTA register) or the Continuous Receive Enable bit (CREN of the RCxSTA register). When SREN is set and CREN is clear, only as many clock cycles are generated as there are data bits in a single character. The SREN bit is automatically cleared at the completion of one character. When CREN is set, clocks are continuously generated until CREN is cleared. If CREN is cleared in the middle of a character the CK clock stops immediately and the partial character is discarded. If SREN and CREN are both set, then SREN is cleared at the completion of the first character and CREN takes precedence. To initiate reception, set either SREN or CREN. Data is sampled at the RX/DT pin on the trailing edge of the TX/CK clock pin and is shifted into the Receive Shift Register (RSR). When a complete character is received into the RSR, the RCIF bit is set and the character is automatically transferred to the two character receive FIFO. The Least Significant eight bits of the top character in the receive FIFO are available in RCxREG. The RCIF bit remains set as long as there are unread characters in the receive FIFO. Note: 25.5.1.6 If the RX/DT function is on an analog pin, the corresponding ANSEL bit must be cleared for the receiver to function. Slave Clock Synchronous data transfers use a separate clock line, which is synchronous with the data. A device configured as a slave receives the clock on the TX/CK line. The TX/ CK pin output driver is automatically disabled when the device is configured for synchronous slave transmit or receive operation. Serial data bits change on the leading edge to ensure they are valid at the trailing edge of each clock. One data bit is transferred for each clock cycle. Only as many clock cycles should be received as there are data bits. Note: If the device is configured as a slave and the TX/CK function is on an analog pin, the corresponding ANSEL bit must be cleared. DS40001770A-page 344 Receive Overrun Error The receive FIFO buffer can hold two characters. An overrun error will be generated if a third character, in its entirety, is received before RCxREG is read to access the FIFO. When this happens the OERR bit of the RCxSTA register is set. Previous data in the FIFO will not be overwritten. The two characters in the FIFO buffer can be read, however, no additional characters will be received until the error is cleared. The OERR bit can only be cleared by clearing the overrun condition. If the overrun error occurred when the SREN bit is set and CREN is clear then the error is cleared by reading RCxREG. If the overrun occurred when the CREN bit is set then the error condition is cleared by either clearing the CREN bit of the RCxSTA register or by clearing the SPEN bit which resets the EUSART. 25.5.1.8 Receiving 9-bit Characters The EUSART supports 9-bit character reception. When the RX9 bit of the RCxSTA register is set the EUSART will shift nine bits into the RSR for each character received. The RX9D bit of the RCxSTA register is the ninth, and Most Significant, data bit of the top unread character in the receive FIFO. When reading 9-bit data from the receive FIFO buffer, the RX9D data bit must be read before reading the eight Least Significant bits from the RCxREG. 25.5.1.9 Synchronous Master Reception Setup: 1. Initialize the SPxBRGH, SPxBRGL register pair for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. 2. Clear the ANSEL bit for the RX pin (if applicable). 3. Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. 4. Ensure bits CREN and SREN are clear. 5. If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. 6. If 9-bit reception is desired, set bit RX9. 7. Start reception by setting the SREN bit or for continuous reception, set the CREN bit. 8. Interrupt flag bit RCIF will be set when reception of a character is complete. An interrupt will be generated if the enable bit RCIE was set. 9. Read the RCxSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. 10. Read the 8-bit received data by reading the RCxREG register. 11. If an overrun error occurs, clear the error by either clearing the CREN bit of the RCxSTA register or by clearing the SPEN bit which resets the EUSART. Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 FIGURE 25-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) RX/DT pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to bit SREN SREN bit CREN bit `0' `0' RCIF bit (Interrupt) Read RCxREG Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0. Note: TABLE 25-8: Name SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page -- -- ANSA4 -- ANSA2 ANSA1 ANSA0 160 -- ANSB5 ANSB4 -- -- -- -- 167 ANSC7(1) ANSC6(1) -- -- ANSC3 ANSC2 ANSC1 ANSC0 174 ABDOVF RCIDL -- SCKP BRG16 -- WUE ABDEN -- -- -- Bit 7 Bit 6 ANSELA -- ANSELB(1) -- ANSELC BAUD1CON CKPPS CKPPS<4:0> 330 182, 180 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 105 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 106 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF INTCON RC1REG EUSART Receive Data Register RC1STA SPEN RX9 SREN RXPPS -- -- -- RxyPPS -- -- -- SP1BRGL TRISB(1) TRISC TX1STA Legend: * Note 1: 2: ADDEN FERR OERR RX9D RXPPS<4:0> 329 182, 180 RxyPPS<4:0> 180 BRG<7:0> SP1BRGH TRISA CREN 111 323* 331* BRG<15:8> 331* -- -- TRISA5 TRISA4 --(2) TRISA2 TRISA1 TRISA0 159 TRISB7 TRISB6 TRISB5 TRISB4 -- -- -- -- 166 TRISC7(1) TRISC6(1) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 173 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 328 -- = unimplemented location, read as `0'. Shaded cells are not used for synchronous master reception. Page provides register information. PIC16(L)F1619 only. Unimplemented, read as `1'. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 345 PIC16(L)F1615/9 25.5.2 SYNCHRONOUS SLAVE MODE 25.5.2.2 The following bits are used to configure the EUSART for synchronous slave operation: * * * * * SYNC = 1 CSRC = 0 SREN = 0 (for transmit); SREN = 1 (for receive) CREN = 0 (for transmit); CREN = 1 (for receive) SPEN = 1 2. 3. 4. Setting the SYNC bit of the TXxSTA register configures the device for synchronous operation. Clearing the CSRC bit of the TXxSTA register configures the device as a slave. Clearing the SREN and CREN bits of the RCxSTA register ensures that the device is in the Transmit mode, otherwise the device will be configured to receive. Setting the SPEN bit of the RCxSTA register enables the EUSART. 25.5.2.1 1. 5. 6. 7. 8. Synchronous Slave Transmission Set-up: Set the SYNC and SPEN bits and clear the CSRC bit. Clear the ANSEL bit for the CK pin (if applicable). Clear the CREN and SREN bits. If interrupts are desired, set the TXIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. If 9-bit transmission is desired, set the TX9 bit. Enable transmission by setting the TXEN bit. If 9-bit transmission is selected, insert the Most Significant bit into the TX9D bit. Start transmission by writing the Least Significant eight bits to the TXxREG register. EUSART Synchronous Slave Transmit The operation of the Synchronous Master and Slave modes are identical (see Section 25.5.1.3 "Synchronous Master Transmission"), except in the case of the Sleep mode. If two words are written to the TXxREG and then the SLEEP instruction is executed, the following will occur: 1. 2. 3. 4. 5. The first character will immediately transfer to the TSR register and transmit. The second word will remain in the TXxREG register. The TXIF bit will not be set. After the first character has been shifted out of TSR, the TXxREG register will transfer the second character to the TSR and the TXIF bit will now be set. If the PEIE and TXIE bits are set, the interrupt will wake the device from Sleep and execute the next instruction. If the GIE bit is also set, the program will call the Interrupt Service Routine. DS40001770A-page 346 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 TABLE 25-9: Name ANSELA ANSELB(1) SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page -- -- -- ANSA4 -- ANSA2 ANSA1 ANSA0 160 167 -- -- ANSB5 ANSB4 -- -- -- -- ANSELC ANSC7(1) ANSC6(1) -- -- ANSC3 ANSC2 ANSC1 ANSC0 174 BAUD1CON ABDOVF RCIDL -- SCKP BRG16 -- WUE ABDEN 330 CKPPS -- -- -- INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 105 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 106 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 111 RC1STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 329 RXPPS -- -- -- RXPPS<4:0> RxyPPS -- -- -- RxyPPS<4:0> TRISA -- -- TRISA5 (1) CKPPS<4:0> TRISA4 --(2) TRISA2 182, 180 182, 180 180 TRISA1 TRISA0 159 TRISB TRISB7 TRISB6 TRISB5 TRISB4 -- -- -- -- 166 TRISC TRISC7(1) TRISC6(1) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 173 TRMT TX9D TX1REG TX1STA Legend: * Note 1: 2: EUSART Transmit Data Register CSRC TX9 TXEN SYNC SENDB 320* BRGH 328 -- = unimplemented location, read as `0'. Shaded cells are not used for synchronous slave transmission. Page provides register information. PIC16(L)F1619 only. Unimplemented, read as `1'. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 347 PIC16(L)F1615/9 25.5.2.3 EUSART Synchronous Slave Reception 25.5.2.4 The operation of the Synchronous Master and Slave modes is identical (Section 25.5.1.5 "Synchronous Master Reception"), with the following exceptions: * Sleep * CREN bit is always set, therefore the receiver is never idle * SREN bit, which is a "don't care" in Slave mode 1. 2. 3. A character may be received while in Sleep mode by setting the CREN bit prior to entering Sleep. Once the word is received, the RSR register will transfer the data to the RCxREG register. If the RCIE enable bit is set, the interrupt generated will wake the device from Sleep and execute the next instruction. If the GIE bit is also set, the program will branch to the interrupt vector. 4. 5. 6. 7. 8. 9. Synchronous Slave Reception Setup: Set the SYNC and SPEN bits and clear the CSRC bit. Clear the ANSEL bit for both the CK and DT pins (if applicable). If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. If 9-bit reception is desired, set the RX9 bit. Set the CREN bit to enable reception. The RCIF bit will be set when reception is complete. An interrupt will be generated if the RCIE bit was set. If 9-bit mode is enabled, retrieve the Most Significant bit from the RX9D bit of the RCxSTA register. Retrieve the eight Least Significant bits from the receive FIFO by reading the RCxREG register. If an overrun error occurs, clear the error by either clearing the CREN bit of the RCxSTA register or by clearing the SPEN bit which resets the EUSART. TABLE 25-10: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Name Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page -- -- ANSA4 -- ANSA2 ANSA1 ANSA0 160 -- ANSB5 ANSB4 -- -- -- -- 167 Bit 7 Bit 6 ANSELA -- ANSELB(1) -- (1) (1) ANSELC ANSC7 -- -- ANSC3 ANSC2 ANSC1 ANSC0 174 BAUD1CON ABDOVF RCIDL -- SCKP BRG16 -- WUE ABDEN 330 CKPPS -- -- -- INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 105 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 106 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 111 RC1STA SPEN RX9 SREN OERR RX9D RXPPS -- -- -- TRISA -- -- TRISB7 ANSC6 RC1REG TRISB(1) TRISC TX1STA Legend: * Note 1: 2: CKPPS<4:0> 182, 180 EUSART Receive Data Register 323* CREN ADDEN FERR TRISA5 TRISA4 --(2) TRISA2 TRISA1 TRISA0 159 TRISB6 TRISB5 TRISB4 -- -- -- -- 166 TRISC7(1) TRISC6(1) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 173 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 328 RXPPS<4:0> 329 182, 180 -- = unimplemented location, read as `0'. Shaded cells are not used for synchronous slave reception. Page provides register information. PIC16(L)F1619 only. Unimplemented, read as `1'. DS40001770A-page 348 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 25.6 EUSART Operation During Sleep The EUSART will remain active during Sleep only in the Synchronous Slave mode. All other modes require the system clock and therefore cannot generate the necessary signals to run the Transmit or Receive Shift registers during Sleep. Synchronous Slave mode uses an externally generated clock to run the Transmit and Receive Shift registers. 25.6.1 SYNCHRONOUS RECEIVE DURING SLEEP To receive during Sleep, all the following conditions must be met before entering Sleep mode: * RCxSTA and TXxSTA Control registers must be configured for Synchronous Slave Reception (see Section 25.5.2.4 "Synchronous Slave Reception Set-up:"). * If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. * The RCIF interrupt flag must be cleared by reading RCxREG to unload any pending characters in the receive buffer. Upon entering Sleep mode, the device will be ready to accept data and clocks on the RX/DT and TX/CK pins, respectively. When the data word has been completely clocked in by the external device, the RCIF interrupt flag bit of the PIR1 register will be set. Thereby, waking the processor from Sleep. 25.6.2 SYNCHRONOUS TRANSMIT DURING SLEEP To transmit during Sleep, all the following conditions must be met before entering Sleep mode: * The RCxSTA and TXxSTA Control registers must be configured for synchronous slave transmission (see Section 25.5.2.2 "Synchronous Slave Transmission Set-up:"). * The TXIF interrupt flag must be cleared by writing the output data to the TXxREG, thereby filling the TSR and transmit buffer. * If interrupts are desired, set the TXIE bit of the PIE1 register and the PEIE bit of the INTCON register. * Interrupt enable bits TXIE of the PIE1 register and PEIE of the INTCON register must set. Upon entering Sleep mode, the device will be ready to accept clocks on TX/CK pin and transmit data on the RX/DT pin. When the data word in the TSR has been completely clocked out by the external device, the pending byte in the TXxREG will transfer to the TSR and the TXIF flag will be set. Thereby, waking the processor from Sleep. At this point, the TXxREG is available to accept another character for transmission, which will clear the TXIF flag. Upon waking from Sleep, the instruction following the SLEEP instruction will be executed. If the Global Interrupt Enable (GIE) bit is also set then the Interrupt Service Routine at address 0004h will be called. Upon waking from Sleep, the instruction following the SLEEP instruction will be executed. If the Global Interrupt Enable (GIE) bit of the INTCON register is also set, then the Interrupt Service Routine at address 004h will be called. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 349 PIC16(L)F1615/9 26.0 CAPTURE/COMPARE/PWM MODULES 26.1 The Capture/Compare/PWM module is a peripheral which allows the user to time and control different events, and to generate Pulse-Width Modulation (PWM) signals. In Capture mode, the peripheral allows the timing of the duration of an event. The Compare mode allows the user to trigger an external event when a predetermined amount of time has expired. The PWM mode can generate Pulse-Width Modulated signals of varying frequency and duty cycle. This family of devices contains two standard Capture/ Compare/PWM modules (CCP1 and CCP2). Note 1: In devices with more than one CCP module, it is very important to pay close attention to the register names used. A number placed after the module acronym is used to distinguish between separate modules. For example, the CCP1CON and CCP2CON control the same operational aspects of two completely different CCP modules. 2: Throughout this section, generic references to a CCP module in any of its operating modes may be interpreted as being equally applicable to CCPx module. Register names, module signals, I/O pins, and bit names may use the generic designator `x' to indicate the use of a numeral to distinguish a particular module, when required. Capture Mode The Capture mode function described in this section is available and identical for all CCP modules. Capture mode makes use of the 16-bit Timer1 resource. When an event occurs on the CCPx input, the 16-bit CCPRxH:CCPRxL register pair captures and stores the 16-bit value of the TMR1H:TMR1L register pair, respectively. An event is defined as one of the following and is configured by the MODE<3:0> bits of the CCPxCON register: * * * * * Every edge (rising or falling) Every falling edge Every rising edge Every 4th rising edge Every 16th rising edge The CCPx capture input signal is configured by the CTS bits of the CCPxCAP register with the following options: * * * * CCPx pin Comparator 1 output (C1_OUT_sync) Comparator 2 output (C2_OUT_sync) Interrupt-on-change interrupt trigger (IOC_interrupt) When a capture is made, the Interrupt Request Flag bit CCPxIF of the PIRx register is set. The interrupt flag must be cleared in software. If another capture occurs before the value in the CCPRxH, CCPRxL register pair is read, the old captured value is overwritten by the new captured value. Figure 26-1 shows a simplified diagram of the capture operation. 26.1.1 CCP PIN CONFIGURATION In Capture mode, select the interrupt source using the CTS bits of the CCPxCAP register. If the CCPx pin is chosen, it should be configured as an input by setting the associated TRIS control bit. DS40001770A-page 350 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 FIGURE 26-1: CAPTURE MODE OPERATION BLOCK DIAGRAM Rev. 10-000158D 7/17/2014 RxyPPS CCPx CTS<2:0> TRIS Control Reserved 111 Reserved 110 LC2_output 101 LC1_output 100 IOC_interrupt 011 C2OUT_sync 010 C1OUT_sync 001 CCPx 26.1.2 CCPRxH CCPRxL 16 Prescaler 1,4,16 set CCPxIF and Edge Detect 16 MODE <3:0> TMR1H TMR1L 000 26.1.5 TIMER1 MODE RESOURCE CAPTURE DURING SLEEP Timer1 must be running in Timer mode or Synchronized Counter mode for the CCP module to use the capture feature. In Asynchronous Counter mode, the capture operation may not work. Capture mode depends upon the Timer1 module for proper operation. There are two options for driving the Timer1 module in Capture mode. It can be driven by the instruction clock (FOSC/4), or by an external clock source. See Section 22.0 "Timer1 Module with Gate Control" for more information on configuring Timer1. When Timer1 is clocked by FOSC/4, Timer1 will not increment during Sleep. When the device wakes from Sleep, Timer1 will continue from its previous state. 26.1.3 SOFTWARE INTERRUPT MODE When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCPxIE interrupt enable bit of the PIEx register clear to avoid false interrupts. Additionally, the user should clear the CCPxIF interrupt flag bit of the PIRx register following any change in Operating mode. Note: 26.1.4 Clocking Timer1 from the system clock (FOSC) should not be used in Capture mode. In order for Capture mode to recognize the trigger event on the CCPx pin, Timer1 must be clocked from the instruction clock (FOSC/4) or from an external clock source. Capture mode will operate during Sleep when Timer1 is clocked by an external clock source. 26.1.6 CAPTURE OUTPUT Whenever a capture occurs, the output of the CCP will go high for a period equal to one system clock period (1/FOSC). This output is available as an input signal to the CWG, as an auto-conversion trigger for the ADC, as an External Reset Signal for the TMR2 modules, and as a window input to the SMT. In addition, if the CCPx pin is not used as the input to the capture, the OE bit of the CCPxCON register allows the output of the CCP to control the CCPx pin. CCP PRESCALER There are four prescaler settings specified by the MODE<3:0> bits of the CCPxCON register. Whenever the CCP module is turned off, or the CCP module is not in Capture mode, the prescaler counter is cleared. Any Reset will clear the prescaler counter. Switching from one capture prescaler to another does not clear the prescaler and may generate a false interrupt. To avoid this unexpected operation, turn the module off by clearing the EN bit of the CCPxCON register before changing the prescaler. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 351 PIC16(L)F1615/9 26.2 Compare Mode The Compare mode function described in this section is available and identical for all CCP modules. Compare mode makes use of the 16-bit Timer1 resource. The 16-bit value of the CCPRxH:CCPRxL register pair is constantly compared against the 16-bit value of the TMR1H:TMR1L register pair. When a match occurs, one of the following events can occur: * * * * * * Toggle the CCPx output Set the CCPx output Clear the CCPx output Pulse the CCPx output Generate a Software Interrupt Optionally Reset TMR1 FIGURE 26-2: The action on the pin is based on the value of the MODE<3:0> control bits of the CCPxCON register. At the same time, the interrupt flag CCPxIF bit is set. All Compare modes can generate an interrupt. Figure 26-2 shows a simplified diagram of the compare operation. 26.2.1 CCPx PIN CONFIGURATION The user must configure the CCPx pin as an output by clearing the associated TRIS bit. COMPARE MODE OPERATION BLOCK DIAGRAM Rev. 10-000 159A 12/10/201 3 To Peripherals CCPRxH CCPRxL OE set CCPxIF Comparator Output Logic 4 TMR1H DS40001770A-page 352 TMR1L S R Q CCP x TRIS Control MODE<3:0> Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 26.2.2 TIMER1 MODE RESOURCE In Compare mode, Timer1 must be running in either Timer mode or Synchronized Counter mode. The compare operation may not work in Asynchronous Counter mode. See Section 22.0 "Timer1 Module with Gate Control" for more information on configuring Timer1. Note: 26.2.3 Clocking Timer1 from the system clock (FOSC) should not be used in Compare mode. In order for Compare mode to recognize the trigger event on the CCPx pin, TImer1 must be clocked from the instruction clock (FOSC/4) or from an external clock source. SOFTWARE INTERRUPT MODE When Generate Software Interrupt mode is chosen (MODE<3:0> = 1010), the CCPx module does not assert control of the CCPx pin (see the CCPxCON register). 26.2.4 COMPARE DURING SLEEP The Compare mode is dependent upon the system clock (FOSC) for proper operation. Since FOSC is shut down during Sleep mode, the Compare mode will not function properly during Sleep. 26.2.5 CAPTURE OUTPUT When in Compare mode, the CCP will provide an output upon the 16-bit value of the CCPRxH:CCPRxL register pair matching the TMR1H:TMR1L register pair. The compare output depends on which Compare mode the CCP is configured as. If the MODE bits of CCPxCON register are equal to `1011' or `1010', the CCP module will output high, while TMR1 is equal to CCPRxH:CCPRxL register pair. This means that the pulse width is determined by the TMR1 prescaler. If the MODE bits of CCPxCON are equal to `0001' or `0010', the output will toggle upon a match, going from `0' to `1' or vice-versa. If the MODE bits of CCPxCON are equal to `1001', the output is cleared on a match, and if the MODE bits are equal to `1000', the output is set on a match. This output is available as an input signal to the CWG, as an auto-conversion trigger for the ADC, as an external Reset signal for the TMR2 modules, and as a window input to the SMT. In addition, the OE bit of the CCPxCON register allows the output of the CCP to control the CCPx pin. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 353 PIC16(L)F1615/9 26.3 PWM resolution defines the maximum number of steps that can be present in a single PWM period. A higher resolution allows for more precise control of the pulse width time and in turn the power that is applied to the load. PWM Overview Pulse-Width Modulation (PWM) is a scheme that provides power to a load by switching quickly between fully on and fully off states. The PWM signal resembles a square wave where the high portion of the signal is considered the on state and the low portion of the signal is considered the off state. The high portion, also known as the pulse width, can vary in time and is defined in steps. A larger number of steps applied, which lengthens the pulse width, also supplies more power to the load. Lowering the number of steps applied, which shortens the pulse width, supplies less power. The PWM period is defined as the duration of one complete cycle or the total amount of on and off time combined. FIGURE 26-3: The term duty cycle describes the proportion of the on time to the off time and is expressed in percentages, where 0% is fully off and 100% is fully on. A lower duty cycle corresponds to less power applied and a higher duty cycle corresponds to more power applied. Figure shows a typical waveform of the PWM signal. SIMPLIFIED PWM BLOCK DIAGRAM Rev. 10-000 157A 1/22/201 4 Duty cycle registers CCPRxH CCPRxL CCPx_out To Peripherals set CCPIF 10-bit Latch(2) (Not visible to user) OE Comparator R Q CCPx S TRIS Control TMR2 Module R TMR2 (1) ERS logic Comparator CCPx_pset PR2 Note 1: 2: 8-bit timer is concatenated with two bits generated by Fosc or two bits of the internal prescaler to create 10-bit time-base. The alignment of the ten bits from the CCPR register is determined by the FMT bit. Refer to Figure 26-4 for more information. DS40001770A-page 354 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 26.3.1 STANDARD PWM OPERATION 26.3.2 SETUP FOR PWM OPERATION The standard PWM function described in this section is available and identical for all CCP modules. The following steps should be taken when configuring the CCP module for standard PWM operation: The standard PWM mode generates a Pulse-Width Modulation (PWM) signal on the CCPx pin with up to 10 bits of resolution. The period, duty cycle, and resolution are controlled by the following registers: 1. * PR2/4/6 registers * T2CON/T4CON/T6CON registers * CCPRxH:CCPRxL register pair 3. Disable the CCPx pin output driver by setting the associated TRIS bit. Determine which timer will be used to clock the CCP; Timer2/4/6. Load the associated PR2/4/6 register with the PWM period value. Configure the CCP module for the PWM mode by loading the CCPxCON register with the appropriate values. Load the CCPRxH:CCPRxL register pair with the PWM duty cycle value. Configure and start Timer2/4/6: * Clear the TMR2IF/TMR4IF/TMR6IF interrupt flag bit of the PIRx register. See Note below. * Configure the CKPS bits of the TxCON register with the Timer prescale value. * Enable the Timer by setting the ON bit of the TxCON register. Enable PWM output pin: * Wait until the Timer overflows and the TMR2IF/TMR4IF/TMR6IF bit of the PIRx register is set. See Note below. * Enable the CCPx pin output driver by clearing the associated TRIS bit. 2. 4. Figure 26-3 shows a simplified block diagram of PWM operation. Note 1: The corresponding TRIS bit must be cleared to enable the PWM output on the CCPx pin. 5. 6. 2: Clearing the CCPxCON register will relinquish control of the CCPx pin. 7. Note: 2014 Microchip Technology Inc. Preliminary In order to send a complete duty cycle and period on the first PWM output, the above steps must be included in the setup sequence. If it is not critical to start with a complete PWM signal on the first output, then step 6 may be ignored. DS40001770A-page 355 PIC16(L)F1615/9 26.4 CCP/PWM Clock Selection The PIC16(L)F1615/9 allows each individual CCP and PWM module to select the timer source that controls the module. Each module has an independent selection. As there are up to three 8-bit timers with auto-reload (Timer2/4/6), PWM mode on the CCP and PWM modules can use any of these timers. The CCPTMRS register is used to select which timer is used. 26.4.1 The PWM period is specified by the PR2/4/6 register of Timer2/4/6. The PWM period can be calculated using the formula of Equation 26-1. PWM PERIOD PWM Period = PR2 + 1 4 T OSC (TMR2 Prescale Value) EQUATION 26-3: DUTY CYCLE RATIO CCPRxH:CCPRxL Duty Cycle Ratio = -------------------------------------------------4 PRx + 1 The PWM duty cycle registers are double buffered for glitchless PWM operation. The 8-bit timer TMR2/4/6 register is concatenated with either the 2-bit internal system clock (FOSC), or two bits of the prescaler, to create the 10-bit time base. The system clock is used if the Timer2/4/6 prescaler is set to 1:1. When the 10-bit time base matches the internal buffer register, then the CCPx pin is cleared (see Figure 26-3). (TMR2 Prescale Value) Note 1: PULSE WIDTH Pulse Width = CCPRxH:CCPRxL T OSC PWM PERIOD EQUATION 26-1: Equation 26-2 is used to calculate the PWM pulse width. Equation 26-3 is used to calculate the PWM duty cycle ratio. EQUATION 26-2: USING THE TMR2/4/6 WITH THE CCP MODULE This device has a new version of the TMR2 module that has many new modes, which allow for greater customization and control of the PWM signals than older parts. Refer to Section 23.5 "Operation Examples" for examples of PWM signal generation using the different modes of Timer2. The CCP operation requires that the timer used as the PWM time base has the FOSC/4 clock source selected. 26.4.2 Significant two bits of the duty cycle should be written to bits <7:6> of the CCPRxL register and the Most Significant eight bits to the CCPRxH register. This is illustrated in Figure 26-4. These bits can be written at any time. The duty cycle value is not latched into the internal latch until after the period completes (i.e., a match between PR2/4/6 and TMR2/4/6 registers occurs). TOSC = 1/FOSC FIGURE 26-4: CCPx DUTY-CYCLE ALIGNMENT When TMR2/4/6 is equal to its respective PR2/4/6 register, the following three events occur on the next increment cycle: Rev. 10-000 160A 12/9/201 3 * TMR2/4/6 is cleared * The CCPx pin is set. (Exception: If the PWM duty cycle = 0%, the pin will not be set.) * The PWM duty cycle is latched from the CCPRxH:CCPRxL pair into the internal 10-bit latch. Note: 26.4.3 CCPRxH CCPRxL 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 FMT = 1 FMT = 0 CCPRxH CCPRxL 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 10-bit Duty Cycle The Timer postscaler (see Figure 26-1) is not used in the determination of the PWM frequency. 9 8 7 6 5 4 3 2 1 0 PWM DUTY CYCLE The PWM duty cycle is specified by writing a 10-bit value to two registers: the CCPRxH:CCPRxL register pair. Where the particular bits go is determined by the FMT bit of the CCPxCON register. If FMT = 0, the two Most Significant bits of the duty cycle value should be written to bits <1:0> of CCPRxH register and the remaining eight bits to the CCPRxL register. If FMT = 1, the Least DS40001770A-page 356 26.4.4 PWM RESOLUTION The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles. Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 The maximum PWM resolution is ten bits when PR2/4/6 is 255. The resolution is a function of the PR2/4/6 register value as shown by Equation 26-4. EQUATION 26-4: PWM RESOLUTION log 4 PR2 + 1 Resolution = ------------------------------------------ bits log 2 Note: If the pulse width value is greater than the period, the assigned PWM pin(s) will remain unchanged. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 357 PIC16(L)F1615/9 TABLE 26-1: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz) PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz 16 4 1 1 1 1 0xFF 0xFF 0xFF 0x3F 0x1F 0x17 10 10 10 8 7 6 Timer Prescale PR2 Value Maximum Resolution (bits) TABLE 26-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz) PWM Frequency 1.22 kHz Timer Prescale PR2 Value 19.61 kHz 76.92 kHz 153.85 kHz 200.0 kHz 16 4 1 1 1 1 0x65 0x65 0x65 0x19 0x0C 0x09 8 8 8 6 5 5 Maximum Resolution (bits) 26.4.5 4.90 kHz CHANGES IN SYSTEM CLOCK FREQUENCY The PWM frequency is derived from the system clock frequency. Any changes in the system clock frequency will result in changes to the PWM frequency. See Section 5.0 "Oscillator Module" for additional details. 26.4.6 EFFECTS OF RESET Any Reset will force all ports to Input mode and the CCP registers to their Reset states. 26.4.7 PWM OUTPUT The output of the CCP in PWM mode is the PWM signal generated by the module and described above. This output is available as an input signal to the CWG, as an auto-conversion trigger for the ADC, as an external Reset signal for the TMR2 modules, and as a window input to the SMT. In addition, the OE bit of the CCPxCON register allows the output of the CCP to control the CCPx pin. DS40001770A-page 358 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 26.5 Register Definitions: CCP Control REGISTER 26-1: CCPxCON: CCPx CONTROL REGISTER R/W-0/0 R/W-0/0 R-x R/W-0/0 EN OE OUT FMT R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 MODE<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset `1' = Bit is set `0' = Bit is cleared bit 7 EN: CCPx Module Enable bit 1 = CCPx is enabled 0 = CCPx is disabled bit 6 OE: CCPx Output Enable bit 1 = CCPx port pin output enabled 0 = CCPx port pin output disabled bit 5 OUT: CCPx Output Data bit (read-only) bit 4 FMT: CCPW (Pulse-Width) Alignment bit If MODE = PWM Mode 1 = Left-aligned format, CCPRxH <7> is the MSB of the PWM duty cycle 0 = Right-aligned format, CCPRxL<0> is the LSB of the PWM duty cycle bit 3-0 MODE<3:0>: CCPx Mode Selection bit 11xx = PWM mode 1011 = 1010 = 1001 = 1000 = Compare mode: Pulse output, clear TMR1 Compare mode: Pulse output (0 - 1 - 0) Compare mode: clear output on compare match Compare mode: set output on compare match 0111 = 0110 = 0101 = 0100 = Capture mode: every 16th rising edge Capture mode: every 4th rising edge Capture mode: every rising edge Capture mode: every falling edge 0011 = 0010 = 0001 = 0000 = Capture mode: every rising or falling edge Compare mode: toggle output on match Compare mode: Toggle output and clear TMR1 on match Capture/Compare/PWM off (resets CCPx module) (reserved for backwards compatibility) 2014 Microchip Technology Inc. Preliminary DS40001770A-page 359 PIC16(L)F1615/9 REGISTER 26-2: R/W-0/0 CCPTMRS: PWM TIMER SELECTION CONTROL REGISTER 0 R/W-0/0 P4TSEL<1:0> R/W-0/0 R/W-0/0 R/W-0/0 P3TSEL<1:0> R/W-0/0 R/W-0/0 C2TSEL<1:0> R/W-0/0 C1TSEL<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 P4TSEL<1:0>: PWM4 Timer Selection bits 11 = Reserved 10 = PWM4 is based off Timer6 in PWM mode 01 = PWM4 is based off Timer4 in PWM mode 00 = PWM4 is based off Timer2 in PWM mode bit 5-4 P3TSEL<1:0>: PWM3 Timer Selection bits 11 = Reserved 10 = PWM3 is based off Timer6 in PWM mode 01 = PWM3 is based off Timer4 in PWM mode 00 = PWM3 is based off Timer2 in PWM mode bit 3-2 C2TSEL<1:0>: CCP2 (PWM2) Timer Selection bits 11 = Reserved 10 = CCP2 is based off Timer6 in PWM mode 01 = CCP2 is based off Timer4 in PWM mode 00 = CCP2 is based off Timer2 in PWM mode bit 1-0 C1TSEL<1:0>: CCP1 (PWM1) Timer Selection bits 11 = Reserved 10 = CCP1 is based off Timer6 in PWM mode 01 = CCP1 is based off Timer4 in PWM mode 00 = CCP1 is based off Timer2 in PWM mode DS40001770A-page 360 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 REGISTER 26-3: R/W-0/0 CCPRxL: CCPx LOW BYTE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 CCPR<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset `1' = Bit is set `0' = Bit is cleared bit 7-0 MODE = Capture Mode CCPRxL<7:0>: LSB of captured TMR1 value MODE = Compare Mode CCPRxL<7:0>: LSB compared to TMR1 value MODE = PWM Mode && FMT = 0 CCPRxL<7:0>: CCPW<7:0> -- Pulse width Least Significant eight bits MODE = PWM Mode && FMT = 1 CCPRxL<7:6>: CCPW<1:0> -- Pulse width Least Significant two bits CCPRxL<5:0>: Not used 2014 Microchip Technology Inc. Preliminary DS40001770A-page 361 PIC16(L)F1615/9 REGISTER 26-4: R/W-0/0 CCPRxH: CCPx HIGH BYTE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 CCPR<15:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset `1' = Bit is set `0' = Bit is cleared bit 7-0 MODE = Capture Mode CCPRxH<7:0>: MSB of captured TMR1 value MODE = Compare Mode CCPRxH<7:0>: MSB compared to TMR1 value MODE = PWM Mode && FMT = 0 CCPRxH<7:2>: Not used CCPRxH<1:0>: CCPW<9:8> -- Pulse width Most Significant two bits MODE = PWM Mode && FMT = 1 CCPRxH<7:0>: CCPW<9:2> -- Pulse width Most Significant eight bits REGISTER 26-5: CCPxCAP: CCPx CAPTURE INPUT SELECTION REGISTER U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- R/W-0/0 R/W-0/0 R/W-0/0 CTS<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset `1' = Bit is set `0' = Bit is cleared bit 7-3 Unimplemented: Read as `0' bit 2-0 CTS<2:0>: Capture Trigger Input Selection bits 111 = LC4_out 110 = LC3_out 101 = LC2_out 100 = LC1_out 011 = IOC_interrupt 010 = C2_OUT_sync 001 = C1_OUT_sync 000 = CCPx pin DS40001770A-page 362 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 TABLE 26-3: Name CCPxCAP CCPxCON SUMMARY OF REGISTERS ASSOCIATED WITH STANDARD PWM Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 -- -- -- -- -- -- EN OE OUT FMT CCPRxL Capture/Compare/PWM Register x (LSB) CCPRxH Capture/Compare/PWM Register x (MSB) CCPTMRS P4TSEL<1:0> Bit 1 Bit 0 CTS<1:0> MODE<3:0> Register on Page 362 359 361 362 P3TSEL<1:0> C2TSEL<1:0> C1TSEL<1:0> 360 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 105 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 106 PIE2 OSFIE C2IE C1IE -- BCL1IE TMR6IE TMR4IE CCP2IE 107 INTCON PR2 T2CON Timer2 Period Register ON 245* CKPS<2:0> OUTPS<3:0> 258 TMR2 Timer2 Module Register 245 PR4 Timer4 Period Register 245* T4CON ON CKPS<2:0> TMR4 Timer4 Module Register PR6 Timer6 Period Register T6CON TMR6 TRISA ON OUTPS<3:0> 258 245 245* CKPS<2:0> OUTPS<3:0> 258 Timer6 Module Register -- -- 245 TRISA5 TRISA4 --(1) TRISA2 TRISA1 TRISA0 159 Legend: -- = Unimplemented location, read as `0'. Shaded cells are not used by the PWM. * Page provides register information. Note 1: Unimplemented, read as `1'. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 363 PIC16(L)F1615/9 27.0 Figure 27-1 shows a simplified block diagram of PWM operation. PULSE-WIDTH MODULATION (PWM) MODULE For a step-by-step procedure on how to set up this module for PWM operation, refer to Section 27.1.9 "Setup for PWM Operation using PWMx Pins". The PWM module generates a Pulse-Width Modulated signal determined by the duty cycle, period, and resolution that are configured by the following registers: * * * * * PR2 T2CON PWMxDCH PWMxDCL PWMxCON FIGURE 27-1: SIMPLIFIED PWM BLOCK DIAGRAM Rev. 10-000022B 9/24/2014 PWMxDCL<7:6> Duty cycle registers PWMxDCH PWMx_out 10-bit Latch (Not visible to user) R Comparator Q 0 1 S To Peripherals PPS PWMx Q TMR2 Module TMR2 Comparator R PWMxPOL (1) RxyPPS TRIS Control T2_match PR2 Note 1: 8-bit timer is concatenated with two bits generated by Fosc or two bits of the internal prescaler to create 10-bit time-base. DS40001770A-page 364 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 27.1 PWMx Pin Configuration All PWM outputs are multiplexed with the PORT data latch. The user must configure the pins as outputs by clearing the associated TRIS bits. Note: 27.1.1 Clearing the PWMxOE bit will relinquish control of the PWMx pin. FUNDAMENTAL OPERATION The PWM module produces a 10-bit resolution output. Timer2 and PR2 set the period of the PWM. The PWMxDCL and PWMxDCH registers configure the duty cycle. The period is common to all PWM modules, whereas the duty cycle is independently controlled. Note: The Timer2 postscaler is not used in the determination of the PWM frequency. The postscaler could be used to have a servo update rate at a different frequency than the PWM output. All PWM outputs associated with Timer2 are set when TMR2 is cleared. Each PWMx is cleared when TMR2 is equal to the value specified in the corresponding PWMxDCH (8 MSb) and PWMxDCL<7:6> (2 LSb) registers. When the value is greater than or equal to PR2, the PWM output is never cleared (100% duty cycle). Note: 27.1.2 The PWMxDCH and PWMxDCL registers are double buffered. The buffers are updated when Timer2 matches PR2. Care should be taken to update both registers before the timer match occurs. When TMR2 is equal to PR2, the following three events occur on the next increment cycle: * TMR2 is cleared * The PWM output is active. (Exception: When the PWM duty cycle = 0%, the PWM output will remain inactive.) * The PWMxDCH and PWMxDCL register values are latched into the buffers. Note: 27.1.4 PWM DUTY CYCLE The PWM duty cycle is specified by writing a 10-bit value to the PWMxDCH and PWMxDCL register pair. The PWMxDCH register contains the eight MSbs and the PWMxDCL<7:6>, the two LSbs. The PWMxDCH and PWMxDCL registers can be written to at any time. Equation 27-2 is used to calculate the PWM pulse width. Equation 27-3 is used to calculate the PWM duty cycle ratio. EQUATION 27-2: PULSE WIDTH Pulse Width = PWMxDCH:PWMxDCL<7:6> T OS C (TMR2 Prescale Value) Note: TOSC = 1/FOSC EQUATION 27-3: DUTY CYCLE RATIO PWM OUTPUT POLARITY PWMxDCH:PWMxDCL<7:6> Duty Cycle Ratio = ----------------------------------------------------------------------------------4 PR2 + 1 The output polarity is inverted by setting the PWMxPOL bit of the PWMxCON register. 27.1.3 The Timer2 postscaler has no effect on the PWM operation. PWM PERIOD The PWM period is specified by the PR2 register of Timer2. The PWM period can be calculated using the formula of Equation 27-1. The 8-bit timer TMR2 register is concatenated with the two Least Significant bits of 1/FOSC, adjusted by the Timer2 prescaler to create the 10-bit time base. The system clock is used if the Timer2 prescaler is set to 1:1. EQUATION 27-1: Figure 27-2 shows a waveform of the PWM signal when the duty cycle is set for the smallest possible pulse. PWM PERIOD PWM Period = PR2 + 1 4 T OSC FIGURE 27-2: PWM OUTPUT (TMR2 Prescale Value) Q1 Note: Q2 Q3 Q4 Rev. 10-000023A 7/30/2013 TOSC = 1/FOSC FOSC PWM Pulse Width TMR2 = 0 TMR2 = PWMxDC TMR2 = PR2 2014 Microchip Technology Inc. Preliminary DS40001770A-page 365 PIC16(L)F1615/9 27.1.5 PWM RESOLUTION The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles. The maximum PWM resolution is ten bits when PR2 is 255. The resolution is a function of the PR2 register value as shown by Equation 27-4. EQUATION 27-4: PWM RESOLUTION log 4 PR2 + 1 Resolution = ------------------------------------------ bits log 2 Note: If the pulse width value is greater than the period the assigned PWM pin(s) will remain unchanged. TABLE 27-1: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz) PWM Frequency 0.31 kHz Timer Prescale PR2 Value 78.12 kHz 156.3 kHz 208.3 kHz 64 4 1 1 1 1 0xFF 0xFF 0x3F 0x1F 0x17 10 10 10 8 7 6.6 EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz) PWM Frequency 0.31 kHz Timer Prescale PR2 Value 4.90 kHz 19.61 kHz 76.92 kHz 153.85 kHz 200.0 kHz 64 4 1 1 1 1 0x65 0x65 0x65 0x19 0x0C 0x09 8 8 8 6 5 5 Maximum Resolution (bits) 27.1.6 19.53 kHz 0xFF Maximum Resolution (bits) TABLE 27-2: 4.88 kHz OPERATION IN SLEEP MODE In Sleep mode, the TMR2 register will not increment and the state of the module will not change. If the PWMx pin is driving a value, it will continue to drive that value. When the device wakes up, TMR2 will continue from its previous state. 27.1.7 CHANGES IN SYSTEM CLOCK FREQUENCY The PWM frequency is derived from the system clock frequency (FOSC). Any changes in the system clock frequency will result in changes to the PWM frequency. Refer to Section 5.0 "Oscillator Module" for additional details. 27.1.8 EFFECTS OF RESET Any Reset will force all ports to Input mode and the PWM registers to their Reset states. DS40001770A-page 366 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 27.1.9 SETUP FOR PWM OPERATION USING PWMx PINS The following steps should be taken when configuring the module for PWM operation using the PWMx pins: 1. 2. 3. 4. 5. 6. 7. 8. Disable the PWMx pin output driver(s) by setting the associated TRIS bit(s). Clear the PWMxCON register. Load the PR2 register with the PWM period value. Clear the PWMxDCH register and bits <7:6> of the PWMxDCL register. Configure and start Timer2: * Clear the TMR2IF interrupt flag bit of the PIR1 register. See note below. * Configure the CKPS bits of the T2CON register with the Timer2 prescale value. * Enable Timer2 by setting the ON bit of the T2CON register. Enable PWM output pin and wait until Timer2 overflows, TMR2IF bit of the PIR1 register is set. See note below. Enable the PWMx pin output driver(s) by clearing the associated TRIS bit(s) and setting the PWMxOE bit of the PWMxCON register. Configure the PWM module by loading the PWMxCON register with the appropriate values. Note 1: In order to send a complete duty cycle and period on the first PWM output, the above steps must be followed in the order given. If it is not critical to start with a complete PWM signal, then move Step 8 to replace Step 4. 2: For operation with other peripherals only, disable PWMx pin outputs. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 367 PIC16(L)F1615/9 27.2 Register Definitions: PWM Control REGISTER 27-1: PWMxCON: PWM CONTROL REGISTER R/W-0/0 R/W-0/0 R-0/0 R/W-0/0 U-0 U-0 U-0 U-0 PWMxEN PWMxOE PWMxOUT PWMxPOL -- -- -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 PWMxEN: PWM Module Enable bit 1 = PWM module is enabled 0 = PWM module is disabled bit 6 PWMxOE: PWM Module Output Enable bit 1 = Output to PWMx pin is enabled 0 = Output to PWMx pin is disabled bit 5 PWMxOUT: PWM Module Output Value bit bit 4 PWMxPOL: PWMx Output Polarity Select bit 1 = PWM output is active-low 0 = PWM output is active-high bit 3-0 Unimplemented: Read as `0' REGISTER 27-2: R/W-x/u PWMxDCH: PWM DUTY CYCLE HIGH BITS R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u PWMxDCH<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 PWMxDCH<7:0>: PWM Duty Cycle Most Significant bits These bits are the MSbs of the PWM duty cycle. The two LSbs are found in the PWMxDCL register. REGISTER 27-3: R/W-x/u PWMxDCL: PWM DUTY CYCLE LOW BITS R/W-x/u PWMxDCL<7:6> U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 PWMxDCL<7:6>: PWM Duty Cycle Least Significant bits These bits are the LSbs of the PWM duty cycle. The MSbs are found in the PWMxDCH register. bit 5-0 Unimplemented: Read as `0' DS40001770A-page 368 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 TABLE 27-3: Name SUMMARY OF REGISTERS ASSOCIATED WITH PWM Bit 7 Bit 6 Bit 5 PR2 PWM1CON Bit 4 PWM2CON PWM1EN PWM1OE -- PWM1DCL<7:6> PWM2EN PWM2OE PWM3CON EN -- PWM2OUT PWM2POL -- -- -- -- DC<1:0> -- EN -- -- -- -- 368 -- -- -- -- 368 368 368 -- -- -- -- 368 OUT POL -- -- -- -- 368 368 -- -- -- -- -- -- 368 OUT POL -- -- -- -- 368 -- -- -- -- DC<9:2> PWM4DCL -- DC<1:0> ON -- 368 CKPS<2:0> TMR2 OUTPS<3:0> TRISC7 -- (1) TRISC6 (1) 368 148 Timer2 module Register -- 368 -- PWM4DCH TRISC 146* DC<9:2> PWM3DCL Register on Page -- PWM3DCH Legend: * Note 1: Bit 0 PWM2DCH<7:0> PWM2DCL<7:6> TRISA Bit 1 PWM1DCH<7:0> PWM2DCL T2CON -- PWM1OUT PWM1POL PWM2DCH PWM4CON Bit 2 Timer2 module Period Register PWM1DCH PWM1DCL Bit 3 245* TRISA5 TRISA4 --(1) TRISA2 TRISA1 TRISA0 159 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 173 - = Unimplemented locations, read as `0', u = unchanged, x = unknown. Shaded cells are not used by the PWM. Page provides register information. Unimplemented, read as `1'. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 369 PIC16(L)F1615/9 NOTES: DS40001770A-page 370 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 28.0 COMPLEMENTARY WAVEFORM GENERATOR (CWG) MODULE The Complementary Waveform Generator (CWG) produces half-bridge, full-bridge, and steering of PWM waveforms. It is backwards compatible with previous ECCP functions. The CWG has the following features: * Six operating modes: - Synchronous Steering mode - Asynchronous Steering mode - Full-Bridge mode, Forward - Full-Bridge mode, Reverse - Half-Bridge mode - Push-Pull mode * Output polarity control * Output steering - Synchronized to rising event - Immediate effect * Independent 6-bit rising and falling event deadband timers - Clocked dead band - Independent rising and falling dead-band enables * Auto-shutdown control with: - Selectable shutdown sources - Auto-restart enable - Auto-shutdown pin override control 2014 Microchip Technology Inc. 28.1 Fundamental Operation The CWG module can operate in six different modes, as specified by MODE of the CWGxCON0 register: * Half-Bridge mode (Figure 28-9) * Push-Pull mode (Figure 28-2) - Full-Bridge mode, Forward (Figure 28-3) - Full-Bridge mode, Reverse (Figure 28-3) * Steering mode (Figure 28-10) * Synchronous Steering mode (Figure 28-11) It may be necessary to guard against the possibility of circuit faults or a feedback event arriving too late or not at all. In this case, the active drive must be terminated before the Fault condition causes damage. Thus, all output modes support auto-shutdown, which is covered in 28.10 "Auto-Shutdown". 28.1.1 HALF-BRIDGE MODE In Half-Bridge mode, two output signals are generated as true and inverted versions of the input as illustrated in Figure 28-9. A non-overlap (dead-band) time is inserted between the two outputs to prevent shoot through current in various power supply applications. Dead-band control is described in Section 28.5 "Dead-Band Control". The unused outputs CWGxC and CWGxD drive similar signals, with polarity independently controlled by the POLC and POLD bits of the CWGxCON1 register, respectively. Preliminary DS40001770A-page 371 SIMPLIFIED CWG BLOCK DIAGRAM (HALF-BRIDGE MODE) Rev. 10-000166B 8/29/2014 CWG_data Rising Deadband Block See CWGxISM Register CWG_dataA clock signal_out CWG_dataC signal_in D Q CWGxISM<3:0> E Preliminary R Q Falling Deadband Block CWG_dataB clock signal_out signal_in EN SHUTDOWN HFINTOSC 1 FOSC 0 CWGxCLK<0> CWG_dataD PIC16(L)F1615/9 DS40001770A-page 372 FIGURE 28-1: 2014 Microchip Technology Inc. PIC16(L)F1615/9 28.1.2 PUSH-PULL MODE In Push-Pull mode, two output signals are generated, alternating copies of the input as illustrated in Figure 28-2. This alternation creates the push-pull effect required for driving some transformer-based power supply designs. The push-pull sequencer is reset whenever EN = 0 or if an auto-shutdown event occurs. The sequencer is clocked by the first input pulse, and the first output appears on CWGxA. The unused outputs CWGxC and CWGxD drive copies of CWGxA and CWGxB, respectively, but with polarity controlled by the POLC and POLD bits of the CWGxCON1 register, respectively. 28.1.3 FULL-BRIDGE MODES In Forward and Reverse Full-Bridge modes, three outputs drive static values while the fourth is modulated by the input data signal. In Forward Full-Bridge mode, CWGxA is driven to its active state, CWGxB and CWGxC are driven to their inactive state, and CWGxD is modulated by the input signal. In Reverse Full-Bridge mode, CWGxC is driven to its active state, CWGxA and CWGxD are driven to their inactive states, and CWGxB is modulated by the input signal. In Full-Bridge mode, the dead-band period is used when there is a switch from forward to reverse or vice-versa. This dead-band control is described in Section 28.5 "Dead-Band Control", with additional details in Section 28.6 "Rising Edge and Reverse Dead Band" and Section 28.7 "Falling Edge and Forward Dead Band". The mode selection may be toggled between forward and reverse toggling the MODE<0> bit of the CWGxCON0 while keeping MODE<2:1> static, without disabling the CWG module. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 373 SIMPLIFIED CWG BLOCK DIAGRAM (PUSH-PULL MODE) Rev. 10-000167B 8/29/2014 CWG_data See CWGxISM Register D Q CWG_dataA Q CWG_dataC R CWG_dataB Preliminary D Q E Q CWG_dataD CWGxISM<3:0> EN SHUTDOWN R PIC16(L)F1615/9 DS40001770A-page 374 FIGURE 28-2: 2014 Microchip Technology Inc. 2014 Microchip Technology Inc. FIGURE 28-3: SIMPLIFIED CWG BLOCK DIAGRAM (FORWARD AND REVERSE FULL-BRIDGE MODES) Rev. 10-000165B 8/29/2014 Reverse Deadband Block MODE0 clock signal_out See CWGxISM Register signal_in CWG_dataA D D Q Q CWG_dataB Q CWG_dataC CWGxISM<3:0> E Preliminary R CWG_dataD Q clock signal_out signal_in Forward Deadband Block EN CWG_data SHUTDOWN HFINTOSC FOSC 0 DS40001770A-page 375 PIC16(L)F1615/9 CWGxCLK<0> 1 PIC16(L)F1615/9 28.1.4 STEERING MODES In Steering modes, the data input can be steered to any or all of the four CWG output pins. In Synchronous Steering mode, changes to steering selection registers take effect on the next rising input. In Non-Synchronous mode, steering takes effect on the next instruction cycle. Additional details are provided in Section 28.9 "CWG Steering Mode". DS40001770A-page 376 Preliminary 2014 Microchip Technology Inc. 2014 Microchip Technology Inc. FIGURE 28-4: SIMPLIFIED CWG BLOCK DIAGRAM (OUTPUT STEERING MODES) Rev. 10-000164B 8/29/2014 See CWGxISM Register CWG_dataA CWG_data CWG_dataB CWG_dataC Preliminary CWG_dataD D Q CWGxISM <3:0> E R Q EN DS40001770A-page 377 PIC16(L)F1615/9 SHUTDOWN PIC16(L)F1615/9 28.2 Clock Source The CWG module allows the following clock sources to be selected: * Fosc (system clock) * HFINTOSC (16 MHz only) The clock sources are selected using the CS bit of the CWGxCLKCON register. 28.3 Selectable Input Sources The CWG generates the output waveforms from the input sources in Table 28-1. TABLE 28-1: SELECTABLE INPUT SOURCES Source Peripheral Signal Name CWG input pin CWGxIN pin Comparator C1 C1_OUT_sync Comparator C2 C2_OUT_sync CCP1 CCP1_out CCP2 CCP2_out CLC1 LC1_out CLC2 LC2_out CLC3 LC3_out CLC4 LC4_out PWM3 PWM3_out PWM4 PWM4_out The input sources are selected using the CWGxISM register. 28.4 28.4.1 Output Control OUTPUT ENABLES Each CWG output pin has individual output enable control. Output enables are selected with the Gx1OEx <3:0> bits. When an output enable control is cleared, the module asserts no control over the pin. When an output enable is set, the override value or active PWM waveform is applied to the pin per the port priority selection. The output pin enables are dependent on the module enable bit, EN of the CWGxCON0 register. When EN is cleared, CWG output enables and CWG drive levels have no effect. 28.4.2 POLARITY CONTROL The polarity of each CWG output can be selected independently. When the output polarity bit is set, the corresponding output is active-high. Clearing the output polarity bit configures the corresponding output as active-low. However, polarity does not affect the override levels. Output polarity is selected with the POLx bits of the CWGxCON1. Auto-shutdown and steering options are unaffected by polarity. DS40001770A-page 378 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 FIGURE 28-5: CWG OUTPUT BLOCK DIAGRAM Rev. 10-000171B 9/24/2014 LSAC<1:0> CWG_dataA 1 POLA OVRA `1' 11 `0' 10 High Z 01 00 0 RxyPPS TRIS Control 1 0 PPS CWGxA STRA(1) LSBD<1:0> CWG_dataB 1 POLB OVRB `1' 11 `0' 10 High Z 01 00 0 RxyPPS TRIS Control 1 0 CWGxB PPS STRB(1) LSAC<1:0> CWG_dataC 1 POLC OVRC `1' 11 `0' 10 High Z 01 00 0 RxyPPS TRIS Control 1 0 CWGxC PPS STRC(1) LSBD<1:0> CWG_dataD 1 POLD OVRD `1' 11 `0' 10 High Z 01 00 0 RxyPPS TRIS Control 1 0 PPS CWGxD STRD(1) CWG_shutdown Note 1: 2014 Microchip Technology Inc. STRx is held to 1 in all modes other than Output Steering Mode. Preliminary DS40001770A-page 379 PIC16(L)F1615/9 28.5 Dead-Band Control 28.7 The dead-band control provides non-overlapping PWM signals to prevent shoot-through current in PWM switches. Dead-band operation is employed for HalfBridge and Full-Bridge modes. The CWG contains two 6-bit dead-band counters. One is used for the rising edge of the input source control in Half-Bridge mode or for reverse dead-band Full-Bridge mode. The other is used for the falling edge of the input source control in Half-Bridge mode or for forward dead band in FullBridge mode. Dead band is timed by counting CWG clock periods from zero up to the value in the rising or falling deadband counter registers. See CWGxDBR and CWGxDBF registers, respectively. 28.5.1 Falling Edge and Forward Dead Band CWGxDBF controls the dead-band time at the leading edge of CWGxB (Half-Bridge mode) or the leading edge of CWGxD (Full-Bridge mode). The CWGxDBF value is double-buffered. When EN = 0, the CWGxDBF register is loaded immediately when CWGxDBF is written. When EN = 1 then software must set the LD bit of the CWGxCON0 register, and the buffer will be loaded at the next falling edge of the CWG input signal. If the input source signal is not present for enough time for the count to be completed, no output will be seen on the respective output. Refer to Figure 28.6 and Figure 28-7 for examples. DEAD-BAND FUNCTIONALITY IN HALF-BRIDGE MODE In Half-Bridge mode, the dead-band counters dictate the delay between the falling edge of the normal output and the rising edge of the inverted output. This can be seen in Figure 28-9. 28.5.2 DEAD-BAND FUNCTIONALITY IN FULL-BRIDGE MODE In Full-Bridge mode, the dead-band counters are used when undergoing a direction change. The MODE<0> bit of the CWGxCON0 register can be set or cleared while the CWG is running, allowing for changes from Forward to Reverse mode. The CWGxA and CWGxC signals will change immediately upon the first rising input edge following a direction change, but the modulated signals (CWGxB or CWGxD, depending on the direction of the change) will experience a delay dictated by the dead-band counters. This is demonstrated in Figure 28-3. 28.6 Rising Edge and Reverse Dead Band CWGxDBR controls the rising edge dead-band time at the leading edge of CWGxA (Half-Bridge mode) or the leading edge of CWGxB (Full-Bridge mode). The CWGxDBR value is double-buffered. When EN = 0, the CWGxDBR register is loaded immediately when CWGxDBR is written. When EN = 1, then software must set the LD bit of the CWGxCON0 register, and the buffer will be loaded at the next falling edge of the CWG input signal. If the input source signal is not present for enough time for the count to be completed, no output will be seen on the respective output. DS40001770A-page 380 Preliminary 2014 Microchip Technology Inc. 2014 Microchip Technology Inc. FIGURE 28-6: DEAD-BAND OPERATION CWGXDBR = 0X01, CWGXDBF = 0X02 cwg_clock Input Source CWGxA CWGxB Preliminary FIGURE 28-7: DEAD-BAND OPERATION, CWGXDBR = 0X03, CWGXDBF = 0X04, SOURCE SHORTER THAN DEAD BAND cwg_clock CWGxA CWGxB DS40001770A-page 381 source shorter than dead band PIC16(L)F1615/9 Input Source PIC16(L)F1615/9 28.8 EQUATION 28-1: Dead-Band Uncertainty When the rising and falling edges of the input source are asynchronous to the CWG clock, it creates uncertainty in the dead-band time delay. The maximum uncertainty is equal to one CWG clock period. Refer to Equation 28-1 for more details. DEAD-BAND UNCERTAINTY 1 TDEADBAND_UNCERTAINTY = ----------------------------Fcwg_clock Example: FCWG_CLOCK = 16 MHz Therefore: 1 TDEADBAND_UNCERTAINTY = ----------------------------Fcwg_clock 1 = -----------------16MHz = 62.5ns FIGURE 28-8: EXAMPLE OF PWM DIRECTION CHANGE MODE0 CWGxA CWGxB CWGxC CWGxD No delay CWGxDBR No delay CWGxDBF CWGx_data Note 1:WGPOL{ABCD} = 0 2: The direction bit MODE<0> (Register 28-1) can be written any time during the PWM cycle, and takes effect at the next rising CWGx_data. 3: When changing directions, CWGxA and CWGxC switch at rising CWGx_data; modulated CWGxB and CWGxD are held inactive for the dead band duration shown; dead band affects only the first pulse after the direction change. FIGURE 28-9: CWG HALF-BRIDGE MODE OPERATION CWGx_clock CWGxA CWGxC Falling Event Dead Band Rising Event Dead Band Rising Event D Falling Event Dead Band CWGxB CWGxD CWGx_data Note: CWGx_rising_src = CCP1_out, CWGx_falling_src = ~CCP1_out DS40001770A-page 382 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 28.9 28.9.1 CWG Steering Mode In Steering mode (MODE = 00x), the CWG allows any combination of the CWGxx pins to be the modulated signal. The same signal can be simultaneously available on multiple pins, or a fixed-value output can be presented. When the respective STRx bit of CWGxOCON0 is `0', the corresponding pin is held at the level defined. When the respective STRx bit of CWGxOCON0 is `1', the pin is driven by the input data signal. The user can assign the input data signal to one, two, three, or all four output pins. The POLx bits of the CWGxCON1 register control the signal polarity only when STRx = 1. The CWG auto-shutdown operation also applies in Steering modes as described in Section 28.10 "AutoShutdown". An auto-shutdown event will only affect pins that have STRx = 1. FIGURE 28-10: STEERING SYNCHRONIZATION Changing the MODE bits allows for two modes of steering, synchronous and asynchronous. When MODE = 000, the steering event is asynchronous and will happen at the end of the instruction that writes to STRx (that is, immediately). In this case, the output signal at the output pin may be an incomplete waveform. This can be useful for immediately removing a signal from the pin. When MODE = 001, the steering update is synchronous and occurs at the beginning of the next rising edge of the input data signal. In this case, steering the output on/off will always produce a complete waveform. Figure 28-10 and Figure 28-11 illustrate the timing of asynchronous and synchronous steering, respectively. EXAMPLE OF STEERING EVENT AT END OF INSTRUCTION (MODE<2:0> = 000) Rising Event CWGx_data (Rising and Falling Source) STR<D:A> CWGx<D:A> OVR<D:A> Data OVR<D:A> follows CWGx_data FIGURE 28-11: EXAMPLE OF STEERING EVENT AT BEGINNING OF INSTRUCTION (MODE<2:0> = 001) CWGx_data (Rising and Falling Source) STR<D:A> CWGx<D:A> OVR<D:A> Data OVR<D:A> Data follows CWGx_data 2014 Microchip Technology Inc. Preliminary DS40001770A-page 383 PIC16(L)F1615/9 28.10 Auto-Shutdown 28.11 Operation During Sleep Auto-shutdown is a method to immediately override the CWG output levels with specific overrides that allow for safe shutdown of the circuit. The shutdown state can be either cleared automatically or held until cleared by software. The auto-shutdown circuit is illustrated in Figure 28-12. The CWG module operates independently from the system clock and will continue to run during Sleep, provided that the clock and input sources selected remain active. 28.10.1 * CWG module is enabled * Input source is active * HFINTOSC is selected as the clock source, regardless of the system clock source selected. SHUTDOWN The shutdown state can be entered by either of the following two methods: * Software generated * External Input 28.10.1.1 Software Generated Shutdown Setting the SHUTDOWN bit of the CWGxAS0 register will force the CWG into the shutdown state. When the auto-restart is disabled, the shutdown state will persist as long as the SHUTDOWN bit is set. The HFINTOSC remains active during Sleep when all the following conditions are met: In other words, if the HFINTOSC is simultaneously selected as the system clock and the CWG clock source, when the CWG is enabled and the input source is active, then the CPU will go idle during Sleep, but the HFINTOSC will remain active and the CWG will continue to operate. This will have a direct effect on the Sleep mode current. When auto-restart is enabled, the SHUTDOWN bit will clear automatically and resume operation on the next rising edge event. 28.10.2 EXTERNAL INPUT SOURCE External shutdown inputs provide the fastest way to safely suspend CWG operation in the event of a Fault condition. When any of the selected shutdown inputs goes active, the CWG outputs will immediately go to the selected override levels without software delay. Several input sources can be selected to cause a shutdown condition. All input sources are active-low. The sources are: * * * * * * Comparator C1_OUT_sync Comparator C2_OUT_sync Timer 2 - TMR2_postscaled Timer 4 - TMR4_postscaled Timer 6 - TMR6_postscaled CWGxIN input pin Shutdown inputs are selected using the CWGxAS1 register (Register 28-6). Note: Shutdown inputs are level sensitive, not edge sensitive. The shutdown state cannot be cleared, except by disabling autoshutdown, as long as the shutdown input level persists. DS40001770A-page 384 Preliminary 2014 Microchip Technology Inc. 2014 Microchip Technology Inc. FIGURE 28-12: CWG SHUTDOWN BLOCK DIAGRAM Write `1' to SHUTDOWN bit Rev. 10-000172B 7/9/2014 CWGxIN INAS C1OUT_sync C1AS C2OUT_sync C2AS TMR2_postscaled TMR2AS TMR4_postscaled TMR4AS TMR6_postscaled TMR6AS S Q SHUTDOWN S D FREEZE REN Write `0' to SHUTDOWN bit Q CWG_shutdown R CWG_data CK Preliminary PIC16(L)F1615/9 DS40001770A-page 385 PIC16(L)F1615/9 28.12 Configuring the CWG 28.12.2 The following steps illustrate how to properly configure the CWG. After an auto-shutdown event has occurred, there are two ways to resume operation: 1. * Software controlled * Auto-restart 2. 3. 4. 5. Ensure that the TRIS control bits corresponding to the desired CWG pins for your application are set so that the pins are configured as inputs. Clear the EN bit, if not already cleared. Set desired mode of operation with the MODE bits. Set desired dead-band times, if applicable to mode, with the CWGxDBR and CWGxDBF registers. Setup the following controls in the CWGxAS0 and CWGxAS1 registers. a. Select the desired shutdown source. b. Select both output overrides to the desired levels (this is necessary even if not using autoshutdown because start-up will be from a shutdown state). c. Set which pins will be affected by auto-shutdown with the CWGxAS1 register. d. Set the SHUTDOWN bit and clear the REN bit. 6. 7. Select the desired input source using the CWGxISM register. Configure the following controls. a. Select desired clock source CWGxCLKCON register. using the AUTO-SHUTDOWN RESTART The restart method is selected with the REN bit of the CWGxCON2 register. Waveforms of software controlled and automatic restarts are shown in Figure 28-13 and Figure 28-14. 28.12.2.1 Software Controlled Restart When the REN bit of the CWGxAS0 register is cleared, the CWG must be restarted after an auto-shutdown event by software. Clearing the shutdown state requires all selected shutdown inputs to be low, otherwise the SHUTDOWN bit will remain set. The overrides will remain in effect until the first rising edge event after the SHUTDOWN bit is cleared. The CWG will then resume operation. 28.12.2.2 Auto-Restart When the REN bit of the CWGxCON2 register is set, the CWG will restart from the auto-shutdown state automatically. The SHUTDOWN bit will clear automatically when all shutdown sources go low. The overrides will remain in effect until the first rising edge event after the SHUTDOWN bit is cleared. The CWG will then resume operation. b. Select the desired output polarities using the CWGxCON1 register. c. Set the output enables for the desired outputs. 8. 9. Set the EN bit. Clear TRIS control bits corresponding to the desired output pins to configure these pins as outputs. 10. If auto-restart is to be used, set the REN bit and the SHUTDOWN bit will be cleared automatically. Otherwise, clear the SHUTDOWN bit to start the CWG. 28.12.1 PIN OVERRIDE LEVELS The levels driven to the output pins, while the shutdown input is true, are controlled by the LSBD and LSAC bits of the CWGxAS0 register. LSBD<1:0> controls the CWGxB and D override levels and LSAC<1:0> controls the CWGxA and C override levels. The control bit logic level corresponds to the output logic drive level while in the shutdown state. The polarity control does not affect the override level. DS40001770A-page 386 Preliminary 2014 Microchip Technology Inc. 2014 Microchip Technology Inc. FIGURE 28-13: SHUTDOWN FUNCTIONALITY, AUTO-RESTART DISABLED (REN = 0, LSAC = 01, LSBD = 01) Shutdown Event Ceases REN Cleared by Software CWG Input Source Shutdown Source SHUTDOWN CWGxA CWGxC Tri-State (No Pulse) CWGxB CWGxD Tri-State (No Pulse) No Shutdown Preliminary Shutdown Output Resumes PIC16(L)F1615/9 DS40001770A-page 387 SHUTDOWN FUNCTIONALITY, AUTO-RESTART ENABLED (REN = 1, LSAC = 01, LSBD = 01) Shutdown Event Ceases REN auto-cleared by hardware CWG Input Source Shutdown Source SHUTDOWN CWGxA CWGxC CWGxB CWGxD Tri-State (No Pulse) Tri-State (No Pulse) No Shutdown Preliminary Shutdown Output Resumes PIC16(L)F1615/9 DS40001770A-page 388 FIGURE 28-14: 2014 Microchip Technology Inc. PIC16(L)F1615/9 28.13 Register Definitions: CWG Control REGISTER 28-1: CWGxCON0: CWGx CONTROL REGISTER 0 R/W-0/0 R/W/HC-0/0 U-0 U-0 U-0 EN LD(1) -- -- -- R/W-0/0 R/W-0/0 R/W-0/0 MODE<2:0> bit 7 bit 0 Legend: HC = Bit is cleared by hardware HS = Bit is set by hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7 EN: CWGx Enable bit 1 = Module is enabled 0 = Module is disabled bit 6 LD: CWGx Load Buffer bits(1) 1 = Buffers to be loaded on the next rising/falling event 0 = Buffers not loaded bit 5-3 Unimplemented: Read as `0' bit 2-0 MODE<2:0>: CWGx Mode bits 111 = Reserved 110 = Reserved 101 = CWG outputs operate in Push-Pull mode 100 = CWG outputs operate in Half-Bridge mode 011 = CWG outputs operate in Reverse Full-Bridge mode 010 = CWG outputs operate in Forward Full-Bridge mode 001 = CWG outputs operate in Synchronous Steering mode 000 = CWG outputs operate in Steering mode Note 1: This bit can only be set after EN = 1 and cannot be set in the same instruction that EN is set. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 389 PIC16(L)F1615/9 REGISTER 28-2: CWGxCON1: CWGx CONTROL REGISTER 1 U-0 U-0 R-x U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 -- -- IN -- POLD POLC POLB POLA bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-6 Unimplemented: Read as `0' bit 5 IN: CWG Input Value bit 4 Unimplemented: Read as `0' bit 3 POLD: CWGxD Output Polarity bit 1 = Signal output is inverted polarity 0 = Signal output is normal polarity bit 2 POLC: CWGxC Output Polarity bit 1 = Signal output is inverted polarity 0 = Signal output is normal polarity bit 1 POLB: CWGxB Output Polarity bit 1 = Signal output is inverted polarity 0 = Signal output is normal polarity bit 0 POLA: CWGxA Output Polarity bit 1 = Signal output is inverted polarity 0 = Signal output is normal polarity DS40001770A-page 390 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 REGISTER 28-3: CWGxDBR: CWGx RISING DEAD-BAND COUNTER REGISTER U-0 U-0 -- -- R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u DBR<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-6 Unimplemented: Read as `0' bit 5-0 DBR<5:0>: Rising Event Dead-Band Value for Counter bits REGISTER 28-4: CWGxDBF: CWGx FALLING DEAD-BAND COUNTER REGISTER U-0 U-0 -- -- R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u DBF<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-6 Unimplemented: Read as `0' bit 5-0 DBF<5:0>: Falling Event Dead-Band Value for Counter bits 2014 Microchip Technology Inc. Preliminary DS40001770A-page 391 PIC16(L)F1615/9 REGISTER 28-5: CWGxAS0: CWGx AUTO-SHUTDOWN CONTROL REGISTER 0 R/W/HS-0/0 R/W-0/0 SHUTDOWN(1, 2) REN R/W-0/0 R/W-1/1 R/W-0/0 LSBD<1:0> R/W-1/1 LSAC<1:0> U-0 U-0 -- -- bit 7 bit 0 Legend: HC = Bit is cleared by hardware HS = Bit is set by hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7 SHUTDOWN: Auto-Shutdown Event Status bit(1, 2) 1 = An Auto-Shutdown state is in effect 0 = No Auto-shutdown event has occurred bit 6 REN: Auto-Restart Enable bit 1 = Auto-restart enabled 0 = Auto-restart disabled bit 5-4 LSBD<1:0>: CWGxB and CWGxD Auto-Shutdown State Control bits 11 = A logic `1' is placed on CWGxB/D when an auto-shutdown event is present 10 = A logic `0' is placed on CWGxB/D when an auto-shutdown event is present 01 = Pin is tri-stated on CWGxB/D when an auto-shutdown event is present 00 = The inactive state of the pin, including polarity, is placed on CWGxB/D after the required dead-band interval bit 3-2 LSAC<1:0>: CWGxA and CWGxC Auto-Shutdown State Control bits 11 = A logic `1' is placed on CWGxA/C when an auto-shutdown event is present 10 = A logic `0' is placed on CWGxA/C when an auto-shutdown event is present 01 = Pin is tri-stated on CWGxA/C when an auto-shutdown event is present 00 = The inactive state of the pin, including polarity, is placed on CWGxA/C after the required dead-band interval bit 1-0 Unimplemented: Read as `0' Note 1: This bit may be written while EN = 0 (CWGxCON0 register) to place the outputs into the shutdown configuration. 2: The outputs will remain in auto-shutdown state until the next rising edge of the input signal after this bit is cleared. DS40001770A-page 392 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 REGISTER 28-6: U-1 CWGxAS1: CWGx AUTO-SHUTDOWN CONTROL REGISTER 1 R/W-0/0 -- TMR6AS R/W-0/0 TMR4AS R/W-0/0 TMR2AS U-1 R/W-0/0 R/W-0/0 R/W-0/0 -- C2AS(1) C1AS INAS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7 Unimplemented: Read as `1' bit 6 TMR6AS: TMR6 Postscale Output bit 1 = TMR6 postscale shut-down is enabled 0 = TMR6 postscale shut-down is disabled bit 5 TMR4AS: TMR4 Postscale Output bit 1 = TMR4 postscale shut-down is enabled 0 = TMR4 postscale shut-down is disabled bit 4 TMR2AS: TMR2 Postscale Output bit 1 = TMR2 postscale shut-down is enabled 0 = TMR2 postscale shut-down is disabled bit 3 Unimplemented: Read as `1' bit 2 C2AS: Comparator C2 Output bit 1 = C2 output shut-down is enabled 0 = C2 output shut-down is disabled bit 1 C1AS: Comparator C1 Output bit 1 = C1 output shut-down is enabled 0 = C1 output shut-down is disabled bit 0 INAS: CWGx Input Pin bit 1 = CWGxIN input pin shut-down is enabled 0 = CWGxIN input pin shut-down is disabled 2014 Microchip Technology Inc. Preliminary DS40001770A-page 393 PIC16(L)F1615/9 CWGxOCON0: CWGx STEERING CONTROL REGISTER(1) REGISTER 28-7: R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 OVRD OVRC OVRB OVRA STRD(2) STRC(2) STRB(2) STRA(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7 OVRD: Steering Data D bit bit 6 OVRC: Steering Data C bit bit 5 OVRB: Steering Data B bit bit 4 OVRA: Steering Data A bit bit 3 STRD: Steering Enable D bit(2) 1 = CWGxD output has the CWGx_data waveform with polarity control from POLD bit 0 = CWGxD output is assigned the value of OVRD bit bit 2 STRC: Steering Enable C bit(2) 1 = CWGxC output has the CWGx_data waveform with polarity control from POLC bit 0 = CWGxC output is assigned the value of OVRC bit bit 1 STRB: Steering Enable B bit(2) 1 = CWGxB output has the CWGx_data waveform with polarity control from POLB bit 0 = CWGxB output is assigned the value of OVRB bit bit 0 STRA: Steering Enable A bit(2) 1 = CWGxA output has the CWGx_data waveform with polarity control from POLA bit 0 = CWGxA output is assigned the value of OVRA bit Note 1: The bits in this register apply only when MODE<2:0> = 00x. 2: This bit is effectively double-buffered when MODE<2:0> = 001. DS40001770A-page 394 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 REGISTER 28-8: CWGxOCON1: CWGx OUTPUT ENABLE REGISTER 1 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 -- -- -- -- OED OEC OEB OEA bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-4 Unimplemented: Read as `0' bit 3 OED: CWGx D Output Pin Enable bit 1 = CWGx D output pin is enabled 0 = CWGx D output pin is disabled bit 2 OEC: CWGx C Output Pin Enable bit 1 = CWGx C output pin is enabled 0 = CWGx C output pin is disabled bit 1 OEB: CWGx B Output Pin Enable bit 1 = CWGx B output pin is enabled 0 = CWGx B output pin is disabled bit 0 OEA: CWGx A Output Pin Enable bit 1 = CWGx A output pin is enabled 0 = CWGx A output pin is disabled 2014 Microchip Technology Inc. Preliminary DS40001770A-page 395 PIC16(L)F1615/9 REGISTER 28-9: CWGxCLKCON: CWGx CLOCK SELECTION CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 -- -- -- -- -- -- -- CS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-1 Unimplemented: Read as `0' bit 0 CS: CWGx Clock Selection bit 1 = HFINTOSC 16 MHz is selected 0 = FOSC is selected REGISTER 28-10: CWGxISM: CWGx INPUT SELECTION REGISTER U-0 U-0 U-0 U-0 -- -- -- -- R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 IS<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-4 Unimplemented: Read as `0' bit 3-0 IS<3:0>: CWGx Input Selection bits 1111 = Reserved. No channel connected. * * * 1011 = Reserved. No channel connected. 1010 = PWM4_out 1001 = PWM3_out 1000 = LC4_out 0111 = LC3_out 0110 = LC2_out 0101 = LC1_out 0100 = CCP2_out 0011 = CCP1_out 0010 = C2_OUT_sync 0001 = C1_OUT_sync 0000 = CWGxIN pin DS40001770A-page 396 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 TABLE 28-2: Name SUMMARY OF REGISTERS ASSOCIATED WITH CWG Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 LSBD<1:0> Bit 2 Bit 1 LSAC<1:0> Bit 0 Register on Page CWG1AS0 SHUTDOWN REN -- -- 392 CWG1AS1 -- TMR6AS TMR4AS TMR2AS -- C2AS C1AS INAS 393 CWG1CLKCON -- -- -- -- -- -- -- CS CWG1CON0 EN LD -- -- -- IN -- POLD MODE<2:0> 396 394 CWG1CON1 -- -- CWG1DBF -- -- CWG1DBR -- -- CWG1ISM -- -- -- -- CWG1OCON0 OVRD OVRC OVRB OVRA STRD STRC STRB STRA 394 CWG1OCON1 -- -- -- -- OED OEC OEB OEA 395 Legend: POLC POLB POLA DBF<5:0> 390 391 DBR<5:0> 391 IS<3:0> 396 x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by CWG. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 397 PIC16(L)F1615/9 29.0 Refer to Figure 29-1 for a simplified diagram showing signal flow through the CLCx. CONFIGURABLE LOGIC CELL (CLC) The Configurable Logic Cell (CLCx) provides programmable logic that operates outside the speed limitations of software execution. The logic cell takes up to 16 input signals, and through the use of configurable gates, reduces the 16 inputs to four logic lines that drive one of eight selectable single-output logic functions. Input sources are a combination of the following: * * * * I/O pins Internal clocks Peripherals Register bits The output can be directed internally to peripherals and to an output pin. FIGURE 29-1: Possible configurations include: * Combinatorial Logic - AND - NAND - AND-OR - AND-OR-INVERT - OR-XOR - OR-XNOR * Latches - S-R - Clocked D with Set and Reset - Transparent D with Set and Reset - Clocked J-K with Reset CONFIGURABLE LOGIC CELL BLOCK DIAGRAM Rev. 10-000025E 7/7/2014 D Q LCxOUT MLCxOUT Q1 . . . LCx_in[38] LCx_in[39] LCx_in[40] LCx_out Input Data Selection Gates(1) LCx_in[0] LCx_in[1] LCx_in[2] EN g1 g2 g3 Logic Function to Peripherals CLCxPPS q PPS CLCx (2) g4 POL MODE<2:0> TRIS Interrupt det INTP INTN set bit CLCxIF Interrupt det Note 1: See Figure 29-2. 2: See Figure 29-3. DS40001770A-page 398 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 29.1 CLCx Setup Programming the CLCx module is performed by configuring the four stages in the logic signal flow. The four stages are: * * * * Data selection Data gating Logic function selection Output polarity Each stage is setup at run time by writing to the corresponding CLCx Special Function Registers. This has the added advantage of permitting logic reconfiguration on-the-fly during program execution. 29.1.1 DATA SELECTION There are 41 signals available as inputs to the configurable logic. Four 41 input multiplexers are used to select the inputs to pass on to the next stage. This allows for any of the possible input signals to be used as any of the four inputs to the CLC module. Data selection is through four multiplexers as indicated on the left side of Figure 29-2. Data inputs in the figure are identified by a generic numbered input name. TABLE 29-1: Data Input CLCx DATA INPUT SELECTION CLCxSELy CLC Input Signal LCx_in[0] 000000 CLCIN0 LCx_in[1] 000001 CLCIN1 LCx_in[2] 000010 CLCIN2 LCx_in[3] 000011 CLCIN3 LCx_in[4] 000100 LC1_out LCx_in[5] 000101 LC2_out LCx_in[6] 000110 LC3_out LCx_in[7] 000111 LC4_out LCx_in[8] 001000 C1OUT_sync LCx_in[9] 001001 C2OUT_sync LCx_in[10] 001010 CWGOUTA LCx_in[11] 001011 CWGOUTB LCx_in[12] 001100 CCP1_out LCx_in[13] 001101 CCP2_out LCx_in[14] 001110 PWM3_out Table 29-1 correlates the generic input name to the actual signal for each CLC module. The column labeled CLCxSELy refers to the value of any of the four registers associated with the four multiplexers, CLCxSEL0 through CLCxSEL3. LCx_in[15] 001111 PWM4_out LCx_in[16] 010000 AT1_cmp1 LCx_in[17] 010001 AT1_cmp2 LCx_in[18] 010010 AT1_cmp3 Data inputs for each multiplexer are selected with their respective CLCxSELy registers. LCx_in[19] 010011 SMT1_match LCx_in[20] 010100 SMT2_match LCx_in[21] 010101 ZCD1_output LCx_in[22] 010110 TMR0_overflow LCx_in[23] 010111 TMR1_overflow LCx_in[24] 011000 TMR2_postscaled LCx_in[25] 011001 TMR3_overflow LCx_in[26] 011010 TMR4_postscaled LCx_in[27] 011011 TMR5_overflow LCx_in[28] 011100 TMR6_postscaled LCx_in[29] 011101 IOC_interrupt LCx_in[30] 011110 ADC_rc LCx_in[31] 011111 LFINTOSC LCx_in[32] 100000 HFINTOSC LCx_in[33] 100001 FOSC LCx_in[34] 100010 AT1_missedpulse LCx_in[35] 100011 AT1_perclk LCx_in[36] 100100 AT1_phsclk LCx_in[37] 100101 TX LCx_in[38] 100110 RX LCx_in[39] 100111 SCK LCx_in[40] 101000 SDO Note: Data selections are undefined at power-up. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 399 PIC16(L)F1615/9 29.2 Data Gating Outputs from the input multiplexers are directed to the desired logic function input through the data gating stage. Each data gate can direct any combination of the four selected inputs. Note: 29.2.1 Data gating is undefined at power-up. The gate stage is more than just signal direction. The gate can be configured to direct each input signal as inverted or non-inverted data. Directed signals are ANDed together in each gate. The output of each gate can be inverted before going on to the logic function stage. The gating is in essence a 1-to-4 input AND/NAND/OR/ NOR gate. When every input is inverted and the output is inverted, the gate is an OR of all enabled data inputs. When the inputs and output are not inverted, the gate is an AND or all enabled inputs. Table 29-2 summarizes the basic logic that can be obtained in gate 1 by using the gate logic select bits. The table shows the logic of four input variables, but each gate can be configured to use less than four. If no inputs are selected, the output will be zero or one, depending on the gate output polarity bit. TABLE 29-2: LCxG1POL Gate Logic 0x55 1 AND 0x55 0 NAND 0xAA 1 NOR 0xAA 0 OR 0x00 0 Logic 0 0x00 1 Logic 1 LOGIC FUNCTION There are eight available logic functions including: * * * * * * * * AND-OR OR-XOR AND S-R Latch D Flip-Flop with Set and Reset D Flip-Flop with Reset J-K Flip-Flop with Reset Transparent Latch with Set and Reset Logic functions are shown in Figure 29-3. Each logic function has four inputs and one output. The four inputs are the four data gate outputs of the previous stage. The output is fed to the inversion stage and from there to other peripherals, an output pin, and back to the CLCx itself. 29.2.2 OUTPUT POLARITY The last stage in the configurable logic cell is the output polarity. Setting the LCxPOL bit of the CLCxCON register inverts the output signal from the logic stage. Changing the polarity while the interrupts are enabled will cause an interrupt for the resulting output transition. DATA GATING LOGIC CLCxGLS0 Data gating is indicated in the right side of Figure 29-2. Only one gate is shown in detail. The remaining three gates are configured identically with the exception that the data enables correspond to the enables for that gate. It is possible (but not recommended) to select both the true and negated values of an input. When this is done, the gate output is zero, regardless of the other inputs, but may emit logic glitches (transient-induced pulses). If the output of the channel must be zero or one, the recommended method is to set all gate bits to zero and use the gate polarity bit to set the desired level. Data gating is configured with the logic gate select registers as follows: * * * * Gate 1: CLCxGLS0 (Register 29-8) Gate 2: CLCxGLS1 (Register 29-9) Gate 3: CLCxGLS2 (Register 29-10) Gate 4: CLCxGLS3 (Register 29-11) Register number suffixes are different than the gate numbers because other variations of this module have multiple gate selections in the same register. DS40001770A-page 400 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 29.2.3 CLCx SETUP STEPS 29.3 The following steps should be followed when setting up the CLCx: * Disable CLCx by clearing the LCxEN bit. * Select desired inputs using CLCxSEL0, CLCxSEL1, CLCxSEL2 and CLCxSEL3 registers (See Table 29-1). * Clear any associated ANSEL bits. * Set all TRIS bits associated with inputs. * Clear all TRIS bits associated with outputs. * Enable the chosen inputs through the four gates using CLCxGLS0, CLCxGLS1, CLCxGLS2, and CLCxGLS3 registers. * Select the gate output polarities with the LCxPOLy bits of the CLCxPOL register. * Select the desired logic function with the LCxMODE<2:0> bits of the CLCxCON register. * Select the desired polarity of the logic output with the LCxPOL bit of the CLCxPOL register. (This step may be combined with the previous gate output polarity step). * If driving a device, set the desired pin PPS control register and also clear the TRIS bit corresponding to that output. * If interrupts are desired, configure the following bits: - Set the LCxINTP bit in the CLCxCON register for rising event. - Set the LCxINTN bit in the CLCxCON register or falling event. - Set the CLCxIE bit of the associated PIE registers. - Set the GIE and PEIE bits of the INTCON register. * Enable the CLCx by setting the LCxEN bit of the CLCxCON register. CLCx Interrupts An interrupt will be generated upon a change in the output value of the CLCx when the appropriate interrupt enables are set. A rising edge detector and a falling edge detector are present in each CLC for this purpose. The CLCxIF bit of the associated PIR registers will be set when either edge detector is triggered and its associated enable bit is set. The LCxINTP enables rising edge interrupts and the LCxINTN bit enables falling edge interrupts. Both are located in the CLCxCON register. To fully enable the interrupt, set the following bits: * LCxON bit of the CLCxCON register * CLCxIE bit of the associated PIE registers * LCxINTP bit of the CLCxCON register (for a rising edge detection) * LCxINTN bit of the CLCxCON register (for a falling edge detection) * PEIE and GIE bits of the INTCON register The CLCxIF bit of the associated PIR registers, must be cleared in software as part of the interrupt service. If another edge is detected while this flag is being cleared, the flag will still be set at the end of the sequence. 29.4 Output Mirror Copies Mirror copies of all LCxCON output bits are contained in the CLCxDATA register. Reading this register reads the outputs of all CLCs simultaneously. This prevents any reading skew introduced by testing or reading the CLCxOUT bits in the individual CLCxCON registers. 29.5 Effects of a Reset The CLCxCON register is cleared to zero as the result of a Reset. All other selection and gating values remain unchanged. 29.6 Operation During Sleep The CLC module operates independently from the system clock and will continue to run during Sleep, provided that the input sources selected remain active. The HFINTOSC remains active during Sleep when the CLC module is enabled and the HFINTOSC is selected as an input source, regardless of the system clock source selected. In other words, if the HFINTOSC is simultaneously selected as the system clock and as a CLC input source, when the CLC is enabled, the CPU will go idle during Sleep, but the CLC will continue to operate and the HFINTOSC will remain active. This will have a direct effect on the Sleep mode current. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 401 PIC16(L)F1615/9 FIGURE 29-2: LCx_in[0] INPUT DATA SELECTION AND GATING Data Selection 00000 Data GATE 1 LCx_in[31] lcxd1T LCxD1G1T lcxd1N LCxD1G1N 11111 LCxD2G1T LCxD1S<4:0> LCxD2G1N LCx_in[0] lcxg1 00000 LCxD3G1T lcxd2T LCxG1POL LCxD3G1N lcxd2N LCx_in[31] LCxD4G1T 11111 LCxD2S<4:0> LCx_in[0] LCxD4G1N 00000 Data GATE 2 lcxg2 lcxd3T (Same as Data GATE 1) lcxd3N LCx_in[31] Data GATE 3 11111 lcxg3 LCxD3S<4:0> LCx_in[0] (Same as Data GATE 1) Data GATE 4 00000 lcxg4 (Same as Data GATE 1) lcxd4T lcxd4N LCx_in[31] 11111 LCxD4S<4:0> Note: All controls are undefined at power-up. DS40001770A-page 402 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 FIGURE 29-3: PROGRAMMABLE LOGIC FUNCTIONS Rev. 10-000122A 7/30/2013 AND-OR OR-XOR lcxg1 lcxg1 lcxg2 lcxg2 lcxq lcxq lcxg3 lcxg3 lcxg4 lcxg4 LCxMODE<2:0> = 000 LCxMODE<2:0> = 001 4-input AND S-R Latch lcxg1 lcxg1 S Q lcxq Q lcxq lcxg2 lcxg2 lcxq lcxg3 lcxg3 R lcxg4 lcxg4 LCxMODE<2:0> = 010 LCxMODE<2:0> = 011 1-Input D Flip-Flop with S and R 2-Input D Flip-Flop with R lcxg4 lcxg2 D S lcxg4 Q lcxq D lcxg2 lcxg1 lcxg1 R R lcxg3 lcxg3 LCxMODE<2:0> = 100 LCxMODE<2:0> = 101 J-K Flip-Flop with R 1-Input Transparent Latch with S and R lcxg4 lcxg2 J Q lcxq lcxg2 D lcxg3 LE S Q lcxq lcxg1 lcxg4 K R lcxg3 R lcxg1 LCxMODE<2:0> = 110 2014 Microchip Technology Inc. LCxMODE<2:0> = 111 Preliminary DS40001770A-page 403 PIC16(L)F1615/9 29.7 Register Definitions: CLC Control REGISTER 29-1: CLCxCON: CONFIGURABLE LOGIC CELL CONTROL REGISTER R/W-0/0 R/W-0/0 R-0/0 R/W-0/0 R/W-0/0 LCxEN LCxOE LCxOUT LCxINTP LCxINTN R/W-0/0 R/W-0/0 R/W-0/0 LCxMODE<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 LCxEN: Configurable Logic Cell Enable bit 1 = Configurable logic cell is enabled and mixing input signals 0 = Configurable logic cell is disabled and has logic zero output bit 6 LCxOE: Configurable Logic Cell Output Enable bit 1 = Configurable logic cell port pin output enabled 0 = Configurable logic cell port pin output disabled bit 5 LCxOUT: Configurable Logic Cell Data Output bit Read-only: logic cell output data, after LCxPOL; sampled from lcx_out wire. bit 4 LCxINTP: Configurable Logic Cell Positive Edge Going Interrupt Enable bit 1 = CLCxIF will be set when a rising edge occurs on lcx_out 0 = CLCxIF will not be set bit 3 LCxINTN: Configurable Logic Cell Negative Edge Going Interrupt Enable bit 1 = CLCxIF will be set when a falling edge occurs on lcx_out 0 = CLCxIF will not be set bit 2-0 LCxMODE<2:0>: Configurable Logic Cell Functional Mode bits 111 = Cell is 1-input transparent latch with S and R 110 = Cell is J-K flip-flop with R 101 = Cell is 2-input D flip-flop with R 100 = Cell is 1-input D flip-flop with S and R 011 = Cell is S-R latch 010 = Cell is 4-input AND 001 = Cell is OR-XOR 000 = Cell is AND-OR DS40001770A-page 404 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 REGISTER 29-2: CLCxPOL: SIGNAL POLARITY CONTROL REGISTER R/W-0/0 U-0 U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxPOL -- -- -- LCxG4POL LCxG3POL LCxG2POL LCxG1POL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 LCxPOL: LCOUT Polarity Control bit 1 = The output of the logic cell is inverted 0 = The output of the logic cell is not inverted bit 6-4 Unimplemented: Read as `0' bit 3 LCxG4POL: Gate 4 Output Polarity Control bit 1 = The output of gate 4 is inverted when applied to the logic cell 0 = The output of gate 4 is not inverted bit 2 LCxG3POL: Gate 3 Output Polarity Control bit 1 = The output of gate 3 is inverted when applied to the logic cell 0 = The output of gate 3 is not inverted bit 1 LCxG2POL: Gate 2 Output Polarity Control bit 1 = The output of gate 2 is inverted when applied to the logic cell 0 = The output of gate 2 is not inverted bit 0 LCxG1POL: Gate 1 Output Polarity Control bit 1 = The output of gate 1 is inverted when applied to the logic cell 0 = The output of gate 1 is not inverted 2014 Microchip Technology Inc. Preliminary DS40001770A-page 405 PIC16(L)F1615/9 REGISTER 29-3: CLCxSEL0: MULTIPLEXER DATA 0 SELECT REGISTERS U-0 U-0 -- -- R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxD1S<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 Unimplemented: Read as `0' bit 5-0 LCxD1S<5:0>: Input Data 1 Selection Control bits See Table 29-1 for signal names associated with inputs. REGISTER 29-4: CLCxSEL1: MULTIPLEXER DATA 1 SELECT REGISTERS U-0 U-0 -- -- R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxD2S<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 Unimplemented: Read as `0' bit 5-0 LCxD2S<5:0>: Input Data 2 Selection Control bits See Table 29-1 for signal names associated with inputs. REGISTER 29-5: CLCxSEL2: MULTIPLEXER DATA 2 SELECT REGISTERS U-0 U-0 -- -- R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxD3S<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 Unimplemented: Read as `0' bit 5-0 LCxD3S<5:0>: Input Data 3 Selection Control bits See Table 29-1 for signal names associated with inputs. REGISTER 29-6: CLCxSEL3: MULTIPLEXER DATA 3 SELECT REGISTERS U-0 U-0 -- -- DS40001770A-page 406 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxD4S<5:0> Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 REGISTER 29-6: CLCxSEL3: MULTIPLEXER DATA 3 SELECT REGISTERS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 Unimplemented: Read as `0' bit 5-0 LCxD4S<5:0>: Input Data 4 Selection Control bits See Table 29-1 for signal names associated with inputs. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 407 PIC16(L)F1615/9 REGISTER 29-7: CLCxSEL3: MULTIPLEXER DATA 3 SELECT REGISTERS U-0 U-0 -- -- R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxD4S<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 Unimplemented: Read as `0' bit 5-0 LCxD4S<5:0>: Input Data 4 Selection Control bits See Table 29-1 for signal names associated with inputs. DS40001770A-page 408 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 REGISTER 29-8: CLCxGLS0: GATE 1 LOGIC SELECT REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxG1D4T LCxG1D4N LCxG1D3T LCxG1D3N LCxG1D2T LCxG1D2N LCxG1D1T LCxG1D1N bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 LCxG1D4T: Gate 1 Data 4 True (non-inverted) bit 1 = lcxd4T is gated into lcxg1 0 = lcxd4T is not gated into lcxg1 bit 6 LCxG1D4N: Gate 1 Data 4 Negated (inverted) bit 1 = lcxd4N is gated into lcxg1 0 = lcxd4N is not gated into lcxg1 bit 5 LCxG1D3T: Gate 1 Data 3 True (non-inverted) bit 1 = lcxd3T is gated into lcxg1 0 = lcxd3T is not gated into lcxg1 bit 4 LCxG1D3N: Gate 1 Data 3 Negated (inverted) bit 1 = lcxd3N is gated into lcxg1 0 = lcxd3N is not gated into lcxg1 bit 3 LCxG1D2T: Gate 1 Data 2 True (non-inverted) bit 1 = lcxd2T is gated into lcxg1 0 = lcxd2T is not gated into lcxg1 bit 2 LCxG1D2N: Gate 1 Data 2 Negated (inverted) bit 1 = lcxd2N is gated into lcxg1 0 = lcxd2N is not gated into lcxg1 bit 1 LCxG1D1T: Gate 1 Data 1 True (non-inverted) bit 1 = lcxd1T is gated into lcxg1 0 = lcxd1T is not gated into lcxg1 bit 0 LCxG1D1N: Gate 1 Data 1 Negated (inverted) bit 1 = lcxd1N is gated into lcxg1 0 = lcxd1N is not gated into lcxg1 2014 Microchip Technology Inc. Preliminary DS40001770A-page 409 PIC16(L)F1615/9 REGISTER 29-9: CLCxGLS1: GATE 2 LOGIC SELECT REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxG2D4T LCxG2D4N LCxG2D3T LCxG2D3N LCxG2D2T LCxG2D2N LCxG2D1T LCxG2D1N bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 LCxG2D4T: Gate 2 Data 4 True (non-inverted) bit 1 = lcxd4T is gated into lcxg2 0 = lcxd4T is not gated into lcxg2 bit 6 LCxG2D4N: Gate 2 Data 4 Negated (inverted) bit 1 = lcxd4N is gated into lcxg2 0 = lcxd4N is not gated into lcxg2 bit 5 LCxG2D3T: Gate 2 Data 3 True (non-inverted) bit 1 = lcxd3T is gated into lcxg2 0 = lcxd3T is not gated into lcxg2 bit 4 LCxG2D3N: Gate 2 Data 3 Negated (inverted) bit 1 = lcxd3N is gated into lcxg2 0 = lcxd3N is not gated into lcxg2 bit 3 LCxG2D2T: Gate 2 Data 2 True (non-inverted) bit 1 = lcxd2T is gated into lcxg2 0 = lcxd2T is not gated into lcxg2 bit 2 LCxG2D2N: Gate 2 Data 2 Negated (inverted) bit 1 = lcxd2N is gated into lcxg2 0 = lcxd2N is not gated into lcxg2 bit 1 LCxG2D1T: Gate 2 Data 1 True (non-inverted) bit 1 = lcxd1T is gated into lcxg2 0 = lcxd1T is not gated into lcxg2 bit 0 LCxG2D1N: Gate 2 Data 1 Negated (inverted) bit 1 = lcxd1N is gated into lcxg2 0 = lcxd1N is not gated into lcxg2 DS40001770A-page 410 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 REGISTER 29-10: CLCxGLS2: GATE 3 LOGIC SELECT REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxG3D4T LCxG3D4N LCxG3D3T LCxG3D3N LCxG3D2T LCxG3D2N LCxG3D1T LCxG3D1N bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 LCxG3D4T: Gate 3 Data 4 True (non-inverted) bit 1 = lcxd4T is gated into lcxg3 0 = lcxd4T is not gated into lcxg3 bit 6 LCxG3D4N: Gate 3 Data 4 Negated (inverted) bit 1 = lcxd4N is gated into lcxg3 0 = lcxd4N is not gated into lcxg3 bit 5 LCxG3D3T: Gate 3 Data 3 True (non-inverted) bit 1 = lcxd3T is gated into lcxg3 0 = lcxd3T is not gated into lcxg3 bit 4 LCxG3D3N: Gate 3 Data 3 Negated (inverted) bit 1 = lcxd3N is gated into lcxg3 0 = lcxd3N is not gated into lcxg3 bit 3 LCxG3D2T: Gate 3 Data 2 True (non-inverted) bit 1 = lcxd2T is gated into lcxg3 0 = lcxd2T is not gated into lcxg3 bit 2 LCxG3D2N: Gate 3 Data 2 Negated (inverted) bit 1 = lcxd2N is gated into lcxg3 0 = lcxd2N is not gated into lcxg3 bit 1 LCxG3D1T: Gate 3 Data 1 True (non-inverted) bit 1 = lcxd1T is gated into lcxg3 0 = lcxd1T is not gated into lcxg3 bit 0 LCxG3D1N: Gate 3 Data 1 Negated (inverted) bit 1 = lcxd1N is gated into lcxg3 0 = lcxd1N is not gated into lcxg3 2014 Microchip Technology Inc. Preliminary DS40001770A-page 411 PIC16(L)F1615/9 REGISTER 29-11: CLCxGLS3: GATE 4 LOGIC SELECT REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxG4D4T LCxG4D4N LCxG4D3T LCxG4D3N LCxG4D2T LCxG4D2N LCxG4D1T LCxG4D1N bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 LCxG4D4T: Gate 4 Data 4 True (non-inverted) bit 1 = lcxd4T is gated into lcxg4 0 = lcxd4T is not gated into lcxg4 bit 6 LCxG4D4N: Gate 4 Data 4 Negated (inverted) bit 1 = lcxd4N is gated into lcxg4 0 = lcxd4N is not gated into lcxg4 bit 5 LCxG4D3T: Gate 4 Data 3 True (non-inverted) bit 1 = lcxd3T is gated into lcxg4 0 = lcxd3T is not gated into lcxg4 bit 4 LCxG4D3N: Gate 4 Data 3 Negated (inverted) bit 1 = lcxd3N is gated into lcxg4 0 = lcxd3N is not gated into lcxg4 bit 3 LCxG4D2T: Gate 4 Data 2 True (non-inverted) bit 1 = lcxd2T is gated into lcxg4 0 = lcxd2T is not gated into lcxg4 bit 2 LCxG4D2N: Gate 4 Data 2 Negated (inverted) bit 1 = lcxd2N is gated into lcxg4 0 = lcxd2N is not gated into lcxg4 bit 1 LCxG4D1T: Gate 4 Data 1 True (non-inverted) bit 1 = lcxd1T is gated into lcxg4 0 = lcxd1T is not gated into lcxg4 bit 0 LCxG4D1N: Gate 4 Data 1 Negated (inverted) bit 1 = lcxd1N is gated into lcxg4 0 = lcxd1N is not gated into lcxg4 DS40001770A-page 412 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 REGISTER 29-12: CLCDATA: CLC DATA OUTPUT U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0 -- -- -- -- MLC4OUT MLC3OUT MLC2OUT MLC1OUT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-4 Unimplemented: Read as `0' bit 3 MLC4OUT: Mirror copy of LC4OUT bit bit 2 MLC3OUT: Mirror copy of LC3OUT bit bit 1 MLC2OUT: Mirror copy of LC2OUT bit bit 0 MLC1OUT: Mirror copy of LC1OUT bit TABLE 29-3: Name ANSELA SUMMARY OF REGISTERS ASSOCIATED WITH CLCx Bit7 Bit6 -- -- Bit4 BIt3 Bit2 Bit1 Bit0 Register on Page -- ANSA4 -- ANSA2 ANSA1 ANSA0 99 ANSB4 -- -- -- -- 103 ANSC3 ANSC2 ANSC1 ANSC0 107 Bit5 ANSELB -- -- ANSB5 ANSELC ANSC7(2) ANSC6(2) -- -- CLC1CON LC1EN -- LC1OUT LC1INTP LC1INTN CLCDATA -- -- -- -- MLC4OUT LC1MODE<2:0> MLC3OUT MLC2OUT 404 MLC1OUT 413 CLC1GLS0 LC1G1D4T LC1G1D4N LC1G1D3T LC1G1D3N LC1G1D2T LC1G1D2N LC1G1D1T LC1G1D1N 409 CLC1GLS1 LC1G2D4T LC1G2D4N LC1G2D3T LC1G2D3N LC1G2D2T LC1G2D2N LC1G2D1T LC1G2D1N 410 CLC1GLS2 LC1G3D4T LC1G3D4N LC1G3D3T LC1G3D3N LC1G3D2T LC1G3D2N LC1G3D1T LC1G3D1N 411 CLC1GLS3 LC1G4D4T LC1G4D4N LC1G4D3T LC1G4D3N LC1G4D2T LC1G4D2N LC1G4D1T LC1G4D1N 412 -- -- LC1G4POL LC1G3POL LC1G2POL LC1G1POL CLC1POL LC1POL -- CLC1SEL0 -- -- LC1D1S<5:0> 406 CLC1SEL1 -- -- LC1D2S<5:0> 406 CLC1SEL2 -- -- LC1D3S<5:0> 406 CLC1SEL3 -- -- LC1D4S<5:0> CLC2CON LC2EN -- LC2OUT LC2INTP LC2INTN CLC2GLS0 LC2G1D4T LC2G1D4N LC2G1D3T LC2G1D3N LC2G1D2T LC2G1D2N LC2G1D1T LC2G1D1N 409 CLC2GLS1 LC2G2D4T LC2G2D4N LC2G2D3T LC2G2D3N LC2G2D2T LC2G2D2N LC2G2D1T LC2G2D1N 410 CLC2GLS2 LC2G3D4T LC2G3D4N LC2G3D3T LC2G3D3N LC2G3D2T LC2G3D2N LC2G3D1T LC2G3D1N 411 CLC2GLS3 LC2G4D4T LC2G4D4N LC2G4D3T LC2G4D3N LC2G4D2T LC2G4D2N LC2G4D1T LC2G4D1N 412 -- -- LC2G4POL LC2G3POL LC2G2POL LC2G1POL 405 408 LC2MODE<2:0> 404 CLC2POL LC2POL -- CLC2SEL0 -- -- LC2D1S<5:0> 406 CLC2SEL1 -- -- LC2D2S<5:0> 406 CLC2SEL2 -- -- LC2D3S<5:0> 406 CLC2SEL3 -- -- LC2D4S<5:0> CLC3CON LC3EN -- LC3OUT LC3INTP LC3INTN LC3G1D4T LC3G1D4N LC3G1D3T LC3G1D3N LC3G1D2T CLC3GLS0 Legend: Note 1: 2: 408 LC3MODE<2:0> LC3G1D2N 405 LC3G1D1T 404 LC3G1D1N 409 -- = unimplemented read as `0',. Shaded cells are not used for CLC module. Unimplemented, read as `1'. PIC16(L)F1619 only. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 413 PIC16(L)F1615/9 TABLE 29-3: Name SUMMARY OF REGISTERS ASSOCIATED WITH CLCx (continued) Bit7 Bit6 Bit5 Bit4 BIt3 Bit2 Bit1 Bit0 Register on Page 410 CLC3GLS1 LC3G2D4T LC3G2D4N LC3G2D3T LC3G2D3N LC3G2D2T LC3G2D2N LC3G2D1T LC3G2D1N CLC3GLS2 LC3G3D4T LC3G3D4N LC3G3D3T LC3G3D3N LC3G3D2T LC3G3D2N LC3G3D1T LC3G3D1N 411 CLC3GLS3 LC3G4D4T LC3G4D4N LC3G4D3T LC3G4D3N LC3G4D2T LC3G4D2N LC3G4D1T LC3G4D1N 412 -- -- LC3G4POL LC3G3POL LC3G2POL LC3G1POL 405 CLC3POL LC3POL -- CLC3SEL0 -- -- LC3D1S<5:0> 406 CLC3SEL1 -- -- LC3D2S<5:0> 406 CLC3SEL2 -- -- LC3D3S<5:0> 406 CLC3SEL3 -- -- LC3D4S<5:0> 408 CLC4CON LC4EN -- LC4OUT LC4INTP LC4INTN CLC4GLS0 LC4G1D4T LC4G1D4N LC4G1D3T LC4G1D3N LC4G1D2T LC4MODE<2:0> LC4G1D2N LC4G1D1T 404 LC4G1D1N 409 CLC4GLS1 LC4G2D4T LC4G2D4N LC4G2D3T LC4G2D3N LC4G2D2T LC4G2D2N LC4G2D1T LC4G2D1N 410 CLC4GLS2 LC4G3D4T LC4G3D4N LC4G3D3T LC4G3D3N LC4G3D2T LC4G3D2N LC4G3D1T LC4G3D1N 411 CLC4GLS3 LC4G4D4T LC4G4D4N LC4G4D3T LC4G4D3N LC4G4D2T LC4G4D2N LC4G4D1T LC4G4D1N 412 CLC4POL LC4POL -- -- -- LC4G4POL LC4G3POL LC4G2POL LC4G1POL 405 CLC4SEL0 -- -- LC4D1S<5:0> 406 CLC4SEL1 -- -- LC4D2S<5:0> 406 CLC4SEL2 -- -- LC4D3S<5:0> 406 CLC4SEL3 -- -- LC4D4S<5:0> GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 64 PIE3 -- -- CWGIE ZCDIE CLC4IE CLC3IE CLC2IE CLC1IE 108 PIR3 -- -- CWGIF ZCDIF CLC4IF CLC3IF CLC2IF CLC1IF 113 TRISA -- -- TRISA5 TRISA4 --(1) TRISA2 TRISA1 TRISA0 98 TRISB TRISB7 TRISB6 TRISB5 TRISB4 -- -- -- -- 102 TRISC TRISC7(2) TRISC6(2) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 106 INTCON Legend: Note 1: 2: 408 -- = unimplemented read as `0',. Shaded cells are not used for CLC module. Unimplemented, read as `1'. PIC16(L)F1619 only. DS40001770A-page 414 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 30.0 SIGNAL MEASUREMENT TIMER (SMT) The SMT is a 24-bit counter with advanced clock and gating logic, which can be configured for measuring a variety of digital signal parameters such as pulse width, frequency and duty cycle, and the time difference between edges on two signals. Features of the SMT include: * 24-bit timer/counter - Three 8-bit registers (SMTxL/H/U) - Readable and writable - Optional 16-bit operating mode * Two 24-bit measurement capture registers * One 24-bit period match register * Multi-mode operation, including relative timing measurement * Interrupt on period match * Multiple clock, gate and signal sources * Interrupt on acquisition complete * Ability to read current input values Note: These devices implement two SMT modules. All references to SMTx apply to SMT1 and SMT2. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 415 PIC16(L)F1615/9 FIGURE 30-1: SMT BLOCK DIAGRAM Rev. 10-000161B 7/3/2014 Period Latch SMT_window SMT Clock Sync Circuit SMT_signal SMT Clock Sync Circuit Set SMTxPRAIF SMTxPR Control Logic Set SMTxIF Comparator Reset SMTxTMR Enable Reserved 111 AT1_perclk 110 MFINTOSC 101 MFINTOSC/16 100 LFINTOSC 011 HFINTOSC 010 FOSC/4 001 FOSC 000 Window Latch 24-bit Buffer SMTxCPR 24-bit Buffer SMTxCPW Set SMTxPWAIF Prescaler SMTxCLK<2:0> FIGURE 30-2: SMT SIGNAL AND WINDOW BLOCK DIAGRAM Rev. 10-000173B 7/21/2014 See SMTxSIG Register SMTxSIG<3:0> DS40001770A-page 416 SMT_signal See SMTxWIN Register SMT_window SMTxWIN<3:0> Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 30.1 30.2.3 SMT Operation PERIOD LATCH REGISTERS The core of the module is the 24-bit counter, SMTxTMR combined with a complex data acquisition front-end. Depending on the mode of operation selected, the SMT can perform a variety of measurements summarized in Table 30-1. The SMTxCPR registers are the 24-bit SMT period latch. They are used to latch in other values of the SMTxTMR when triggered by various other signals, which are determined by the mode the SMT is currently in. 30.1.1 The SMTxCPR registers can also be updated with the current value of the SMTxTMR value by setting the CPRU bit in the SMTxSTAT register. CLOCK SOURCES Clock sources available to the SMT include: * * * * * FOSC FOSC/4 HFINTOSC 16 MHz LFINTOSC MFINTOSC 31.25 kHz 30.3 The SMT clock source is selected by configuring the CSEL<2:0> bits in the SMTxCLK register. The clock source can also be prescaled using the PS<1:0> bits of the SMTxCON0 register. The prescaled clock source is used to clock both the counter and any synchronization logic used by the module. 30.1.2 PERIOD MATCH INTERRUPT Similar to other timers, the SMT triggers an interrupt when SMTxTMR rolls over to `0'. This happens when SMTxTMR = SMTxPR, regardless of mode. Hence, in any mode that relies on an external signal or a window to reset the timer, proper operation requires that SMTxPR be set to a period larger than that of the expected signal or window. 30.2 Basic Timer Function Registers 30.2.1 PULSE WIDTH LATCH REGISTERS The SMTxCPW registers are the 24-bit SMT pulse width latch. They are used to latch in the value of the SMTxTMR when triggered by various signals, which are determined by the mode the SMT is currently in. The SMTxCPW registers can also be updated with the current value of the SMTxTMR value by setting the CPWUP bit of the SMTxSTAT register. 2014 Microchip Technology Inc. 30.4 Polarity Control The three input signals for the SMT have polarity control to determine whether or not they are active high/positive edge or active low/negative edge signals. The following bits apply to Polarity Control: * WSEL bit (Window Polarity) * SSEL bit (Signal Polarity) * CSEL bit (Clock Polarity) These bits are located in the SMTxCON0 register. Status Information The SMT provides input status information for the user without requiring the need to deal with the polarity of the incoming signals. 30.5.1 TIME BASE The SMTxTMR is the 24-bit counter that is the center of the SMT. It is used as the basic counter/timer for measurement in each of the modes of the SMT. It can be reset to a value of 24'h00_0000 by setting the RST bit of the SMTxSTAT register. It can be written to and read from software, but it is not guarded for atomic access, therefore reads and writes to the SMTxTMR should only be made when the GO = 0, or the software should have other measures to ensure integrity of SMTxTMR reads/writes. 30.2.2 The counter can be prevented from rolling-over using the STP bit in the SMTxCON0 register. When halting is enabled, the period match interrupt persists until the SMTxTMR is reset (either by a manual reset, Section 30.2.1 "Time Base") or by clearing the SMTxGO bit of the SMTxCON1 register and writing the SMTxTMR values in software. 30.5 The SMTxTMR time base and the SMTxCPW/SMTxPR/SMTxCPR buffer registers serve several functions and can be manually updated using software. Halt Operation WINDOW STATUS Window status is determined by the WS bit of the SMTxSTAT register. This bit is only used in Windowed Measure, Gated Counter and Gated Window Measure modes, and is only valid when TS = 1, and will be delayed in time by synchronizer delays in non-Counter modes. 30.5.2 SIGNAL STATUS Signal status is determined by the AS bit of the SMTxSTAT register. This bit is used in all modes except Window Measure, Time of Flight and Capture modes, and is only valid when TS = 1, and will be delayed in time by synchronizer delays in non-Counter modes. 30.5.3 GO STATUS Timer run status is determined by the TS bit of the SMTxSTAT register, and will be delayed in time by synchronizer delays in non-Counter modes. Preliminary DS40001770A-page 417 PIC16(L)F1615/9 30.6 30.6.1 Modes of Operation Timer mode is the simplest mode of operation where the SMTxTMR is used as a 16/24-bit timer. No data acquisition takes place in this mode. The timer increments as long as the SMTxGO bit has been set by software. No SMT window or SMT signal events affect the SMTxGO bit. Everything is synchronized to the SMT clock source. When the timer experiences a period match (SMTxTMR = SMTxPR), SMTxTMR is reset and the period match interrupt trips. See Figure 30-3. The modes of operation are summarized in Table 30-1. The following sections provide detailed descriptions, examples of how the modes can be used. Note that all waveforms assume WPOL/SPOL/CPOL = 0. When WPOL/SPOL/CPOL = 1, all SMTSIGx, SMTWINx and SMT clock signals will have a polarity opposite to that indicated. For all modes, the REPEAT bit controls whether the acquisition is repeated or single. When REPEAT = 0 (Single Acquisition mode), the timer will stop incrementing and the SMTxGO bit will be reset upon the completion of an acquisition. Otherwise, the timer will continue and allow for continued acquisitions to overwrite the previous ones until the timer is stopped in software. TABLE 30-1: TIMER MODE MODES OF OPERATION MODE Mode of Operation Synchronous Operation Reference 0000 Timer Yes Section 30.6.1 "Timer Mode" 0001 Gated Timer Yes Section 30.6.2 "Gated Timer Mode" 0010 Period and Duty Cycle Acquisition Yes Section 30.6.3 "Period and Duty-Cycle Mode" 0011 High and Low Time Measurement Yes Section 30.6.4 "High and Low Measure Mode" 0100 Windowed Measurement Yes Section 30.6.5 "Windowed Measure Mode" 0101 Gated Windowed Measurement Yes Section 30.6.6 "Gated Window Measure Mode" 0110 Time of Flight Yes Section 30.6.7 "Time of Flight Measure Mode" 0111 Capture Yes Section 30.6.8 "Capture Mode" 1000 Counter No Section 30.6.9 "Counter Mode" 1001 Gated Counter No Section 30.6.10 "Gated Counter Mode" Windowed Counter No Section 30.6.11 "Windowed Counter Mode" Reserved -- -- 1010 1011 - 1111 DS40001770A-page 418 Preliminary 2014 Microchip Technology Inc. TIMER MODE TIMING DIAGRAM Rev. 10-000 174A 12/19/201 3 SMTx Clock SMTxEN SMTxGO SMTxGO_sync SMTxPR SMTxTMR Preliminary SMTxIF 11 0 1 2 3 4 5 6 7 8 9 10 11 0 1 2 3 4 5 6 7 8 9 PIC16(L)F1615/9 DS40001770A-page 419 FIGURE 30-3: 2014 Microchip Technology Inc. PIC16(L)F1615/9 30.6.2 GATED TIMER MODE Gated Timer mode uses the SMTSIGx input to control whether or not the SMTxTMR will increment. Upon a falling edge of the external signal, the SMTxCPW register will update to the current value of the SMTxTMR. Example waveforms for both repeated and single acquisitions are provided in Figure 30-4 and Figure 30-5. DS40001770A-page 420 Preliminary 2014 Microchip Technology Inc. GATED TIMER MODE REPEAT ACQUISITION TIMING DIAGRAM Rev. 10-000 176A 12/19/201 3 SMTx_signal SMTx_signalsync SMTx Clock SMTxEN SMTxGO SMTxGO_sync Preliminary SMTxPR SMTxTMR SMTxCPW SMTxPWAIF 0xFFFFFF 0 1 2 3 4 5 6 5 7 7 PIC16(L)F1615/9 DS40001770A-page 421 FIGURE 30-4: 2014 Microchip Technology Inc. 2014 Microchip Technology Inc. FIGURE 30-5: GATED TIMER MODE SINGLE ACQUISITION TIMING DIAGRAM Rev. 10-000 175A 12/19/201 3 SMTx_signal SMTx_signalsync SMTx Clock SMTxEN SMTxGO SMTxGO_sync SMTxPR Preliminary SMTxTMR SMTxCPW 0xFFFFFF 0 1 2 3 4 5 5 SMTxPWAIF PIC16(L)F1615/9 DS40001770A-page 422 PIC16(L)F1615/9 30.6.3 PERIOD AND DUTY-CYCLE MODE In Duty-Cycle mode, either the duty cycle or period (depending on polarity) of the SMTx_signal can be acquired relative to the SMT clock. The CPW register is updated on a falling edge of the signal, and the CPR register is updated on a rising edge of the signal, along with the SMTxTMR resetting to 0x0001. In addition, the SMTxGO bit is reset on a rising edge when the SMT is in Single Acquisition mode. See Figure 30-6 and Figure 30-7. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 423 2014 Microchip Technology Inc. FIGURE 30-6: PERIOD AND DUTY-CYCLE REPEAT ACQUISITION MODE TIMING DIAGRAM Rev. 10-000 177A 12/19/201 3 SMTx_signal SMTx_signalsync SMTx Clock SMTxEN SMTxGO SMTxGO_sync Preliminary SMTxTMR SMTxCPW SMTxCPR 0 1 2 3 4 5 6 7 8 9 10 11 1 2 3 4 5 5 2 11 SMTxPWAIF SMTxPRAIF PIC16(L)F1615/9 DS40001770A-page 424 PERIOD AND DUTY-CYCLE SINGLE ACQUISITION TIMING DIAGRAM Rev. 10-000 178A 12/19/201 3 SMTx_signal SMTx_signalsync SMTx Clock SMTxEN SMTxGO SMTxGO_sync Preliminary SMTxTMR SMTxCPW SMTxCPR SMTxPWAIF SMTxPRAIF 0 1 2 3 4 5 6 7 8 9 10 11 5 11 PIC16(L)F1615/9 DS40001770A-page 425 FIGURE 30-7: 2014 Microchip Technology Inc. PIC16(L)F1615/9 30.6.4 HIGH AND LOW MEASURE MODE This mode measures the high and low pulse time of the SMTSIGx relative to the SMT clock. It begins incrementing the SMTxTMR on a rising edge on the SMTSIGx input, then updates the SMTxCPW register with the value and resets the SMTxTMR on a falling edge, starting to increment again. Upon observing another rising edge, it updates the SMTxCPR register with its current value and once again resets the SMTxTMR value and begins incrementing again. See Figure 30-8 and Figure 30-9. DS40001770A-page 426 Preliminary 2014 Microchip Technology Inc. HIGH AND LOW MEASURE MODE REPEAT ACQUISITION TIMING DIAGRAM Rev. 10-000 180A 12/19/201 3 SMTx_signal SMTx_signalsync SMTx Clock SMTxEN SMTxGO SMTxGO_sync SMTxTMR Preliminary SMTxCPW SMTxCPR SMTxPWAIF SMTxPRAIF 0 1 2 3 4 5 1 2 3 4 5 6 1 2 1 2 3 5 2 6 PIC16(L)F1615/9 DS40001770A-page 427 FIGURE 30-8: 2014 Microchip Technology Inc. 2014 Microchip Technology Inc. FIGURE 30-9: HIGH AND LOW MEASURE MODE SINGLE ACQUISITION TIMING DIAGRAM Rev. 10-000 179A 12/19/201 3 SMTx_signal SMTx_signalsync SMTx Clock SMTxEN SMTxGO SMTxGO_sync SMTxTMR Preliminary SMTxCPW SMTxCPR 0 1 2 3 4 5 1 2 3 4 5 6 5 6 SMTxPWAIF SMTxPRAIF PIC16(L)F1615/9 DS40001770A-page 428 PIC16(L)F1615/9 30.6.5 WINDOWED MEASURE MODE This mode measures the window duration of the SMTWINx input of the SMT. It begins incrementing the timer on a rising edge of the SMTWINx input and updates the SMTxCPR register with the value of the timer and resets the timer on a second rising edge. See Figure 30-10 and Figure 30-11. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 429 2014 Microchip Technology Inc. FIGURE 30-10: WINDOWED MEASURE MODE REPEAT ACQUISITION TIMING DIAGRAM Rev. 10-000 182A 12/19/201 3 SMTxWIN SMTxWIN_sync SMTx Clock SMTxEN SMTxGO SMTxGO_sync Preliminary SMTxTMR SMTxCPR 0 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 12 5 6 7 8 1 2 3 4 8 SMTxPRAIF PIC16(L)F1615/9 DS40001770A-page 430 WINDOWED MEASURE MODE SINGLE ACQUISITION TIMING DIAGRAM Rev. 10-000 181A 12/19/201 3 SMTxWIN SMTxWIN_sync SMTx Clock SMTxEN SMTxGO SMTxGO_sync Preliminary SMTxTMR SMTxCPR SMTxPRAIF 0 1 2 3 4 5 6 7 8 9 10 11 12 12 PIC16(L)F1615/9 DS40001770A-page 431 FIGURE 30-11: 2014 Microchip Technology Inc. PIC16(L)F1615/9 30.6.6 GATED WINDOW MEASURE MODE This mode measures the duty cycle of the SMTx_signal input over a known input window. It does so by incrementing the timer on each pulse of the clock signal while the SMTx_signal input is high, updating the SMTxCPR register and resetting the timer on every rising edge of the SMTWINx input after the first. See Figure 30-12 and Figure 30-13. DS40001770A-page 432 Preliminary 2014 Microchip Technology Inc. GATED WINDOWED MEASURE MODE REPEAT ACQUISITION TIMING DIAGRAM Rev. 10-000 184A 12/19/201 3 SMTxWIN SMTxWIN_sync SMTx_signal SMTx_signalsync SMTx Clock SMTxEN SMTxGO Preliminary SMTxGO_sync SMTxTMR SMTxCPR SMTxPRAIF 0 1 2 3 4 5 6 0 1 6 2 3 0 3 PIC16(L)F1615/9 DS40001770A-page 433 FIGURE 30-12: 2014 Microchip Technology Inc. 2014 Microchip Technology Inc. FIGURE 30-13: GATED WINDOWED MEASURE MODE SINGLE ACQUISITION TIMING DIAGRAMS Rev. 10-000 183A 12/19/201 3 SMTxWIN SMTxWIN_sync SMTx_signal SMTx_signalsync SMTx Clock SMTxEN Preliminary SMTxGO SMTxGO_sync SMTxTMR SMTxCPR 0 1 2 3 4 5 6 6 SMTxPRAIF PIC16(L)F1615/9 DS40001770A-page 434 PIC16(L)F1615/9 30.6.7 TIME OF FLIGHT MEASURE MODE This mode measures the time interval between a rising edge on the SMTWINx input and a rising edge on the SMTx_signal input, beginning to increment the timer upon observing a rising edge on the SMTWINx input, while updating the SMTxCPR register and resetting the timer upon observing a rising edge on the SMTx_signal input. In the event of two SMTWINx rising edges without an SMTx_signal rising edge, it will update the SMTxCPW register with the current value of the timer and reset the timer value. See Figure 30-14 and Figure 30-15. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 435 2014 Microchip Technology Inc. FIGURE 30-14: TIME OF FLIGHT MODE REPEAT ACQUISITION TIMING DIAGRAM Rev. 10-000 186A 12/19/201 3 SMTxWIN SMTxWIN_sync SMTx_signal SMTx_signalsync SMTx Clock SMTxEN Preliminary SMTxGO SMTxGO_sync SMTxTMR 0 1 2 1 SMTxCPW SMTxCPR 2 3 4 5 6 7 8 9 10 11 12 13 1 2 13 1 SMTxPWAIF DS40001770A-page 436 PIC16(L)F1615/9 SMTxPRAIF TIME OF FLIGHT MODE SINGLE ACQUISITION TIMING DIAGRAM Rev. 10-000 185A 12/19/201 3 SMTxWIN SMTxWIN_sync SMTx_signal SMTx_signalsync SMTx Clock SMTxEN Preliminary SMTxGO SMTxGO_sync SMTxTMR 0 1 2 0 SMTxCPW SMTxCPR SMTxPWAIF SMTxPRAIF 1 PIC16(L)F1615/9 DS40001770A-page 437 FIGURE 30-15: 2014 Microchip Technology Inc. PIC16(L)F1615/9 30.6.8 CAPTURE MODE This mode captures the Timer value based on a rising or falling edge on the SMTWINx input and triggers an interrupt. This mimics the capture feature of a CCP module. The timer begins incrementing upon the SMTxGO bit being set, and updates the value of the SMTxCPR register on each rising edge of SMTWINx, and updates the value of the CPW register on each falling edge of the SMTWINx. The timer is not reset by any hardware conditions in this mode and must be reset by software, if desired. See Figure 30-16 and Figure 30-17. DS40001770A-page 438 Preliminary 2014 Microchip Technology Inc. CAPTURE MODE REPEAT ACQUISITION TIMING DIAGRAM Rev. 10-000 188A 12/19/201 3 SMTxWIN SMTxWIN_sync SMTx Clock SMTxEN SMTxGO SMTxGO_sync Preliminary SMTxTMR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 SMTxCPW SMTxCPR SMTxPWAIF SMTxPRAIF 3 2 19 18 32 31 PIC16(L)F1615/9 DS40001770A-page 439 FIGURE 30-16: 2014 Microchip Technology Inc. 2014 Microchip Technology Inc. FIGURE 30-17: CAPTURE MODE SINGLE ACQUISITION TIMING DIAGRAM Rev. 10-000 187A 12/19/201 3 SMTxWIN SMTxWIN_sync SMTx Clock SMTxEN SMTxGO SMTxGO_sync Preliminary SMTxTMR 0 1 2 3 SMTxCPW SMTxCPR 3 2 SMTxPWAIF SMTxPRAIF PIC16(L)F1615/9 DS40001770A-page 440 PIC16(L)F1615/9 30.6.9 COUNTER MODE This mode increments the timer on each pulse of the SMTx_signal input. This mode is asynchronous to the SMT clock and uses the SMTx_signal as a time source. The SMTxCPW register will be updated with the current SMTxTMR value on the rising edge of the SMTxWIN input. See Figure 30-18. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 441 2014 Microchip Technology Inc. FIGURE 30-18: COUNTER MODE TIMING DIAGRAM Rev. 10-000189A 9/25/2014 SMTxWIN SMTx_signal SMTxEN SMTxGO SMTxTMR SMTxCPW 0 1 2 3 4 5 6 7 8 27 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 12 25 Preliminary PIC16(L)F1615/9 DS40001770A-page 442 PIC16(L)F1615/9 30.6.10 GATED COUNTER MODE This mode counts pulses on the SMTx_signal input, gated by the SMTxWIN input. It begins incrementing the timer upon seeing a rising edge of the SMTxWIN input and updates the SMTxCPW register upon a falling edge on the SMTxWIN input. See Figure 30-19 and Figure 30-20. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 443 2014 Microchip Technology Inc. FIGURE 30-19: GATED COUNTER MODE REPEAT ACQUISITION TIMING DIAGRAM Rev. 10-000190A 12/18/2013 SMTxWIN SMTx_signal SMTxEN SMTxGO SMTxTMR 0 1 2 3 4 5 6 7 8 SMTxCPW 9 10 11 12 8 13 13 SMTxPWAIF Preliminary FIGURE 30-20: GATED COUNTER MODE SINGLE ACQUISITION TIMING DIAGRAM Rev. 10-000191A 12/18/2013 SMTxWIN SMTxEN SMTxGO SMTxTMR DS40001770A-page 444 SMTxCPW SMTxPWAIF 0 1 2 3 4 5 6 7 8 8 PIC16(L)F1615/9 SMTx_signal PIC16(L)F1615/9 30.6.11 WINDOWED COUNTER MODE This mode counts pulses on the SMTx_signal input, within a window dictated by the SMTxWIN input. It begins counting upon seeing a rising edge of the SMTxWIN input, updates the SMTxCPW register on a falling edge of the SMTxWIN input, and updates the SMTxCPR register on each rising edge of the SMTxWIN input beyond the first. See Figure 30-21 and Figure 30-22. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 445 2014 Microchip Technology Inc. FIGURE 30-21: WINDOWED COUNTER MODE REPEAT ACQUISITION TIMING DIAGRAM SMTxWIN SMTx_signal SMTxEN SMTxGO SMTxTMR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 SMTxCPW 2 3 5 4 9 5 SMTxCPR 16 SMTxPWAIF Preliminary SMTxPRAIF FIGURE 30-22: WINDOWED COUNTER MODE SINGLE ACQUISITION TIMING DIAGRAM SMTxWIN SMTx_signal SMTxEN SMTxTMR SMTxCPW DS40001770A-page 446 SMTxCPR SMTxPWAIF SMTxPRAIF 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 9 16 PIC16(L)F1615/9 SMTxGO PIC16(L)F1615/9 30.7 Interrupts The SMT can trigger an interrupt under three different conditions: * PW Acquisition Complete * PR Acquisition Complete * Counter Period Match The interrupts are controlled by the PIR and PIE registers of the device. 30.7.1 PW AND PR ACQUISITION INTERRUPTS The SMT can trigger interrupts whenever it updates the SMTxCPW and SMTxCPR registers, the circumstances for which are dependent on the SMT mode, and are discussed in each mode's specific section. The SMTxCPW interrupt is controlled by SMTxPWAIF and SMTxPWAIE bits in registers PIR4 and PIE4, respectively. The SMTxCPR interrupt is controlled by the SMTxPRAIF and SMTxPRAIE bits, also located in registers PIR4 and PIE4, respectively. In synchronous SMT modes, the interrupt trigger is synchronized to the SMTxCLK. In Asynchronous modes, the interrupt trigger is asynchronous. In either mode, once triggered, the interrupt will be synchronized to the CPU clock. 30.7.2 COUNTER PERIOD MATCH INTERRUPT As described in Section 30.1.2 "Period Match interrupt", the SMT will also interrupt upon SMTxTMR, matching SMTxPR with its period match limit functionality described in Section 30.3 "Halt Operation". The period match interrupt is controlled by SMTxIF and SMTxIE, located in registers PIR4 and PIE4, respectively. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 447 PIC16(L)F1615/9 30.8 Register Definitions: SMT Control Long bit name prefixes for the Signal Measurement Timer peripherals are shown in Table 30-2. Refer to Section 1.1 "Register and Bit Naming Conventions" for more information. TABLE 30-2: Peripheral Bit Name Prefix SMT1 SMT1 SMT2 SMT2 REGISTER 30-1: SMTxCON0: SMT CONTROL REGISTER 0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 EN(1) -- STP WPOL SPOL CPOL R/W-0/0 R/W-0/0 SMTxPS<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 EN: SMT Enable bit(1) 1 = SMT is enabled 0 = SMT is disabled; internal states are reset, clock requests are disabled bit 6 Unimplemented: Read as `0' bit 5 STP: SMT Counter Halt Enable bit When SMTxTMR = SMTxPR: 1 = Counter remains SMTxPR; period match interrupt occurs when clocked 0 = Counter resets to 24'h000000; period match interrupt occurs when clocked bit 4 WPOL: SMTxWIN Input Polarity Control bit 1 = SMTxWIN signal is active-low/falling edge enabled 0 = SMTxWIN signal is active-high/rising edge enabled bit 3 SPOL: SMTxSIG Input Polarity Control bit 1 = SMTx_signal is active-low/falling edge enabled 0 = SMTx_signal is active-high/rising edge enabled bit 2 CPOL: SMT Clock Input Polarity Control bit 1 = SMTxTMR increments on the falling edge of the selected clock signal 0 = SMTxTMR increments on the rising edge of the selected clock signal bit 1-0 SMTxPS<1:0>: SMT Prescale Select bits 11 = Prescaler = 1:8 10 = Prescaler = 1:4 01 = Prescaler = 1:2 00 = Prescaler = 1:1 Note 1: Setting EN to `0` does not affect the register contents. DS40001770A-page 448 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 REGISTER 30-2: SMTxCON1: SMT CONTROL REGISTER 1 R/W/HC-0/0 R/W-0/0 U-0 U-0 SMTxGO REPEAT -- -- R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 MODE<3:0> bit 7 bit 0 Legend: HC = Bit is cleared by hardware HS = Bit is set by hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7 SMTxGO: SMT GO Data Acquisition bit 1 = Incrementing, acquiring data is enabled 0 = Incrementing, acquiring data is disabled bit 6 REPEAT: SMT Repeat Acquisition Enable bit 1 = Repeat Data Acquisition mode is enabled 0 = Single Acquisition mode is enabled bit 5-4 Unimplemented: Read as `0' bit 3-0 MODE<3:0> SMT Operation Mode Select bits 1111 = Reserved * * * 1011 = Reserved 1010 = Windowed counter 1001 = Gated counter 1000 = Counter 0111 = Capture 0110 = Time of flight 0101 = Gated windowed measure 0100 = Windowed measure 0011 = High and low time measurement 0010 = Period and Duty-Cycle Acquisition 0001 = Gated Timer 0000 = Timer 2014 Microchip Technology Inc. Preliminary DS40001770A-page 449 PIC16(L)F1615/9 REGISTER 30-3: SMTxSTAT: SMT STATUS REGISTER R/W/HC-0/0 R/W/HC-0/0 R/W/HC-0/0 U-0 U-0 R-0/0 R-0/0 R-0/0 CPRUP CPWUP RST -- -- TS WS AS bit 7 bit 0 Legend: HC = Bit is cleared by hardware HS = Bit is set by hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7 CPRUP: SMT Manual Period Buffer Update bit 1 = Request update to SMTxPRx registers 0 = SMTxPRx registers update is complete bit 6 CPWUP: SMT Manual Pulse Width Buffer Update bit 1 = Request update to SMTxCPW registers 0 = SMTxCPW registers update is complete bit 5 RST: SMT Manual Timer Reset bit 1 = Request Reset to SMTxTMR registers 0 = SMTxTMR registers update is complete bit 4-3 Unimplemented: Read as `0' bit 2 TS: SMT GO Value Status bit 1 = SMT timer is incrementing 0 = SMT timer is not incrementing bit 1 WS: SMTxWIN Value Status bit 1 = SMT window is open 0 = SMT window is closed bit 0 AS: SMT_signal Value Status bit 1 = SMT acquisition is in progress 0 = SMT acquisition is not in progress DS40001770A-page 450 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 REGISTER 30-4: SMTxCLK: SMT CLOCK SELECTION REGISTER U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- R/W-0/0 R/W-0/0 R/W-0/0 CSEL<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-3 Unimplemented: Read as `0' bit 2-0 CSEL<2:0>: SMT Clock Selection bits 111 = Reserved 110 = AT1_perclk 101 = MFINTOSC 100 = MFINTOSC/16 011 = LFINTOSC 010 = HFINTOSC 16 MHz 001 = FOSC/4 000 = FOSC 2014 Microchip Technology Inc. Preliminary DS40001770A-page 451 PIC16(L)F1615/9 REGISTER 30-5: SMT1WIN: SMT1 WINDOW INPUT SELECT REGISTER U-0 U-0 U-0 -- -- -- R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 WSEL<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-5 Unimplemented: Read as `0' bit 4-0 WSEL<4:0>: SMT1 Window Selection bits 11111 = Reserved * * * 11000 = Reserved 10111 = MFINTOSC/16 10110 = AT1_perclk 10101 = LFINTOSC 10100 = PWM4_out 10011 = PWM3_out 10010 = SMT2_match 10001 = Reserved 10000 = TMR0_overflow 01111 = TMR5_overflow 01110 = TMR3_overflow 01101 = TMR1_overflow 01100 = LC4_out 01011 = LC3_out 01010 = LC2_out 01001 = LC1_out 01000 = TMR6_postscaled 00111 = TMR4_postscaled 00110 = TMR2_postscaled 00101 = ZCD1_out 00100 = CCP2_out 00011 = CCP1_out 00010 = C2OUT_sync 00001 = C1OUT_sync 00000 = SMTWINx pin DS40001770A-page 452 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 REGISTER 30-6: SMT2WIN: SMT2 WINDOW INPUT SELECT REGISTER U-0 U-0 U-0 -- -- -- R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 WSEL<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-5 Unimplemented: Read as `0' bit 4-0 WSEL<4:0>: SMT2 Window Selection bits 11111 = Reserved * * * 11000 = Reserved 10111 = MFINTOSC/16 10110 = AT1_perclk 10101 = LFINTOSC 10100 = PWM4_out 10011 = PWM3_out 10010 = Reserved 10001 = SMT1_match 10000 = TMR0_overflow 01111 = TMR5_overflow 01110 = TMR3_overflow 01101 = TMR1_overflow 01100 = LC4_out 01011 = LC3_out 01010 = LC2_out 01001 = LC1_out 01000 = TMR6_postscaled 00111 = TMR4_postscaled 00110 = TMR2_postscaled 00101 = ZCD1_out 00100 = CCP2_out 00011 = CCP1_out 00010 = C2OUT_sync 00001 = C1OUT_sync 00000 = SMTWINx pin 2014 Microchip Technology Inc. Preliminary DS40001770A-page 453 PIC16(L)F1615/9 REGISTER 30-7: SMT1SIG: SMT1 SIGNAL INPUT SELECT REGISTER U-0 U-0 U-0 -- -- -- R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 SSEL<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-5 Unimplemented: Read as `0' bit 4-0 SSEL<4:0>: SMT1 Signal Selection bits 11111 = Reserved * * * 10101 = Reserved 10100 = PWM4_out 10011 = PWM3_out 10010 = CCP2_out 10001 = CCP1_out 10000 = TMR0_overflow 01111 = SMT2_match 01110 = Reserved 01101 = TMR5_overflow 01100 = TMR3_overflow 01011 = TMR1_overflow 01010 = LC4_out 01001 = LC3_out 01000 = LC2_out 00111 = LC1_out 00110 = TMR6_postscaled 00101 = TMR4_postscaled 00100 = TMR2_postscaled 00011 = ZCD1_out 00010 = C2OUT_sync 00001 = C1OUT_sync 00000 = SMTxSIG pin DS40001770A-page 454 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 REGISTER 30-8: SMT2SIG: SMT2 SIGNAL INPUT SELECT REGISTER U-0 U-0 U-0 -- -- -- R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 SSEL<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-5 Unimplemented: Read as `0' bit 4-0 SSEL<4:0>: SMT2 Signal Selection bits 11111 = Reserved * * * 10101 = Reserved 10100 = PWM4_out 10011 = PWM3_out 10010 = CCP2_out 10001 = CCP1_out 10000 = TMR0_overflow 01111 = Reserved 01110 = SMT1_match 01101 = TMR5_overflow 01100 = TMR3_overflow 01011 = TMR1_overflow 01010 = LC4_out 01001 = LC3_out 01000 = LC2_out 00111 = LC1_out 00110 = TMR6_postscaled 00101 = TMR4_postscaled 00100 = TMR2_postscaled 00011 = ZCD1_out 00010 = C2OUT_sync 00001 = C1OUT_sync 00000 = SMTxSIG pin 2014 Microchip Technology Inc. Preliminary DS40001770A-page 455 PIC16(L)F1615/9 REGISTER 30-9: R/W-0/0 SMTxTMRL: SMT TIMER REGISTER - LOW BYTE R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 SMTxTMR<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 SMTxTMR<7:0>: Significant bits of the SMT Counter - Low Byte REGISTER 30-10: SMTxTMRH: SMT TIMER REGISTER - HIGH BYTE R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 SMTxTMR<15:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 SMTxTMR<15:8>: Significant bits of the SMT Counter - High Byte REGISTER 30-11: SMTxTMRU: SMT TIMER REGISTER - UPPER BYTE R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 SMTxTMR<23:16> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 SMTxTMR<23:16>: Significant bits of the SMT Counter - Upper Byte DS40001770A-page 456 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 REGISTER 30-12: SMTxCPRL: SMT CAPTURED PERIOD REGISTER - LOW BYTE R-x/x R-x/x R-x/x R-x/x R-x/x R-x/x R-x/x R-x/x SMTxCPR<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 SMTxCPR<7:0>: Significant bits of the SMT Period Latch - Low Byte REGISTER 30-13: SMTxCPRH: SMT CAPTURED PERIOD REGISTER - HIGH BYTE R-x/x R-x/x R-x/x R-x/x R-x/x R-x/x R-x/x R-x/x SMTxCPR<15:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 SMTxCPR<15:8>: Significant bits of the SMT Period Latch - High Byte REGISTER 30-14: SMTxCPRU: SMT CAPTURED PERIOD REGISTER - UPPER BYTE R-x/x R-x/x R-x/x R-x/x R-x/x R-x/x R-x/x R-x/x SMTxCPR<23:16> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 SMTxCPR<23:16>: Significant bits of the SMT Period Latch - Upper Byte 2014 Microchip Technology Inc. Preliminary DS40001770A-page 457 PIC16(L)F1615/9 REGISTER 30-15: SMTxCPWL: SMT CAPTURED PULSE WIDTH REGISTER - LOW BYTE R-x/x R-x/x R-x/x R-x/x R-x/x R-x/x R-x/x R-x/x SMTxCPW<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 SMTxCPW<7:0>: Significant bits of the SMT PW Latch - Low Byte REGISTER 30-16: SMTxCPWH: SMT CAPTURED PULSE WIDTH REGISTER - HIGH BYTE R-x/x R-x/x R-x/x R-x/x R-x/x R-x/x R-x/x R-x/x SMTxCPW<15:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 SMTxCPW<15:8>: Significant bits of the SMT PW Latch - High Byte REGISTER 30-17: SMTxCPWU: SMT CAPTURED PULSE WIDTH REGISTER - UPPER BYTE R-x/x R-x/x R-x/x R-x/x R-x/x R-x/x R-x/x R-x/x SMTxCPW<23:16> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 SMTxCPW<23:16>: Significant bits of the SMT PW Latch - Upper Byte DS40001770A-page 458 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 REGISTER 30-18: SMTxPRL: SMT PERIOD REGISTER - LOW BYTE R/W-x/1 R/W-x/1 R/W-x/1 R/W-x/1 R/W-x/1 R/W-x/1 R/W-x/1 R/W-x/1 SMTxPR<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 SMTxPR<7:0>: Significant bits of the SMT Timer Value for Period Match - Low Byte REGISTER 30-19: SMTxPRH: SMT PERIOD REGISTER - HIGH BYTE R/W-x/1 R/W-x/1 R/W-x/1 R/W-x/1 R/W-x/1 R/W-x/1 R/W-x/1 R/W-x/1 SMTxPR<15:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 SMTxPR<15:8>: Significant bits of the SMT Timer Value for Period Match - High Byte REGISTER 30-20: SMTxPRU: SMT PERIOD REGISTER - UPPER BYTE R/W-x/1 R/W-x/1 R/W-x/1 R/W-x/1 R/W-x/1 R/W-x/1 R/W-x/1 R/W-x/1 SMTxPR<23:16> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 SMTxPR<23:16>: Significant bits of the SMT Timer Value for Period Match - Upper Byte 2014 Microchip Technology Inc. Preliminary DS40001770A-page 459 PIC16(L)F1615/9 TABLE 30-3: Name SUMMARY OF REGISTERS ASSOCIATED WITH SMTx Bit 5 Bit 4 Bit 3 Bit 0 Register on Page SMT1PWAIE SMT1PRAIE SMT1IE 109 SMT1PWAIF SMT1IF Bit 7 Bit 6 PIE4 SCANIE CRCIE SMT2PWAIE SMT2PRAIE SMT2IE PIR4 SCANIF CRCIF SMT2PWAIF SMT2PRAIF SMT2IF SMT1CON0 EN -- STP WPOL SPOL CPOL SMT1CON1 SMT1GO REPEAT -- -- Bit 2 Bit 1 SMT1PRAIF SMT1PS<1:0> MODE<3:0> 114 448 449 SMT1CPRH SMT1CPR<15:8> 457 SMT1CPRL SMT1CPR<7:0> 457 SMT1CPRU SMT1CPR<23:16> 457 SMT1CPWH SMT1CPW<15:8> 458 SMT1CPWL SMT1CPW<7:0> 458 SMT1CPWU SMT1CPW<23:16> 458 SMT1PRH SMT1PR<15:8> 459 SMT1PRL SMT1PR<7:0> 459 SMT1PRU SMT1PR<23:16> SMT1SIG SMT1STAT -- -- -- CPRUP CPWUP RST 459 SSEL<4:0> -- -- TS 454 WS AS 450 SMT1TMRH SMT1TMR<15:8> 456 SMT1TMRL SMT1TMR<7:0> 456 SMT1TMRU SMT1TMR<23:16> SMT1WIN -- -- -- SMT2CLK -- -- -- -- -- SMT2CON0 EN -- STP WPOL SPOL SMT2CON1 SMT2GO REPEAT -- 456 WSEL<4:0> -- 452 CSEL<2:0> CPOL 451 SMT2PS<1:0> MODE<3:0> 448 449 SMT2CPRH SMT2CPR<15:8> 457 SMT2CPRL SMT2CPR<7:0> 457 SMT2CPRU SMT2CPR<23:16> 457 SMT2CPWH SMT2CPW<15:8> 458 SMT2CPWL SMT2CPW<7:0> 458 SMT2CPWU SMT2CPW<23:16> 458 SMT2PRH SMT2PR<15:8> 459 SMT2PRL SMT2PR<7:0> 459 SMT2PRU SMT2PR<23:16> SMT2SIG SMT2STAT -- -- -- -- -- CPRUP CPWUP RST -- -- 459 SSEL<2:0> TS WS 454 AS 450 SMT2TMRH SMT2TMR<15:8> 456 SMT2TMRL SMT2TMR<7:0> 456 SMT2TMRU SMT2TMR<23:16> SMT2WIN Legend: -- -- -- 456 WSEL<4:0> 453 x = unknown, u = unchanged, -- = unimplemented read as `0', q = value depends on condition. Shaded cells are not used for SMTx module. DS40001770A-page 460 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 NOTES: 2014 Microchip Technology Inc. Preliminary DS40001770A-page 461 PIC16(L)F1615/9 31.0 ANGULAR TIMER (AT) MODULE The Angular Timer (AT) module subdivides periodic signals into smaller equally spaced intervals, the number of which remain constant as the periodic signal frequency changes. A counter tracks the intervals starting at zero at each period event. The counter can be compared to user defined values to cause events, or the counter value can be captured by events external to the module. This allows for a variety of applications, such as measuring of A/C mains, stall detection for motors, commutation for brushless motors, and TDC detection for internal combustion engines. A second counter tracks the period time. This can be used to measure the error of the period based on a pre-programmed set point, as well as detect missing pulses in the signal. The angular timer includes the following features: * Two operating modes - Single-pulse per period - Multiple-pulses per period * Two missing pulse modes - Adaptive - Fixed * Multiple selectable clock sources * Phase clock output with polarity control * Period clock output with polarity control * Missing pulse output with polarity control * Interrupts for phase and period clock generation, as well as for missing pulse detect * Period set point and error register * Compare-pulse outputs - Independent interrupts * Capture inputs - Input polarity control - Independent interrupts 31.1 Principle of Operation Consider the statements in Equation 31-1: EQUATION 31-1: If: And: Then: F P = --R F A = --P A = R In these three equations: * * * * P represents the period count ATxPER A represents the angle or phase count ATxPHS R represents the desired resolution ATxRES F represents some arbitrary scaler value Notice that the phase count equals the desired resolution regardless of what F is. If we let F equal the ratio of a system clock to the input signal frequency then that means the phase count is a constant equaling the desired resolution regardless of the input frequency. This has many extraordinary uses including: * Use phase compare feature to create an event at a fixed phase angle in the period * Use capture feature to capture the phase angle at which an event occurs * Use error feature to monitor deviations from a user specified period time The details of these features, and more, are described in the following sections of this chapter. 31.2 Angular Timer Operating Modes The AT module operates in two basic modes: * Single-Pulse mode * Multi-Pulse mode Both modes function on the same principle: Dividing a periodic input signal into intervals, and allowing events to trigger off of these smaller intervals. The primary difference between these two modes is how the period is determined. The Single-Pulse mode determines the period as the time between every pulse in the input pulse stream. The Multi-Pulse mode determines the period as the time between missing pulses in the input pulse stream. The primary parameter for both modes is the ATxRES register pair. This value is used to determine the granularity of the phase counter and the frequency of the phase clock output of the module. DS40001770A-page 462 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 31.2.1 SINGLE-PULSE MODE The operation of Single-Pulse mode is illustrated in Figure 31-1. The calculations on the input signal are done in a few distinct steps. First, there is a divider that divides the module clock by the ATxRES register pair and uses the resulting signal to increment a period counter. This operation is expressed by Equation 31-2. This equation differs slightly from that of Equation 31-1 because the counters include the count of zero. To compensate for this, the number written to the resolution register, ATxRES, must be one less than the desired resolution. EQUATION 31-2: F ATxclk --------------------------F ATxsig ATxPER = ----------------------------------- ATxRES + 1 Notice that the division is ATxPER + 1. Ideally, this would be just ATxPER but the divider includes zero in the count. In most applications, ATxPER is a large number so the error introduced by adding one is negligible. ATxPHS counting from 0 to ATxRES is useful when the input signal represents a rotation (for example, a motor or A/C mains). In this case, the input signal is understood to provide a period pulse every 360 degrees. Since the phase clock equally divides the signal period into a number of intervals determined by the ATxRES register pair, each pulse on the phase clock output marks a fixed phase angle in that rotation, as expressed by Equation 31-4. EQUATION 31-4: 360degrees AngleReso l ution = ---------------------------------ATxRES + 1 Variables in Equation 31-2 are as follows: * ATxPER is the value of the period counter latched by the input signal. * ATxRES is the user-specified resolution. The phase counter will count up to this value. * F(ATxclk) is the ATx clock frequency. * F(ATxsig) is the input signal frequency. The second step in the angular timer's operation is the creation of the phase clock, which is also illustrated in Figure 31-1. The input clock is divided by the ATxPER value, latched-in during the previous step, and the resulting signal is used to increment the phase counter. This signal also is used as the phase clock output, and for setting the PHSIF interrupt flag bit of the ATxIR0 register. The result is that the phase counter counts from zero to a final value expressed in Equation 31-3, outputting a pulse each time the counter increments. The value of the phase counter can be accessed by software by reading the ATxPHS register pair. However, because of the synchronization required, in order for reads of this register pair to be accurate, the instruction clock (FOSC/4) needs to be at least 3x the ATx_phsclk output frequency. EQUATION 31-5: ATxPHS Angle = 360degrees ------------------------------ATxRES + 1 31.2.2 MULTI-PULSE MODE The operation of Multi-Pulse mode is illustrated in Figure 31-3. The calculations on the input signal are similar to those in Single-Pulse mode, with the primary difference relating to when the ATxPHS register pair is reset. The period counter is latched into the ATxPER register pair and reset on every input pulse except the pulse immediately following a missing pulse. The first active pulse following a missing pulse triggers all of the following: * Period clock output * PERIF interrupt * Phase counter reset EQUATION 31-3: ATxclk F --------------------------- F ATxsig ATxPHS final = ------------------------------------ ATxPER + 1 The result is a period clock output that has a period length equal to the time between missing pulses (e.g., a missing tooth in a gear). This leads to a significantly different relation between ATxRES and the maximum phase count, ATxPHS, as shown in Equation 31-6. The variables in Equation 31-3 are as follows: * ATxPHS(final) is the maximum value that the phase counter will reach before being reset by the input signal. As noted in Equation 31-1, this will equal ATxRES. * ATxPER is the maximum value of the period counter. * F(ATxclk) is the ATx clock frequency. * F(ATxsig) is the input signal frequency. 2014 Microchip Technology Inc. ATxRES can then be used with the instantaneous value of the ATxPHS register pair to get the instantaneous angle of the rotation using Equation 31-5. EQUATION 31-6: Preliminary MissP ATxPHS final = ATxRES ------------------ PulseP DS40001770A-page 463 PIC16(L)F1615/9 The variables in Equation 31-6 are as follows: * MissP is the period between missing pulses * PulseP is the period between input pulses * ATxPHS(final) is the maximum value of the phase counter This results in a phase clock output that pulses ATxRES+1 times every input pulse, and a phase counter that increments from 0 to ATxPHS(final) over the entire time between the missing pulses. Similar to Single-Pulse mode, this allows for triggered events to occur at fixed phase angles in the signal's period where the period is defined as the time between missing pulses. An example of multi-pulse operation is illustrated in the timing diagram of Figure 31-5, which also demonstrates what happens as a result of variations in the input signal period. DS40001770A-page 464 Preliminary 2014 Microchip Technology Inc. ANGULAR TIMER SIMPLIFIED BLOCK DIAGRAM, SINGLE-PULSE MODE Rev. 10-000245A 8/29/2014 ATxRES 15 Set PERIF SSEL Divide by ATxRES+1 R LC4_out 111 LC3_out 110 LC2_out 101 LC1_out 100 Preliminary ZCD1_out 011 C2OUT_sync 010 C1OUT_sync 001 Period Counter R ATx_perclk PRP 15 PREC Sync (2 Clocks) ATxsig LD ATxPER 15 ATxMISS Divide by 2 + Difference - 1 000 PPS MPP 0 APMOD ATx_missedpulse Comparator ATxINPPS PHP 1 Clock Delay PS CS HFINTOSC (16 MHz) 1 FOSC 0 Prescaler ATxclk Divide by ATxPER+1 R Phase Counter R ATx_phsclk Set PHSIF ATxclkcc 2014 Microchip Technology Inc. 15 Instruction Clock To Capture/ Compare LD ATxPHS PIC16(L)F1615/9 DS40001770A-page 465 FIGURE 31-1: 2014 Microchip Technology Inc. FIGURE 31-2: ANGULAR TIMER SIMPLIFIED BLOCK DIAGRAM, MULTI-PULSE MODE Rev. 10-000246A 7/25/2014 ATxRES 15 SSEL Divide by ATxRES+1 R LC4_out 111 LC3_out 110 LC2_out 101 LC1_out 100 Preliminary ZCD1_out 011 C2OUT_sync 010 C1OUT_sync 001 Set PERIF Period Counter R PREC ATx_missedpulse ATx_in Missing Pulse Period Trigger ATx_perclk PRP 15 ATxMISS ATxperiod ATxsig ATxPER LD 15 + Difference - Divide by 2 1 000 PPS MPP 0 APMOD ATx_missedpulse Comparator ATxINPPS PHP 1 Clock Delay PS CS 1 FOSC 0 Prescaler ATxclk Divide by ATxPER+1 R R Phase Counter Set PHSIF ATxclkcc 15 DS40001770A-page 466 Instruction Clock To Capture/ Compare LD ATxPHS PIC16(L)F1615/9 HFINTOSC (16 MHz) ATx_phsclk ANGULAR TIMER SIMPLIFIED MULTI-PULSE PERIOD TRIGGER BLOCK DIAGRAM Rev. 10-000247A 7/25/2014 1 D Q D Q ATxsig Atx_in R Atxclk ATxperiod 1 D Q Preliminary Atx_missedpulse R D Q PIC16(L)F1615/9 DS40001770A-page 467 FIGURE 31-3: 2014 Microchip Technology Inc. PIC16(L)F1615/9 31.2.3 MISSING PULSE DETECTION In both Single-Pulse and Multi-Pulse modes, the AT module monitors for missing pulses in the following manner. The latched value of the ATxPER register pair is continuously subtracted from the value of the period counter as it counts up. The result of this subtraction is compared to a third value and a missing pulse event is generated when the comparison is equal. The third value is either the ATxMISS register pair or the ATxPER register pair divided by two. The APMOD bit of ATxCON0 register (Register 31-1) selects which of these two values is used. In Single-Pulse mode, a missing pulse event generates the missing pulse output of the module as well as triggering the MISSIF interrupt. In Multi-Pulse mode, a missing pulse event generates the output and interrupt, and is also used to determine the period signal timing. 31.2.4 MISSING PULSE MODES Missing pulse detection has two modes of operation selected with the APMOD bit of the ATxCON0 register: * Adaptive * Fixed 31.2.4.1 Adaptive Missing Pulse Mode When APMOD = 1, the missing pulse detection is in the Adaptive mode. In Adaptive mode, the difference between the period counter and the latched ATxPER value is compared to the latched ATxPER value divided by two. A missing pulse event will occur when an input signal pulse is not detected within 1.5 times the previous time between pulses. If the signal input period changes, the missing pulse comparison adapts to the change to maintain the relative time to the missing pulse event at 1.5 times the previous pulse interval. 31.2.4.2 Fixed Missing Pulse Mode When APMOD = 0, the missing pulse detection is in the Fixed mode. In Fixed mode, the difference between the period counter and the latched ATxPER value is compared to the value in the ATxMISS register pair. This gives the user absolute control over when the missing pulse will be detected, with the trade-off of not being adaptive to changes in the period. DS40001770A-page 468 Preliminary 2014 Microchip Technology Inc. TIMING DIAGRAM FOR MISSING PULSE MODE Input Signal (case #1: narrow) Rev. 10-000243A 7/25/2014 Input Signal (case #2: wide) ATxPER ATx_perclk ATx_phsclk ATxPHS Preliminary FIGURE 31-5: TIMING DIAGRAM FOR MULTI-PULSE MODE Rev. 10-000244A 7/25/2014 Input Signal ATxPER ATx_missedpulse 2014 Microchip Technology Inc. ATx_perclk ATx_phsclk ATxPHS PIC16(L)F1615/9 DS40001770A-page 469 FIGURE 31-4: PIC16(L)F1615/9 31.2.5 VALID BIT The actual error can be determined with Equation 31-7. Several values used by the AT module must be calculated from external signals. As such, these values may be inaccurate for a period of time after the angular timer starts up. Because of this, the module will not output signals or trigger interrupts for a period of time after the module is enabled, or under certain other conditions that might jeopardize accurate output values. This output inhibition is indicated by the read-only VALID bit of the ATxCON1 being clear. EQUATION 31-7: F ATxclk period = --------------------------------------------------------------------F ATxsig ATxRES + 1 period - int period + 1 error% = 100 -------------------------------------------------------------- period The following cases will clear the VALID bit in hardware: * Any write to ATxRES register pair * Phase counter overflow (ATxPHS register pair) clocked beyond 0x3FF) * In-Circuit Debugger halt * EN = 0 * ATxPER register pair = 0 * Device Reset 31.3 As long as the VALID bit is cleared, the following occurs: * Period clock is not output and associated interrupts do not trigger. * Missed pulse is not output and associated interrupts do not trigger. * Phase clock is not output and associated interrupts do not trigger. * Phase counter does not increment. * Capture logic does not function and associated interrupts do not trigger. * Compare logic does not function and associated interrupts do not trigger. * Every ATxsig edge latches the period counter into the ATxPER register pair, regardless of mode. In single-pulse modes, the VALID bit becomes set upon the 3rd active input edge of the signal that latches the ATxPER register pair. In multi-pulse modes, a missing pulse trigger is also required, ensuring that at least one full revolution of the input has occurred. Input and Clock Selection The input clock for the AT module can come from either the FOSC system clock or the 16 MHz HFINTOSC, and is chosen by the CS0 bit of the ATxCLK register. In addition, the clock is run through a prescaler that can be /1, /2, /4, or /8, which is configured by the PS<1:0> bits of the ATxCON0 register. This prescaled clock is then used for all clock operations of the Angular Timer, and as such, should be used for all of the equations demonstrated above determining the Angular Timer's behavior. The input signal for the AT module can come from a variety of sources. The source is selected by the SSEL bits of the ATxSIG register (Register 31-4). 31.4 31.4.1 Module Outputs ANGLE/PHASE CLOCK OUTPUT The angle/phase clock signal (ATx_phsclk) can be used by the CLC as an input signal to combinational logic. The polarity of this signal is configured by the PHP bit of the ATxCON1 register. 31.4.2 PERIOD CLOCK OUTPUT An example of the VALID bit in Single-Pulse mode is shown in Figure 31-6. The period clock signal (ATx_perclk) can be used as an input clock for the Timer2/4/6 and Signal Measurement module, as well as an input signal to the CLC for combinational logic. The polarity of this signal is configured by the PRP bit of the ATxCON1 register (Register 31-2). 31.2.6 31.4.3 DETERMINING ACCURACY The ATxRES register pair determines the resolution of the period measurement and, by extension, the maximum value that the phase counter reaches at the end of each input signal period. The interim value, ATxPER, used to derive the phase counter is, by nature of the circuitry, an integer. The ratio of the integer value obtained by the circuit and the calculated floating point value is the inherent error of the measurement. When ATxRES is small then integer rounding results in large errors. Factors that contribute to large errors include: MISSED PULSE OUTPUT The missed pulse signal (ATx_missedpulse) can be used by the CLC as an input signal to combinational logic. The polarity of this signal is configured by the MPP bit of the ATxCON1 register. * Large values for ATxRES * Relatively low ATxclk frequency * Relatively high ATxsig input frequency DS40001770A-page 470 Preliminary 2014 Microchip Technology Inc. EXAMPLE OPERATION (ATxRES = 4) Rev. 10-000242A 5/29/2014 ATxRES 4 Input Signal ATxPER 5 20 Atx_phsclk ATxPHS VALID 0 0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2 3 PIC16(L)F1615/9 DS40001770A-page 471 FIGURE 31-6: Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 31.5 The capture event also generates a pulse that can be used for the following: Period Set Point and Error Measurement The ATxSTPT register pair controls the period set point of the AT module. The signal period captured in the ATxPER register pair at every signal input pulse. The unsigned 15-bit ATxSTPT value is subtracted from the unsigned 15-bit ATxPER value and the signed 16-bit result is placed in the ATxERR register pair. The ATxSTPT value is double buffered requiring an ATxSTPTL value write for the ATxSTPTH value to take effect. This is done so that all 16 bits update at the same time, thereby avoiding a miscalculation of the error. FIGURE 31-7: The capture input signal source is selected by the capture/compare's respective ATxCSELy register (Register 31-22), and its polarity is selected by the ATxCAPyP bit of the ATxCCONy register (Register 31-21). Note that when in Capture mode, the ATxCCy register pair is read-only. COMPARE MODE Compare mode is selected when the CCyMODE bit (of the ATxCCONy register) = 0. Refer to Figure 31-9. In Compare mode, the module compares the current value in the ATxCCy register pair to the phase counter value. When the two values are equal then a compare event is generated and output to the following: ATxSTPT + See Section 31.7 "Interrupts" for more details on the interrupts triggered by the AT module. 31.6.2 ANGULAR TIMER SET POINT CALCULATION BLOCK DIAGRAM Rev. 10-000216A 7/25/2014 ATxPER * Trigger an ADC reading * CLC logic input * Set the CCyIF bit * Trigger an ADC reading * CLC logic input * Set the CCyIF bit Difference See Section 31.7 "Interrupts" for more details on the interrupts triggered by the AT module. ATxERR 31.6 Capture and Compare Functions The angular timer contains multiple built-in capture/compare modules. These are controlled by their respective ATxCCONy registers where "x" refers to the AT instance and "y' refers to the Capture/Compare instance within that AT module. This particular device contains three capture/compare modules within the AT module. The CCyMODE bit of the ATxCCONy register controls whether each particular module is in Capture or Compare mode. The polarity of each module's respective output signal is controlled by the CCyPOL bit of the ATxCCONy register (Register 31-21). Both the Capture and Compare modes use an edge detect that runs off of the ATxclk signal. 31.6.1 CAPTURE MODE Capture mode is selected when the CCyMODE bit (of the ATxCCONy register) = 1. Refer to Figure 31-8. In Capture mode, the value of the phase counter is written to the respective ATxCCy registers on the rising edge of the capture input signal. DS40001770A-page 472 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 FIGURE 31-8: ANGULAR TIMER CAPTURE/COMPARE UNIT BLOCK DIAGRAM: CAPTURE MODE Rev. 10-000218A 7/25/2014 ATxPHS FOSC Clock Sync(2) Set CCyIF(1) ATxCCy(1) CCPyPOL ATx_cmpy(1) PPS ATCCyPPS(1) Notes 1: This diagram applies to all capture/compare units in the Angular Timer module. Replace "y" with the appropriate number for all registers/ signals The CCyIF interrupt trigger is synchronized with FOSC unless the device is in Sleep, in which case this synchronizer is bypassed 2: FIGURE 31-9: ANGULAR TIMER CAPTURE/COMPARE UNIT BLOCK DIAGRAM: COMPARE MODE Rev. 10-000217A 7/25/2014 ATxCCy(1) FOSC Clock Sync(2) CCPyPOL Compare Set CCyIF(1) ATx_cmpy(1) ATx_clkcc ATxPHS Notes 1: 2: This diagram applies to all capture/compare units in the Angular Timer module. Replace "y" with the appropriate number for all registers/ signals The CCyIF interrupt trigger is synchronized with FOSC unless the device is in Sleep, in which case this synchronizer is bypassed 2014 Microchip Technology Inc. Preliminary DS40001770A-page 473 PIC16(L)F1615/9 31.7 31.7.4 Interrupts The angular timer and its capture/compare features can generate multiple interrupt conditions. To accommodate all of these interrupt sources, the module is provided with its own interrupt logic structure, similar to that of the micro controller. Angular timer interrupts are enabled by the ATxIE0 register (Register 31-13) and their respective flags are located in the ATxIR0 register (Register 31-14). The capture/compare interrupts are enabled by the ATxIE1 register (Register 31-15) with flags in the ATxIR1 register (Register 31-16). All sources are funneled into a single Angular Timer Interrupt Flag bit, ATxIF of the PIR5 register (Register 7-11). This means that upon a triggered interrupt, the ATxIR0 and ATxIR1 register bits will indicate the source of the triggered interrupt. It also means that in order for specific interrupts to generate a microcontroller interrupt, both the ATxIE bit of the PIE register and the desired enable bit in either ATxIE0 or ATxIE1 must be set. Note: 31.7.1 ANGULAR TIMER CAPTURE/COMPARE INTERRUPTS Capture and compare interrupts are triggered by the capture/compare functions of the module. If configured for Capture mode, the interrupt will trigger after the capture signal has successfully latched the value of the phase counter into the capture registers. If configured for Compare mode, the interrupt will trigger when a match is detected between the value placed in the compare register and the value of the phase counter. These interrupts are controlled by the CC1IE, CC2IE, and CC3IE bits of the ATxIE1 register, respectively, and are similarly indicated by the CC1IF, CC2IF, and CC3IF bits of the ATxIR1 register. Due to the nature of the angular timer interrupts, the ATxIF flag bit of the PIR5 register is read-only. ANGULAR TIMER PERIOD INTERRUPT This interrupt is triggered when the AT module detects a period event. In Single-Pulse mode, a period event occurs on every input signal edge. In Multi-Pulse mode, a period event occurs on the input signal edge following a missed pulse. The period interrupt generation matches with the pulses on the period clock output of the timer. It is enabled by the ATPERIE bit of the ATxIE0 register and the status is indicated by the PERIF bit of the ATxIR0 register. 31.7.2 ANGULAR TIMER PHASE CLOCK INTERRUPT This interrupt is triggered on each pulse of the phase clock output of the timer. It is enabled by the ATPHIE bit of the ATxIE0 register and the status is indicated by the PHSIF bit of the ATxIR0 register. 31.7.3 ANGULAR TIMER MISSING PULSE INTERRUPT This interrupt is triggered upon the output of a missing pulse detection signal. Refer to Section 31.2.3 "Missing Pulse Detection" for more information. This interrupt is enabled by the ATMISSIE bit of the ATxIE0 register and its status is indicated by the ATMISSIF bit of the ATxIR0 register. DS40001770A-page 474 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 31.8 Angular Timer Control Registers Long bit name prefixes for the angular timer peripherals are shown in Table 31-1. Refer to Section 1.1 "Register and Bit Naming Conventions" for more information. TABLE 31-1: Peripheral Bit Name Prefix AT1 AT1 REGISTER 31-1: ATxCON0: ANGULAR TIMER CONTROL 0 REGISTER R/W-0/0 R/W-0/0 EN PREC R/W-0/0 R/W-0/0 PS<1:0> R/W-0/0 U-0 R/W-0/0 R/W-0/0 POL -- APMOD MODE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7 EN: Angular Timer Enable bit 1 = Angular timer is enabled; internal clocks are active 0 = Angular timer is disabled bit 6 PREC: Period Precision Control bit 1 = Period prescaler is reset at the start of every period 0 = Period prescaler is not reset at the start of every period; fraction period affects next period measurement bit 5-4 PS<1:0>: Clock Prescaler Control bits 11 = Resolution and phase counter prescale logic is clocked by ATxCLK/8 10 = Resolution and phase counter prescale logic is clocked by ATxCLK/4 01 = Resolution and phase counter prescale logic is clocked by ATxCLK/2 00 = Resolution and phase counter prescale logic is clocked by ATxCLK bit 3 POL: ATxsig Active Edge (Polarity) Select bit 1 = Falling edge of ATxsig is the active edge 0 = Rising edge of ATxsig is the active edge bit 2 Unimplemented: Read as `0' bit 1 APMOD: Adaptive Missing Pulse Mode Select bit 1 = Adaptive Missing Pulse mode. Missing pulse is detected when no pulse is detected within 1.5 times ATxPER 0 = Fixed Missing Pulse mode. ATxMISS register pair determines missing pulse event. bit 0 MODE: Angular Timer Mode Select bit 1 = Angular timer is in Multi-Pulse mode (period of input signal defined by missing pulses) 0 = Angular timer is in Single-Pulse mode (period of input signal defined by input pulses) 2014 Microchip Technology Inc. Preliminary DS40001770A-page 475 PIC16(L)F1615/9 REGISTER 31-2: ATxCON1: ANGULAR TIMER CONTROL 1 REGISTER U-0 R/W-0/0 U-0 R/W-0/0 U-0 R/W-0/0 R-0/0 R-0/0 -- PHP -- PRP -- MPP ACCS VALID bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7 Unimplemented: Read as `0' bit 6 PHP: Phase Clock Output Polarity bit 1 = Phase clock output is active-low 0 = Phase clock output is active-high bit 5 Unimplemented: Read as `0' bit 4 PRP: Period Clock Output Polarity bit 1 = Period clock output is active-low 0 = Period clock output is active-high bit 3 Unimplemented: Read as `0' bit 2 MPP: Missing Pulse Output Polarity bit 1 = Missing pulse output is active-low 0 = Missing pulse output is active-high bit 1 ACCS: Acceleration Sign bit 1 = The value currently in ATxPER is less than the previous value 0 = The value currently in ATxPER is greater than or equal to the previous value bit 0 VALID: Valid Measurement bit 1 = Sufficient input cycles have occurred to make ATxPER and ATxPHS valid. 0 = The values in ATxPER and ATxPHS are not valid; not enough input cycles have occurred DS40001770A-page 476 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 REGISTER 31-3: ATxCLK: ANGULAR TIMER CLOCK SELECTION REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-x/x -- -- -- -- -- -- -- CS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-1 Unimplemented: Read as `0' bit 0 CS0: Angular Timer Clock Selection bit 1 = HFINTOSC 16 MHz 0 = FOSC REGISTER 31-4: ATxSIG: ANGULAR TIMER INPUT SIGNAL SELECTION REGISTER U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- R/W-x/x R/W-x/x R/W-x/x SSEL<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-3 Unimplemented: Read as `0' bit 2-0 SSEL<2:0>: Angular Timer Clock Selection bit 111 = LC4_out 110 = LC3_out 101 = LC2_out 100 = LC1_out 011 = ZCD1_out 010 = cmp2_sync 001 = cmp1_sync 000 = ATxINPPS 2014 Microchip Technology Inc. Preliminary DS40001770A-page 477 PIC16(L)F1615/9 REGISTER 31-5: ATxRESH: ANGULAR TIMER RESOLUTION HIGH REGISTER U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- R/W-x/u R/W-x/u RES<9:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-2 Unimplemented: Read as `0' bit 1-0 RES<9:8>: ATxRES Most Significant bits, the Phase Counter Resolution Note 1: 2: Writing to this register resets VALID bit of the ATxCON1 (Register 31-2); output signals are inhibited for at least two input cycles. This register is not guarded for atomic access, and should only be accessed while the timer is not running. REGISTER 31-6: R/W-x/u ATxRESL: ANGULAR TIMER RESOLUTION LOW REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u RES<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition RES<7:0>: ATxRES Least Significant bits, the Phase Counter Resolution bit 7-0 Note 1: 2: Writing to this register resets VALID bit of the ATxCON1 (Register 31-2); output signals are inhibited for at least two input cycles. This register is not guarded for atomic access, and should only be accessed while the timer is not running. DS40001770A-page 478 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 REGISTER 31-7: R/W-x/u ATxMISSH: ANGULAR TIMER MISSING PULSE DELAY HIGH REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u MISS<15:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-0 MISS<15:8>: Most Significant bits (2's complement) of ATxMISS. ATxMISS defines the period counter value at which the missing pulse output becomes valid, based on the difference between the current counter value and the latched-in value of ATxPER. REGISTER 31-8: R/W-x/u ATxMISSL: ANGULAR TIMER MISSING PULSE DELAY LOW REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u MISS<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-0 MISS<7:0>: Least Significant bits (2's complement) of ATxMISS. ATxMISS defines the period counter value at which the missing pulse output becomes valid, based on the difference between the current counter value and the latched-in value of ATxPER. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 479 PIC16(L)F1615/9 REGISTER 31-9: R-x/x ATxPERH: ANGULAR TIMER MEASURED PERIOD HIGH REGISTER R-x/x R-x/x R-x/x POV R-x/x R-x/x R-x/x R-x/x PER<14:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7 POV: Period Counter Overflow bit 1 = Counter rolled over one or more times during measurement 0 = Value shown by ATxPER is valid bit 6-0 PER<14:8>: Most Significant bits of ATxPER. ATxPER is the measured period value from the period counter. REGISTER 31-10: ATxPERL: ANGULAR TIMER MEASURED PERIOD LOW REGISTER R-x/x R-x/x R-x/x R-x/x R-x/x R-x/x R-x/x R-x/x PER<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-0 PER<7:0>: Least Significant bits of ATxPER. ATxPER is the measured period value from the period counter. DS40001770A-page 480 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 REGISTER 31-11: ATxPHSH: ANGULAR TIMER PHASE COUNTER HIGH REGISTER U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- R-x/x R-x/x PHS<9:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-2 Unimplemented: Read as `0' bit 1-0 PHS<9:8>: Most Significant bits of ATxPHS. ATxPHS is the instantaneous value of the phase counter. REGISTER 31-12: ATxPHSL: ANGULAR TIMER PHASE COUNTER LOW REGISTER R-x/x R-x/x R-x/x R-x/x R-x/x R-x/x R-x/x R-x/x PHS<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-0 PHS<7:0>: Least Significant bits of ATxPHS. ATxPHS is the instantaneous value of the phase counter. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 481 PIC16(L)F1615/9 REGISTER 31-13: ATxIE0: ANGULAR TIMER ENABLE 0 REGISTER U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 -- -- -- -- -- PHSIE MISSIE PERIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-3 Unimplemented: Read as `0' bit 2 PHSIE: Phase Interrupt Enable bit 1 = The phase interrupt is enabled 0 = The phase interrupt is disabled bit 1 MISSIE: Missed Pulse Interrupt Enable bit 1 = The missed pulse interrupt is enabled 0 = The missed pulse interrupt is disabled bit 0 PERIE: Period Interrupt Enable bit 1 = The period interrupt is enabled 0 = The period interrupt is disabled REGISTER 31-14: ATxIR0: ANGULAR TIMER INTERRUPT FLAG 0 REGISTER U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 -- -- -- -- -- PHSIF MISSIF PERIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-3 Unimplemented: Read as `0' bit 2 PHSIF: Phase Interrupt Flag bit 1 = The phase interrupt has occurred 0 = The phase interrupt has not occurred, or has been cleared bit 1 MISSIF: Missed Pulse Interrupt Flag bit 1 = The missed pulse interrupt has occurred 0 = The missed pulse interrupt has not occurred, or has been cleared bit 0 PERIF: Period Interrupt Flag bit 1 = The period interrupt has occurred 0 = The period interrupt has not occurred, or has been cleared DS40001770A-page 482 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 REGISTER 31-15: ATxIE1: ANGULAR TIMER ENABLE 1 REGISTER U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 -- -- -- -- -- CC3IE CC2IE CC1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-3 Unimplemented: Read as `0' bit 2 CC3IE: Capture/Compare Interrupt 3 Enable bit If CC3MODE = 1 (Capture) 1 = Capture interrupt 3 is enabled 0 = Capture interrupt 3 is disabled If CC3MODE = 0 (Compare) 1 = Compare interrupt 3 is enabled 0 = Compare interrupt 3 is disabled bit 1 CC2IE: Capture/Compare Interrupt 2 Enable bit If CC2MODE = 1 (Capture) 1 = Capture interrupt 2 is enabled 0 = Capture interrupt 2 is disabled If CC2MODE = 0 (Compare) 1 = Compare interrupt 2 is enabled 0 = Compare interrupt 2 is disabled bit 0 CC1IE: Capture/Compare Interrupt 1 Enable bit If CC1MODE = 1 (Capture) 1 = Capture interrupt 1 is enabled 0 = Capture interrupt 1 is disabled If CC1MODE = 0 (Compare) 1 = Compare interrupt 1 is enabled 0 = Compare interrupt 1 is disabled 2014 Microchip Technology Inc. Preliminary DS40001770A-page 483 PIC16(L)F1615/9 REGISTER 31-16: ATxIR1: ANGULAR TIMER INTERRUPT FLAG 1 REGISTER U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 -- -- -- -- -- CC3IF CC2IF CC1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-3 Unimplemented: Read as `0' bit 2 CC3IF: Capture/Compare Interrupt 3 Flag bit If CC3MODE = 1 (Capture) 1 = Capture interrupt 3 has occurred; captured phase value is in ATxCC3 0 = Capture interrupt 3 has not occurred, or has been cleared If CC3MODE = 0 (Compare) 1 = Compare interrupt 3 has occurred 0 = Compare interrupt 3 has not occurred, or has been cleared bit 1 CC2IF: Capture/Compare Interrupt 2 Flag bit If CC2MODE = 1 (Capture) 1 = Capture interrupt 2 has occurred; captured phase value is in ATxCC2 0 = Capture interrupt 2 has not occurred, or has been cleared If CC2MODE = 0 (Compare) 1 = Compare interrupt 2 has occurred 0 = Compare interrupt 2 has not occurred, or has been cleared bit 0 CC1IF: Capture/Compare Interrupt 1 Flag bit If CC1MODE = 1 (Capture) 1 = Capture interrupt 1 has occurred; captured phase value is in ATxCC1 0 = Capture interrupt 1 has not occurred, or has been cleared If CC1MODE = 0 (Compare) 1 = Compare interrupt 1 has occurred 0 = Compare interrupt 1 has not occurred, or has been cleared DS40001770A-page 484 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 REGISTER 31-17: ATxSTPTH: ANGULAR TIMER SET POINT HIGH REGISTER (1) U-0 R/W-x/u R/W-x/u R/W-x/u -- R/W-x/u R/W-x/u R/W-x/u R/W-x/u STPT<14:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7 Unimplemented: Read as `0' bit 6-0 STPT<14:8>: Set Point Most Significant bits. ATxSTPT determines the threshold setting that the period is compared against for error calculation. Note 1: Writes to ATxSTPTH are double buffered. The value written to this register is held until a write to ATxSTPTL occurs, at which point the value will be latched into the register REGISTER 31-18: ATxSTPTL: ANGULAR TIMER SET POINT LOW REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u STPT<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-0 STPT<7:0>: Set Point Least Significant bits. ATxSTPT determines the threshold setting that the period is compared against for error calculation. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 485 PIC16(L)F1615/9 REGISTER 31-19: ATxERRH: ANGULAR TIMER SET POINT ERROR VALUE HIGH REGISTER R-x/x R-x/x R-x/x R-x/x R-x/x R-x/x R-x/x R-x/x ERR<15:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-0 ERR<15:8>: Most Significant bits of ATxERR. ATxERR is the error of the measured period value compared to the threshold setting, defined as ATxPER-ATxSTPTP. REGISTER 31-20: ATxERRL: ANGULAR TIMER SET POINT ERROR VALUE LOW REGISTER R-x/x R-x/x R-x/x R-x/x R-x/x R-x/x R-x/x R-x/x ERR<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-0 ERR<7:0>: Least Significant bits of ATxERR. ATxERR is the error of the measured period value compared to the threshold setting, defined as ATxPER-ATxSTPTP. DS40001770A-page 486 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 REGISTER 31-21: ATxCCONy: ANGULAR TIMER CAPTURE/COMPARE CONTROL 1 REGISTER R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 CCyEN -- -- CCPyPOL CAPyP -- -- CCyMODE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7 CCyEN: Capture/Compare Enable bit 1 = Capture/Compare logic is enabled 0 = Capture/Compare logic is disabled bit 6-5 Unimplemented: Read as `0' bit 4 CCyPOL: Capture/Compare Output Polarity bit In Capture mode (CCyMODE = 1): 1 = ATxCCOUT1 is active low when ATxCCy is updated 0 = ATxCCOUT1 is active high when ATxCCy is updated In Compare mode (CCyMODE = 0): 1 = ATxCCOUT1 is active low when ATxPHS = ATxCCy 0 = ATxCCOUT1 is active high when ATxPHS = ATxCCy bit 3 CAPyP: Capture Input Polarity bit In Capture mode (CCyMODE = 1): 1 = At falling edge of the capture input (Selected by ATxCSELy) the value of the phase counter is captured in ATxCC1 0 = At rising edge of the capture input (Selected by ATxCSELy) the value of the phase counter is captured in ATxCC1 In Compare mode (CCyMODE = 0): This bit is ignored. bit 2-1 Unimplemented: Read as `0' bit 0 CCyMODE: Capture/Compare Mode Select bit 1 = Capture/compare logic is in Capture mode 0 = Capture/compare logic is in Compare mode 2014 Microchip Technology Inc. Preliminary DS40001770A-page 487 PIC16(L)F1615/9 REGISTER 31-22: ATxCSELy: ANGULAR TIMER CAPTURE INPUT SELECT y REGISTER U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- R/W-0/0 R/W-0/0 R/W-0/0 CPyS<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-3 Unimplemented: Read as `0' bit 2-0 CPyS<2:0>: Capture Input Source Select bits 111 = CWG_interrupt 110 = LC4_out 101 = LC3_out 100 = LC2_out 111 = LC1_out 010 = cmp2_sync 001 = cmp1_sync 000 = ATxCAP pin DS40001770A-page 488 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 REGISTER 31-23: ATxCCyH: ANGULAR TIMER CAPTURE/COMPARE y HIGH REGISTER U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- R/q-0/0 R/q-0/0 CCy<9:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-2 Unimplemented: Read as `0' bit 1-0 CCy<9:8>: ATxCCy Most Significant bits In Capture mode (CCyMODE = 1) (Read-only): ATxCCy is the captured value of ATxPHS when the capture input is signaled. In Compare mode (CCyMODE = 0): ATxCCy is the value that is compared to the current value of ATxPHS to trigger an interrupt/output pulse. Note 1: Writes to ATxCCyH are double buffered. The value written to this register is held until a write to ATxCCyL occurs, at which point the value will be latched into the register REGISTER 31-24: ATxCCyL: ANGULAR TIMER CAPTURE/COMPARE y LOW REGISTER R/q-0/0 R/q-0/0 R/q-0/0 R/q-0/0 R/q-0/0 R/q-0/0 R/q-0/0 R/q-0/0 CCy<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-0 CCy<7:0>: ATxCCy Least Significant bits In Capture mode (CCyMODE = 1) (Read-only): ATxCCy is the captured value of ATxPHS when the capture input is signaled. In Compare mode (CCyMODE = 0): ATxCCy is the value that is compared to the current value of ATxPHS to trigger an interrupt/output pulse. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 489 PIC16(L)F1615/9 TABLE 31-2: Name SUMMARY OF REGISTERS ASSOCIATED WITH THE ANGULAR TIMER MODULE Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 -- -- -- -- -- -- AT1CCON1 CC1EN -- -- CC1POL CAP1P -- -- CC1MODE 487 AT1CCON2 CC2EN -- -- CC2POL CAP2P -- -- CC2MODE 487 AT1CCON3 AT1CC1H AT1CC1L Bit 1 Bit 0 Register on page Bit 7 CC1<9:8> CC1<7:0> 489 489 CC3EN -- -- CC3POL CAP3P -- -- CC3MODE 487 AT1CLK -- -- -- -- -- -- -- CS0 477 AT1CON0 EN PREC POL -- APMOD MODE 475 MPP ACCS VALID 476 PS<1:0> AT1CON1 -- PHP -- PRP -- AT1CSEL1 -- -- -- -- -- CP1S<2:0> 488 AT1CSEL2 -- -- -- -- -- CP2S<2:0> 488 AT1CSEL3 -- -- -- -- -- CP3S<2:0> 488 AT1ERRH ERR<15:8> 486 AT1ERRL ERR<7:0> 486 AT1IE0 -- -- -- -- -- PHSIE MISSIE PERIE 482 AT1IR0 -- -- -- -- -- PHSIF MISSIF PERIF 482 AT1IE1 -- -- -- -- -- CC3IE CC2IE CC1IE 483 AT1IR1 -- -- -- -- -- CC3IF CC2IF CC1IF 484 AT1MISSH MISS<15:8> 479 AT1MISSL MISS<7:0> 479 AT1PERH POV PER<14:8> AT1PERL AT1PHSH -- -- -- -- AT1PHSL AT1RESH 480 PER<7:0> -- 480 -- PHS<9:8> PHS<7:0> -- -- -- -- AT1RESL -- 481 -- RES<9:8> RES<7:0> AT1SIG -- AT1STPTH -- -- -- -- 478 478 -- SSEL<2:0> 477 STPT<14:8> AT1STPTL 481 485 STPT<7:0> 485 PIE5 TMR3GIE TMR3IE TMR5GIE TMR5IE -- AT1IE PID1EIE PID1DIE 110 PIR5 TMR3GIF TMR3IF TMR5GIF TMR5IF -- AT1IF PID1EIF PID1DIF 115 Legend: -- = unimplemented, read as `0'. Shaded cells are unused by the AT module. DS40001770A-page 490 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 NOTES: 2014 Microchip Technology Inc. Preliminary DS40001770A-page 491 PIC16(L)F1615/9 32.0 MATH ACCELERATOR WITH PROPORTIONAL-INTEGRALDERIVATIVE (PID) MODULE The math accelerator module is a mathematics module that can perform a variety of operations, most prominently acting as a PID (Proportional-Integral-Derivative) controller. A PID controller is an algorithm that uses the present error (proportional), the sum of the present and all previous errors (integral), and the difference between the present and previous change (derivative) to correct errors and provide stability in a system. It provides feedback to a system through a series of iterations, using the present error as well as previous errors to calculate a new input to the controller. The data flow for both PID modes is illustrated in Figure 32-1. The module accomplishes the task of calculating the PID algorithm by utilizing user-provided coefficients along with a multiplier and accumulator. As such, this multiplier and accumulator can also be configured to quickly and efficiently perform signed and unsigned multiply-and-add calculations both with and without accumulation. The data flow for these modes is illustrated in Figure 32-2. 32.1 PID Module Setup Summary The PID module can be configured either as a PID controller or as a multiply and accumulate module. Multiply and accumulate can be performed in four modes: * * * * Unsigned multiply and add, without accumulation Unsigned multiply and accumulate Signed multiply and add, without accumulation Signed multiply and accumulate All of the modes are selected by the MODE<2:0> bits of the PIDxCON register. 32.1.1 PID MODE SETUP AND OPERATION When the MODE<2:0> bits of the PIDxCON register are equal to `101', the module is in PID controller mode. The operation of the module in PID controller mode is generally performed as a loop. The input from an external system is fed into the controller, and the controller's output is fed back into the external system. This will produce a new response from the system that is then looped back into the PID controller. The data flow for the PID operation is illustrated in Figure 32-1. Features of this module include: * Signed multiplier * 35-bit signed accumulator * PID controller support with user inputs for K1, K2, K3, system error and desired set point * Completion and Error interrupts * Multiple user modes allowing for PID with or without accumulation as well as several multiplication operations DS40001770A-page 492 Preliminary 2014 Microchip Technology Inc. PID MODULE BASIC DATA FLOW BLOCK DIAGRAM, PID MODES PIDxSET Rev. 10-000227A 6/5/2014 PIDxK1 + Difference Multiplier - PIDxIIN PIDxK2 Preliminary PIDxZ1 Multiplier + + + Adder PIDxACC + + Accumulator PIDxK3 2014 Microchip Technology Inc. PIDxZ2 Note 1: Multiplier After the results of PIDxZ2 are multiplied by PIDxK3 and the result is added to the accumulator, the current value from PIDxZ1 is loaded into PIDxZ2. The same is true for PIDxZ1 and the current SET-IN value. PIDxOUT PIC16(L)F1615/9 DS40001770A-page 493 FIGURE 32-1: PIC16(L)F1615/9 Within the controller, the input is subtracted from a preprogrammed set point to get an error value. This error value, along with the previous two error values (if any), are multiplied by user-input coefficients and the results of these multiplications are added together to make up the output. If the MODE<2:0> bits of the PIDxCON register = 101, the PID output is equal to the current output added to any previous outputs. To operate the module in PID controller mode, perform the following steps: The three user-input coefficients (K1, K2, and K3) are derived from the three classic PID coefficients Kp, Ki, and Kd, and must be calculated prior to using the PID module. 3. 1. Set the MODE<2:0> bits of the PIDxCON register to `101', then set the EN bit of the PIDxCON register. Write the previously calculated K1, K2, and K3 values to the PIDxK1, PIDxK2, and PIDxK3 registers, respectively. Write the desired set point that the input will be compared against to the PIDxSET registers. Write the high byte of the value from the external system to PIDxINH. Then write the low byte of the value from the external system to PIDxINL. This will begin the calculation and set the BUSY bit of the PIDxCON register. Either poll the BUSY bit of the PIDxCON register to check for it clearing or wait for the PIDxDIF interrupt to trigger, indicating that the operation has completed. Read the PIDxOUT registers for the output value. If the PID was in Accumulation mode, PIDxOUT will contain the accumulation of the output added to the previous outputs, otherwise, it will contain only the latest output. For proper PID operation, this output needs to be applied to the external system before the next input to the PID is applied. This is to ensure that the system can adjust based on the PID controller's feedback before the next calculation is made. 2. 4. K1 is the coefficient that is multiplied with the current error (SET-IN). It is defined by the following equation: 5. EQUATION 32-1: 6. Kd K1 = Kp + Ki T + ------T Note: 2. 1. T is the sampling period. 7. K2 is the coefficient that is multiplied with the previous iteration's error (Z1). Where T is the sampling period, it is defined by the following equation: Note: EQUATION 32-2: 2Kd K2 = - Kp + ---------- T Note: 3. 32.1.2 T is the sampling period. K3 is the coefficient that is multiplied with the error that occurred two iterations previous to the current one (Z2). It is defined by the following equation: EQUATION 32-3: Kd K3 = ------T Note: The BUSY bit of the PIDxCON register goes high as soon as PIDxINL is written and remains high until all computation is complete. Until the BUSY bit goes low, the PIDxOUT values are not valid, and none of the registers associated with the PID module should be written to, as any such writes will corrupt the calculation. CONTEXT SAVING It is possible to save the current state of the PID controller in software and restore it at a later time. In order to perform this, a calculation must not currently be active (BUSY = 0). Saving the PIDxOUT, PIDxZ1, and PIDxZ2 values elsewhere in memory will save the current state of the PID controller, although it may be desirable to also save PIDxK1, PIDxK2, PIDxK3, and/ or PIDxSET, depending on the application. At the desired later time, these values can be written back into their respective registers, writing PIDxINL last, and the PID will continue from its previous state. T is the sampling period. DS40001770A-page 494 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 32.2 Add and Multiply Mode Setup and Operation The PID module can also be used to perform 16-bit Add and Multiply computations. When the MODE<2:0> bits of the PIDxCON register are equal to `000', `001', `010', or `011', the module is in Add and Multiply mode. The data flow for the multiply and add operation is illustrated in Figure 32-2. FIGURE 32-2: PID MODULE BASIC DATA FLOW BLOCK DIAGRAM, ADD AND MULTIPLY MODES Rev. 10-000228A 5/12/2014 0 PIDxIN PIDxK1 0 MODE<0> + Adder Multiplier PIDxACC + + 1 Adder PIDxOUT + PIDxSET All Add and Multiply modes perform operations of the following form. 1. EQUATION 32-4: OUTPUT = A + B C Note: In order to perform an Add and Multiply operation, perform the following steps: 2. A = PIDxIN, B = PICxSET, and C = PIDxK1. 3. The four different Add and Multiply modes are: * MODE<2:0> = 000: Inputs are unsigned, and the output does not accumulate * MODE<2:0> = 001: Inputs are unsigned, and the output accumulates with previous outputs * MODE<2:0> = 010: Inputs are signed, and the output does not accumulate * MODE<2:0> = 011: Inputs are signed, and the output accumulates with previous outputs 4. 5. Set the MODE<2:0> bits of the PIDxCON register to one of the four Add/Multiply modes, depending on which form of the calculation is desired, then set the EN bit of the PIDxCON register. Write the value of C to the PIDxK1H/L register pair and the value of B to the PIDxSETH/L register pair, as well as the high byte of A to the PIDxINH register. Finally, write the low byte of A to the PIDxINL register. This will begin the mathematical operation and set the BUSY bit of the PIDxCON register. Either poll the BUSY bit of the PIDxCON register to check for it clearing or wait for the PIDxDIF interrupt to trigger, indicating that the operation has completed. Read the PIDxOUT registers for the result of the calculation. In accumulation modes, the PIDxOUT register will hold any previous values added to the current calculation's value. In nonaccumulation modes, the PIDxOUT register will just hold the current calculation's value. These modes can also be used to perform 16-bit addition (by setting the C term in the above equation to 1) or 16-bit multiplication (by setting A or B to 0). 2014 Microchip Technology Inc. Preliminary DS40001770A-page 495 PIC16(L)F1615/9 32.3 Interrupts The PID module has two interrupts, indicated by the interrupt flags PIDxDIF and PIDxEIF in the PIR5 register, and controlled by the interrupt control bits PIDxDIE and PIDxEIE, respectively, in the PIE5 register. The PIDxDIF interrupt triggers at the successful completion of a calculation, when the BUSY bit of the PIDxCON register goes low. The PIDxEIF interrupt triggers when there is an error in the PID or multiply and add calculation, specifically an overflow error on the output value. 32.4 Handling Error Overflow If a calculation causes an overflow of the value in the OUT registers, the value in said registers will roll over and the PIDxEIF interrupt will trigger. In the case of a PID calculation, this indicates that the error has outpaced the PID's capability to correct for the error of the system. In this case, it is recommended to `saturate' the OUT registers in software whenever the PIDxEIF interrupt is set as part of the Interrupt Service Routine (IRS), as shown in Example 32-1. EXAMPLE 32-1: HANDLING PID OVERFLOWS //Interrupt service routine void interrupt ISR(void) IF (PIR5BITS.PID1EIF==1&&PIE5BITS.PID1EIE==1) { //saturate the PID1OUT registers PID1OUTHH=0xFF; PID1OUTHL=0xFF; PID1OUTLH=0xFF; PID1OUTLL=0xFF; PID1OUTHH=0xFF; //clear the interrupt flag PIR5bits.PID1EIF=0; } DS40001770A-page 496 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 32.5 PID Control Registers Long bit name prefixes for the 16-bit PID peripherals are shown in Table 32-1. Refer to Section 1.1 "Register and Bit Naming Conventions" for more information TABLE 32-1: Peripheral Bit Name Prefix PID1 PID1 REGISTER 32-1: PIDxCON: PID CONFIGURATION REGISTER R/W-0/0 R/HS/HC-0/0 U-0 U-0 U-0 EN BUSY -- -- -- R/W-0/0 R/W-0/0 R/W-0/0 MODE<2:0> bit 7 bit 0 Legend: HC = Bit is cleared by hardware HS = Bit is set by hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -m/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7 EN: PID Module Enable bit 1 = PID module is enabled 0 = PID module is disabled bit 6 BUSY: PID module is currently calculating bit 5-3 Unimplemented: Read as `0' bit 2-0 MODE<2:0>: PID Mode Control bits 11x = Reserved. Do not use. 101 = PID output is the calculated output (current error plus accumulated previous errors) in 2's complement notation 100 = Reserved. Do not use. 011 = (IN<15:0>+SET<15:0>)*K1<15:0> 2's complement signed inputs, with accumulation 010 = (IN<15:0>+SET<15:0>)*K1<15:0> 2's complement signed inputs, without accumulation 001 = (IN<15:0>+SET<15:0>)*K1<15:0> unsigned inputs, with accumulation 000 = (IN<15:0>+SET<15:0>)*K1<15:0> unsigned inputs, without accumulation 2014 Microchip Technology Inc. Preliminary DS40001770A-page 497 PIC16(L)F1615/9 REGISTER 32-2: R/W-x/u PIDxINH: PID INPUT HIGH REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u IN<15:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-0 IN<15:8>: IN upper eight bits. IN is the 16-bit input from the control system to the PID module REGISTER 32-3: R/W-x/u PIDxINL: PID INPUT LOW REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u IN<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-0 IN<7:0>: IN lower eight bits. IN is the 16-bit input from the control system to the PID module REGISTER 32-4: R/W-0/0 PIDxSETH: PID SET POINT HIGH REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 SET<15:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-0 U = Unimplemented bit, read as `0' SET<15:8>: SET upper eight bits. SET is the 16-bit user-controlled variable that the input from the control system is compared against to determine the error in the system REGISTER 32-5: R/W-0/0 PIDxSETL: PID SET POINT LOW REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 SET<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-0 SET<7:0>: SET lower eight bits. SET is the 16-bit user-controlled variable that the input from the control system is compared against to determine the error in the system DS40001770A-page 498 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 REGISTER 32-6: R/W-0/0 PIDxK1H: PID K1 HIGH REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 K1<15:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-0 K1<15:8>: K1 upper eight bits. K1 is the 16-bit user-controlled coefficient calculated from Kp + Ki + Kd REGISTER 32-7: R/W-0/0 PIDxK1L: PID K1 LOW REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 K1<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-0 K1<7:0>: K1 lower eight bits. K1 is the 16-bit user-controlled coefficient calculated from Kp + Ki + Kd REGISTER 32-8: R/W-0/0 PIDxK2H: PID K2 HIGH REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 K2<15:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-0 U = Unimplemented bit, read as `0' K2<15:8>: K2 upper eight bits. K2 is the 16-bit user-controlled coefficient calculated from -(Kp + 2Kd) REGISTER 32-9: R/W-0/0 PIDxK2L: PID K2 LOW REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 K2<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-0 U = Unimplemented bit, read as `0' K2<7:0>: K2 lower eight bits. K2 is the 16-bit user-controlled coefficient calculated from -(Kp + 2Kd) 2014 Microchip Technology Inc. Preliminary DS40001770A-page 499 PIC16(L)F1615/9 REGISTER 32-10: PIDxK3H: PID K3 HIGH REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 K3<15:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-0 K3<15:8>: K3 upper eight bits. K3 is the 16-bit user-controlled coefficient calculated from Kd REGISTER 32-11: PIDxK3L: PID K3 LOW REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 K3<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-0 K3<7:0>: K3 lower eight bits. K3 is the 16-bit user-controlled coefficient calculated from Kd DS40001770A-page 500 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 REGISTER 32-12: PIDxOUTU: PID OUTPUT UPPER REGISTER U-0 U-0 U-0 U-0 -- -- -- -- R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 OUT<35:32> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-4 Unimplemented: Read as `0' bit 3-0 OUT<35:32>: Bits <35:32> of OUT. OUT is the output value of the PID after completing the designated calculation on the specified inputs. REGISTER 32-13: PIDxOUTHH: PID OUTPUT HIGH HIGH REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 OUT<31:24> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-0 OUT<31:24>: Bits <31:24> of OUT. OUT is the output value of the PID after completing the designated calculation on the specified inputs. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 501 PIC16(L)F1615/9 REGISTER 32-14: PIDxOUTHL: PID OUTPUT HIGH LOW REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 OUT<23:16> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-0 OUT<23:16>: Bits <23:16> of OUT. OUT is the output value of the PID after completing the designated calculation on the specified inputs. REGISTER 32-15: PIDxOUTLH: PID OUTPUT LOW HIGH REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 OUT<15:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-0 OUT<15:8>: Bits <15:8> of OUT. OUT is the output value of the PID after completing the designated calculation on the specified inputs. REGISTER 32-16: PIDxOUTLL: PID OUTPUT LOW LOW REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 OUT<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-0 OUT<7:0>: Bits <7:0> of OUT. OUT is the output value of the PID after completing the designated calculation on the specified inputs. DS40001770A-page 502 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 REGISTER 32-17: PIDxZ1U: PID Z1 UPPER REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 -- -- -- -- -- -- -- Z116 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-1 Unimplemented: Read as `0' bit 0 Z116: Bit 16 of Z1. In PID mode, Z1 is the value of the error (IN minus SET) from the previous iteration of the PID control loop. REGISTER 32-18: PIDxZ1H: PID Z1 HIGH REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 Z1<15:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-0 Z1<15:8>: Bits <15:8> of Z1. In PID mode, Z1 is the value of the error (IN minus SET) from the previous iteration of the PID control loop. REGISTER 32-19: PIDxZ1L: PID Z1 LOW REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 Z1<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-0 Z1<7:0>: Bits <7:0> of Z1. In PID mode, Z1 is the value of the error (IN minus SET) from the previous iteration of the PID control loop. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 503 PIC16(L)F1615/9 REGISTER 32-20: PIDxZ2U: PID Z2 UPPER REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 -- -- -- -- -- -- -- Z216 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-1 Unimplemented: Read as `0' bit 0 Z216: Bit 16 of Z2. In PID mode, Z2 is the value of the error (IN minus SET) from the previous iteration of the PID control loop. REGISTER 32-21: PIDxZ2H: PID Z2 HIGH REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 Z2<15:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-0 Z2<15:8>: Bits <15:8> of Z2. In PID mode, Z2 is the value of the error (IN minus SET) from the previous iteration of the PID control loop. REGISTER 32-22: PIDxZ2L: PID Z2 LOW REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 Z2<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-0 Z2<7:0>: Bits <7:0> of Z2. In PID mode, Z2 is the value of the error (IN minus SET) from the previous iteration of the PID control loop. DS40001770A-page 504 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 REGISTER 32-23: PIDxACCU: PID ACCUMULATOR UPPER REGISTER U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- R/W-0/0 R/W-0/0 R/W-0/0 ACC<34:32> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-3 Unimplemented: Read as `0' bit 2-0 ACC<34:32>: Bits <34:32> of ACC. ACC is the accumulator register in which all of the multiplier results for the PID are accumulated before being written to the output. REGISTER 32-24: PIDxACCHH: PID ACCUMULATOR HIGH HIGH REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ACC<31:24> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-0 ACC<31:24>: Bits <31:24> of ACC. ACC is the accumulator register in which all of the multiplier results for the PID are accumulated before being written to the output. REGISTER 32-25: PIDxACCHL: PID ACCUMULATOR HIGH LOW REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ACC<23:16> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-0 ACC<23:16>: Bits <23:16> of ACC. ACC is the accumulator register in which all of the multiplier results for the PID are accumulated before being written to the output. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 505 PIC16(L)F1615/9 REGISTER 32-26: PIDxACCLH: PID ACCUMULATOR LOW HIGH REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ACC<15:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-0 ACC<15:8>: Bits <15:8> of ACC. ACC is the accumulator register in which all of the multiplier results for the PID are accumulated before being written to the output. REGISTER 32-27: PIDxACCLL: PID ACCUMULATOR LOW LOW REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ACC<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-0 ACC<7:0>: Bits <7:0> of ACC. ACC is the accumulator register in which all of the multiplier results for the PID are accumulated before being written to the output. DS40001770A-page 506 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 TABLE 32-2: Name PID1ACCU SUMMARY OF REGISTERS ASSOCIATED WITH THE PID MODULE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 -- -- -- -- -- Bit 2 Bit 1 Bit 0 ACC<34:32> Register on page 505 PID1ACCHH ACC<31:24> 505 PID1ACCHL ACC<23:16> 505 PID1ACCLH ACC<15:8> 506 PID1ACCLL ACC<7:0> PID1CON EN BUSY -- -- PID1INH 506 -- MODE<2:0> 497 IN<15:8> 498 PID1INL IN<7:0> 498 PID1K1H K1<15:8> 499 PID1K1L K1<7:0> 499 PID1K2H K2<15:8> 499 PID1K2L K2<7:0> 499 PID1K3H K3<15:8> 500 PID1K3L K3<7:0> 500 -- PID1OUTU -- -- -- OUT<35:32> 501 PID1OUTHH OUT<31:24> 501 PID1OUTHL OUT<23:16> 502 PID1OUTLH OUT<15:8> 502 PID1OUTLL OUT<7:0> 502 PID1SETH SET<15:8> 498 PID1SETL SET<7:0> PID1Z1U -- -- -- -- -- PID1Z1H Z1<15:8> PID1Z1L Z1<7:0> PID1Z2U -- -- -- -- 498 -- -- Z116 503 503 503 -- -- -- Z216 504 PID1Z2H Z2<15:8> 504 PID1Z2L Z2<7:0> 504 PIE5 TMR3GIE TMR3IE TMR5GIE TMR5IE -- AT1IE PID1EIE PID1DIE 110 PIR5 TMR3GIF TMR3IF TMR5GIF TMR5IF -- AT1IF PID1EIF PID1DIF 115 Legend: -- = unimplemented, read as `0'. Shaded cells are unused by the PID module. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 507 PIC16(L)F1615/9 33.0 IN-CIRCUIT SERIAL PROGRAMMINGTM (ICSPTM) 33.3 ICSPTM programming allows customers to manufacture circuit boards with unprogrammed devices. Programming can be done after the assembly process allowing the device to be programmed with the most recent firmware or a custom firmware. Five pins are needed for ICSPTM programming: * ICSPCLK * ICSPDAT * MCLR/VPP * VDD * VSS Common Programming Interfaces Connection to a target device is typically done through an ICSPTM header. A commonly found connector on development tools is the RJ-11 in the 6P6C (6-pin, 6-connector) configuration. See Figure 33-1. FIGURE 33-1: In Program/Verify mode the program memory, user IDs and the Configuration Words are programmed through serial communications. The ICSPDAT pin is a bidirectional I/O used for transferring the serial data and the ICSPCLK pin is the clock input. For more information on ICSPTM refer to the "PIC12(L)F1501/PIC16(L)F150X Memory Programming Specification" (DS41573). VDD ICD RJ-11 STYLE CONNECTOR INTERFACE ICSPDAT NC 2 4 6 ICSPCLK 1 3 5 VPP/MCLR VSS Target PC Board Bottom Side Pin Description* 33.1 High-Voltage Programming Entry Mode 1 = VPP/MCLR 2 = VDD Target 3 = VSS (ground) The device is placed into High-Voltage Programming Entry mode by holding the ICSPCLK and ICSPDAT pins low then raising the voltage on MCLR/VPP to VIHH. 4 = ICSPDAT 5 = ICSPCLK 6 = No Connect 33.2 Low-Voltage Programming Entry Mode The Low-Voltage Programming Entry mode allows the PIC(R) Flash MCUs to be programmed using VDD only, without high voltage. When the LVP bit of Configuration Words is set to `1', the ICSP Low-Voltage Programming Entry mode is enabled. To disable the Low-Voltage ICSP mode, the LVP bit must be programmed to `0'. Another connector often found in use with the PICkitTM programmers is a standard 6-pin header with 0.1 inch spacing. Refer to Figure 33-2. Entry into the Low-Voltage Programming Entry mode requires the following steps: 1. 2. MCLR is brought to VIL. A 32-bit key sequence is presented on ICSPDAT, while clocking ICSPCLK. Once the key sequence is complete, MCLR must be held at VIL for as long as Program/Verify mode is to be maintained. If low-voltage programming is enabled (LVP = 1), the MCLR Reset function is automatically enabled and cannot be disabled. See Section 6.5 "MCLR" for more information. The LVP bit can only be reprogrammed to `0' by using the High-Voltage Programming mode. DS40001770A-page 508 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 FIGURE 33-2: PICkitTM PROGRAMMER STYLE CONNECTOR INTERFACE Rev. 10-000128A 7/30/2013 Pin 1 Indicator Pin Description* 1 = VPP/MCLR 1 2 3 4 5 6 2 = VDD Target 3 = VSS (ground) 4 = ICSPDAT 5 = ICSPCLK 6 = No connect * The 6-pin header (0.100" spacing) accepts 0.025" square pins For additional interface recommendations, refer to your specific device programmer manual prior to PCB design. FIGURE 33-3: It is recommended that isolation devices be used to separate the programming pins from other circuitry. The type of isolation is highly dependent on the specific application and may include devices such as resistors, diodes, or even jumpers. See Figure 33-3 for more information. TYPICAL CONNECTION FOR ICSPTM PROGRAMMING Rev. 10-000129A 7/30/2013 External Programming Signals Device to be Programmed VDD VDD VDD VPP MCLR/VPP VSS VSS Data ICSPDAT Clock ICSPCLK * * * To Normal Connections * Isolation devices (as required). 2014 Microchip Technology Inc. Preliminary DS40001770A-page 509 PIC16(L)F1615/9 34.0 INSTRUCTION SET SUMMARY Each instruction is a 14-bit word containing the operation code (opcode) and all required operands. The opcodes are broken into three broad categories. BRW, BTFSS, BTFSC, DECFSZ, INCSFZ) * One additional instruction cycle will be used when any instruction references an indirect file register and the file select register is pointing to program memory. * Byte Oriented * Bit Oriented * Literal and Control One instruction cycle consists of 4 oscillator cycles; for an oscillator frequency of 4 MHz, this gives a nominal instruction execution rate of 1 MHz. The literal and control category contains the most varied instruction word format. All instruction examples use the format `0xhh' to represent a hexadecimal number, where `h' signifies a hexadecimal digit. Table 34-3 lists the instructions recognized by the MPASMTM assembler. All instructions are executed within a single instruction cycle, with the following exceptions, which may take two or three cycles: * Subroutine takes two cycles (CALL, CALLW) * Returns from interrupts or subroutines take two cycles (RETURN, RETLW, RETFIE) * Program branching takes two cycles (GOTO, BRA, TABLE 34-1: Register file address (0x00 to 0x7F) Working register (accumulator) b Bit address within an 8-bit file register k Literal field, constant data or label x Don't care location (= 0 or 1). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. d Destination select; d = 0: store result in W, d = 1: store result in file register f. Default is d = 1. n FSR or INDF number. (0-1) Pre-post increment-decrement mode selection TABLE 34-2: ABBREVIATION DESCRIPTIONS Field Description PC Program Counter TO Time-Out bit C DC Z PD Any instruction that specifies a file register as part of the instruction performs a Read-Modify-Write (R-M-W) operation. The register is read, the data is modified, and the result is stored according to either the instruction, or the destination designator `d'. A read operation is performed on a register even if the instruction writes Description W mm Read-Modify-Write Operations OPCODE FIELD DESCRIPTIONS Field f 34.1 Carry bit Digit Carry bit Zero bit Power-Down bit DS40001770A-page 510 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 FIGURE 34-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 13 8 7 6 OPCODE d f (FILE #) 0 d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 7 6 OPCODE b (BIT #) f (FILE #) 0 b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 OPCODE 8 7 0 k (literal) k = 8-bit immediate value CALL and GOTO instructions only 13 11 10 OPCODE 0 k (literal) k = 11-bit immediate value MOVLP instruction only 13 OPCODE 7 6 0 k (literal) k = 7-bit immediate value MOVLB instruction only 13 5 4 OPCODE 0 k (literal) k = 5-bit immediate value BRA instruction only 13 9 8 0 OPCODE k (literal) k = 9-bit immediate value FSR Offset instructions 13 OPCODE 7 6 n 5 0 k (literal) n = appropriate FSR k = 6-bit immediate value FSR Increment instructions 13 OPCODE 3 2 1 0 n m (mode) n = appropriate FSR m = 2-bit mode value OPCODE only 13 0 OPCODE 2014 Microchip Technology Inc. Preliminary DS40001770A-page 511 PIC16(L)F1615/9 TABLE 34-3: ENHANCED MID-RANGE INSTRUCTION SET 14-Bit Opcode Mnemonic, Operands Description Cycles MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ADDWFC ANDWF ASRF LSLF LSRF CLRF CLRW COMF DECF INCF IORWF MOVF MOVWF RLF RRF SUBWF SUBWFB SWAPF XORWF f, d f, d f, d f, d f, d f, d f - f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d f, d Add W and f Add with Carry W and f AND W with f Arithmetic Right Shift Logical Left Shift Logical Right Shift Clear f Clear W Complement f Decrement f Increment f Inclusive OR W with f Move f Move W to f Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Subtract with Borrow W from f Swap nibbles in f Exclusive OR W with f 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 00 11 00 11 11 11 00 00 00 00 00 00 00 00 00 00 00 11 00 00 0111 1101 0101 0111 0101 0110 0001 0001 1001 0011 1010 0100 1000 0000 1101 1100 0010 1011 1110 0110 dfff dfff dfff dfff dfff dfff lfff 0000 dfff dfff dfff dfff dfff 1fff dfff dfff dfff dfff dfff dfff ffff ffff ffff ffff ffff ffff ffff 00xx ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff C, DC, Z C, DC, Z Z C, Z C, Z C, Z Z Z Z Z Z Z Z C C C, DC, Z C, DC, Z Z 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 BYTE ORIENTED SKIP OPERATIONS DECFSZ INCFSZ f, d f, d Decrement f, Skip if 0 Increment f, Skip if 0 BCF BSF f, b f, b Bit Clear f Bit Set f 1(2) 1(2) 00 00 1, 2 1, 2 1011 dfff ffff 1111 dfff ffff BIT-ORIENTED FILE REGISTER OPERATIONS 1 1 00bb bfff ffff 01bb bfff ffff 2 2 01 01 10bb bfff ffff 11bb bfff ffff 1, 2 1, 2 11 11 11 00 11 11 11 11 1110 1001 1000 0000 0001 0000 1100 1010 01 01 BIT-ORIENTED SKIP OPERATIONS BTFSC BTFSS f, b f, b Bit Test f, Skip if Clear Bit Test f, Skip if Set ADDLW ANDLW IORLW MOVLB MOVLP MOVLW SUBLW XORLW k k k k k k k k Add literal and W AND literal with W Inclusive OR literal with W Move literal to BSR Move literal to PCLATH Move literal to W Subtract W from literal Exclusive OR literal with W 1 (2) 1 (2) LITERAL OPERATIONS 1 1 1 1 1 1 1 1 kkkk kkkk kkkk 001k 1kkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk C, DC, Z Z Z C, DC, Z Z Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one additional instruction cycle. DS40001770A-page 512 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 TABLE 34-3: ENHANCED MID-RANGE INSTRUCTION SET (CONTINUED) 14-Bit Opcode Mnemonic, Operands Description Cycles MSb LSb Status Affected Notes CONTROL OPERATIONS BRA BRW CALL CALLW GOTO RETFIE RETLW RETURN k - k - k k k - Relative Branch Relative Branch with W Call Subroutine Call Subroutine with W Go to address Return from interrupt Return with literal in W Return from Subroutine CLRWDT NOP OPTION RESET SLEEP TRIS - - - - - f Clear Watchdog Timer No Operation Load OPTION_REG register with W Software device Reset Go into Standby mode Load TRIS register with W ADDFSR MOVIW n, k n mm MOVWI k[n] n mm Add Literal k to FSRn Move Indirect FSRn to W with pre/post inc/dec modifier, mm Move INDFn to W, Indexed Indirect. Move W to Indirect FSRn with pre/post inc/dec modifier, mm Move W to INDFn, Indexed Indirect. 2 2 2 2 2 2 2 2 11 00 10 00 10 00 11 00 001k 0000 0kkk 0000 1kkk 0000 0100 0000 kkkk 0000 kkkk 0000 kkkk 0000 kkkk 0000 kkkk 1011 kkkk 1010 kkkk 1001 kkkk 1000 00 00 00 00 00 00 0000 0000 0000 0000 0000 0000 0110 0000 0110 0000 0110 0110 0100 TO, PD 0000 0010 0001 0011 TO, PD 0fff INHERENT OPERATIONS 1 1 1 1 1 1 C-COMPILER OPTIMIZED k[n] 1 1 11 00 1 1 11 00 0001 0nkk kkkk 0000 0001 0nmm Z kkkk 1111 0nkk 1nmm Z 0000 0001 kkkk 1 11 1111 1nkk 2, 3 2 2, 3 2 Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one additional instruction cycle. 3: See Table in the MOVIW and MOVWI instruction descriptions. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 513 PIC16(L)F1615/9 34.2 Instruction Descriptions ADDFSR Add Literal to FSRn ANDLW AND literal with W Syntax: [ label ] ADDFSR FSRn, k Syntax: [ label ] ANDLW Operands: -32 k 31 n [ 0, 1] k Operands: 0 k 255 Operation: (W) .AND. (k) (W) Operation: FSR(n) + k FSR(n) Status Affected: Z Status Affected: None Description: Description: The signed 6-bit literal `k' is added to the contents of the FSRnH:FSRnL register pair. The contents of W register are AND'ed with the 8-bit literal `k'. The result is placed in the W register. Add literal and W ANDWF AND W with f Syntax: [ label ] ADDLW Syntax: [ label ] ANDWF Operands: 0 k 255 Operands: Operation: (W) + k (W) 0 f 127 d 0,1 Status Affected: C, DC, Z Operation: (W) .AND. (f) (destination) Description: The contents of the W register are added to the 8-bit literal `k' and the result is placed in the W register. FSRn is limited to the range 0000h FFFFh. Moving beyond these bounds will cause the FSR to wrap-around. ADDLW k f,d Status Affected: Z Description: AND the W register with register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. ASRF Arithmetic Right Shift Syntax: [ label ] ASRF ADDWF Add W and f Syntax: [ label ] ADDWF Operands: 0 f 127 d 0,1 Operands: 0 f 127 d [0,1] Operation: (W) + (f) (destination) Operation: (f<7>) dest<7> (f<7:1>) dest<6:0>, (f<0>) C, Status Affected: C, Z Description: The contents of register `f' are shifted one bit to the right through the Carry flag. The MSb remains unchanged. If `d' is `0', the result is placed in W. If `d' is `1', the result is stored back in register `f'. f,d Status Affected: C, DC, Z Description: Add the contents of the W register with register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. ADDWFC ADD W and CARRY bit to f Syntax: [ label ] ADDWFC Operands: 0 f 127 d [0,1] Operation: (W) + (f) + (C) dest register f C f {,d} Status Affected: C, DC, Z Description: Add W, the Carry flag and data memory location `f'. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed in data memory location `f'. DS40001770A-page 514 f {,d} Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 BCF Bit Clear f Syntax: [ label ] BCF BTFSC f,b Bit Test f, Skip if Clear Syntax: [ label ] BTFSC f,b 0 f 127 0b7 Operands: 0 f 127 0b7 Operands: Operation: 0 (f<b>) Operation: skip if (f<b>) = 0 Status Affected: None Status Affected: None Description: Bit `b' in register `f' is cleared. Description: If bit `b' in register `f' is `1', the next instruction is executed. If bit `b', in register `f', is `0', the next instruction is discarded, and a NOP is executed instead, making this a 2cycle instruction. BRA Relative Branch BTFSS Bit Test f, Skip if Set Syntax: [ label ] BRA label [ label ] BRA $+k Syntax: [ label ] BTFSS f,b Operands: 0 f 127 0b<7 Operands: -256 label - PC + 1 255 -256 k 255 Operation: skip if (f<b>) = 1 Operation: (PC) + 1 + k PC Status Affected: None Status Affected: None Description: Description: Add the signed 9-bit literal `k' to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 1 + k. This instruction is a 2-cycle instruction. This branch has a limited range. If bit `b' in register `f' is `0', the next instruction is executed. If bit `b' is `1', then the next instruction is discarded and a NOP is executed instead, making this a 2-cycle instruction. BRW Relative Branch with W CALL Call Subroutine Syntax: [ label ] BRW Operands: None Operation: (PC) + (W) PC Status Affected: None Description: Add the contents of W (unsigned) to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 1 + (W). This instruction is a 2-cycle instruction. BSF Bit Set f Syntax: [ label ] BSF Operands: 0 f 127 0b7 Operation: 1 (f<b>) Status Affected: None Description: Bit `b' in register `f' is set. 2014 Microchip Technology Inc. Syntax: [ label ] CALL k Operands: 0 k 2047 Operation: (PC)+ 1 TOS, k PC<10:0>, (PCLATH<6:3>) PC<14:11> Status Affected: None Description: Call Subroutine. First, return address (PC + 1) is pushed onto the stack. The 11-bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH. CALL is a 2-cycle instruction. f,b Preliminary DS40001770A-page 515 PIC16(L)F1615/9 COMF CALLW Subroutine Call With W Syntax: [ label ] CALLW Operands: None Operation: (PC) +1 TOS, (W) PC<7:0>, (PCLATH<6:0>) PC<14:8> Complement f Syntax: [ label ] COMF Operands: 0 f 127 d [0,1] Operation: (f) (destination) f,d Status Affected: Z Description: The contents of register `f' are complemented. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f'. DECF Decrement f Status Affected: None Description: Subroutine call with W. First, the return address (PC + 1) is pushed onto the return stack. Then, the contents of W is loaded into PC<7:0>, and the contents of PCLATH into PC<14:8>. CALLW is a 2-cycle instruction. CLRF Clear f Syntax: [ label ] CLRF Operands: 0 f 127 Operation: 00h (f) 1Z Status Affected: Z Description: The contents of register `f' are cleared and the Z bit is set. CLRW Clear W Syntax: [ label ] CLRW Operands: None Syntax: [ label ] DECFSZ f,d Operation: 00h (W) 1Z Operands: 0 f 127 d [0,1] Status Affected: Z Operation: Description: W register is cleared. Zero bit (Z) is set. (f) - 1 (destination); skip if result = 0 Status Affected: None Description: The contents of register `f' are decremented. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. If the result is `1', the next instruction is executed. If the result is `0', then a NOP is executed instead, making it a 2-cycle instruction. f CLRWDT Clear Watchdog Timer Syntax: [ label ] CLRWDT Operands: None Operation: 00h WDT 0 WDT prescaler, 1 TO 1 PD Status Affected: TO, PD Description: CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set. DS40001770A-page 516 Syntax: [ label ] DECF f,d Operands: 0 f 127 d [0,1] Operation: (f) - 1 (destination) Status Affected: Z Description: Decrement register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. DECFSZ Decrement f, Skip if 0 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 Unconditional Branch IORWF Syntax: [ label ] Syntax: [ label ] Operands: 0 k 2047 Operands: Operation: k PC<10:0> PCLATH<6:3> PC<14:11> 0 f 127 d [0,1] Operation: (W) .OR. (f) (destination) Status Affected: None Status Affected: Z Description: GOTO is an unconditional branch. The 11-bit immediate value is loaded into PC bits <10:0>. The upper bits of PC are loaded from PCLATH<4:3>. GOTO is a 2-cycle instruction. Description: Inclusive OR the W register with register `f'. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. INCF Increment f Syntax: [ label ] Operands: 0 f 127 d [0,1] Operation: (f) + 1 (destination) Status Affected: Z Description: The contents of register `f' are incremented. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. GOTO GOTO k LSLF INCF f,d INCFSZ Increment f, Skip if 0 Syntax: [ label ] Operands: 0 f 127 d [0,1] Operation: (f) + 1 (destination), skip if result = 0 Status Affected: None Description: The contents of register `f' are incremented. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. If the result is `1', the next instruction is executed. If the result is `0', a NOP is executed instead, making it a 2-cycle instruction. Inclusive OR W with f IORWF f,d Logical Left Shift Syntax: [ label ] LSLF Operands: 0 f 127 d [0,1] f {,d} Operation: (f<7>) C (f<6:0>) dest<7:1> 0 dest<0> Status Affected: C, Z Description: The contents of register `f' are shifted one bit to the left through the Carry flag. A `0' is shifted into the LSb. If `d' is `0', the result is placed in W. If `d' is `1', the result is stored back in register `f'. C register f 0 INCFSZ f,d IORLW Inclusive OR literal with W Syntax: [ label ] Operands: 0 k 255 Operation: (W) .OR. k (W) Status Affected: Z Description: The contents of the W register are OR'ed with the 8-bit literal `k'. The result is placed in the W register. LSRF Logical Right Shift Syntax: [ label ] LSRF Operands: 0 f 127 d [0,1] Operation: 0 dest<7> (f<7:1>) dest<6:0>, (f<0>) C, Status Affected: C, Z Description: The contents of register `f' are shifted one bit to the right through the Carry flag. A `0' is shifted into the MSb. If `d' is `0', the result is placed in W. If `d' is `1', the result is stored back in register `f'. 0 f {,d} register f C IORLW k 2014 Microchip Technology Inc. Preliminary DS40001770A-page 517 PIC16(L)F1615/9 MOVF Move f Syntax: [ label ] Operands: 0 f 127 d [0,1] MOVF f,d Operation: (f) (dest) Status Affected: Z Description: The contents of register f is moved to a destination dependent upon the status of d. If d = 0, destination is W register. If d = 1, the destination is file register f itself. d = 1 is useful to test a file register since status flag Z is affected. Words: 1 Cycles: 1 Example: MOVF MOVIW Move INDFn to W Syntax: [ label ] MOVIW ++FSRn [ label ] MOVIW --FSRn [ label ] MOVIW FSRn++ [ label ] MOVIW FSRn-[ label ] MOVIW k[FSRn] Operands: n [0,1] mm [00,01, 10, 11] -32 k 31 Operation: INDFn W Effective address is determined by * FSR + 1 (preincrement) * FSR - 1 (predecrement) * FSR + k (relative offset) After the Move, the FSR value will be either: * FSR + 1 (all increments) * FSR - 1 (all decrements) * Unchanged Status Affected: Z Mode Syntax mm Preincrement ++FSRn 00 Predecrement --FSRn 01 Postincrement FSRn++ 10 Postdecrement FSRn-- 11 Description: This instruction is used to move data between W and one of the indirect registers (INDFn). Before/after this move, the pointer (FSRn) is updated by pre/post incrementing/decrementing it. FSR, 0 After Instruction W = value in FSR register Z = 1 Note: The INDFn registers are not physical registers. Any instruction that accesses an INDFn register actually accesses the register at the address specified by the FSRn. FSRn is limited to the range 0000h FFFFh. Incrementing/decrementing it beyond these bounds will cause it to wrap-around. MOVLB DS40001770A-page 518 Move literal to BSR Syntax: [ label ] MOVLB k Operands: 0 k 31 Operation: k BSR Status Affected: None Description: The 5-bit literal `k' is loaded into the Bank Select Register (BSR). Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 MOVLP Move literal to PCLATH MOVWI Move W to INDFn Syntax: [ label ] MOVLP k Syntax: Operands: 0 k 127 [ label ] MOVWI ++FSRn [ label ] MOVWI --FSRn [ label ] MOVWI FSRn++ [ label ] MOVWI FSRn-[ label ] MOVWI k[FSRn] Operands: n [0,1] mm [00,01, 10, 11] -32 k 31 Operation: W INDFn Effective address is determined by * FSR + 1 (preincrement) * FSR - 1 (predecrement) * FSR + k (relative offset) After the Move, the FSR value will be either: * FSR + 1 (all increments) * FSR - 1 (all decrements) Unchanged Status Affected: None Mode Syntax Preincrement ++FSRn 00 Predecrement --FSRn 01 Postincrement FSRn++ 10 Postdecrement FSRn-- 11 Description: This instruction is used to move data between W and one of the indirect registers (INDFn). Before/after this move, the pointer (FSRn) is updated by pre/post incrementing/decrementing it. Operation: k PCLATH Status Affected: None Description: The 7-bit literal `k' is loaded into the PCLATH register. MOVLW Move literal to W Syntax: [ label ] MOVLW k Operands: 0 k 255 Operation: k (W) Status Affected: None Description: The 8-bit literal `k' is loaded into W register. The "don't cares" will assemble as `0's. Words: 1 Cycles: 1 Example: MOVLW 0x5A After Instruction W = MOVWF Move W to f Syntax: [ label ] Operands: 0 f 127 Operation: (W) (f) MOVWF 0x5A f Status Affected: None Description: Move data from W register to register `f'. Words: 1 Cycles: 1 Example: MOVWF OPTION_REG Before Instruction OPTION_REG = W = After Instruction OPTION_REG = W = 2014 Microchip Technology Inc. mm Note: The INDFn registers are not physical registers. Any instruction that accesses an INDFn register actually accesses the register at the address specified by the FSRn. FSRn is limited to the range 0000h FFFFh. Incrementing/decrementing it beyond these bounds will cause it to wrap-around. 0xFF 0x4F 0x4F 0x4F The increment/decrement operation on FSRn WILL NOT affect any Status bits. Preliminary DS40001770A-page 519 PIC16(L)F1615/9 NOP No Operation RETFIE Return from Interrupt Syntax: [ label ] Syntax: [ label ] Operands: None Operands: None Operation: No operation Operation: Status Affected: None TOS PC, 1 GIE Description: No operation. Status Affected: None Words: 1 Description: Cycles: 1 Return from Interrupt. Stack is POPed and Top-of-Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a 2-cycle instruction. Words: 1 Cycles: 2 Example: NOP NOP OPTION Load OPTION_REG Register with W Syntax: [ label ] OPTION Operands: None Operation: (W) OPTION_REG Status Affected: None Description: Move data from W register to OPTION_REG register. Example: RETFIE RETFIE After Interrupt PC = GIE = RESET Software Reset Syntax: [ label ] RESET Operands: None Operation: Execute a device Reset. Resets the RI flag of the PCON register. Status Affected: None Description: This instruction provides a way to execute a hardware Reset by software. RETLW Return with literal in W Syntax: [ label ] RETLW k Operands: 0 k 255 Operation: k (W); TOS PC Status Affected: None Description: The W register is loaded with the 8-bit literal `k'. The program counter is loaded from the top of the stack (the return address). This is a 2-cycle instruction. Words: 1 Cycles: 2 Example: TABLE CALL TABLE;W contains table ;offset value * ;W now has table value * * ADDWF PC ;W = offset RETLW k1 ;Begin table RETLW k2 ; * * * RETLW kn ; End of table Before Instruction W = After Instruction W = DS40001770A-page 520 TOS 1 Preliminary 0x07 value of k8 2014 Microchip Technology Inc. PIC16(L)F1615/9 RETURN Return from Subroutine RRF Syntax: [ label ] Operands: 0 f 127 d [0,1] Operation: See description below Syntax: [ label ] Operands: None RETURN Operation: TOS PC Status Affected: None Description: Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a 2-cycle instruction. Rotate Right f through Carry RRF f,d Status Affected: C Description: The contents of register `f' are rotated one bit to the right through the Carry flag. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. C Register f SLEEP Enter Sleep mode RLF Rotate Left f through Carry Syntax: [ label ] Syntax: [ label ] Operands: None Operands: 0 f 127 d [0,1] Operation: Operation: See description below 00h WDT, 0 WDT prescaler, 1 TO, 0 PD Status Affected: TO, PD Description: The power-down Status bit, PD is cleared. Time-out Status bit, TO is set. Watchdog Timer and its prescaler are cleared. The processor is put into Sleep mode with the oscillator stopped. RLF f,d Status Affected: C Description: The contents of register `f' are rotated one bit to the left through the Carry flag. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is stored back in register `f'. C Words: 1 Cycles: 1 Example: RLF Register f REG1,0 Before Instruction REG1 C After Instruction REG1 W C 2014 Microchip Technology Inc. SLEEP = = 1110 0110 0 = = = 1110 0110 1100 1100 1 Preliminary DS40001770A-page 521 PIC16(L)F1615/9 SUBLW Subtract W from literal Syntax: [ label ] Operands: 0 k 255 Syntax: [ label ] Operation: k - (W) W) Operands: Status Affected: C, DC, Z 0 f 127 d [0,1] Description: The W register is subtracted (2's complement method) from the 8-bit literal `k'. The result is placed in the W register. Operation: (f<3:0>) (destination<7:4>), (f<7:4>) (destination<3:0>) Status Affected: None Description: The upper and lower nibbles of register `f' are exchanged. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed in register `f'. TRIS Load TRIS Register with W Syntax: [ label ] TRIS f SWAPF SUBLW k C=0 Wk C=1 Wk DC = 0 W<3:0> k<3:0> DC = 1 W<3:0> k<3:0> SUBWF Subtract W from f Syntax: [ label ] Operands: 0 f 127 d [0,1] Operation: (f) - (W) destination) Status Affected: C, DC, Z Description: Subtract (2's complement method) W register from register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f. SUBWF f,d C=0 Wf C=1 Wf DC = 0 W<3:0> f<3:0> DC = 1 W<3:0> f<3:0> SUBWFB Subtract W from f with Borrow Syntax: SUBWFB Operands: 0 f 127 d [0,1] Operation: (f) - (W) - (B) dest SWAPF f,d Operands: 5f7 Operation: (W) TRIS register `f' Status Affected: None Description: Move data from W register to TRIS register. When `f' = 5, TRISA is loaded. When `f' = 6, TRISB is loaded. When `f' = 7, TRISC is loaded. f {,d} Status Affected: C, DC, Z Description: Subtract W and the BORROW flag (CARRY) from register `f' (2's complement method). If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f'. DS40001770A-page 522 Swap Nibbles in f Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 XORLW Exclusive OR literal with W Syntax: [ label ] Operands: 0 k 255 XORLW k Operation: (W) .XOR. k W) Status Affected: Z Description: The contents of the W register are XOR'ed with the 8-bit literal `k'. The result is placed in the W register. XORWF Exclusive OR W with f Syntax: [ label ] Operands: 0 f 127 d [0,1] Operation: (W) .XOR. (f) destination) Status Affected: Z Description: Exclusive OR the contents of the W register with register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. XORWF 2014 Microchip Technology Inc. f,d Preliminary DS40001770A-page 523 PIC16(L)F1615/9 35.0 ELECTRICAL SPECIFICATIONS 35.1 Absolute Maximum Ratings() Ambient temperature under bias...................................................................................................... -40C to +125C Storage temperature ........................................................................................................................ -65C to +150C Voltage on pins with respect to VSS on VDD pin PIC16F1615/9 ........................................................................................................... -0.3V to +6.5V PIC16LF1615/9 ......................................................................................................... -0.3V to +4.0V on MCLR pin ........................................................................................................................... -0.3V to +9.0V on all other pins ............................................................................................................ -0.3V to (VDD + 0.3V) Maximum current on VSS pin(1) -40C TA +85C .............................................................................................................. 170 mA -40C TA +125C .............................................................................................................. 70 mA on VDD pin(1) -40C TA +85C .............................................................................................................. 170 mA -40C TA +125C .............................................................................................................. 70 mA on any standard I/O pin ...................................................................................................................... 25 mA on any High Current I/O pin................................................................................................................ 100 mA Clamp current, IK (VPIN < 0 or VPIN > VDD) ................................................................................................... 20 mA Note 1: Maximum current rating requires even load distribution across I/O pins. Maximum current rating may be limited by the device package power dissipation characterizations, see Table 35-6: "Thermal Characteristics" to calculate device specifications. NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended periods may affect device reliability. DS40001770A-page 524 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 35.2 Standard Operating Conditions The standard operating conditions for any device are defined as: Operating Voltage: Operating Temperature: VDDMIN VDD VDDMAX TA_MIN TA TA_MAX VDD -- Operating Supply Voltage(1) PIC16LF1615/9 VDDMIN (Fosc 16 MHz) ......................................................................................................... +1.8V VDDMIN (Fosc 32 MHz) ......................................................................................................... +2.5V VDDMAX .................................................................................................................................... +3.6V PIC16F1615/9 VDDMIN (Fosc 16 MHz) ......................................................................................................... +2.3V VDDMIN (Fosc 32 MHz) ......................................................................................................... +2.5V VDDMAX .................................................................................................................................... +5.5V TA -- Operating Ambient Temperature Range Industrial Temperature TA_MIN ...................................................................................................................................... -40C TA_MAX .................................................................................................................................... +85C Extended Temperature TA_MIN ...................................................................................................................................... -40C TA_MAX .................................................................................................................................. +125C Note 1: See Parameter D001, DS Characteristics: Supply Voltage. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 525 PIC16(L)F1615/9 VOLTAGE FREQUENCY GRAPH, -40C TA +125C, PIC16F1615/9 ONLY FIGURE 35-1: Rev. 10-000130B 9/19/2013 VDD (V) 5.5 2.5 2.3 0 16 32 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table 35-7 for each Oscillator mode's supported frequencies. VOLTAGE FREQUENCY GRAPH, -40C TA +125C, PIC16LF1615/9 ONLY FIGURE 35-2: Rev. 10-000131B 9/19/2013 VDD (V) 3.6 2.5 1.8 0 16 32 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table 35-7 for each Oscillator mode's supported frequencies. DS40001770A-page 526 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 35.3 DC Characteristics TABLE 35-1: SUPPLY VOLTAGE PIC16LF1615/9 Standard Operating Conditions (unless otherwise stated) PIC16F1615/9 Param. No. D001 Sym. VDD Characteristic Min. Typ Max. Units VDDMIN 1.8 2.5 -- -- VDDMAX 3.6 3.6 V V FOSC 16 MHz FOSC 32 MHz 2.3 2.5 -- -- 5.5 5.5 V V FOSC 16 MHz FOSC 32 MHz 1.5 -- -- V Device in Sleep mode 1.7 -- -- V Device in Sleep mode -- 1.6 -- V -- 1.6 -- V -- 0.8 -- V -- 1.5 -- V -- 1.024 -- V -40C TA +85C -- 1.024 -- V -40C TA +85C -4 -- +4 % 1x VFVR, VDD 2.5V 2x VFVR, VDD 2.5V -4 -- +4 % 1x VFVR, VDD 2.5V 2x VFVR, VDD 2.5V 4x VFVR, VDD 4.75V -4 -- +4 % 1x VFVR, VDD 2.5V 2x VFVR, VDD 2.5V -4 -- +4 % 1x VFVR, VDD 2.5V 2x VFVR, VDD 2.5V 4x VFVR, VDD 4.75V 0.05 -- -- V/ms Ensures that the Power-on Reset signal is released properly. 0.05 -- -- V/ms Ensures that the Power-on Reset signal is released properly. Supply Voltage D001 D002* VDR RAM Data Retention Voltage(1) D002* D002A* VPOR Power-on Reset Release Voltage(2) D002A* D002B* VPORR* Power-on Reset Rearm Voltage(2) D002B* D003 VFVR Fixed Voltage Reference Voltage D003 D003A VADFVR FVR Gain Voltage Accuracy for ADC D003A D003B VCDAFVR FVR Gain Voltage Accuracy for Comparator D003B D004* Conditions SVDD VDD Rise Rate(2) D004* * These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data. 2: See Figure 35-3, POR and POR REARM with Slow Rising VDD. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 527 PIC16(L)F1615/9 FIGURE 35-3: POR AND POR REARM WITH SLOW RISING VDD VDD VPOR VPORR SVDD VSS NPOR(1) POR REARM VSS TPOR(3) TVLOW(2) Note 1: 2: 3: TABLE 35-2: When NPOR is low, the device is held in Reset. TPOR 1 s typical. TVLOW 2.7 s typical. SUPPLY CURRENT (IDD)(1,2) PIC16LF1615/9 Standard Operating Conditions (unless otherwise stated) PIC16F1615/9 Param. No. Device Characteristics D013 D013 D014 D014 Conditions Min. Typ Max. Units VDD Note FOSC = 1 MHz, External Clock (ECM), Medium-Power mode -- 30 90 A 1.8 -- 55 110 A 3.0 -- 65 120 A 2.3 -- 85 150 A 3.0 -- 115 200 A 5.0 -- 115 260 A 1.8 -- 210 380 A 3.0 -- 180 310 A 2.3 -- 240 410 A 3.0 -- 295 520 A 5.0 FOSC = 1 MHz, External Clock (ECM), Medium-Power mode FOSC = 4 MHz, External Clock (ECM), Medium-Power mode FOSC = 4 MHz, External Clock (ECM), Medium-Power mode * These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VSS; MCLR = VDD; WDT disabled. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. DS40001770A-page 528 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 TABLE 35-2: SUPPLY CURRENT (IDD)(1,2) (CONTINUED) PIC16LF1615/9 Standard Operating Conditions (unless otherwise stated) PIC16F1615/9 Param. No. Device Characteristics D015 D015 D016 D016 Conditions Min. Typ Max. Units -- 9.6 36 A 1.8 -- 16.2 60 A 3.0 -- 39 84 A 2.3 -- 45 90 A 3.0 -- 51 108 A 5.0 -- 215 360 A 1.8 -- 275 480 A 3.0 -- 270 450 A 2.3 -- 300 500 A 3.0 -- 350 620 A 5.0 D017* -- 410 800 A 1.8 -- 630 1200 A 3.0 D017* -- 530 950 A 2.3 -- 660 1300 A 3.0 -- 730 1400 A 5.0 -- 600 1200 A 1.8 -- 970 1850 A 3.0 -- 780 1500 A 2.3 -- 1000 1900 A 3.0 -- 1090 2100 A 5.0 D018 D018 Note VDD FOSC = 31 kHz, LFINTOSC, -40C TA +85C FOSC = 31 kHz, LFINTOSC, -40C TA +85C FOSC = 500 kHz, HFINTOSC FOSC = 500 kHz, HFINTOSC FOSC = 8 MHz, HFINTOSC FOSC = 8 MHz, HFINTOSC FOSC = 16 MHz, HFINTOSC FOSC = 16 MHz, HFINTOSC * These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VSS; MCLR = VDD; WDT disabled. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 529 PIC16(L)F1615/9 TABLE 35-2: SUPPLY CURRENT (IDD)(1,2) (CONTINUED) PIC16LF1615/9 Standard Operating Conditions (unless otherwise stated) PIC16F1615/9 Param. No. Device Characteristics D019 D019 D020A D020A D020B D020B D020C D020C Conditions Min. Typ Max. Units VDD -- 1.6 5.0 mA 3.0 -- 1.9 6.0 mA 3.6 -- 1.6 5.0 mA 3.0 -- 1.9 6.0 mA 5.0 -- 1.6 5.0 mA 3.0 -- 1.9 6.0 mA 3.6 -- 1.6 5.0 mA 3.0 -- 1.9 6.0 mA 5.0 -- 6 16 A 1.8 -- 8 22 A 3.0 -- 13 43 A 2.3 -- 15 55 A 3.0 -- 16 57 A 5.0 -- 19 40 A 1.8 -- 32 60 A 3.0 -- 31 60 A 2.3 -- 38 90 A 3.0 -- 44 100 A 5.0 Note FOSC = 32 MHz, HFINTOSC FOSC = 32 MHz, HFINTOSC FOSC = 32 MHz, External Clock (ECH), High-Power mode FOSC = 32 MHz, External Clock (ECH), High-Power mode FOSC = 32 kHz, External Clock (ECL), Low-Power mode FOSC = 32 kHz, External Clock (ECL), Low-Power mode FOSC = 500 kHz, External Clock (ECL), Low-Power mode FOSC = 500 kHz, External Clock (ECL), Low-Power mode * These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VSS; MCLR = VDD; WDT disabled. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. DS40001770A-page 530 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 TABLE 35-3: POWER-DOWN CURRENTS (IPD)(1,2) PIC16LF1615/9 Operating Conditions: (unless otherwise stated) Low-Power Sleep Mode PIC16F1615/9 Low-Power Sleep Mode, VREGPM = 1 Param. No. D022 Device Characteristics Base IPD D022 Base IPD D022A Base IPD D023 D023 D023A D023A Min. Typ Conditions Max. +85C Max. +125C Units Note VDD -- 0.020 1.0 8.0 A 1.8 -- 0.025 2.0 9.0 A 3.0 -- 0.25 3.0 10 A 2.3 -- 0.30 4.0 12 A 3.0 -- 0.40 6.0 15 A 5.0 -- 9.8 16 18 A 2.3 -- 10.3 18 20 A 3.0 -- 11.5 21 26 A 5.0 -- 0.26 2.0 9.0 A 1.8 -- 0.44 3.0 10 A 3.0 -- 0.43 6.0 15 A 2.3 -- 0.53 7.0 20 A 3.0 -- 0.64 8.0 22 A 5.0 -- 15 28 30 A 1.8 -- 18 30 33 A 3.0 -- 18 33 35 A 2.3 -- 19 35 37 A 3.0 WDT, BOR, FVR disabled, all Peripherals inactive WDT, BOR, FVR disabled, all Peripherals inactive, Low-Power Sleep mode WDT, BOR, FVR disabled, all Peripherals inactive, Normal-Power Sleep mode, VREGPM = 0 WDT Current WDT Current FVR Current FVR Current -- 20 37 39 A 5.0 D024 -- 6.0 17 20 A 3.0 BOR Current D024 -- 7.0 17 30 A 3.0 BOR Current -- 8.0 20 40 A 5.0 D24A -- 0.1 4.0 10 A 3.0 LPBOR Current D24A -- 0.35 5.0 14 A 3.0 LPBOR Current -- 0.45 8.0 17 A 5.0 D026 -- 0.11 1.5 9.0 A 1.8 -- 0.12 2.7 10 A 3.0 -- 0.30 4.0 11 A 2.3 -- 0.35 5.0 13 A 3.0 -- 0.45 8.0 16 A 5.0 -- 250 -- -- A 1.8 -- 250 -- -- A 3.0 -- 280 -- -- A 2.3 -- 280 -- -- A 3.0 -- 280 -- -- A 5.0 D026 D026A* D026A* * Legend: Note 1: 2: 3: ADC Current (Note 3), No conversion in progress ADC Current (Note 3), No conversion in progress ADC Current (Note 3), Conversion in progress ADC Current (Note 3), Conversion in progress These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. TBD = To Be Determined The peripheral current can be determined by subtracting the base IPD current from this limit. Max. values should be used when calculating total current consumption. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VSS. ADC clock source is FRC. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 531 PIC16(L)F1615/9 TABLE 35-3: POWER-DOWN CURRENTS (IPD)(1,2) (CONTINUED) PIC16LF1615/9 Operating Conditions: (unless otherwise stated) Low-Power Sleep Mode PIC16F1615/9 Low-Power Sleep Mode, VREGPM = 1 Param. No. Device Characteristics D027 D027 * Legend: Note 1: 2: 3: Min. Typ Conditions Max. +85C Max. +125C Units VDD -- 7 22 25 A 1.8 -- 8 23 27 A 3.0 -- 17 35 37 A 2.3 -- 18 37 38 A 3.0 -- 19 38 40 A 5.0 Note Comparator, CxSP = 0 Comparator, CxSP = 0 These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. TBD = To Be Determined The peripheral current can be determined by subtracting the base IPD current from this limit. Max. values should be used when calculating total current consumption. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VSS. ADC clock source is FRC. DS40001770A-page 532 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 TABLE 35-4: I/O PORTS Standard Operating Conditions (unless otherwise stated) Param. No. Sym. VIL Characteristic Min. Typ Max. Units Conditions Input Low Voltage I/O PORT: D030 with TTL buffer D030A D031 with Schmitt Trigger buffer D032 MCLR VIH -- -- 0.8 V 4.5V VDD 5.5V -- -- 0.15 VDD V 1.8V VDD 4.5V -- -- 0.2 VDD V 2.0V VDD 5.5V -- -- 0.2 VDD V Input High Voltage I/O PORT: D040 with TTL buffer D040A D041 with Schmitt Trigger buffer D042 MCLR IIL D060 MCLR(3) IPUR D080 -- V 4.5V VDD 5.5V -- -- V 1.8V VDD 4.5V 2.0V VDD 5.5V 0.8 VDD -- -- V 0.8 VDD -- -- V -- 5 125 nA VSS VPIN VDD, Pin at high-impedance, 85C -- 5 1000 nA VSS VPIN VDD, Pin at high-impedance, 125C -- 50 200 nA VSS VPIN VDD, Pin at high-impedance, 85C 25 100 200 A VDD = 3.3V, VPIN = VSS 25 140 300 A VDD = 5.0V, VPIN = VSS -- -- 0.6 V -- 0.6 -- V 0.6 -- V IOL = 10 mA, VDD = 2.3V HIDCX = 1 IOL = 37 mA, VDD = 3.0V HIDCX = 1 IOL = 51 mA, VDD = 5.0V HIDCX = 1 VDD - 0.7 -- -- V IOH = 3.5 mA, VDD = 5V IOH = 3 mA, VDD = 3.3V IOH = 1 mA, VDD = 1.8V -- VDD - 0.7 -- V -- VDD - 0.7 -- V -- -- 50 pF Weak Pull-up Current D070* VOL -- Input Leakage Current(1) I/O Ports D061 2.0 0.25 VDD + 0.8 Output Low Voltage(3) Standard I/O D080A High Drive I/O VOH D090 -- Output High Voltage(3) Standard I/O D090A D101A* CIO IOL = 8 mA, VDD = 5V IOL = 6 mA, VDD = 3.3V IOL = 1.8 mA, VDD = 1.8V High Drive I/O All I/O pins IOL = 10 mA, VDD = 2.3V HIDCX = 1 IOL = 37 mA, VDD = 3.0V HIDCX = 1 IOL = 54 mA, VDD = 5.0V HIDCX = 1 * These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Negative current is defined as current sourced by the pin. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Excluding OSC2 in CLKOUT mode. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 533 PIC16(L)F1615/9 TABLE 35-5: MEMORY PROGRAMMING SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Characteristic Min. Typ Max. Units Conditions Program Memory Programming Specifications D110 VIHH Voltage on MCLR/VPP pin 8.0 -- 9.0 V D111 IDDP Supply Current during Programming -- -- 10 mA D112 VBE VDD for Bulk Erase D113 VPEW VDD for Write or Row Erase D114 (Note 2) 2.7 -- VDDMAX V VDDMIN -- VDDMAX V IPPPGM Current on MCLR/VPP during Erase/Write -- 1.0 -- mA D115 IDDPGM Current on VDD during Erase/ Write -- 5.0 -- mA D121 EP Cell Endurance 10K -- -- E/W D122 VPRW VDD for Read/Write VDDMIN -- VDDMAX V D123 TIW Self-timed Write Cycle Time -- 2 2.5 ms D124 TRETD Characteristic Retention -- 40 -- Year Provided no other specifications are violated D125 EHEFC High-Endurance Flash Cell 100K -- -- E/W 0C TA +60C, lower byte last 128 addresses Program Flash Memory -40C TA +85C (Note 1) Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Self-write and Block Erase. 2: Required only if single-supply programming is disabled. DS40001770A-page 534 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 TABLE 35-6: THERMAL CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Param. No. TH01 TH02 Sym. Characteristic JA Thermal Resistance Junction to Ambient JC TH03 TJMAX TH04 PD TH05 Thermal Resistance Junction to Case Maximum Junction Temperature Power Dissipation PINTERNAL Internal Power Dissipation Typ. Units Conditions 62.2 C/W 20-pin DIP package 77.7 C/W 20-pin SOIC package 87.3 C/W 20-pin SSOP package 43 C/W 20-pin QFN 4X4mm package 27.5 C/W 20-pin DIP package 23.1 C/W 20-pin SOIC package 31.1 C/W 20-pin SSOP package 5.3 C/W 20-pin QFN 4X4mm package 150 C -- W PD = PINTERNAL + PI/O -- W PINTERNAL = IDD x VDD(1) TH06 PI/O I/O Power Dissipation -- W PI/O = (IOL * VOL) + (IOH * (VDD - VOH)) TH07 PDER Derated Power -- W PDER = PDMAX (TJ - TA)/JA(2) Note 1: IDD is current to run the chip alone without driving any load on the output pins. 2: TA = Ambient Temperature; TJ = Junction Temperature 2014 Microchip Technology Inc. Preliminary DS40001770A-page 535 PIC16(L)F1615/9 35.4 AC Characteristics Timing Parameter Symbology has been created with one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKOUT cs CS di SDIx do SDO dt Data in io I/O PORT mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (High-impedance) L Low FIGURE 35-4: T Time osc rd rw sc ss t0 t1 wr CLKIN RD RD or WR SCKx SS T0CKI T1CKI WR P R V Z Period Rise Valid High-impedance LOAD CONDITIONS Rev. 10-000133A 8/1/2013 Load Condition Pin CL VSS Legend: CL=50 pF for all pins DS40001770A-page 536 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 FIGURE 35-5: CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 CLKIN OS12 OS02 OS11 OS03 CLKOUT (CLKOUT mode) Note 1: See Table 35-10. TABLE 35-7: CLOCK OSCILLATOR TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param. No. OS01 Sym. FOSC Characteristic External CLKIN Frequency(1) Min. Typ Max. Units Conditions DC -- 0.5 MHz External Clock (ECL) DC -- 4 MHz External Clock (ECM) DC -- 32 MHz External Clock (ECH) OS02 TOSC External CLKIN Period(1) 31.25 -- ns External Clock (EC) OS03 TCY Instruction Cycle Time(1) 200 TCY DC ns TCY = 4/FOSC * These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min" values with an external clock applied to CLKIN pin. When an external clock input is used, the "max" cycle time limit is "DC" (no clock) for all devices. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 537 PIC16(L)F1615/9 TABLE 35-8: OSCILLATOR PARAMETERS Standard Operating Conditions (unless otherwise stated) Param. No. OS08 Sym. Characteristic Freq. Tolerance Min. Typ Max. Units -- MHz VDD = 3.0V, TA = 25C, (Note 2) (Note 3) HFOSC Internal Calibrated HFINTOSC Frequency(1) 2% -- 16.0 OS09 LFOSC Internal LFINTOSC Frequency -- -- 31 -- kHz OS10* TIOSC ST HFINTOSC Wake-up from Sleep Start-up Time -- -- 5 15 s OS10A* TLFOSC ST LFINTOSC Wake-up from Sleep Start-up Time -- -- 0.5 -- ms Conditions -40C TA +125C * These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1:To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 F and 0.01 F values in parallel are recommended. 2: See Figure 35-6: "HFINTOSC Frequency Accuracy over Device VDD and Temperature", Figure 36-27: "HFINTOSC Accuracy Over Temperature, VDD = 1.8V, PIC16LF1615/9 Only" and Figure 36-28: "HFINTOSC Accuracy Over Temperature, 2.3V VDD 5.5V". 3: See Figure 36-25: "LFINTOSC Frequency over VDD and Temperature, PIC16LF1615/9 Only", and Figure 36-26: "LFINTOSC Frequency over VDD and Temperature, PIC16F1615/9 Only". HFINTOSC FREQUENCY ACCURACY OVER VDD AND TEMPERATURE FIGURE 35-6: Rev. 10-000 135B 12/4/201 3 125 5% 85 Temperature (C) 3% 60 25 2% 0 5% -40 1.8 2.3 5.5 VDD (V) Note: See Figure 36-27: "HFINTOSC Accuracy Over Temperature, VDD = 1.8V, PIC16LF1615/9 Only", and Figure 36-28: "HFINTOSC Accuracy Over Temperature, 2.3V VDD 5.5V". DS40001770A-page 538 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 TABLE 35-9: PLL CLOCK TIMING SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Param No. Sym. F10 Min. Typ Max. Units FOSC Oscillator Frequency Range 4 -- 8 MHz F11 FSYS On-Chip VCO System Frequency 16 -- 32 MHz F12 TRC PLL Start-up Time (Lock Time) -- -- 2 ms CLK CLKOUT Stability (Jitter) -0.25% -- +0.25% % F13* Characteristic Conditions * These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 539 PIC16(L)F1615/9 FIGURE 35-7: CLKOUT AND I/O TIMING Cycle F Write Fetch Read Execute Q4 Q1 Q2 Q3 OSC OS12 OS11 OS20 CLKOUT OS21 OS19 OS18 OS16 OS13 OS17 I/O pin (Input) OS14 OS15 I/O pin (Output) New Value Old Value OS18, OS19 TABLE 35-10: CLKOUT AND I/O TIMING PARAMETERS Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Characteristic Min. Typ Max. Units Conditions TosH2ckL FOSC to CLKOUT(1) -- -- 70 ns 3.3V VDD 5.0V OS12 TosH2ckH FOSC to CLKOUT -- -- 72 ns 3.3V VDD 5.0V OS13 TckL2ioV CLKOUT to Port out valid(1) -- -- 20 ns OS14 TioV2ckH Port input valid before CLKOUT(1) TOSC + 200 ns -- -- ns OS15 TosH2ioV Fosc (Q1 cycle) to Port out valid -- 50 70* ns 3.3V VDD 5.0V OS16 TosH2ioI Fosc (Q2 cycle) to Port input invalid (I/O in setup time) 50 -- -- ns 3.3V VDD 5.0V OS17 TioV2osH Port input valid to Fosc(Q2 cycle) (I/O in setup time) 20 -- -- ns OS18* TioR Port output rise time -- -- 40 15 72 32 ns VDD = 1.8V 3.3V VDD 5.0V OS19* TioF Port output fall time -- -- 28 15 55 30 ns VDD = 1.8V 3.3V VDD 5.0V OS11 (1) OS20* Tinp INT pin input high or low time 25 -- -- ns OS21* Tioc Interrupt-on-change new input level time 25 -- -- ns * These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. Note 1: Measurements are taken in EXTRC mode where CLKOUT output is 4 x TOSC. DS40001770A-page 540 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 FIGURE 35-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING Vdd MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Start-up Time Internal Reset(1) Watchdog Timer Reset(1) 34 31 34 I/O pins Note 1:Asserted low. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 541 PIC16(L)F1615/9 TABLE 35-11: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET PARAMETERS Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Characteristic Min. Typ Max. Units Conditions 30 TMCL 2 -- -- s 31 TWDTLP Low-Power Watchdog Timer Time-out Period 10 16 27 ms 32 TOST Oscillator Start-up Timer Period(1) -- 1024 -- TOSC 33* TPWRT Power-up Timer Period 40 65 140 ms 34* TIOZ I/O high-impedance from MCLR Low or Watchdog Timer Reset -- -- 2.0 s 35 VBOR Brown-out Reset Voltage(2) 2.55 2.70 2.85 V BORV = 0 2.35 1.80 2.45 1.90 2.58 2.05 V V BORV = 1 (PIC16F1615/9) BORV = 1 (PIC16LF1615/9) 0 25 60 mV MCLR Pulse Width (low) VDD = 3.3V-5V, 1:16 Prescaler used PWRTE = 0 -40C TA +85C 36* VHYST 37* TBORDC Brown-out Reset DC Response Time 1 16 35 s VDD VBOR 38 VLPBOR Low-Power Brown-Out Reset Voltage 1.8 2.1 2.5 V LPBOR = 1 Brown-out Reset Hysteresis * These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: By design, the Oscillator Start-up Timer (OST) counts the first 1024 cycles, independent of frequency. 2: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 F and 0.01 F values in parallel are recommended. FIGURE 35-9: BROWN-OUT RESET TIMING AND CHARACTERISTICS V DD VBOR and VHYST VBOR (Device in Brown-out Reset) (Device not in Brown-out Reset) 37 Reset 33 (due to BOR) DS40001770A-page 542 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 FIGURE 35-10: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 T1CKI 45 46 49 47 TMR0 or TMR1 TABLE 35-12: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param. No. 40* Sym. TT0H Characteristic T0CKI High Pulse Width Min. No Prescaler TT0L T0CKI Low Pulse Width No Prescaler Max. Units 0.5 TCY + 20 -- -- ns 10 -- -- ns With Prescaler 41* Typ 0.5 TCY + 20 -- -- ns 10 -- -- ns Greater of: 20 or TCY + 40 N -- -- ns With Prescaler 42* TT0P T0CKI Period 45* TT1H T1CKI High Synchronous, No Prescaler Time Synchronous, with Prescaler 0.5 TCY + 20 -- -- ns 15 -- -- ns Asynchronous 30 -- -- ns Synchronous, No Prescaler 0.5 TCY + 20 -- -- ns Synchronous, with Prescaler 15 -- -- ns Asynchronous 30 -- -- ns Greater of: 30 or TCY + 40 N -- -- ns TT1L 46* T1CKI Low Time 47* TT1P T1CKI Input Synchronous Period 49* TCKEZTMR1 Delay from External Clock Edge to Timer Increment Asynchronous * 60 -- -- ns 2 TOSC -- 7 TOSC -- Conditions N = prescale value N = prescale value Timers in Sync mode These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 543 PIC16(L)F1615/9 TABLE 35-13: ANALOG-TO-DIGITAL CONVERTER (ADC) CHARACTERISTICS(1,2,3) Operating Conditions (unless otherwise stated) VDD = 3.0V, TA = 25C Param. Sym. No. Characteristic Min. Typ Max. AD01 NR Resolution -- -- 10 AD02 EIL Integral Error -- 1 1.7 AD03 EDL Differential Error -- 1 1 AD04 EOFF Offset Error AD05 EGN Gain Error AD06 VREF Reference Voltage AD07 VAIN Full-Scale Range AD08 ZAIN Recommended Impedance of Analog Voltage Source Units Conditions bit LSb VREF = 3.0V LSb No missing codes VREF = 3.0V -- 1 2.5 LSb VREF = 3.0V -- 1 2.0 LSb VREF = 3.0V 1.8 -- VDD V VSS -- VREF V -- -- 10 k VREF = (VRPOS - VRNEG) (Note 4) Can go higher if external 0.01F capacitor is present on input pin. * These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1:Total Absolute Error includes integral, differential, offset and gain errors. 2: The ADC conversion result never decreases with an increase in the input voltage and has no missing codes. 3: See Section 36.0 "DC and AC Characteristics Graphs and Charts" for operating characterization. 4: ADC VREF is selected by ADPREF<0> bit. DS40001770A-page 544 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 FIGURE 35-11: ADC CONVERSION TIMING (ADC CLOCK FOSC-BASED) BSF ADCON0, GO 1 Tcy AD133 AD131 Q4 AD130 ADC_clk 9 ADC Data 8 6 7 3 2 1 0 NEW_DATA OLD_DATA ADRES 1 Tcy ADIF GO DONE Sampling Stopped AD132 Sample FIGURE 35-12: ADC CONVERSION TIMING (ADC CLOCK FROM FRC) BSF ADCON0, GO AD133 1 Tcy AD131 Q4 AD130 ADC_clk 9 ADC Data 8 7 6 OLD_DATA ADRES 2 1 0 NEW_DATA 1 Tcy ADIF GO Sample 3 DONE AD132 Sampling Stopped Note 1: If the ADC clock source is selected as FRC, a time of TCY is added before the ADC clock starts. This allows the SLEEP instruction to be executed. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 545 PIC16(L)F1615/9 TABLE 35-14: ADC CONVERSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param. Sym. No. AD130* TAD AD131 TCNV Characteristic Min. Typ Max. Units ADC Clock Period (TADC) 1.0 -- 6.0 ADC Internal FRC Oscillator Period (TFRC) 1.0 2.0 Conversion Time (not including Acquisition Time)(1) -- 11 Conditions s FOSC-based 6.0 s ADCS<2:0> = x11 (ADC FRC mode) -- TAD Set GO/DONE bit to conversion complete s AD132* TACQ Acquisition Time -- 5.0 -- AD133* THCD Holding Capacitor Disconnect Time -- -- 1/2 TAD 1/2 TAD + 1TCY -- -- FOSC-based ADCS<2:0> = x11 (ADC FRC mode) * These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The ADRES register may be read on the following TCY cycle. TABLE 35-15: COMPARATOR SPECIFICATIONS(1) Operating Conditions (unless otherwise stated) VDD = 3.0V, TA = 25C Param. No. Sym. Characteristics Min. Typ. Max. Units -- 7.5 60 mV Comments CM01 Vioff Input Offset Voltage CM02 Vicm Input Common Mode Voltage 0 -- VDD V CM03 CMRR Common Mode Rejection Ratio -- 50 -- dB CM04A Response Time Rising Edge -- 400 800 ns CxSP = 1 CM04B Response Time Falling Edge -- 200 400 ns CxSP = 1 CM04C Tresp(2) CM04D Response Time Rising Edge -- 1200 -- ns CxSP = 0 Response Time Falling Edge -- 550 -- ns CxSP = 0 Comparator Mode Change to Output Valid -- -- 10 s -- 25 -- mV CM05* Tmc2ov CM06 CHYSTER Comparator Hysteresis * Note 1: 2: CxSP = 1, Vicm = VDD/2 CxHYS = 1, CxSP = 1 These parameters are characterized but not tested. See Section 36.0 "DC and AC Characteristics Graphs and Charts" for operating characterization. Response time measured with one comparator input at VDD/2, while the other input transitions from Vss to VDD. DS40001770A-page 546 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 TABLE 35-16: DIGITAL-TO-ANALOG CONVERTER (DAC) SPECIFICATIONS(1) Operating Conditions (unless otherwise stated) VDD = 3.0V, TA = 25C Param. No. Sym. Characteristics Min. Typ. Max. Units DAC01* CLSB Step Size -- VDD/256 -- V DAC02* CACC Absolute Accuracy -- -- 1.5 LSb DAC03* CR Unit Resistor Value (R) -- -- -- CST Time(2) -- -- 10 s DAC04* * Note 1: 2: Settling Comments These parameters are characterized but not tested. See Section 36.0 "DC and AC Characteristics Graphs and Charts" for operating characterization. Settling time measured while DACR<4:0> transitions from `0000' to `1111'. TABLE 35-17: ZERO CROSS PIN SPECIFICATIONS Operating Conditions (unless otherwise stated) VDD = 3.0V, TA = 25C Param. No. Sym. Characteristics Min. Typ. Max. Units ZC01 ZCPINV Voltage on Zero Cross Pin -- 0.75 -- V ZC02 ZCSRC Source current -- 300 -- A ZC03 ZCSNK Sink current -- 300 -- A ZC04 ZCISW Response Time Rising Edge -- 1 -- s Response Time Falling Edge -- 1 -- s ZC05 ZCOUT Response Time Rising Edge -- 1 -- s Response Time Falling Edge -- 1 -- s * Comments These parameters are characterized but not tested. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 547 PIC16(L)F1615/9 36.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are ensured to operate properly only within the specified range. Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. "Typical" represents the mean of the distribution at 25C. "MAXIMUM", "Max.", "MINIMUM" or "Min." represents (mean + 3) or (mean - 3) respectively, where is a standard deviation, over each temperature range. DS40001770A-page 548 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 FIGURE 36-1: VOH vs. IOH OVER TEMPERATURE, VDD = 5.5V, PIC16F1615/9 ONLY 6 Max: 125C + 3i Typical: 25C Min: -40C - 3i 5 VOH (V) 4 Min. (-40C) 3 Typical (25C) 2 Max. (125C) 1 0 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 IOH (mA) FIGURE 36-2: VOL vs. IOL OVER TEMPERATURE, VDD = 5.5V, PIC16F1615/9 ONLY 5 Max: 125C + 3i Typical: 25C Min: -40C - 3i 4 Max. (125C) VOL (V) Typical (25C) 3 Min. (-40C) 2 1 0 0 10 20 2014 Microchip Technology Inc. 30 40 50 IOL (mA) Preliminary 60 70 80 90 100 DS40001770A-page 549 PIC16(L)F1615/9 FIGURE 36-3: VOH vs. IOH OVER TEMPERATURE, VDD = 3.0V 3.5 Max: 125C + 3i Typical: 25C Min: -40C - 3i 3.0 VOH (V) 2.5 2.0 1.5 1.0 Min. (-40C) Typical (25C) Max. (125C) 0.5 0.0 -15 -13 -11 -9 -7 -5 -3 -1 IOH (mA) FIGURE 36-4: VOL vs. IOL OVER TEMPERATURE, VDD = 3.0V 3.0 Max: 125C + 3i Typical: 25C Min: -40C - 3i 2.5 VOL (V) 2.0 Max. (125C) Typical (25C) Min. (-40C) 1.5 1.0 0.5 0.0 0 5 10 15 20 25 30 35 40 IOL (mA) DS40001770A-page 550 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 FIGURE 36-5: VOH vs. IOH OVER TEMPERATURE, VDD = 1.8V, PIC16LF1615/9 ONLY 2.0 1.8 Max: 125C + 3i Typical: 25C Min: -40C - 3i 1.6 VOH (V) 1.4 1.2 Min. (-40C) Max. (125C) Typical (25C) 1.0 0.8 0.6 0.4 0.2 0.0 -4.5 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 IOH (mA) FIGURE 36-6: VOL vs. IOL OVER TEMPERATURE, VDD = 1.8V, PIC16LF1615/9 ONLY 1.8 Max: 125C + 3i Typical: 25C Min: -40C - 3i 1.6 1.4 VOL (V) 1.2 1.0 0.8 Max. (125C) Min. (-40C) Typical (25C) 0.6 0.4 0.2 0.0 0 1 2 3 4 5 6 7 8 9 10 IOL (mA) 2014 Microchip Technology Inc. Preliminary DS40001770A-page 551 PIC16(L)F1615/9 FIGURE 36-7: POR RELEASE VOLTAGE 1.70 1.68 Max. 1.66 Voltage (V) 1.64 Typical 1.62 Min. 1.60 1.58 1.56 Max: Typical + 3i Typical: 25C Min: Typical - 3i 1.54 1.52 1.50 -60 -40 -20 0 20 40 60 80 100 120 140 120 140 Temperature (C) FIGURE 36-8: POR REARM VOLTAGE, PIC16F1615/9 ONLY 1.54 Max: Typical + 3i Typical: 25C Min: Typical - 3i 1.52 1.50 Max. Voltage (V) 1.48 1.46 1.44 Typical 1.42 1.40 Min. 1.38 1.36 1.34 -60 -40 -20 0 20 40 60 80 100 Temperature (C) DS40001770A-page 552 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 FIGURE 36-9: BROWN-OUT RESET VOLTAGE, BORV = 1, PIC16LF1615/9 ONLY 2.00 Max. Voltage (V) 1.95 Typical 1.90 1.85 Min. Max: Typical + 3i Min: Typical - 3i 1.80 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (C) FIGURE 36-10: BROWN-OUT RESET HYSTERESIS, BORV = 1, PIC16LF1615/9 ONLY 60 50 Max. Max: Typical + 3i Typical: 25C Min: Typical - 3i Voltage (mV) 40 Typical 30 20 Min. 10 0 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (C) 2014 Microchip Technology Inc. Preliminary DS40001770A-page 553 PIC16(L)F1615/9 FIGURE 36-11: BROWN-OUT RESET VOLTAGE, BORV = 1, PIC16F1615/9 ONLY 2.60 Max. 2.55 Voltage (V) 2.50 Typical 2.45 Min. 2.40 Max: Typical + 3i Min: Typical - 3i 2.35 2.30 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (C) FIGURE 36-12: BROWN-OUT RESET HYSTERESIS, BORV = 1, PIC16F1615/9 ONLY 70 Max. 60 Max: Typical + 3i Typical: 25C Min: Typical - 3i Voltage (mV) 50 40 Typical 30 20 Min. 10 0 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (C) DS40001770A-page 554 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 FIGURE 36-13: BROWN-OUT RESET VOLTAGE, BORV = 0 2.80 2.75 Voltage (V) Max. 2.70 Typical 2.65 Min. Max: Typical + 3i Min: Typical - 3i 2.60 2.55 -60 -40 -20 0 20 40 60 80 100 120 140 120 140 Temperature (C) FIGURE 36-14: BROWN-OUT RESET HYSTERESIS, BORV = 0 90 80 Min. 70 Voltage (mV) 60 Typical 50 40 Max: Typical + 3i Typical: 25C Min: Typical - 3i 30 20 Max. 10 0 -60 -40 -20 0 20 40 60 80 100 Temperature (C) 2014 Microchip Technology Inc. Preliminary DS40001770A-page 555 PIC16(L)F1615/9 FIGURE 36-15: LOW-POWER BROWN-OUT RESET VOLTAGE, LPBOR = 0 2.50 Max. Max: Typical + 3i Min: Typical - 3i 2.40 Voltage (V) 2.30 Typical 2.20 2.10 2.00 Min. 1.90 1.80 -60 -40 -20 0 20 40 60 80 100 120 140 120 140 Temperature (C) FIGURE 36-16: LOW-POWER BROWN-OUT RESET HYSTERESIS, LPBOR = 0 45 Max: Typical + 3i Typical: 25C Min: Typical - 3i 40 35 Max. Typical Voltage (mV) 30 25 Min. 20 15 10 5 0 -60 -40 -20 0 20 40 60 80 100 Temperature (C) DS40001770A-page 556 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 FIGURE 36-17: WDT TIME-OUT PERIOD 24 22 Max. Time (ms) 20 18 Typical 16 Min. 14 Max: Typical + 3i (-40C to +125C) Typical: statistical mean @ 25C Min: Typical - 3i (-40C to +125C) 12 10 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 36-18: PWRT PERIOD 100 Max: Typical + 3i (-40C to +125C) Typical: statistical mean @ 25C Min: Typical - 3i (-40C to +125C) 90 Max. Time (ms) 80 70 Typical 60 Min. 50 40 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) 2014 Microchip Technology Inc. Preliminary DS40001770A-page 557 PIC16(L)F1615/9 FIGURE 36-19: FVR STABILIZATION PERIOD 60 Max: Typical + 3i Typical: statistical mean @ 25C 50 Max. Time (us) 40 Typical 30 20 Note: The FVR Stabilization Period applies when: 1) coming out of RESET or exiting Sleep mode for PIC12/16LFxxxx devices. 2) when exiting sleep mode with VREGPM = 1 for PIC12/16Fxxxx devices In all other cases, the FVR is stable when released from RESET. 10 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) DS40001770A-page 558 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 FIGURE 36-20: COMPARATOR HYSTERESIS, NORMAL-POWER MODE (CxSP = 1, CxHYS = 1) 40 35 Max. Hysteresis (mV) 30 25 Typical 20 15 Min. 10 Max: Typical + 3i Typical: 25C Min: Typical - 3i 5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 36-21: COMPARATOR HYSTERESIS, LOW-POWER MODE (CxSP = 0, CxHYS = 1) 8 7 Max. Hysteresis (mV) 6 5 Typical 4 3 2 Max: Typical + 3i Typical: 25C Min: Typical - 3i 1 Min. 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) 2014 Microchip Technology Inc. Preliminary DS40001770A-page 559 PIC16(L)F1615/9 FIGURE 36-22: COMPARATOR RESPONSE TIME, NORMAL-POWER MODE (CxSP = 1) 350 300 Time (ns) 250 Max. 200 Typical 150 100 Max: Typical + 3i Typical: 25C 50 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 36-23: COMPARATOR RESPONSE TIME OVER TEMPERATURE, NORMAL-POWER MODE (CxSP = 1) 400 Max: 125C + 3i Typical: 25C Min: -45C - 3i 350 Time (ns) 300 250 Max. (125C) 200 150 Typical (25C) 100 Min. (-40C) 50 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) DS40001770A-page 560 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 FIGURE 36-24: COMPARATOR INPUT OFFSET AT 25C, NORMAL-POWER MODE (CxSP = 1), PIC16F1615/9 ONLY 50 40 30 Max. Offset Voltage (mV) 20 10 Typical 0 Min. -10 -20 Max: Typical + 3i Typical: 25C Min: Typical - 3i -30 -40 -50 0.0 1.0 2.0 3.0 4.0 5.0 Common Mode Voltage (V) 2014 Microchip Technology Inc. Preliminary DS40001770A-page 561 PIC16(L)F1615/9 FIGURE 36-25: LFINTOSC FREQUENCY OVER VDD AND TEMPERATURE, PIC16LF1615/9 ONLY 36 34 Max. Frequency (kHz) 32 30 Typical 28 Min. 26 24 Max: Typical + 3i (-40C to +125C) Typical: statistical mean @ 25C Min: Typical - 3i (-40C to +125C) 22 20 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 36-26: LFINTOSC FREQUENCY OVER VDD AND TEMPERATURE, PIC16F1615/9 ONLY 36 34 Max. Frequency (kHz) 32 30 Typical 28 26 Min. 24 Max: Typical + 3i (-40C to +125C) Typical: statistical mean @ 25C Min: Typical - 3i (-40C to +125C) 22 20 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) DS40001770A-page 562 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 FIGURE 36-27: HFINTOSC ACCURACY OVER TEMPERATURE, VDD = 1.8V, PIC16LF1615/9 ONLY 8% 6% Max: Typical + 3i Typical: statistical mean Min: Typical - 3i Accuracy (%) 4% Max. 2% 0% Typical -2% -4% Min. -6% -8% -10% -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (C) FIGURE 36-28: HFINTOSC ACCURACY OVER TEMPERATURE, 2.3V VDD 5.5V 8% 6% Max: Typical + 3i Typical: statistical mean Min: Typical - 3i Accuracy (%) 4% Max. 2% Typical 0% -2% Min. -4% -6% -8% -10% -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (C) 2014 Microchip Technology Inc. Preliminary DS40001770A-page 563 PIC16(L)F1615/9 FIGURE 36-29: SLEEP MODE, WAKE PERIOD WITH HFINTOSC SOURCE, PIC16LF1615/9 ONLY 5.0 4.5 Max. 4.0 Time (us) 3.5 Typical 3.0 2.5 2.0 1.5 Max: 85C + 3i Typical: 25C 1.0 0.5 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) DS40001770A-page 564 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 FIGURE 36-30: LOW-POWER SLEEP MODE, WAKE PERIOD WITH HFINTOSC SOURCE, VREGPM = 1, PIC16F1615/9 ONLY 35 Max. 30 Typical Time (us) 25 20 15 10 Max: 85C + 3i Typical: 25C 5 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 36-31: SLEEP MODE, WAKE PERIOD WITH HFINTOSC SOURCE, VREGPM = 0, PIC16F1615/9 ONLY 12 Max. 10 Time (us) 8 Typical 6 4 Max: 85C + 3i Typical: 25C 2 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) 2014 Microchip Technology Inc. Preliminary DS40001770A-page 565 PIC16(L)F1615/9 37.0 DEVELOPMENT SUPPORT 37.1 The PIC(R) microcontrollers (MCU) and dsPIC(R) digital signal controllers (DSC) are supported with a full range of software and hardware development tools: * Integrated Development Environment - MPLAB(R) X IDE Software * Compilers/Assemblers/Linkers - MPLAB XC Compiler - MPASMTM Assembler - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB Assembler/Linker/Librarian for Various Device Families * Simulators - MPLAB X SIM Software Simulator * Emulators - MPLAB REAL ICETM In-Circuit Emulator * In-Circuit Debuggers/Programmers - MPLAB ICD 3 - PICkitTM 3 * Device Programmers - MPLAB PM3 Device Programmer * Low-Cost Demonstration/Development Boards, Evaluation Kits and Starter Kits * Third-party development tools MPLAB X Integrated Development Environment Software The MPLAB X IDE is a single, unified graphical user interface for Microchip and third-party software, and hardware development tool that runs on Windows(R), Linux and Mac OS(R) X. Based on the NetBeans IDE, MPLAB X IDE is an entirely new IDE with a host of free software components and plug-ins for highperformance application development and debugging. Moving between tools and upgrading from software simulators to hardware debugging and programming tools is simple with the seamless user interface. With complete project management, visual call graphs, a configurable watch window and a feature-rich editor that includes code completion and context menus, MPLAB X IDE is flexible and friendly enough for new users. With the ability to support multiple tools on multiple projects with simultaneous debugging, MPLAB X IDE is also suitable for the needs of experienced users. Feature-Rich Editor: * Color syntax highlighting * Smart code completion makes suggestions and provides hints as you type * Automatic code formatting based on user-defined rules * Live parsing User-Friendly, Customizable Interface: * Fully customizable interface: toolbars, toolbar buttons, windows, window placement, etc. * Call graph window Project-Based Workspaces: * * * * Multiple projects Multiple tools Multiple configurations Simultaneous debugging sessions File History and Bug Tracking: * Local file history feature * Built-in support for Bugzilla issue tracker DS40001770A-page 566 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 37.2 MPLAB XC Compilers 37.4 The MPLAB XC Compilers are complete ANSI C compilers for all of Microchip's 8, 16, and 32-bit MCU and DSC devices. These compilers provide powerful integration capabilities, superior code optimization and ease of use. MPLAB XC Compilers run on Windows, Linux or MAC OS X. For easy source level debugging, the compilers provide debug information that is optimized to the MPLAB X IDE. The free MPLAB XC Compiler editions support all devices and commands, with no time or memory restrictions, and offer sufficient code optimization for most applications. MPLAB XC Compilers include an assembler, linker and utilities. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. MPLAB XC Compiler uses the assembler to produce its object file. Notable features of the assembler include: * * * * * * Support for the entire device instruction set Support for fixed-point and floating-point data Command-line interface Rich directive set Flexible macro language MPLAB X IDE compatibility 37.3 MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for PIC10/12/16/18 MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel(R) standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code, and COFF files for debugging. The MPASM Assembler features include: MPLINK Object Linker/ MPLIB Object Librarian The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: * Efficient linking of single libraries instead of many smaller files * Enhanced code maintainability by grouping related modules together * Flexible creation of libraries with easy module listing, replacement, deletion and extraction 37.5 MPLAB Assembler, Linker and Librarian for Various Device Families MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24, PIC32 and dsPIC DSC devices. MPLAB XC Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: * * * * * * Support for the entire device instruction set Support for fixed-point and floating-point data Command-line interface Rich directive set Flexible macro language MPLAB X IDE compatibility * Integration into MPLAB X IDE projects * User-defined macros to streamline assembly code * Conditional assembly for multipurpose source files * Directives that allow complete control over the assembly process 2014 Microchip Technology Inc. Preliminary DS40001770A-page 567 PIC16(L)F1615/9 37.6 MPLAB X SIM Software Simulator The MPLAB X SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB X SIM Software Simulator fully supports symbolic debugging using the MPLAB XC Compilers, and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. 37.7 MPLAB REAL ICE In-Circuit Emulator System The MPLAB REAL ICE In-Circuit Emulator System is Microchip's next generation high-speed emulator for Microchip Flash DSC and MCU devices. It debugs and programs all 8, 16 and 32-bit MCU, and DSC devices with the easy-to-use, powerful graphical user interface of the MPLAB X IDE. The emulator is connected to the design engineer's PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with in-circuit debugger systems (RJ-11) or with the new high-speed, noise tolerant, LowVoltage Differential Signal (LVDS) interconnection (CAT5). The emulator is field upgradeable through future firmware downloads in MPLAB X IDE. MPLAB REAL ICE offers significant advantages over competitive emulators including full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, logic probes, a ruggedized probe interface and long (up to three meters) interconnection cables. DS40001770A-page 568 37.8 MPLAB ICD 3 In-Circuit Debugger System The MPLAB ICD 3 In-Circuit Debugger System is Microchip's most cost-effective, high-speed hardware debugger/programmer for Microchip Flash DSC and MCU devices. It debugs and programs PIC Flash microcontrollers and dsPIC DSCs with the powerful, yet easy-to-use graphical user interface of the MPLAB IDE. The MPLAB ICD 3 In-Circuit Debugger probe is connected to the design engineer's PC using a highspeed USB 2.0 interface and is connected to the target with a connector compatible with the MPLAB ICD 2 or MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3 supports all MPLAB ICD 2 headers. 37.9 PICkit 3 In-Circuit Debugger/ Programmer The MPLAB PICkit 3 allows debugging and programming of PIC and dsPIC Flash microcontrollers at a most affordable price point using the powerful graphical user interface of the MPLAB IDE. The MPLAB PICkit 3 is connected to the design engineer's PC using a fullspeed USB interface and can be connected to the target via a Microchip debug (RJ-11) connector (compatible with MPLAB ICD 3 and MPLAB REAL ICE). The connector uses two device I/O pins and the Reset line to implement in-circuit debugging and In-Circuit Serial ProgrammingTM (ICSPTM). 37.10 MPLAB PM3 Device Programmer The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages, and a modular, detachable socket assembly to support various package types. The ICSP cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices, and incorporates an MMC card for file storage and data applications. Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 37.11 Demonstration/Development Boards, Evaluation Kits, and Starter Kits 37.12 Third-Party Development Tools A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. Microchip also offers a great collection of tools from third-party vendors. These tools are carefully selected to offer good value and unique functionality. * Device Programmers and Gang Programmers from companies, such as SoftLog and CCS * Software Tools from companies, such as Gimpel and Trace Systems * Protocol Analyzers from companies, such as Saleae and Total Phase * Demonstration Boards from companies, such as MikroElektronika, Digilent(R) and Olimex * Embedded Ethernet Solutions from companies, such as EZ Web Lynx, WIZnet and IPLogika(R) The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEMTM and dsPICDEMTM demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ(R) security ICs, CAN, IrDA(R), PowerSmart battery management, SEEVAL(R) evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 569 PIC16(L)F1615/9 38.0 PACKAGING INFORMATION 38.1 Package Marking Information 14-Lead PDIP Example PIC16F1615 XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN \P 1410017 14-Lead SOIC (.150") Example XXXXXXXXXXX XXXXXXXXXXX YYWWNNN PIC16F1615 \SL Example XXXXXXXX YYWW NNN e3 * Note: * e3 1410017 14-Lead TSSOP Legend: XX...X Y YY WW NNN e3 F1615ST 1410 017 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC(R) designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. Standard PICmicro(R) device marking consists of Microchip part number, year code, week code and traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. DS40001770A-page 570 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 38.1 Package Marking Information (Continued) 20-Lead PDIP (300 mil) Example PIC16F1619 \P e3 XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 1420123 20-Lead SOIC (7.50 mm) Example PIC16F1619 /SO e3 1420123 20-Lead SSOP (5.30 mm) Example PIC16F1619 /SS e3 1420123 2014 Microchip Technology Inc. Preliminary DS40001770A-page 571 PIC16(L)F1615/9 38.1 Package Marking Information (Continued) 16-Lead QFN (4x4x0.5 mm) PIN 1 Example PIN 1 Example 20-Lead QFN/UQFN (4x4x0.5 mm) PIN 1 DS40001770A-page 572 PIN 1 Preliminary PIC16 F1619 /ML e3 420123 PIC16 F1619 /ML e3 420123 2014 Microchip Technology Inc. PIC16(L)F1615/9 38.2 Package Details The following sections give the technical details of the packages. 6 ( ) #( $ ( 7% , #*##( ((588,,,) )8 7 ! 7 ' ( (%( N NOTE 1 E1 1 3 2 D E A2 A L A1 c b1 b e eB 9 (# )# < ) (# :$)+ '! # :.;0 : : := > !( ( ( ! ? ? 3 / 3 4#( ( ! 3 ? ? 0 / /3 %%! 7 $% ( 7## $% @ %( 4. %%! 7@ %( 0 3 B =" <( /3 3 3 ( ( ! < 3 <% 3 / B 3 + 3 D + B 4 ? ? 7## 9 <%@ %( < , <%@ %( =" , - / ! " #$ %&'($ )" *+$()$#(+ (%, ( ( ( % - ' (. ( #( / )# #%0% ( $%) %'# ( $# # %'# ( $# ## (& %1 # % )# %( 023 4.54# )# ( & ("$# ,, ( $(( # 2014 Microchip Technology Inc. Preliminary , .34 DS40001770A-page 573 PIC16(L)F1615/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001770A-page 574 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2014 Microchip Technology Inc. Preliminary DS40001770A-page 575 PIC16(L)F1615/9 6 ( ) #( $ ( 7% , #*##( ((588,,,) )8 7 DS40001770A-page 576 Preliminary ! 7 ' ( (%( 2014 Microchip Technology Inc. PIC16(L)F1615/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2014 Microchip Technology Inc. Preliminary DS40001770A-page 577 PIC16(L)F1615/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001770A-page 578 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2014 Microchip Technology Inc. Preliminary DS40001770A-page 579 PIC16(L)F1615/9 ! 6 ( ) #( $ ( 7% , #*##( ((588,,,) )8 7 ! 7 ' ( (%( N E1 NOTE 1 1 2 3 D E A2 A L c A1 b1 eB e b 9 (# )# < ) (# :$)+ '! # :.;0 : : := > !( ( ( ! ? ? 3 / 3 4#( ( ! 3 ? ? 0 / / /3 %%! 7 $% ( 7## $% @ %( 4. %%! 7@ %( 0 3 B =" <( B / D ( ( ! < 3 <% 3 / B 3 + 3 D + B 4 ? ? 7## 9 <%@ %( < , <%@ %( =" , - / ! " #$ %&'($ )" *+$()$#(+ (%, ( ( ( % - ' (. ( #( / )# #%0% ( $%) %'# ( $# # %'# ( $# ## (& %1 # % )# %( 023 4.5 4# )# ( & ("$# ,, ( $(( # DS40001770A-page 580 Preliminary , .4 2014 Microchip Technology Inc. PIC16(L)F1615/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2014 Microchip Technology Inc. Preliminary DS40001770A-page 581 PIC16(L)F1615/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001770A-page 582 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2014 Microchip Technology Inc. Preliminary DS40001770A-page 583 PIC16(L)F1615/9 ! "#$% " & "" '( ""& 6 ( ) #( $ ( 7% , #*##( ((588,,,) )8 7 ! 7 ' ( (%( D N E E1 NOTE 1 1 2 e b c A2 A A1 L1 9 (# )# < ) (# :$)+ '! # L <<00 : : := > !( =" ; ( ? ? D3 3 B3 (% '' 3 ? ? =" @ %( 0 B B %%! 7@ %( 0 3 3/ 3D =" <( D 3 33 3 3 %%! 7 7## 6 (<( < 6 ( ( < <% 6 7## ( <%@ %( D34. 306 ? _ _ 3 B_ + ? /B ! " #$ %&'($ )" *+$()$#(+ (%, ( ( ( % )# #%0% ( $%) %'# ( $# # %'# ( $# ## (& %)) # % / )# %( 023 4.5 4# )# ( & ("$# ,, ( $(( # 065 ' )# *$#$, ( $(( *' ' )( $ ## DS40001770A-page 584 Preliminary , .4 2014 Microchip Technology Inc. PIC16(L)F1615/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2014 Microchip Technology Inc. Preliminary DS40001770A-page 585 PIC16(L)F1615/9 ) * + , %- . //(0 *+ 6 ( ) #( $ ( 7% , #*##( ((588,,,) )8 7 ! 7 ' ( (%( D2 D EXPOSED PAD e E2 E 2 2 1 1 b TOP VIEW K N N NOTE 1 L BOTTOM VIEW A3 A A1 9 (# )# < ) (# :$)+ '! # <<00 : : := > D !( =" ; ( B (% '' 3 . ( ( 7## / =" @ %( 0 0& #%!%@ %( 0 =" <( 0& #%!%<( D34. 06 4. 3 D3 B 4. 3 D3 . ( (@ %( + 3 / B /3 . ( (<( < / 3 . ( (( 0& #%!% ? ! " #$ %&'($ )" *+$()$#(+ (%, ( ( ( % ! 7 ##,# $(% / )# %( 023 4.5 4# )# ( & ("$# ,, ( $(( # 065 ' )# *$#$, ( $(( *' ' )( $ ## DS40001770A-page 586 Preliminary ? , .4 2014 Microchip Technology Inc. PIC16(L)F1615/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2014 Microchip Technology Inc. Preliminary DS40001770A-page 587 PIC16(L)F1615/9 ! * + , %- . //(0 *+ 6 ( ) #( $ ( 7% , #*##( ((588,,,) )8 7 ! 7 ' ( (%( D D2 EXPOSED PAD e E2 2 E b 2 1 1 K N N NOTE 1 TOP VIEW L BOTTOM VIEW A A1 A3 9 (# )# < ) (# :$)+ '! # <<00 : : := > !( =" ; ( B (% '' 3 . ( ( 7## / =" @ %( 0 0& #%!%@ %( 0 =" <( 0& #%!%<( 34. 06 4. D B 4. D B . ( (@ %( + B 3 / . ( (<( < / 3 . ( (( 0& #%!% ? ? ! " #$ %&'($ )" *+$()$#(+ (%, ( ( ( % ! 7 ##,# $(% / )# %( 023 4.5 4# )# ( & ("$# ,, ( $(( # 065 ' )# *$#$, ( $(( *' ' )( $ ## DS40001770A-page 588 Preliminary , .D4 2014 Microchip Technology Inc. PIC16(L)F1615/9 6 ( ) #( $ ( 7% , #*##( ((588,,,) )8 7 2014 Microchip Technology Inc. Preliminary ! 7 ' ( (%( DS40001770A-page 589 PIC16(L)F1615/9 20-Lead Ultra Thin Plastic Quad Flat, No Lead Package (GZ) - 4x4x0.5 mm Body [UQFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A B N NOTE 1 1 2 E (DATUM B) (DATUM A) 2X 0.20 C 2X TOP VIEW 0.20 C 0.10 C C SEATING PLANE A1 A 20X (A3) 0.08 C SIDE VIEW 0.10 C A B D2 L 0.10 C A B E2 2 K 1 NOTE 1 N 20X b 0.10 e C A B BOTTOM VIEW Microchip Technology Drawing C04-255A Sheet 1 of 2 DS40001770A-page 590 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 20-Lead Ultra Thin Plastic Quad Flat, No Lead Package (GZ) - 4x4x0.5 mm Body [UQFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units Dimension Limits Number of Terminals N e Pitch A Overall Height Standoff A1 A3 Terminal Thickness Overall Width E E2 Exposed Pad Width D Overall Length D2 Exposed Pad Length b Terminal Width Terminal Length L K Terminal-to-Exposed-Pad MIN 0.45 0.00 2.60 2.60 0.20 0.30 0.20 MILLIMETERS NOM 20 0.50 BSC 0.50 0.02 0.127 REF 4.00 BSC 2.70 4.00 BSC 2.70 0.25 0.40 - MAX 0.55 0.05 2.80 2.80 0.30 0.50 - Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated 3. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-255A Sheet 2 of 2 2014 Microchip Technology Inc. Preliminary DS40001770A-page 591 PIC16(L)F1615/9 20-Lead Ultra Thin Plastic Quad Flat, No Lead Package (GZ) - 4x4x0.5 mm Body [UQFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging C1 X2 20 1 2 C2 Y2 G1 Y1 X1 E SILK SCREEN RECOMMENDED LAND PATTERN Units Dimension Limits E Contact Pitch Optional Center Pad Width X2 Optional Center Pad Length Y2 Contact Pad Spacing C1 Contact Pad Spacing C2 Contact Pad Width (X20) X1 Contact Pad Length (X20) Y1 Contact Pad to Center Pad (X20) G1 MIN MILLIMETERS NOM 0.50 BSC MAX 2.80 2.80 4.00 4.00 0.30 0.80 0.20 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-2255A DS40001770A-page 592 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 APPENDIX A: DATA SHEET REVISION HISTORY Revision A (10/2014) Original release. 2014 Microchip Technology Inc. Preliminary DS40001770A-page 593 PIC16(L)F1615/9 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: Users of Microchip products can receive assistance through several channels: * Product Support - Data sheets and errata, application notes and sample programs, design resources, user's guides and hardware support documents, latest software releases and archived software * General Technical Support - Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing * Business of Microchip - Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives * * * * Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Customers should contact their distributor, representative or Field Application Engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://microchip.com/support CUSTOMER CHANGE NOTIFICATION SERVICE Microchip's customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under "Support", click on "Customer Change Notification" and follow the registration instructions. DS40001770A-page 594 Preliminary 2014 Microchip Technology Inc. PIC16(L)F1615/9 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. [X](1) PART NO. Device - X Tape and Reel Temperature Option Range /XX XXX Package Pattern Examples: a) b) Device: PIC16LF1615, PIC16F1615, PIC16LF1619, PIC16F1619 c) Tape and Reel Option: Blank T = Standard packaging (tube or tray) = Tape and Reel(1) Temperature Range: I E = -40C to +85C = -40C to +125C Package:(2) MF ML P SL SN ST GZ = = = = = = = PIC16LF1615T - I/SN Tape and Reel, Industrial temperature, SOIC package PIC16F1619 - I/P Industrial temperature PDIP package PIC16F1619 - E/ML 298 Extended temperature, QFN package QTP pattern #298 (Industrial) (Extended) DFN (8-Lead) QFN (16-Lead and 20-Lead) Plastic DIP SOIC (14-Lead) SOIC (8-Lead) TSSOP UQFN (20-Lead) Note 1: 2: Pattern: QTP, SQTP, Code or Special Requirements (blank otherwise) 2014 Microchip Technology Inc. Preliminary Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. For other small form-factor package availability and marking information, please visit www.microchip.com/packaging or contact your local sales office. DS40001770A-page 595 Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. The Embedded Control Solutions Company and mTouch are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet, KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. (c) 2014, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-63276-682-3 QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 == DS40001770A-page 596 Preliminary Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 2014 Microchip Technology Inc. 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