tm
74F10 Triple 3-Input NAND Gate
May 2007
©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74F10 Rev. 1.3
74F10
Triple 3-Input NAND Gate
General Description
This device contains three independent gates, each of
which performs the logic NAND function.
Ordering Information
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering number.
Connection Diagram Logic Symbol
IEEE/IEC
Unit Loading/Fan Out
Order
Number
Package
Number Package Description
74F10SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74F10SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Pin Names Description
U.L.
HIGH/LOW
Input I
IH
/I
IL
,
Output I
OH
/I
OL
A
n
, B
n
, C
n
Inputs 1.0 / 1.0 20µA / –0.6mA
O
n
Outputs 50 / 33.3 –1mA / 20mA
74F10 Triple 3-Input NAND Gate
©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74F10 Rev. 1.3 2
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Note:
1. Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol Parameter Rating
T
STG
Storage Temperature –65°C to +150°C
T
A
Ambient Temperature Under Bias –55°C to +125°C
T
J
Junction Temperature Under Bias –55°C to +150°C
V
CC
V
CC
Pin Potential to Ground Pin –0.5V to +7.0V
V
IN
Input Voltage
(1)
–0.5V to +7.0V
I
IN
Input Current
(1)
–30mA to +5.0mA
V
O
Voltage Applied to Output in HIGH State (with V
CC
= 0V)
Standard Output
3-STATE Output
–0.5V to V
CC
–0.5V to 5.5V
Current Applied to Output in LOW State (Max.) twice the rated I
OL
(mA)
Symbol Parameter Rating
T
A
Free Air Ambient Temperature 0°C to +70°C
V
CC
Supply Voltage +4.5V to +5.5V
74F10 Triple 3-Input NAND Gate
©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74F10 Rev. 1.3 3
DC Electrical Characteristics
AC Electrical Characteristics
Symbol Parameter V
CC
Conditions Min. Typ. Max. Units
V
IH
Input HIGH Voltage Recognized as a HIGH
Signal
2.0 V
V
IL
Input LOW Voltage Recognized as a LOW
Signal
0.8 V
V
CD
Input Clamp Diode Voltage Min. I
IN
=
–18mA –1.2 V
V
OH
Output HIGH Voltage 10% V
CC
Min. I
OH
=
–1mA 2.5 V
5% V
CC
I
OH
=
–1mA 2.7
V
OL
Output LOW Voltage 10% V
CC
Min. I
OL
=
20mA 0.5 V
I
IH
Input HIGH Current Max. V
IN
=
2.7V 5.0 µA
I
BVI
Input HIGH Current Breakdown
Test
Max. V
IN
=
7.0V 7.0 µA
I
CEX
Output HIGH Leakage Current Max. V
OUT
=
V
CC
50 µA
V
ID
Input Leakage Test 0.0 I
ID
=
1.9µA, All other pins
grounded
4.75 V
I
OD
Output Leakage Circuit Current 0.0 V
IOD
=
150mV, All other
pins grounded
3.75 µA
I
IL
Input LOW Current Max. V
IN
=
0.5V –0.6 mA
I
OS
Output Short-Circuit Current Max. V
OUT
=
0V –60 –150 mA
I
CCH
Power Supply Current Max. V
O
=
HIGH 1.4 2.1 mA
I
CCL
Power Supply Current Max. V
O
=
LOW 5.1 7.7 mA
Symbol Parameter
T
A
=
+25°C,
V
CC
=
+5.0V,
C
L
=
50pF
T
A
=
–55°C to +125°C,
V
CC
=
+5.0V,
C
L
=
50 pF
T
A
=
0°C to +70°C,
V
CC
=
+5.0V,
C
L
=
50pF
UnitsMin. Typ. Max. Min. Max. Min. Max.
t
PLH
Propagation Delay,
A
n
, B
n
, C
n
to O
n
2.4 3.7 5.0 2.0 7.0 2.4 6.0 ns
t
PHL
1.5 3.2 4.3 1.5 6.5 1.5 5.3
74F10 Triple 3-Input NAND Gate
©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74F10 Rev. 1.3 4
Physical Dimensions
Dimensions are in millimeters unless otherwise noted.
Figure 1. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M14A
74F10 Triple 3-Input NAND Gate
©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74F10 Rev. 1.3 5
Physical Dimensions
(Continued)
Dimensions are in millimeters unless otherwise noted.
Figure 2. 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
74F10 Triple 3-Input NAND Gate
©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74F10 Rev. 1.3 6
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PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information Formative or In Design This datasheet contains the design specifications for product
development. Specifications may change in any manner without notice.
Preliminary This datasheet contains preliminary data; supplementary data will be
published at a later date. Fairchild Semiconductor reserves the right to
make changes at any time without notice to improve design.
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First Production
This datasheet contains final specifications. Fairchild Semiconductor
reserves the right to make changes at any time without notice to improve
design.
Obsolete Not In Production This datasheet contains specifications on a product that has been
discontinued by Fairchild Semiconductor. The datasheet is printed for
reference information only.
Rev. I26
