1. General description
The 74HC4046A; 74HCT4046A is a high-speed Si-gate CMOS device. It is specified in
compliance with JEDEC standard no 7A.
2. Features and benefits
Low power consum pt ion
VCO-Inhibit control for ON/OFF keying and for low standby power consumption
Center frequency up to 17 MHz (typical) at VCC =4.5V
Choice of three ph a se com parators:
PC1: EXCLUSIVE-OR
PC2: Edge-triggered J-K flip-flop
PC3: Edge-triggered RS flip-flop
Excellent Voltage Controlled Oscillator (VCO) linearity
Low frequency drift with supply voltage and temperature variations
Operating power supply voltage range:
VCO section 3.0 V to 6.0 V
Digital section 2.0 V to 6.0 V
Zero voltage offset due to operational amplifier buffering
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115 -A ex ce ed s 20 0 V
3. Applications
FM modulation and demodulation
Frequency synthesis and multiplication
Frequency discrimination
Tone decoding
Data synchroni zation and conditioning
Voltage -to-frequency conversion
Motor-speed control
74HC4046A; 74HCT4046A
Phase-locked loop with VCO
Rev. 3 — 8 June 2016 Product data sheet
© Nexperia B.V. 2017. All rights reserved
74HC_HCT4046A All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 8 June 2016 2 of 50
Nexperia 74HC4046A; 74HCT4046A
Phase-locked loop with VCO
4. Ordering information
5. Block diagram
Table 1. Ordering information
Type number Package
Name Description Version
74HC4046AD SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
74HCT4046AD
74HC4046ADB SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1
74HCT4046ADB
74HC4046APW TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
Fig 1. Block diagram
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© Nexperia B.V. 2017. All rights reserved
74HC_HCT4046A All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 8 June 2016 3 of 50
Nexperia 74HC4046A; 74HCT4046A
Phase-locked loop with VCO
6. Functional diagram
Fig 2. Logic symbol Fig 3. IEC logic symbol
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© Nexperia B.V. 2017. All rights reserved
74HC_HCT4046A All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 8 June 2016 4 of 50
Nexperia 74HC4046A; 74HCT4046A
Phase-locked loop with VCO
7. Pinning information
7.1 Pinning
7.2 Pin description
Fig 5. Pin configuration
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Table 2. Pin de scription
Symbol Pin Description
PCP_OUT 1 phase comparator pulse output
PC1_OUT 2 phase comparator 1 output
COMP_IN 3 comparator input
VCO_OUT 4 VCO output
INH 5 inhibit input
C1A 6 capacitor C1 connection A
C1B 7 capacitor C1 connection B
GND 8 ground (0 V)
VCO_IN 9 VCO input
DEM_OUT 10 demodulator output
R1 11 resistor R1 connection
R2 12 resistor R2 connection
PC2_OUT 13 phase comparator 2 output
SIG_IN 14 signal input
PC3_OUT 15 phase comparator 3 output
VCC 16 supply voltage
© Nexperia B.V. 2017. All rights reserved
74HC_HCT4046A All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 8 June 2016 5 of 50
Nexperia 74HC4046A; 74HCT4046A
Phase-locked loop with VCO
8. Functional description
The 74HC4046A; 74HCT4046A is a phase-locked-loop circuit that comprises a linear
voltage-controlled oscillator (VCO) and three different phase comparators (PC1, PC2 and
PC3). It has a common signal input amplifier and a common comparator input (see
Figure 1). The signal input can be directly coupled to a large voltage signal, or indirectly
coupled (with a series capacitor) to a small voltage signal. A self-bias input circuit keeps
small voltage signals within the linear region of the input amplifiers. With a passive
low-pass filter, the 74HC4046A; 74HCT4046A forms a second-order loop PLL. The
excellent VCO linearity is achieved by the use of linear op amp techniques.
8.1 VCO
The VCO requires one external capacitor C1 (between pins C1A and C1B) and one
external resist or R1 (between pins R1 and GND). Alternatively, it requires two external
resistors R1 and R2 (between pins R1 and GND, and R2 and GND). Resistor R1 and
capacitor C1 dete rmine the frequency r ange of the VCO. Resistor R2 en ables the VCO to
have a frequency offset if necessary (see Figure 4).
The high input imped ance of the VCO simplifies the design of the low-pass filters by giving
the designer a wide ch oice of resist or /ca pacitor ranges. In order not to load the low-pass
filter, a demodulator output of the VCO input voltage is provided at pin DEM_OUT. In
contrast to conventional techniques, where the DEM_OUT voltage is one threshold
voltage lower than the VCO in put volt age, the DEM_OUT volt age e quals the VCO inpu t. If
DEM_OUT is used, a series resistor (Rs) should be connected from pin DEM_OUT to
GND; if unused, DEM_OUT should be left open. The VCO output (pin VCO_OUT) can be
connected dir ec tly to the co mparat or input (pin COMP_IN), or connected via a frequency
divider. When the VCO input DC level is held constant, the VCO output signal has a duty
cycle of 50 % (maximum expected deviation 1 %). A LOW-level at the inhibit input
(pin INH) enables the VCO and demodulator, while a HIGH-level turns both off to
minimize standby power consumption.
The only difference between the 74HC4046A and 74HCT4046A is the input level
specification of the INH input. This input disables the VCO section. The sections of the
comparator are identical, so that there is no difference in the SIG_IN or COMP_IN inputs
between the 74HC4046A and 74HCT4046A.
8.2 Phase comparators
The input signal can be coupled to the self-biasing amplifier at pin SIG_IN, when the
signal swing is between the standard HC family input logic levels. Capacitive coupling is
required for signals with smaller swings.
© Nexperia B.V. 2017. All rights reserved
74HC_HCT4046A All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 8 June 2016 6 of 50
Nexperia 74HC4046A; 74HCT4046A
Phase-locked loop with VCO
8.2.1 Phase Comparator 1 (PC1)
This circuit is an EXCLUSIVE-OR network. The signal and comparator input frequencies
(fi) must have a 50 % duty cycle to obtain the maximum locking range. Th e transfer
characteristic of PC1, assuming ripple (fr=2f
i) is suppressed, is:
where:
VDEM_OUT is the demodulator output at pin DEM_OUT
VDEM_OUT =V
PC1_OUT (via low-pass filter)
The phase comparator gain is:
PC1 is fed to the VCO input via the lo w- pass filter and se en at the de mo d ula to r ou tp ut at
pin DEM_OUT (VDEM_OUT). The average output voltage from PC1 is the result of the
phase differences of signals (SIG_IN) and the comparator input (COMP_IN). These phase
dif ferences are shown in Figure 6. T h e ave rage of VDEM_OUT is equal to 0.5VCC when
there is no signal or noise at SIG_IN. Using this input, the VCO oscillates at the center
frequency (f0). Typical waveforms for the PC1 loop locked at f0 are shown in Figure 7.
The frequency capture range (2f c) is defined as the frequency rang e of input signals on
which the PLL locks when it was initially out-of-lock. The frequency lock range (2fL) is the
frequency range of th e input sign als on which th e loop stays locked when it was initially in
lock. The capture range is smaller or equal to the lock range.
With PC1, the captur e ra ng e depen d s on th e low -pass filter char ac te rist ics an d ca n be
made as large as the loc k ran ge. T his co nf ig uration remains locked even with very noisy
input signals. Typical behavior of this type of phase comparator is that it can lock to input
frequencies close to the harmonics of the VCO center frequency.
VDEM_OUT VCC
----------SIG_IN COMP_IN
–=
KpVCC
----------Vr=
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74HC_HCT4046A All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 8 June 2016 7 of 50
Nexperia 74HC4046A; 74HCT4046A
Phase-locked loop with VCO
Fig 6. Phase comparator 1; average output voltage as a function of input phase
difference
Fig 7. Typical waveforms for PLL using phase comparator 1; loop-locked at f0
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VDEM_OUT VPC1_OUT VCC
----------SIG_IN COMP_IN
–==
DEM_OUT SIG_IN COMP_IN
–=
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© Nexperia B.V. 2017. All rights reserved
74HC_HCT4046A All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 8 June 2016 8 of 50
Nexperia 74HC4046A; 74HCT4046A
Phase-locked loop with VCO
8.2.2 Phase Comparator 2 (PC2)
PC2 is a positive edge-triggered phase and frequency detector. When the PLL uses this
comparator, positive signal transitions control the loop and the duty cycles of SIG_ IN an d
COMP_IN are not important. PC2 comprises two D-type flip-flops, control gating and a
3-state output stage. The circuit fu nctions as an up-down counter (se e Figure 4) wher e
SIG_IN causes an up-count and COMP_IN a down count. The transfer function of PC2,
assuming ripple (f r=f
i) is suppressed, is:
where:
VDEM_OUT is the demodulator output at pin DEM_OUT
VDEM_OUT =V
PC2_OUT (via low-pass filter)
The phase comparator gain is:
VDEM_OUT is the resultant of the initial phase differences of SIG_IN and COMP_IN as
shown in Figure 8. Typical waveforms for the PC2 loop locked at fo are shown in Figure 9.
When the SIG_IN and COMP_IN frequencies are equ al but the phase of SIG_IN leads
that of COMP_IN, the p-type output driver at PC2_OUT is held ‘ON’. The time that it is
held ÓN’ corresponds to the phase diff erence (DEM_OUT). When the phase of SIG_IN
lags that of COMP_IN, the n-type driver is held ‘ON’.
When the SIG_IN frequency is higher than the COMP_IN freq ue n cy, the p-type ou tp ut
driver is held ‘ON’ for most of the input sign al cycle time . Fo r th e re ma in de r of the cyc le
time, both n- and p-type drivers are ‘OFF’ (3-state). If the SIG_IN frequency is lower than
the COMP_IN frequency, then it is the n-type driver that is held ‘ON’ for most of the cycle.
The voltage at capacitor (C2) of the low-pass filter, connected to PC2_OUT, varies until
the phase and frequency of the signal and co mparator inputs are equal . At this stable
point, the voltage on C2 remains consta nt as the PC2 output is in 3 -state and the VCO_IN
input is in a high-impedance state. In this condition, the signal at the phase comparator
pulse output (PCP_OUT) is a HIGH level and can be used for indicating a locked
condition.
Thus for PC2 no phase difference exists between SIG_IN and COMP_IN over the full
frequency range of the VCO. The power dissipation due to the low-pass filter is reduced
because both n- and p-type output dr ivers are ‘OFF’ for most of the signal input cycle. The
PLL lock range for this type of phase comparator is equal to the capture range and is
independent of the low-pass filter. With no signal present at SIG_IN the VCO adjust, via
PC2, to its lowest frequency.
VDEM_OUT VCC
4
----------SIG_IN COMP_IN
–=
KpVCC
4
----------Vr=
© Nexperia B.V. 2017. All rights reserved
74HC_HCT4046A All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 8 June 2016 9 of 50
Nexperia 74HC4046A; 74HCT4046A
Phase-locked loop with VCO
Fig 8. Phase comparator 2; average output voltage as a function of input phase
difference
Fig 9. Typical waveforms for PLL using phase comparator 2; loop-locked at f0
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VDEM_OUT VPC2_OUT VCC
----------SIG_IN COMP_IN
–==
DEM_OUT SIG_IN COMP_IN
–=
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© Nexperia B.V. 2017. All rights reserved
74HC_HCT4046A All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 8 June 2016 10 of 50
Nexperia 74HC4046A; 74HCT4046A
Phase-locked loop with VCO
8.2.3 Phase Comparator 3 (PC3)
PC3 is a positive edge-triggered sequential phase detector using an RS-type flip-flop.
When the PLL is using this comp arator, positive signal transitions control the loop and the
duty factors of SIG_IN and COMP_IN are not important. The transfer characteristic of
PC3, assuming ripple (fr=f
i) is suppressed, is:
where:
VDEM_OUT is the demodulator output at pin DEM_OUT
VDEM_OUT =V
PC3_OUT (via low-pass filter)
The phase comparator gain is:
PC3 is fed to the VCO via the low-pass filter and se en at the demodulator output at
pin DEM_OUT. The average output from PC3 is the resultant of the phase differences of
SIG_IN and COMP_IN, see Figure 10. Typical waveforms for the PC3 loop locked at
foare shown in Figure 11.
The phase-to-output response characteristic of PC3 (Figure 10) differs from PC2 in that
the phase angle between SIG_IN and COMP_IN varies between 0 and 360 It is 180 at
the center frequency. Also PC3 gives a greater voltage swing than PC2 for input phase
differences. As a result, the ripple content of the VCO input signal is higher. The PLL lock
range for this type of phase comparator and the capture range are dependent on the
low-pass filter. With no signal present at SIG_IN, the VCO adjusts to its lowest frequency
via PC3.
VDEM_OUT VCC
2
----------SIG_IN COMP_IN
–=
KpVCC
2
----------Vr=
© Nexperia B.V. 2017. All rights reserved
74HC_HCT4046A All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 8 June 2016 11 of 50
Nexperia 74HC4046A; 74HCT4046A
Phase-locked loop with VCO
Fig 10. Phase comparator 3; average output voltage as a function of input phase
difference
Fig 11. Typical waveforms for PLL using phase comparator 3; loop-locked at f0
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VDEM_OUT VPC3_OUT VCC
----------SIG_IN COMP_IN
–==
DEM_OUT SIG_IN COMP_IN
–=
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6,*B,1
&203B,1
9&2B287
3&B287
9&2B,1
© Nexperia B.V. 2017. All rights reserved
74HC_HCT4046A All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 8 June 2016 12 of 50
Nexperia 74HC4046A; 74HCT4046A
Phase-locked loop with VCO
9. Limiting values
[1] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
For SSOP16 and TSSOP16 packages: Ptot derates linearly with 5.5 mW/K above 60 C.
10. Recommended operating conditions
Table 3. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +7 V
IIK input clamping current VI < 0.5 V or VI > VCC + 0.5 V - 20 mA
IOK output clamping current VO < 0.5 V or VO > VCC + 0.5 V - 20 mA
IOoutput current 0.5 V < VO < VCC + 0.5 V - 25 mA
ICC supply current - +50 mA
IGND ground current 50 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb =40 C to +125 C
SO16 and (T)SSOP16 [1] -500mW
Table 4. Recommended operating con ditions
Symbol Parameter Conditions 74HC4046A 74HCT4046A Unit
Min Typ Max Min Typ Max
VCC supply voltage 3.0 5.0 6.0 4.5 5.0 5.5 V
when VCO is not used 2.0 5.0 6.0 4.5 5.0 5.5 V
VIinput voltage 0 - VCC 0-V
CC V
VOoutput voltage 0 - VCC 0-V
CC V
t/V input transition rise and
fall rate pin INH
VCC = 2.0 V - - 625 - - - ns/V
VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V
VCC = 6.0 V - - 83 - - - ns/V
Tamb ambient temperature 40 +25 +125 40 +25 +125 C
© Nexperia B.V. 2017. All rights reserved
74HC_HCT4046A All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 8 June 2016 13 of 50
Nexperia 74HC4046A; 74HCT4046A
Phase-locked loop with VCO
11. Static characteristics
11.1 Static characteristics 74HC4046A
Table 5. Static characteristics 74HC4046A
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
Phase comparator section; Tamb = 25 C
VIH HIGH-level
input voltage pins SIG_IN, COMP_IN; DC coupled
VCC = 2.0 V 1.5 1.2 - V
VCC = 4.5 V 3.15 2.4 - V
VCC = 6.0 V 4.2 3.2 - V
VIL LOW-level
input voltage pins SIG_IN, COMP_IN; DC coupled
VCC =2.0V - 0.8 0.5 V
VCC =4.5V - 2.1 1.35 V
VCC =6.0V - 2.8 1.8 V
VOH HIGH-level
output voltage pins PCP_OUT, PCn_OUT; VI=V
IH or VIL
IO=20 A; VCC =2.0V 1.9 2.0 - V
IO=20 A; VCC =4.5V 4.4 4.5 - V
IO=20 A; VCC =6.0V 5.9 6.0 - V
IO=4mA; V
CC = 4.5 V 3.98 4.32 - V
IO=5.2 mA; VCC = 6.0 V 5.48 5.81 - V
VOL LOW-level
output voltage pins PCP_OUT, PCn_OUT; VI=V
IH or VIL
IO=20A; VCC = 2.0 V - 0 0.1 V
IO=20A; VCC = 4.5 V - 0 0.1 V
IO=20A; VCC = 6.0 V - 0 0.1 V
IO=4mA; V
CC = 4.5 V - 0.15 0.26 V
IO=5.2mA; V
CC = 6.0 V - 0.16 0.26 V
IIinput leakage
current pins SIG_IN, COMP_IN; VI=V
CC or GND
VCC =2.0V - - 3A
VCC =3.0V - - 7A
VCC =4.5V - - 18 A
VCC =6.0V - - 30 A
IOZ OFF-state
output current pin PC2_OUT; VI=V
IH or VIL; VO=V
CC or GND
VCC =6.0V - - 0.5 A
RIinput
resistance pins SIG_IN, COMP_IN; VI at self-bias operating point;
VI= 0.5 V; see Figure 12, 13 and 14
VCC =3.0V - 800 - k
VCC =4.5V - 250 - k
VCC =6.0V - 150 - k
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Product data sheet Rev. 3 — 8 June 2016 14 of 50
Nexperia 74HC4046A; 74HCT4046A
Phase-locked loop with VCO
VCO section; Tamb = 25 C
VIH HIGH-level
input voltage pin INH
VCC = 3.0 V 2.1 1.7 - V
VCC = 4.5 V 3.15 2.4 - V
VCC = 6.0 V 4.2 3.2 - V
VIL LOW-level
input voltage pin INH
VCC =3.0V - 1.3 0.9 V
VCC =4.5V - 2.1 1.35 V
VCC =6.0V - 2.8 1.8 V
VOH HIGH-level
output voltage pin VCO_OUT; VI=V
IH or VIL
IO=20 A; VCC =3.0V 2.9 3.0 - V
IO=20 A; VCC =4.5V 4.4 4.5 - V
IO=20 A; VCC =6.0V 5.9 6.0 - V
IO=4mA; V
CC = 4.5 V 3.98 4.32 - V
IO=5.2 mA; VCC = 6.0 V 5.48 5.81 - V
VOL LOW-level
output voltage pin VCO_OUT; VI=V
IH or VIL
IO=20A; VCC = 3.0 V - 0 0.1 V
IO=20A; VCC = 4.5 V - 0 0.1 V
IO=20A; VCC = 6.0 V - 0 0.1 V
IO=4mA; V
CC = 4.5 V - 0.15 0.26 V
IO=5.2mA; V
CC = 6.0 V - 0.16 0.26 V
pins C1A, C1B; VI=V
IH or VIL
IO=4mA; V
CC = 4.5 V - - 0.40 V
IO=5.2mA; V
CC = 6.0 V - - 0.40 V
IIinput leakage
current pins INH, VCO_IN; VI=V
CC or GND
VCC =6.0V - - 0.1 A
R1 resistor 1 VCC = 3.0 V to 6.0 V [1] 3-300k
R2 resistor 2 VCC = 3.0 V to 6.0 V [1] 3-300k
C1 capacitor 1 VCC = 3.0 V to 6.0 V 40 - no
limit pF
VVCO_IN voltage on pin
VCO_IN over the range specified for R1; for linearity
see Figure 22 and 23
VCC = 3.0 V 1.1 - 1.9 V
VCC = 4.5 V 1.1 - 3.4 V
VCC = 6.0 V 1.1 - 4.9 V
Table 5. Static characteristics 74HC4046A
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
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74HC_HCT4046A All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 8 June 2016 15 of 50
Nexperia 74HC4046A; 74HCT4046A
Phase-locked loop with VCO
Demodulator section; Tamb = 25 C
Rsseries
resistance at Rs > 300 k, the leakage current can influence VDEM_OUT
VCC = 3.0 V to 6.0 V 50 - 300 k
Voffset offset voltage VCO_IN to VDEM_OUT; VI=V
VCO_IN =0.5V
CC; values taken
over Rs range; see Figure 15
VCC =3.0V - 30 - mV
VCC =4.5V - 20 - mV
VCC =6.0V - 10 - mV
Rdyn dynamic
resistance DEM_OUT; VDEM_OUT = 0.5VCC
VCC = 3.0 V to 6.0 V - 25 -
General; Tamb = 25 C
ICC supply current VCO disabled; pins COMP_IN, IN H and SIG_IN at VCC;
pin VCO_IN at GND; II at pins COMP_IN and SIGN_IN to be
excluded
VCC =6.0V - - 8.0 A
CIinput
capacitance pin INH - 3.5 - pF
Phase comparator section; Tamb =40 Cto+85C
VIH HIGH-level
input voltage pins SIG_IN, COMP_IN; DC coupled
VCC = 2.0 V 1.5 - - V
VCC =4.5V 3.15 - - V
VCC = 6.0 V 4.2 - - V
VIL LOW-level
input voltage pins SIG_IN, COMP_IN; DC coupled
VCC =2.0V - - 0.5 V
VCC =4.5V - - 1.35 V
VCC =6.0V - - 1.8 V
VOH HIGH-level
output voltage pins PCP_OUT, PCn_OUT; VI=V
IH or VIL
IO=20 A; VCC =2.0V 1.9 - - V
IO=20 A; VCC =4.5V 4.4 - - V
IO=20 A; VCC =6.0V 5.9 - - V
IO=4mA; V
CC =4.5V 3.84 - - V
IO=5.2 mA; VCC =6.0V 5.34 - - V
VOL LOW-level
output voltage pins PCP_OUT, PCn_OUT; VI=V
IH or VIL
IO=20A; VCC = 2.0 V - - 0.1 V
IO=20A; VCC = 4.5 V - - 0.1 V
IO=20A; VCC = 6.0 V - - 0.1 V
IO=4mA; V
CC = 4.5 V - - 0.33 V
IO=5.2mA; V
CC = 6.0 V - - 0.33 V
Table 5. Static characteristics 74HC4046A
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
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74HC_HCT4046A All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 8 June 2016 16 of 50
Nexperia 74HC4046A; 74HCT4046A
Phase-locked loop with VCO
IIinput leakage
current pins SIG_IN, COMP_IN; VI=V
CC or GND
VCC =2.0V - - 4A
VCC =3.0V - - 9A
VCC =4.5V - - 23 A
VCC =6.0V - - 38 A
IOZ OFF-state
output current pin PC2_OUT; VI=V
IH or VIL; VO=V
CC or GND
VCC =6.0V - - 5A
VCO section; Tamb =40 Cto+85C
VIH HIGH-level
input voltage pin INH
VCC = 3.0 V 2.1 - - V
VCC =4.5V 3.15 - - V
VCC = 6.0 V 4.2 - - V
VIL LOW-level
input voltage pin INH
VCC =3.0V - - 0.9 V
VCC =4.5V - - 1.35 V
VCC =6.0V - - 1.8 V
VOH HIGH-level
output voltage pin VCO_OUT; VI=V
IH or VIL
IO=20 A; VCC =3.0V 2.9 - - V
IO=20 A; VCC =4.5V 4.4 - - V
IO=20 A; VCC =6.0V 5.9 - - V
IO=4mA; V
CC =4.5V 3.84 - - V
IO=5.2 mA; VCC =6.0V 5.34 - - V
VOL LOW-level
output voltage pin VCO_OUT; VI=V
IH or VIL
IO=20A; VCC = 3.0 V - - 0.1 V
IO=20A; VCC = 4.5 V - - 0.1 V
IO=20A; VCC = 6.0 V - - 0.1 V
IO=4mA; V
CC = 4.5 V - - 0.33 V
IO=5.2mA; V
CC = 6.0 V - - 0.33 V
pins C1A, C1B; VI=V
IH or VIL
IO=4mA; V
CC = 4.5 V - - 0.47 V
IO=5.2mA; V
CC = 6.0 V - - 0.47 V
IIinput leakage
current pins INH, VCO_IN; VI=V
CC or GND
VCC =6.0V - - 1A
General; Tamb =40 Cto+85C
ICC supply current VCO disabled; pins COMP_IN, IN H and SIG_IN at VCC;
pin VCO_IN at GND; II at pins COMP_IN and SIGN_IN to be
excluded
VCC =6.0V - - 80.0 A
Table 5. Static characteristics 74HC4046A
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
© Nexperia B.V. 2017. All rights reserved
74HC_HCT4046A All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 8 June 2016 17 of 50
Nexperia 74HC4046A; 74HCT4046A
Phase-locked loop with VCO
Phase comparator section; Tamb =40 Cto+125C
VIH HIGH-level
input voltage pins SIG_IN, COMP_IN; DC coupled
VCC = 2.0 V 1.5 - - V
VCC =4.5V 3.15 - - V
VCC = 6.0 V 4.2 - - V
VIL LOW-level
input voltage pins SIG_IN, COMP_IN; DC coupled
VCC =2.0V - - 0.5 V
VCC =4.5V - - 1.35 V
VCC =6.0V - - 1.8 V
VOH HIGH-level
output voltage pins PCP_OUT, PCn_OUT; VI=V
IH or VIL
IO=20 A; VCC =2.0V 1.9 - - V
IO=20 A; VCC =4.5V 4.4 - - V
IO=20 A; VCC =6.0V 5.9 - - V
IO=4mA; V
CC = 4.5 V 3.7 - - V
IO=5.2 mA; VCC = 6.0 V 5.2 - - V
VOL LOW-level
output voltage pins PCP_OUT, PCn_OUT; VI=V
IH or VIL
IO=20A; VCC = 2.0 V - - 0.1 V
IO=20A; VCC = 4.5 V - - 0.1 V
IO=20A; VCC = 6.0 V - - 0.1 V
IO=4mA; V
CC = 4.5 V - - 0.4 V
IO=5.2mA; V
CC = 6.0 V - - 0.4 V
IIinput leakage
current pins SIG_IN, COMP_IN; VI=V
CC or GND
VCC =2.0V - - 5A
VCC =3.0V - - 11 A
VCC =4.5V - - 27 A
VCC =6.0V - - 45 A
IOZ OFF-state
output current pin PC2_OUT; VI=V
IH or VIL; VO=V
CC or GND
VCC =6.0V - - 10 A
VCO section; Tamb =40 Cto+125C
VIH HIGH-level
input voltage pin INH
VCC = 3.0 V 2.1 - - V
VCC =4.5V 3.15 - - V
VCC = 6.0 V 4.2 - - V
VIL LOW-level
input voltage pin INH
VCC =3.0V - - 0.9 V
VCC =4.5V - - 1.35 V
VCC =6.0V - - 1.8 V
Table 5. Static characteristics 74HC4046A
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
© Nexperia B.V. 2017. All rights reserved
74HC_HCT4046A All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 8 June 2016 18 of 50
Nexperia 74HC4046A; 74HCT4046A
Phase-locked loop with VCO
[1] The parallel value of R1 and R2 should be more than 2.7 k. Optimum performance is achieved when R1 and/ or R2 are/is > 10 k.
VOH HIGH-level
output voltage pin VCO_OUT; VI=V
IH or VIL
IO=20 A; VCC =3.0V 2.9 - - V
IO=20 A; VCC =4.5V 4.4 - - V
IO=20 A; VCC =6.0V 5.9 - - V
IO=4mA; V
CC = 4.5 V 3.7 - - V
IO=5.2 mA; VCC = 6.0 V 5.2 - - V
VOL LOW-level
output voltage pin VCO_OUT; VI=V
IH or VIL
IO=20A; VCC = 3.0 V - - 0.1 V
IO=20A; VCC = 4.5 V - - 0.1 V
IO=20A; VCC = 6.0 V - - 0.1 V
IO=4mA; V
CC = 4.5 V - - 0.4 V
IO=5.2mA; V
CC = 6.0 V - - 0.4 V
pins C1A, C1B; VI=V
IH or VIL
IO=4mA; V
CC = 4.5 V - - 0.54 V
IO=5.2mA; V
CC = 6.0 V - - 0.54 V
IIinput leakage
current pins INH, VCO_IN; VI=V
CC or GND
VCC =6.0V - - 1A
General; Tamb =40 Cto+125C
ICC supply current VCO disabled; pins COMP_IN, IN H and SIG_IN at VCC;
pin VCO_IN at GND; II at pins COMP_IN and SIGN_IN to be
excluded
VCC = 6.0 V - - 160.0 A
Table 5. Static characteristics 74HC4046A
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
© Nexperia B.V. 2017. All rights reserved
74HC_HCT4046A All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 8 June 2016 19 of 50
Nexperia 74HC4046A; 74HCT4046A
Phase-locked loop with VCO
11.2 Static characteristics 74HCT4046A
Table 6. Static characteristics 74HCT4046A
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
Phase comparator section; Tamb = 25 C
VIH HIGH-level
input voltage pins SIG_IN, COMP_IN; DC coupled
VCC = 4.5 V 3.15 2.4 - V
VIL LOW-level
input voltage pins SIG_IN, COMP_IN; DC coupled
VCC =4.5V - 2.1 1.35 V
VOH HIGH-level
output voltage pins PCP_OUT, PCn_OUT; VI=V
IH or VIL
IO=20 A; VCC =4.5V 4.4 4.5 - V
IO=4A; VCC = 4.5 V 3.98 4.32 - V
VOL LOW-level
output voltage pins PCP_OUT, PCn_OUT; VI=V
IH or VIL
IO=20A; VCC = 4.5 V - 0 0.1 V
IO=4mA; V
CC = 4.5 V - 0.15 0.26 V
IIinput leakage
current pins SIG_IN, COMP_IN; VI=V
CC or GND
VCC =5.5V - - 30 A
IOZ OFF-state
output current pin PC2_OUT; VI=V
IH or VIL; VO=V
CC or GND
VCC =5.5V - - 0.5 A
RIinput
resistance pins SIG_IN, COMP_IN; VI at self-bias operating point;
VI= 0.5 V; see Figure 12, 13 and 14
VCC =4.5V - 250 - k
VCO section; Tamb = 25 C
VIH HIGH-level
input voltage pin INH
VCC = 4.5 V to 5.5 V 2.0 1.6 - V
VIL LOW-level
input voltage pin INH
VCC = 4.5 V to 5.5 V - 1.2 0.8 V
VOH HIGH-level
output voltage pin VCO_OUT; VI=V
IH or VIL
IO=20 A; VCC =4.5V 4.4 4.5 - V
IO=4mA; V
CC = 4.5 V 3.98 4.32 - V
VOL LOW-level
output voltage pin VCO_OUT; VI=V
IH or VIL
IO=20A; VCC = 4.5 V - 0 0.1 V
IO=4mA; V
CC = 4.5 V - 0.15 0.26 V
pins C1A, C1B; VI=V
IH or VIL
IO=4mA; V
CC = 4.5 V - - 0.40 V
IIinput leakage
current pins INH, VCO_IN; VCC =5.5V; V
I=V
CC or GND - - 0.1 A
R1 resistor 1 VCC = 4.5 V [1] 3-300k
R2 resistor 2 VCC = 4.5 V [1] 3-300k
C1 capacitor 1 VCC = 4.5 V 40 - no
limit pF
VVCO_IN voltage on pin
VCO_IN over the range specified for R1;
for linearity see Figure 22 and 23
VCC = 4.5 V 1.1 - 3.4 V
© Nexperia B.V. 2017. All rights reserved
74HC_HCT4046A All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 8 June 2016 20 of 50
Nexperia 74HC4046A; 74HCT4046A
Phase-locked loop with VCO
Demodulator section; Tamb = 25 C
Rsseries
resistance at Rs > 300 k, the leakage current can influence VDEM_OUT
VCC =4.5V 50 - 300 k
Voffset offset voltage VCO_IN to VDEM_OUT; VI=V
VCO_IN =0.5V
CC; values taken
over Rs range; see Figure 15
VCC =4.5V - 20 - mV
Rdyn dynamic
resistance DEM_OUT; VDEM_OUT = 0.5VCC
VCC =4.5V - 25 -
General; Tamb = 25 C
ICC supply current VCO disabled; pins COMP_IN, IN H and SIG_IN at VCC;
pin VCO_IN at GND; II at pins COMP_IN and SIGN_IN to be
excluded
VCC =6V - - 8.0 A
ICC additional
supply current pin INH; VI = VCC 2.1 V; pins COMP_IN and SIG_IN at VCC;
pin VCO_IN at GND; II at pins COMP_IN and SIGN_IN to be
excluded
VCC = 4.5 V to 5.5 V - 100 360 A
CIinput
capacitance pin INH - 3.5 - pF
Phase comparator section; Tamb =40 Cto+85C
VIH HIGH-level
input voltage pins SIG_IN, COMP_IN; DC coupled
VCC =4.5V 3.15 - - V
VIL LOW-level
input voltage pins SIG_IN, COMP_IN; DC coupled
VCC =4.5V - - 1.35 V
VOH HIGH-level
output voltage pins PCP_OUT, PCn_OUT; VI=V
IH or VIL
IO=20 A; VCC =4.5V 4.4 - - V
IO=4mA; V
CC =4.5V 3.84 - - V
VOL LOW-level
output voltage pins PCP_OUT, PCn_OUT; VI=V
IH or VIL
IO=20A; VCC = 4.5 V - - 0.1 V
IO=4mA; V
CC = 4.5 V - - 0.33 V
IIinput leakage
current pins SIG_IN, COMP_IN; VI=V
CC or GND
VCC =5.5V - - 38 A
IOZ OFF-state
output current pin PC2_OUT; VI=V
IH or VIL; VO=V
CC or GND
VCC =5.5V - - 5A
Table 6. Static characteristics 74HCT4046A
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
© Nexperia B.V. 2017. All rights reserved
74HC_HCT4046A All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 8 June 2016 21 of 50
Nexperia 74HC4046A; 74HCT4046A
Phase-locked loop with VCO
VCO section; Tamb =40 Cto+85C
VIH HIGH-level
input voltage pin INH
VCC = 4.5 V to 5.5 V 2.0 - - V
VIL LOW-level
input voltage pin INH
VCC = 4.5 V to 5.5 V - - 0.8 V
VOH HIGH-level
output voltage pin VCO_OUT; VI=V
IH or VIL
IO=20 A; VCC =4.5V 4.4 - - V
IO=4mA; V
CC =4.5V 3.84 - - V
VOL LOW-level
output voltage pin VCO_OUT; VI=V
IH or VIL
IO=20A; VCC = 4.5 V - - 0.1 V
IO=4mA; V
CC = 4.5 V - - 0.33 V
pins C1A, C1B; VI=V
IH or VIL
IO=4mA; V
CC = 4.5 V - - 0.47 V
IIinput leakage
current pins INH, VCO_IN; VI=V
CC or GND
VCC =5.5V - - 1A
General; Tamb =40 Cto+85C
ICC supply current VCO disabled; pins COMP_IN, IN H and SIG_IN at VCC;
pin VCO_IN at GND; II at pins COMP_IN and SIGN_IN to be
excluded
VCC =6V - - 80.0 A
ICC additional
supply current pin INH; VI = VCC 2.1 V; pins COMP_IN and SIG_IN at VCC;
pin VCO_IN at GND; II at pins COMP_IN and SIGN_IN to be
excluded
VCC = 4.5 V to 5.5 V - - 450 A
Phase comparator section; Tamb =40 Cto+125C
VIH HIGH-level
input voltage pins SIG_IN, COMP_IN; DC coupled
VCC =4.5V 3.15 - - V
VIL LOW-level
input voltage pins SIG_IN, COMP_IN; DC coupled
VCC =4.5V - - 1.35 V
VOH HIGH-level
output voltage pins PCP_OUT, PCn_OUT; VI=V
IH or VIL
IO=20 A; VCC =4.5V 4.4 - - V
IO=4mA; V
CC = 4.5 V 3.7 - - V
VOL LOW-level
output voltage pins PCP_OUT, PCn_OUT; VI=V
IH or VIL
IO=20A; VCC = 4.5 V - - 0.1 V
IO=4mA; V
CC = 4.5 V - - 0.4 V
IIinput leakage
current pins SIG_IN, COMP_IN; VI=V
CC or GND
VCC =5.5V - - 45 A
IOZ OFF-state
output current pin PC2_OUT; VI=V
IH or VIL; VO=V
CC or GND
VCC =5.5V - - 10 A
Table 6. Static characteristics 74HCT4046A
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
© Nexperia B.V. 2017. All rights reserved
74HC_HCT4046A All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 8 June 2016 22 of 50
Nexperia 74HC4046A; 74HCT4046A
Phase-locked loop with VCO
[1] The parallel value of R1 and R2 should be more than 2.7 k. Optimum performance is achieved when R1 and/ or R2 are/is > 10 k.
VCO section; Tamb =40 Cto+125C
VIH HIGH-level
input voltage pin INH
VCC = 4.5 V to 5.5 V 2.0 - - V
VIL LOW-level
input voltage pin INH
VCC = 4.5 V to 5.5 V - - 0.8 V
VOH HIGH-level
output voltage pin VCO_OUT; VI=V
IH or VIL
IO=20 A; VCC =4.5V 4.4 - - V
IO=4mA; V
CC = 4.5 V 3.7 - - V
VOL LOW-level
output voltage pin VCO_OUT; VI=V
IH or VIL
IO=20A; VCC = 4.5 V - - 0.1 V
IO=4mA; V
CC = 4.5 V - - 0.4 V
pins C1A, C1B; VI=V
IH or VIL
IO=4mA; V
CC = 4.5 V - - 0.54 V
IIinput leakage
current pins INH, VCO_IN; VI=V
CC or GND
VCC =5.5V - - 1A
General; Tamb =40 Cto+125C
ICC supply current VCO disabled; pins COMP_IN, IN H and SIG_IN at VCC;
pin VCO_IN at GND; II at pins COMP_IN and SIGN_IN to be
excluded
VCC = 6 V - - 160.0 A
ICC additional
supply current pin INH; VI = VCC 2.1 V; pins COMP_IN and SIG_IN at VCC;
pin VCO_IN at GND; II at pins COMP_IN and SIGN_IN to be
excluded
VCC = 4.5 V to 5.5 V - - 490 A
Table 6. Static characteristics 74HCT4046A
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
© Nexperia B.V. 2017. All rights reserved
74HC_HCT4046A All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 8 June 2016 23 of 50
Nexperia 74HC4046A; 74HCT4046A
Phase-locked loop with VCO
11.3 Graphs
Fig 12. Typica l inp ut resistance curve at SIG_IN and
COMP_IN Fig 13. Input resistance at SIG_IN, COMP_IN with
VI= 0.5 V at self-bias point
___ Rs = 50 k
- - - Rs = 300 k
Fig 14. Input current at SIG_IN, COMP_IN with
VI= 0.5 V at self-bia s point Fig 15. Offset voltage at demodulator output as a
function of VCO_ IN and Rs
DDD
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9,
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9,
9
,
9
9&& 9&&9&&
DDD
5,
Nȍ
9&& 9
9
9
9
,
9
9&& 9&&9&&
DDD
,,
$
9&& 9
9
9
9
9
9
9
9&2B,1
9
9&& 9&&9&&
DDD
9RIIVHW
P9
9&& 9
9
9
© Nexperia B.V. 2017. All rights reserved
74HC_HCT4046A All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 8 June 2016 24 of 50
Nexperia 74HC4046A; 74HCT4046A
Phase-locked loop with VCO
12. Dynamic characteristics
12.1 Dynamic characteristics 74HC4046A
Table 7. Dynamic characteristics 74HC4046A[1]
GND = 0 V; tr = tf = 6 ns; CL = 50 pF.
Symbol Parameter Conditions Min Typ Max Unit
Phase comparator section; Tamb =25C
tpd propagation
delay pins SIG_IN, COMP_IN to PC1_OUT; see Figure 16 [1]
VCC = 2.0 V - 63 200 ns
VCC = 4.5 V - 23 40 ns
VCC = 6.0 V - 18 34 ns
pins SIG_IN, COMP_IN to PCP_OUT; see Figure 16 [1]
VCC = 2.0 V - 96 340 ns
VCC = 4.5 V - 35 68 ns
VCC = 6.0 V - 28 58 ns
pins SIG_IN, COMP_IN to PC3_OUT; see Figure 16 [1]
VCC = 2.0 V - 77 270 ns
VCC = 4.5 V - 28 54 ns
VCC = 6.0 V - 22 46 ns
ten enable time pins SIG_IN, COMP_IN to PC2_OUT; see Figure 17 [1]
VCC = 2.0 V - 83 280 ns
VCC = 4.5 V - 30 56 ns
VCC = 6.0 V - 24 48 ns
tdis disable time pins SIG_IN, COMP_IN to PC2_OUT; see Figure 17 [1]
VCC = 2.0 V - 99 325 ns
VCC = 4.5 V - 36 65 ns
VCC = 6.0 V - 29 55 ns
tttransition time see Figure 16 [1]
VCC = 2.0 V - 19 75 ns
VCC =4.5V - 7 15 ns
VCC =6.0V - 6 13 ns
Vi(p-p) peak-to-peak
input voltage pins SIGN_IN, COMP_IN; AC coupled; fi=1MHz
VCC =2.0V - 9 - mV
VCC =3.0V - 11 - mV
VCC =4.5V - 15 - mV
VCC =6.0V - 33 - mV
© Nexperia B.V. 2017. All rights reserved
74HC_HCT4046A All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 8 June 2016 25 of 50
Nexperia 74HC4046A; 74HCT4046A
Phase-locked loop with VCO
VCO section; Tamb =25C
f0center
frequency VVCO_IN =0.5V
CC; duty cycle = 50 %; R1 = 3 k;
R2 = ; C1 = 40 pF; see Figure 20 and Figure 21
VCC = 3.0 V 7.0 10.0 - MHz
VCC = 4.5 V 11.0 17.0 - MHz
VCC = 5.0 V - 19.0 - MHz
VCC = 6.0 V 13.0 21.0 - MHz
f/f relative
frequency
variation
R1 = 100 k; R2 = ; C1 = 100 pF;
see Figure 22 and Figure 23
VCC =3.0V - 1.0 - %
VCC =4.5V - 0.4 - %
VCC =6.0V - 0.3 - %
duty cycle pin VCO_OUT; VCC = 3.0 V to 6.0 V - 50 - %
General; Tamb =25C
CPD power
dissipation
capacitance
[3] -24-pF
Phase comparator section; Tamb =40 C to +85 C
tpd propagation
delay pins SIG_IN, COMP_IN to PC1_OUT; see Figure 16 [1]
VCC = 2.0 V - - 250 ns
VCC =4.5V - - 50 ns
VCC =6.0V - - 43 ns
pins SIG_IN, COMP_IN to PCP_OUT; see Figure 16 [1]
VCC = 2.0 V - - 425 ns
VCC =4.5V - - 85 ns
VCC =6.0V - - 72 ns
pins SIG_IN, COMP_IN to PC3_OUT; see Figure 16 [1]
VCC = 2.0 V - - 340 ns
VCC =4.5V - - 68 ns
VCC =6.0V - - 58 ns
ten enable time pins SIG_IN, COMP_IN to PC2_OUT; see Figure 17 [1]
VCC = 2.0 V - - 350 ns
VCC =4.5V - - 70 ns
VCC =6.0V - - 60 ns
tdis disable time pins SIG_IN, COMP_IN to PC2_OUT; see Figure 17 [1]
VCC = 2.0 V - - 405 ns
VCC =4.5V - - 81 ns
VCC =6.0V - - 69 ns
Table 7. Dynamic characteristics 74HC4046A[1] …continued
GND = 0 V; tr = tf = 6 ns; CL = 50 pF.
Symbol Parameter Conditions Min Typ Max Unit
© Nexperia B.V. 2017. All rights reserved
74HC_HCT4046A All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 8 June 2016 26 of 50
Nexperia 74HC4046A; 74HCT4046A
Phase-locked loop with VCO
tttransition time see Figure 16 [1]
VCC =2.0V - - 95 ns
VCC =4.5V - - 19 ns
VCC =6.0V - - 16 ns
VCO section; Tamb =40 C to +85 C
f/T frequency
variation with
temperature
VVCO_IN =0.5V
CC; R1 = 100 k; R2 = k;
C1 = 100 pF; see Figure 18 and Figure 19
VCC = 3.0 V - 0.20 - %/K
VCC = 4.5 V - 0.15 - %/K
VCC = 6.0 V - 0.14 - %/K
Phase comparator section; Tamb =40 C to +125 C
tpd propagation
delay pins SIG_IN, COMP_IN to PC1_OUT; see Figure 16 [1]
VCC = 2.0 V - - 300 ns
VCC =4.5V - - 60 ns
VCC =6.0V - - 51 ns
pins SIG_IN, COMP_IN to PCP_OUT; see Figure 16 [1]
VCC = 2.0 V - - 510 ns
VCC = 4.5 V - - 102 ns
VCC =6.0V - - 87 ns
pins SIG_IN, COMP_IN to PC3_OUT; see Figure 16 [1]
VCC = 2.0 V - - 405 ns
VCC =4.5V - - 81 ns
VCC =6.0V - - 69 ns
ten enable time pins SIG_IN, COMP_IN to PC2_OUT; see Figure 17 [1]
VCC = 2.0 V - - 420 ns
VCC =4.5V - - 84 ns
VCC =6.0V - - 71 ns
tdis disable time pins SIG_IN, COMP_IN to PC2_OUT; see Figure 17 [1]
VCC = 2.0 V - - 490 ns
VCC =4.5V - - 98 ns
VCC =6.0V - - 83 ns
Table 7. Dynamic characteristics 74HC4046A[1] …continued
GND = 0 V; tr = tf = 6 ns; CL = 50 pF.
Symbol Parameter Conditions Min Typ Max Unit
© Nexperia B.V. 2017. All rights reserved
74HC_HCT4046A All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 8 June 2016 27 of 50
Nexperia 74HC4046A; 74HCT4046A
Phase-locked loop with VCO
[1] tpd is the same as tPLH and tPHL. tdis is the same as tPLZ and tPHZ. ten is the same as tPZL and tPZH. tt is the same as tTLH and tTHL.
[2] Applies to the phase comparator section only (VCO disabled). For power dissipation of the VCO and demodulator
sections, see Figure 24, Figure 25 and Figure 26
[3] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fiN+ (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = total load switching outputs;
(CL VCC2 fo) = sum of outputs.
12.2 Dynamic characteristics 74HCT4046A
tttransition time see Figure 16 [1]
VCC =2.0V - - 110 ns
VCC =4.5V - - 22 ns
VCC =6.0V - - 19 ns
Table 7. Dynamic characteristics 74HC4046A[1] …continued
GND = 0 V; tr = tf = 6 ns; CL = 50 pF.
Symbol Parameter Conditions Min Typ Max Unit
Table 8. Dynamic characteristics 74HCT4046A[1]
GND = 0 V; tr = tf = 6 ns; CL = 50 pF.
Symbol Parameter Conditions Min Typ Max Unit
Phase comparator section; Tamb =25C
tpd propagation
delay pins SIG_IN, COMP_I N to PC1_OUT; VCC =4.5V;
see Figure 16 [1] -2340ns
pins SIG_IN, COMP_IN t o PCP_OUT; VCC =4.5V;
see Figure 16 [1] -3568ns
pins SIG_IN, COMP_IN t o PC3_OUT; VCC =4.5V;
see Figure 16 [1] -2854ns
ten enable time pins SIG_IN, COMP_IN to PC2_OUT; VCC =4.5V;
see Figure 17 [1] -3056ns
tdis disable time pins SIG_IN, COMP_IN to PC2_OUT; VCC =4.5V;
see Figure 17 [1] -3665ns
tttransition time VCC =4.5V; see Figure 16 [1] - 7 15 ns
Vi(p-p) peak-to-peak
input voltage pins SIGN_IN, COMP_IN; AC coupled; VCC =4.5V;
fi=1MHz -15-mV
VCO section; Tamb =25C
f0center
frequency VVCO_IN =0.5V
CC; duty cycle = 50 %; R1 = 3 k;
R2 = ; C1 = 40 pF; see Figure 20 and Figure 21
VCC = 4.5 V 11.0 17.0 - MHz
VCC = 5.0 V - 19.0 - MHz
f/f relative
frequency
variation
R1 = 100 k; R2 = ; C1 = 10 0 pF; V CC = 4.5 V;
see Figure 22 and Figure 23 -0.4-%
duty cycle pin VCO_OUT; VCC = 4.5 V - 50 - %
© Nexperia B.V. 2017. All rights reserved
74HC_HCT4046A All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 8 June 2016 28 of 50
Nexperia 74HC4046A; 74HCT4046A
Phase-locked loop with VCO
[1] tpd is the same as tPLH and tPHL. tdis is the same as tPLZ and tPHZ. ten is the same as tPZL and tPZH. tt is the same as tTLH and tTHL.
[2] Applies to the phase comparator section only (VCO disabled). For power dissipation of the VCO and demodulator
sections, see Figure 24, Figure 25 and Figure 26
[3] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fiN+ (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = total load switching outputs;
(CL VCC2 fo) = sum of outputs.
General; Tamb =25C
CPD power
dissipation
capacitance
[2][3] -24-pF
Phase comparator section; Tamb =40 C to +85 C
tpd propagation
delay pins SIG_IN, COMP_I N to PC1_OUT; VCC =4.5V;
see Figure 16 [1] - - 50 ns
pins SIG_IN, COMP_IN t o PCP_OUT; VCC =4.5V;
see Figure 16 [1] - - 85 ns
pins SIG_IN, COMP_IN t o PC3_OUT; VCC =4.5V;
see Figure 16 [1] - - 68 ns
ten enable time pins SIG_IN, COMP_IN to PC2_OUT; VCC = 4.5 V;
see Figure 17 [1] - - 70 ns
tdis disable time pins SIG_IN, COMP_IN to PC2_OUT; VCC = 4.5 V;
see Figure 17 [1] - - 81 ns
tttransition time VCC = 4.5 V; see Figure 16 [1] - - 19 ns
VCO section; Tamb =40 C to +85 C
f/T frequency
variation with
temperature
VVCO_IN =0.5V
CC; R1 = 100 k; R2 = k;
C1 = 100 pF; VCC = 4.5 V; see Figure 18b0.15 - - %/K
Phase comparator section; Tamb =40 C to +125 C
tpd propagation
delay pins SIG_IN, COMP_I N to PC1_OUT; VCC =4.5V;
see Figure 16 [1] - - 60 ns
pins SIG_IN, COMP_IN t o PCP_OUT; VCC = 4.5 V ;
see Figure 16 [1] --102ns
pins SIG_IN, COMP_IN t o PC3_OUT; VCC = 4.5 V;
see Figure 16 [1] - - 81 ns
ten enable time pins SIG_IN, COMP_IN to PC2_OUT; VCC = 4.5 V;
see Figure 17 [1] - - 84 ns
tdis disable time pins SIG_IN, COMP_IN to PC2_OUT; VCC = 4.5 V;
see Figure 17 [1] - - 98 ns
tttransition time VCC = 4.5 V; see Figure 16 [1] - - 22 ns
Table 8. Dynamic characteristics 74HCT4046A[1] …continued
GND = 0 V; tr = tf = 6 ns; CL = 50 pF.
Symbol Parameter Conditions Min Typ Max Unit
© Nexperia B.V. 2017. All rights reserved
74HC_HCT4046A All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 8 June 2016 29 of 50
Nexperia 74HC4046A; 74HCT4046A
Phase-locked loop with VCO
12.3 Waveforms and graphs
VM=0.5V
CC; VI= GND to VCC.
Fig 16. Waveforms showing input (SIG_IN, COMP_IN) to output (PC1_OUT, PC3_OUT, PCP_OUT) propagation
delays and the output transition times
DDD
6,*B,1
&203B,1
3&B287
3&B287
3&3B287
,13876
2873876
W3+/
90
W3/+
W7+/
W7/+
90
VM=0.5V
CC; VI= GND to VCC.
Fig 17. Waveforms showing the enable and disable times for PC2_OUT
DDD
6,*B,1
,13876
287387
&203B,1
3&B287
W3=+ W3+=
90
W3=/
90
90
W3/=
© Nexperia B.V. 2017. All rights reserved
74HC_HCT4046A All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 8 June 2016 30 of 50
Nexperia 74HC4046A; 74HCT4046A
Phase-locked loop with VCO
To obtain optimum temperature stability, C1 must be as small as possible but larger than 100 pF.
In (b), the frequency stability for R1 = R2 = 10 k at 5 V is also given (curve A). The total VCO bias current sets this curve, and
is not simply the addition of the two 10 k stability curves. C1 = 100 pF; VVCO_IN = 0.5VCC; This curve is set as follows:
___ Without offset R2 = k: (a) R1 = 3 k; (b) R1 = 10 k; (c) R1 = 300 k.
- - - With offset R1 = k: (a) R2 = 3 k; (b) R2 = 10 k; (c) R2 = 300 k.
Fig 18. Frequency stability of the VCO as a function of ambient temperature
DDD
7DPE&
I
7DPE&
I
7DPE&
D E F
I
9
9
9
9
9
$
9
9&& 9
9
9
9
9
9&& 9
9
9
9
9&& 9
9
9
9
© Nexperia B.V. 2017. All rights reserved
74HC_HCT4046A All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 8 June 2016 31 of 50
Nexperia 74HC4046A; 74HCT4046A
Phase-locked loop with VCO
To obtain optimum temperature stability, C1 must be as small as possible but larger than 100 pF.
___ With offset; R1 = k: (a) R2 = 3 k; (b) R2 = 10 k; (c) R2 = 300 k.
Fig 19. Frequency stability of the VCO as a function of ambient temperature
7
DPE
&
I
7
DPE
&
I
7
DPE
&
D E F
DDD
I
9
&&
9
9
&&
9
9
9
9
9
&&
9
9
9
9
© Nexperia B.V. 2017. All rights reserved
74HC_HCT4046A All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 8 June 2016 32 of 50
Nexperia 74HC4046A; 74HCT4046A
Phase-locked loop with VCO
To obtain optimum temperature stability, C1 must be as small as possible but larger than 100 pF.
(a) R1 = 3 k; C1 = 40 pF (b) R1 = 3 k; C1 = 100 nF
Fig 20. Gra phs showing VCO fre qu ency as a funct ion of the VC O inp ut v oltage
9
9&2B,1
9
I
9&2
0+]
D E
DDD
9
&&
9
9
9
9
9&2B,1
9
I
9&2
0+] 9
&&
9
9
9
© Nexperia B.V. 2017. All rights reserved
74HC_HCT4046A All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 8 June 2016 33 of 50
Nexperia 74HC4046A; 74HCT4046A
Phase-locked loop with VCO
To obtain optimum temperature stability, C1 must be as small as possible but larger than 100 pF.
(a) R1 = 300 k; C1 = 40 pF (b) R1 = 300 k; C1 = 100 nF
Fig 21. Gra phs showing VCO fre qu ency as a funct ion of the VC O inp ut v oltage
9
9&2B,1
9
I
9&2
0+]
D E
DDD
9
&&
9
9
9
9
9&2B,1
9
I
9&2
0+] 9
&&
9
9
9
© Nexperia B.V. 2017. All rights reserved
74HC_HCT4046A All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 8 June 2016 34 of 50
Nexperia 74HC4046A; 74HCT4046A
Phase-locked loop with VCO
V = 0.5 V over the VCC range.
linearity =
R2 = ; V=0.5V
Fig 22. Definition of VCO frequency linearity Fig 23. Frequency linearity as a function of R1, C1
R2 = ; CL = 50 pF; VVCO_IN = 0.5VCC; Tamb =25C
___ C1 = 40 pF; - - - C1 = 1 FR1 = ; CL = 50 pF; VVCO_IN = GND; Tamb =25C
___ C1 = 40 pF; - - - C1 = 1 F
Fig 24. Power dissipation as a function of R1 Fig 25. Power dissipation as a function of R2
DDD
I
I
I
I
I
PLQ 9
&&
PD[
9
9
9&2B,1
9
DDD
5Nȍ
I
9&2
9
&&
9
9
&&
9
&
S)
&
)
9
9
9
9
9
&
S)
f‘0f1f2
+
2
--------------
=
f‘0f0
–
f‘0
---------------- 100 %
DDD
5Nȍ
35
:
9
9&&
9
9
DDD
5Nȍ
35
:
9
9&&
9
9
© Nexperia B.V. 2017. All rights reserved
74HC_HCT4046A All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 8 June 2016 35 of 50
Nexperia 74HC4046A; 74HCT4046A
Phase-locked loop with VCO
R1 = R2 = ; VVCO_IN = 0.5VCC; Tamb =25C
Fig 26. Typical power dissipation of demodulator sections as a function of Rs
DDD
3'(0
:
5
6
Nȍ
9
9&&
9
9
© Nexperia B.V. 2017. All rights reserved
74HC_HCT4046A All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 8 June 2016 36 of 50
Nexperia 74HC4046A; 74HCT4046A
Phase-locked loop with VCO
13. Application information
This information is a guide for the approximation of values of external components to be
used with the 74HC4046A; 74HCT4046A in a phase-locked-loop system.
References should be made to Figure 30, Figure 31 an d Figure 32 as indicated in
Table 10.
Values of the selected component s should be within the ranges shown in Table 9.
Table 9. Survey of components
Component Value
R1 between 3 k and 300 k
R2 between 3 k and 300 k
R1 + R2 parallel value > 2.7 k
C1 > 40 pF
Table 10 . Design considerations for VCO section
Subject Phase
comparator Design consideration
VCO frequency
without extra
offset
PC1, PC2 or PC3 VCO frequency characteristic. With R2 = and R1 within the range 3 k<R1<
300 k, the characteristics of the VCO operation is as shown in Figure 27a. (Due to
R1, C1 time constant a small offset remains when R2 = ).
PC1 Selection of R1 and C1. Given f0, determine the value s of R1 and C1 us ing
Figure 30.
PC2 or PC3 Given fmax and f0, determine the values of R1 and C1 using Figure 30; use Figure 32
to obtain 2fL and then use it to calculate fmin.
VCO frequency
with extra offset PC1, PC2 or PC3 VCO frequency characteristic with R1 and R2 within the ranges 3 k< R1 < 300 k,
3k < R2 < 300 k. The characteristics of the VCO operation are as shown in
Figure 27b.
PC1, PC2 or PC3 Selection of R1, R2 and C1. Given f0 and fL determine the value of product R1C1 by
using Figure 32. Calculate foff from the equation foff =f
0 1.6fL. Obtain the values of
C1 and R2 by using Figure 31. Calculate the value of R1 from the value of C1 and
the product R1C1.
PLL conditions
no signal at pin
SIG_IN
PC1 VCO adjusts to f0 with DEM_OUT =90 and VVCO_IN =0.5V
CC, see Figure 6
PC2 VCO adjusts to f0 with DEM_OUT =360 and VVCO_IN = minimum, see Figure 8
PC3 VCO adjusts to f0 with DEM_OUT =360 and VVCO_IN = minimum, see Figure 10
© Nexperia B.V. 2017. All rights reserved
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Product data sheet Rev. 3 — 8 June 2016 37 of 50
Nexperia 74HC4046A; 74HCT4046A
Phase-locked loop with VCO
a. Operating without offset; f0= center frequency; 2fL= frequency lock range.
b. Operating with offset; f0= center frequency; 2fL= frequency lock range.
Fig 27. Frequency characteristic of VCO
DDD
IPLQ
I9&2
9 9&& 9&&9
9&2B,1
I
IPD[
9&&
I/GXHWR
5&
DDD
IPLQ
IRII
I9&2
9 9&& 9&&9
9&2B,1
I
IPD[
9&&
I/GXHWR
5&
GXHWR
5&
© Nexperia B.V. 2017. All rights reserved
74HC_HCT4046A All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 8 June 2016 38 of 50
Nexperia 74HC4046A; 74HCT4046A
Phase-locked loop with VCO
Table 11. General design considerat ions
Subject Phase comparator Design consideration
PLL frequency capture range PC1, PC2 or PC3 Loop filter component selection, see Figure 28 and 29
PLL locks on harmonics at
center frequency PC1 or PC3 yes
PC2 no
Noise rejection at signal input PC1 high
PC2 or PC3 low
AC ripple content when PLL is
locked PC1 fr=2f
i; large ripple content at DEM_OUT =90
PC2 fr=f
i; small ripple content at DEM_OUT =0
PC3 fr=f
i; large ripple content at DEM_OUT =180
R3 500 .
A small capture range (2fc) is obtained if
(a) = R3 x C2
(b) amplitude characteristics
(c) pole-zero diagram
Fig 28. Simple loop filter for PLL without offset
DDD
LQSXW RXWSXW
)MȦ
IJ
Ȧ
D E F
5
&
2fc1
---2fL=
R3 + R4 500 .
(a) 1 = R3 x C2; 2 = R4 x C2; 3 = (R3 + R4) x C2
(b) amplitude characteristics
(c) pole-zero diagram
Fig 29. Simple loop filter for PLL with offset
DDD
LQSXW RXWSXW
)
MȦ
IJ
IJ
Ȧ
IJ
IJ
P P 5
55
D E F
5
&
5
© Nexperia B.V. 2017. All rights reserved
74HC_HCT4046A All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 8 June 2016 39 of 50
Nexperia 74HC4046A; 74HCT4046A
Phase-locked loop with VCO
To obtain optimum VCO performance, C1 must be a s small as possible but larger than 100 pF.
Interpolation for various values of R1 can be easily calculated because a constant R1C1 product produces almost the same
VCO output frequency.
R2 = ; VVCO_IN =0.5V
CC; INH = GND; Tamb =25C.
Fig 30. Typica l valu e of VCO center frequency (f0) as a function of C1
IR
+]
DDD
&S)
9
9
9&&
9
9
9
9
9
9
9
9
9
9
Nȍ
Nȍ
Nȍ
5 Nȍ
To obtain optimum VCO performance, C1 must be a s small as possible but larger than 100 pF.
Interpolation for various values of R2 can be easily calculated because a constant R2C1 product produces almost the same
VCO output frequency.
R1 = ; VVCO_IN =0.5V
CC; INH = GND; Tamb =25C.
Fig 31. Typical value of frequency offset as a function of C1
IRII
+]
DDD
&S)
9
9
9&&
9
9
9
9
9
9
9
9
9
Nȍ
Nȍ
Nȍ
5 Nȍ
© Nexperia B.V. 2017. All rights reserved
74HC_HCT4046A All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 8 June 2016 40 of 50
Nexperia 74HC4046A; 74HCT4046A
Phase-locked loop with VCO
VVCO_IN = 0.9 V to (VCC 0.9) V; R2 = .
VCO gain:
Fig 32. Typical frequency lock ra ng e (2 f L) as a function of the product R1C1
I/
+]
DDD
5&S)
9&& 99
9
9
9
Kv2fL
VVCO_IN range
---------------------------------------2rsV=
© Nexperia B.V. 2017. All rights reserved
74HC_HCT4046A All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 8 June 2016 41 of 50
Nexperia 74HC4046A; 74HCT4046A
Phase-locked loop with VCO
13.1 PLL design example
The frequency synthesizer used in the design example shown in Figure 33 has the
following parameters:
Output frequency: 2 MHz to 3 MHz
Frequency steps: 100 kHz
Settling time: 1 ms
Overshoot: < 20 %
The open loop gain is:
where:
Kp= phase comparator gain
Kf= low-pass filter transfer gain
Ko=K
v/s VCO gain
Kn=1⁄n divider ratio
The programmable counte r ratio Kn can be found as follows:
The values of R1, R2 and C1; R2 = 10 k (adjustable) set the VCO.
The values can be determined using the information in Table 10 and Table 11.
With f0= 2.5 MHz and fL= 500 kHz, the following values (VCC = 5.0 V) are given:
R1 = 10 k
R2 = 10 k
C1 = 500 pF
The VCO gain is:
The gain of the phase comparator is:
H(s) G(s) KpKfKoKn
=
Nmin fOUT
fstep
----------- 2 M H z
100 k H z
-------------------- 20== =
Nmax fOUT
fstep
----------- 3 MHz
100 kHz
---------------------30== =
Kv2fL2
VCC 0.9–0.9–
------------------------------------------1 MHz
3.2
----------------- 2210
6rsV==
KpVCC
4
------------ 0.4 Vr==
© Nexperia B.V. 2017. All rights reserved
74HC_HCT4046A All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 8 June 2016 42 of 50
Nexperia 74HC4046A; 74HCT4046A
Phase-locked loop with VCO
The transfer gain of the filter is calculated as follows:
Where:
The characteristic equation is:
It results in:
The natural frequency n defined as:
and the damping value () given as:
In Figure 34, the output frequency response to a step of input frequency is shown.
The overshoot and settling time percentages are now used to determine n.
Figure 34 shows that th e damping r atio = 0.45 produces an overshoot of le ss than 20 %
and settle to within 5 % at nt = 5. The required settling time is 1 ms. It results in:
Rewriting the equation for natural frequency results in:
The maximum overshoo t occurs at Nmax:
When C2 = 470 nF, then:
R3 can be calculated:
Kf12s+
112
+ s+
-----------------------------------
=
1R3 C2=
2R4 C2=
1 + H(s) G(s) 0=
S21K
pKv
Kn
2
+
1+2
---------------------------------------------------- SKpKv
Kn
1+2
------------------------------- 0=++
nKpKvKn
12
+
-------------------------------=
1
2n
--------- 1K
pKvKn2
+
12
+
----------------------------------------------------
=
n5
t
---5
0.001
------------- 510
3rs== =
12
+
KpKvKn
n
2
-------------------------------
=
12
+
0.4210
6
5000230
------------------------------- 0.0011 s==
R4 12
+2
n
1–
KpKv
Kn
C2
------------------------------------------------------------- 315 ==
R3 1
C2
-------R4–2 k==
© Nexperia B.V. 2017. All rights reserved
74HC_HCT4046A All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 8 June 2016 43 of 50
Nexperia 74HC4046A; 74HCT4046A
Phase-locked loop with VCO
For an extensive description and application example, refer to “Application note” ordering number 9398 649 90011.
Fig 33. Frequ ency synthes ize r
DDD
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Ȧ
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The output frequency is proportional to the VCO control voltage. As a result, the PLL frequency
response can be observed with an oscilloscope by monitoring pin VCO_IN of the VCO. The average
frequency response, as calculated by the Laplace method, is found expe rim entally by smoo th in g this
voltage at pin VCO_IN using a simple RC filter. The filter has a long time constant when compared
with the phase dete cto r sa mp lin g ra te but sh or t when compared with the PLL response time.
Fig 35. Frequency compared to the time response
WLPHPV
DDD
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1
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© Nexperia B.V. 2017. All rights reserved
74HC_HCT4046A All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 8 June 2016 44 of 50
Nexperia 74HC4046A; 74HCT4046A
Phase-locked loop with VCO
14. Package outline
Fig 36. Package outline SOT109-1 (SO16)
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© Nexperia B.V. 2017. All rights reserved
74HC_HCT4046A All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 8 June 2016 45 of 50
Nexperia 74HC4046A; 74HCT4046A
Phase-locked loop with VCO
Fig 37. Package outline SOT338-1 (SSOP16)
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© Nexperia B.V. 2017. All rights reserved
74HC_HCT4046A All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 8 June 2016 46 of 50
Nexperia 74HC4046A; 74HCT4046A
Phase-locked loop with VCO
Fig 38. Package outline SOT403-1 (TSSOP16)
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© Nexperia B.V. 2017. All rights reserved
74HC_HCT4046A All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 8 June 2016 47 of 50
Nexperia 74HC4046A; 74HCT4046A
Phase-locked loop with VCO
15. Abbreviations
16. Revision history
Table 12. Abbreviations
Acronym Description
CMOS Complementary Metal Oxide Semiconductors
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
PLL Phase-Locked Loop
VCO Vo ltage Control led Oscillator
Table 13. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74HC_HCT4046A v.3 20160608 Product data sheet - 74HC_HCT4046A_CNV v.2
Modifications: •The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
•Legal texts have been adapted to the new company name where appropriate.
74HC_HCT4046A_CNV v.2 19971125 Product specification - 74HC_HCT4046A v.1
74HC_HCT4046A v.1 19930901 Objective specification - -
© Nexperia B.V. 2017. All rights reserved
74HC_HCT4046A All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 8 June 2016 48 of 50
Nexperia 74HC4046A; 74HCT4046A
Phase-locked loop with VCO
17. Legal information
17.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is document m ay have cha nged since thi s document w as publish ed and may di ffe r in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nexperia.com.
17.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not b e relied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local Nexperia sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall pre va il.
Product specificat io n — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
Nexperia and its customer, unless Nexperia and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the Nexperia product is
deemed to off er functions and qualities beyond those described in the
Product data sheet.
17.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, Nexperia does not give any
representations or warrant ies, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. Nexperia takes no
responsibility for the content in this document if provided by an information
source outside of Nexperia.
In no event shall Nexperia be liable for any indirect, incidental,
punitive, special or consequ ential damages (including - wit hout limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, Nexperia’s aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of Nexperia.
Right to make changes — Nexperia reserves the right to make
changes to information published in this document, including without
limitation specifications and product descripti ons, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use — Nexperia products are not designed,
authorized or warranted to be suitable for use in life support , life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of a Nexperia product can reasonably be expected
to result in perso nal injury , death or severe propert y or environmental
damage. Nexperia and its suppliers accept no liability for
inclusion and/or use of Nexperia products in such equipment or
applications and ther efore such inclu sion and/or use is at the cu stomer’s own
risk.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using Nexperia products, and Nexperia
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the Nexperia
product is suitable and fit for the customer’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Custo mers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Nexperia does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the appl ication or use by customer’s
third party custo mer(s). Customer is responsible for doing all necessa ry
testing for the customer’s applications and products using Nexperia
products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). Nexperia does not accept any liability in this respect.
Terms and conditions of commercial sale — Nexperia
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nexperia.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. Nexperia hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of Nexperia products by customer.
No offer to sell or license — Nothing i n this document may be interpreted or
construed as an of fer t o sell product s that is open for accept ance or the gr ant,
conveyance or implication of any license under any copyrights, patents or
other industrial or inte llectual property right s.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contain s data from the objective specification for product develop ment.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specificat ion.
Product [short] data sheet Production This document contains the product specification.
© Nexperia B.V. 2017. All rights reserved
74HC_HCT4046A All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 8 June 2016 49 of 50
Nexperia 74HC4046A; 74HCT4046A
Phase-locked loop with VCO
Quick reference data — The Quick reference dat a is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific Nexperia product is automotive qualified,
the product is not suitable for automotive use. It i s neit her qua lif ied nor test ed
in accordance with automotive testing or application requirements. Nexperia
accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or app lications.
In the event that customer uses the product for design-in and use in
automotive applications to automot ive specifications and standards, custome r
(a) shall use the product without Nexperia’s warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
Nexperia’s specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies Nexperia for any
liability, damages or failed product claims resulting from custome r design and
use of the product for automotive applications beyond Nexperia’s
standard warranty and Nexperia’s product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
17.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respective ow ners.
18. Contact information
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Nexperia 74HC4046A; 74HCT4046A
Phase-locked loop with VCO
19. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2
6 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
7 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
8 Functional description . . . . . . . . . . . . . . . . . . . 5
8.1 VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
8.2 Phase comparators. . . . . . . . . . . . . . . . . . . . . . 5
8.2.1 Phase Comparator 1 (PC1) . . . . . . . . . . . . . . . 6
8.2.2 Phase Comparator 2 (PC2) . . . . . . . . . . . . . . . 8
8.2.3 Phase Comparator 3 (PC3) . . . . . . . . . . . . . . 10
9 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 12
10 Recommended operating conditions. . . . . . . 12
11 Static characteristics. . . . . . . . . . . . . . . . . . . . 13
11.1 Static characteristics 74HC4046A . . . . . . . . . 13
11.2 Static characteristics 74HCT4046A . . . . . . . . 19
11.3 Graphs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
12 Dynamic characteristics . . . . . . . . . . . . . . . . . 24
12.1 Dynamic characteristics 74HC4046A. . . . . . . 24
12.2 Dynamic characteristics 74HCT4046A. . . . . . 27
12.3 Waveforms and graphs. . . . . . . . . . . . . . . . . . 29
13 Application information. . . . . . . . . . . . . . . . . . 36
13.1 PLL design example. . . . . . . . . . . . . . . . . . . . 41
14 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 44
15 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 47
16 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 47
17 Legal information. . . . . . . . . . . . . . . . . . . . . . . 48
17.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 48
17.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
17.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 48
17.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 49
18 Contact information. . . . . . . . . . . . . . . . . . . . . 49
19 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
© Nexperia B.V. 2017. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release:
08 June 2016
