64-Position Up/Down Control Digital Potentiometer Preliminary Technical Data AD5227 FEATURES * * * * * * * * * * * * For users who consider EEMEM potentiometers, they may refer to some recommendations in the Applications Section. 64-Position 10k, 50k, 100k end-to-end terminal resistance Simple Up/Down Digital or Manual Configurable Control Mid-Scale Preset Low Potentiometer Mode TC 10ppm/oC Low Rheostat Mode TC 35ppm/oC Ultra low power, IDD = 5A Max Fast Adjustment Time, ts = 1s Chip Select Enable Multi-Devices Operation Low Operating Voltage, 2.7V to 5.5V Automotive Temperature Range -40C to +105C Compact Thin SOT23-8 (2.9 mm x 3 mm) package FUNCTIONAL BLOCK DIAGRAM VDD CS A 6-Bit Up/Down Control Logic U/D CLK GND APPLICATIONS * * * * * * Figure 1. Functional Block Diagram Table 1. Truth Table CLK CS U/D 0 0 GENERAL DESCRIPTIONS AD5227 is Analog Devices latest 64-Step Up/Down Control Digital Potentiometer1. This device performs the same electronic adjustment function as a 5V potentiometer or variable resistor. Its common 3-wire up/down interface allows high-speed as well as low-speed digital controls. AD5227 presets to mid-scale in Operation RWB Decrement, RWA Increment 0 1 RWB Increment, RWA Decrement 1 X X No Operation PIN CONFIGURATION 1 CLK VDD 8 power up. When CS is enabled, the Up/Down direction is depended on the state of U/D and it executes at every clock pulse. 2 U/D 3 A The interface is simple that can be controlled by any host controllers, discrete logics, and manually with rotary encoder or push buttons. AD5227 adequate resolution, small footprint, and simple interface enable it to be the potential replacements of mechanical potentiometers and trimmers with typically 6X improved resolution, solid-state reliability, and design layout flexibility. These enhancements can result in considerable cost saving in end users' systems. The AD5227 is available in compact thin SOT23-8 package. All parts are guaranteed to operate over the extended industrial temperature range of -40C to +105C. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties, which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices B WIPER REGISTER POR Mid-scale AD5227 Mechanical Potentiometers and Trimmers Replacements LCD Contrast, Brightness, and Backlight Controls Portable Electronics Level Adjustments Programmable Power Supply Digital Trimmers Replacements Automatic Close Loop Control REV. Pr F 1/20/2004 W 4 GND CS 7 B 6 W 5 SOT23-8 Figure 2. Pin Configuration Note 1. The term digital potentiometer and RDAC are used interchangeably. 1 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2004 Preliminary Technical Data AD5227 TABLE OF CONTENTS General Description ...............Error! Bookmark not defined. AD5227--Specifications........Error! Bookmark not defined. Absolute Maximum Ratings ..................................................... 5 Thermal Resistance............Error! Bookmark not defined. Pin Configurations And Functional Descriptions........ Error! Bookmark not defined. Typical Performance Characteristics ..Error! Bookmark not defined. Theory of Operation .............. Error! Bookmark not defined. Outline Dimensions..................................................................10 ESD Caution..........................................................................10 REVISION HISTORY Revision PrD: Initial Version REV. Pr F 1/20/2004 2 Preliminary Technical Data AD5227 Table 2. ELECTRICAL CHARACTERISTICS 10k , 50k, 100k VERSION (VDD = +3V10% or +5V10%, VA = +VDD, VB = 0V, -40C < TA < +105C unless otherwise noted.) Parameter Symbol Conditions Min Typ1 Max Units RWB, VA=NC RWB, VA=NC -1 -1 -30 0.25 0.5 +1 +1 30 35 200 400 LSB LSB % ppm/C 6 +1 +1 Bits LSB LSB ppm/C LSB LSB DC CHARACTERISTICS RHEOSTAT MODE Resistor Differential NL2 Resistor Nonlinearity2 Nominal resistor tolerance Resistance Temperature Coefficient Wiper Resistance Wiper Resistance R-DNL R-INL RAB/RAB TA = 25C (RAB/RAB)/T RW RW IW = VDD/R, VDD = 5V IW = VDD /R, VDD = 2.7V 120 200 DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Resolution N Integral Nonlinearity4 INL Differential Nonlinearity4 DNL Voltage Divider Temperature Coefficient(VW/VW)/TMid-scale Full-Scale Error VWFSE +32 Steps from Mid-scale (Full-scale) Zero-Scale Error VWZSE -32 Steps from Mid-scale (Zero-scale) -1 -1 -2 0 0.5 0.1 5 -0.5 +0.5 +0 +1 RESISTOR TERMINALS Voltage Range5 Capacitance6 A, B Capacitance6 W Common Mode Leakage VA,B,W CA,B CW ICM DIGITAL INPUTS & OUTPUTS Input Logic High Input Logic Low Input Current Input Capacitance6 VIH VIL IIL CIL POWER SUPPLIES Power Supply Range Supply Current Power Dissipation10 Power Supply Sensitivity VDD IDD PDISS PSS VIH = +5V or VIL = 0V, VDD = +5V VIH = +5V or VIL = 0V, VDD = +5V VDD = +5V 10% BW THDW tS eN_WB RAB = 10k/50k/100k, Mid-scale VA =1Vrms + 2V dc, VB = 2V DC, f=1KHz VA= VDD, VB=0V, 1 LSB error band RWB = 5K, f = 1kHz 0 f = 1 MHz, measured to GND, Mid-scale f = 1 MHz, measured to GND, Mid-scale VA = VB = VW VDD = +5V VDD = +5V VIN = 0V or +5V VDD 45 60 1 2.4 0.8 1 V V A pF +5.5 5 25 0.15 V A W %/% 5 +2.7 0.05 V pF pF nA DYNAMIC CHARACTERISTICS6,9,11 Bandwidth -3dB Total Harmonic Distortion VW Settling Time Resistor Noise Voltage INTERFACE TIMING CHARACTERISTICS applies to all parts(Notes 6,12) Input Clock Pulse Width tCH,tCL Clock level high or low CS to CLK Setup Time tCSS CS Rise to CLK Hold Time tCSH U/D to Clock Fall Setup Time tUDS 600/X/Y 0.05 1 14 10 10 10 10 kHz % s nVHz ns ns ns ns NOTES: 1. 2. 4. 5. 6. 7. 9. 10. Typicals represent average readings at +25C, VDD = +5V. Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0V. DNL specification limits of 1LSB maximum are Guaranteed Monotonic operating conditions. Resistor terminals A,B,W have no limitations on polarity with respect to each other. Guaranteed by design and not subject to production test. Measured at the A terminal. The A terminal is open circuited in shutdown mode. Bandwidth, noise and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth. The highest R value result in the minimum overall power consumption. PDISS is calculated from (IDD x VDD). CMOS logic level inputs result in minimum power dissipation. REV. Pr F 1/20/2004 3 Preliminary Technical Data 11. 12. AD5227 All dynamic characteristics use VDD = +5V. See timing diagram for location of measured values. All input control voltages are specified with tR=tF=1ns(10% to 90% of VDD) and timed from a voltage level of 1.6V. Switching characteristics are measured using both VDD = +5V. REV. Pr F 1/20/2004 4 Preliminary Technical Data AD5227 Absolute Maximum Ratings Table 3. AD5227 Absolute Maximum Ratings Parameter Rating VDD to GND -0.3, +7V VA, VB, VW to GND GND, VDD Maximum Current 20mA IWB, IWA Pulsed IWB Continuous (RWB 1 k, A open) 1 5mA IWA Continuous (RWA 1 k, B open) 1 5mA Digital Input Voltage to GND 0V, VDD Operating Temperature Range -40C to +105C Maximum Junction Temperature (TJ max) 150C Storage Temperature -65C to +150C Lead Temperature (Soldering, 10 - 30 sec) 245C Thermal Resistance2 JA, 230C/W 1 Maximum terminal current is bounded by the maximum applied voltage across any two of the A, B, and W terminals at a given resistance, the maximum current handling of the switches, and the maximum power dissipation of the package. VDD = 5 V. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condition s above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Package Power Dissipation = (TJMAX - TA) / JA Pin Configurations And Functional Descriptions 1 CLK VDD 8 CS 7 2 U/D 3 A B 6 4 GND W 5 Figure 3. SOT23-8 Table 4. Pin Function Descriptions Pin No. Name Description 1 CLK Clock Input. Each Clock Pulse Executes The Step-Up or Step-Down of the Resistances. The Direction is Determined By The State in U/D Pin. Clock is Negative Edge Trigger 2 U/D Up/Down Selections. Logic 1 Selects Up and 0 Selects Down 3 A Resistor Terminal A. GNDVAVDD 4 GND Common Ground 5 W Wiper Terminal W. GNDVWVDD 6 B Resistor Terminal B. GNDVBVDD 7 CS Chip Select. Active Low 8 VDD Positive Power Supply, +2.7 V to +5.5 V INTERFACE TIMING DIAGRAM Figure 4.Stepping Up RWB REV. Pr F 1/20/2004 5 Preliminary Technical Data AD5227 PROGRAMMING THE DIGITAL POTENTIOMETERS Rheostat Operation If only the W-to-B or W-to-A terminals are used as variable resistor, the unused terminal can be opened or shorted with W, such operation is called rheostat mode, Figure 8. Figure 5. Stepping Down RWB CS 1 tCSS 0 tCSH 1 CLK U/D tCL tCH 0 1 Figure 8. Rheostat Mode Configuration tUDS 0 Figure 6. Detail Timing Diagram The end-to-end resistance RAB has 64 contact points accessed by the wiper terminal, plus the B terminal contact if RWB is used, , see Figure 7. Clocking the CLK input will step RWB by one step and the direction is determined by the state of U/D pin. In the open loop applications, the change of resistance, RWB can be determined by the number of clock pulses applied to the clock pin provided its maximum and minimum settings are not reached. The RWB can therefore be approximated as OPERATION The AD5227 provides a 64 position digitally-controlled potentiometer device. It presets to a mid-scale at system power ON. When CS is enabled, changing the resistance settings is achieved by clocking the CLK pin. The direction of stepping is controlled by the U/D control input. Additional CLK pulses will not change the wiper setting when the wiper hits the maximum or the minimum setting. When push button switch is used to control the clock, appropriate de-bounce circuitry should be considered. The timing requirements are shown in Figure 6. R RWB = CP AB + RW 64 where: CP is the number of clock pulses. RAB is the end-to-end resistance. RW is the wiper resistance contributed by the on-resistance of the internal switch. A RS D0 D1 D2 D3 D4 D5 Since in the lowest end of the resistor string, a finite wiper resistance of 60 is present. Care should be taken to limit the current flow between W and B in this state to a maximum pulse current of no more than 20 mA. Otherwise, degradation or possible destruction of the internal switch contact can occur. RS RS W RDAC UP/DOWN CTRL& DECODE Similar to the mechanical potentiometer, the resistance of the RDAC between the wiper W and terminal A also produces a digitally controlled complementary resistance RWA. When these terminals are used, the B-terminal can be opened or shorted to W. The RWA can also be approximated if its maximum and minimum settings are not reached. RW RS B RS=RAB/64 R RWA = (64 - CP ) AB + RW 64 Figure 7. AD5227 Equivalent RDAC Circuit Equations 1 and 2 do not apply when CP = 0. The typical distribution of the resistance tolerance from device to device is process lot dependent and is possible to have 30% tolerance. REV. Pr F 1/20/2004 (1) 6 (2) Preliminary Technical Data AD5227 Potentiometer Mode Operation the U/D control pin. When the state of U/D remains, the device continues to change to the same direction under consecutive clocks until it hits the end of the resistance setting. If all three terminals are used, the operation is called the potentiometer mode. The most common configuration is the voltage divider operation, Figure 9. All digital inputs are protected with a series input resistor and parallel Zener ESD structure shown in Figure 10. Applies to digital input pins CS, U/D, and CLK. 1K LOGIC Figure 10. Equivalent ESD Protection Digital Pins Figure 9. Potentiometer Mode Configuration Terminal Voltage Operation Range The transfer function is: CP R AB + RW VW = 64 VA R AB + 2 RW The AD5227 is designed with internal ESD diodes for protection but they also set the boundary of the terminal operating voltages. Positive signals present on terminal A, B, or W that exceeds VDD will be clamped by the forward biased diode. There is no polarity constraint between VAB, VWA, and VWB but they cannot be higher than VDD-to-GND. (3) If we ignore the effect of the wiper resistance, the transfer function simplifies to VW = CP VA 64 VDD (4) Unlike in rheostat mode operation where the absolute tolerance is high, potentiometer mode operation yields an almost ratio-metric function of CP/64 with a relatively small error contributed by the RW terms, the tolerance effect is therefore almost cancelled. Although the thin film step resistor RS and CMOS switches resistance RW have very different temperature coefficients, the ratio-metric adjustment also makes the overall temperature coefficient effect reduced to 5ppm/oC except at low value codes where RW dominates. A W B GND Figure 11. Maximum Terminal Voltages Set by VDD and GND Power-Up and Power-Down Sequences Since there are ESD protection diodes that limit the voltage compliance at terminals A, B, and W (Figure 11), it is important to power VDD before applying any voltage to terminals A, B, and W. Otherwise, the diodes will be forward biased such that VDD will be powered unintentionally and may affect the rest of the users' circuit. Similarly, VDD should be powered down last. The ideal power-up sequence is in the following order: GND, VDD, digital inputs, and VA/B/W. The order of powering V A, V B, V W, and digital inputs is not important as long as they are powered after VDD. Potentiometer mode operations include others operations such as opamp input and feedback resistors network and other voltage scaling applications. A, W, and B terminals can in fact be input or output terminals and have no polarity constraint provided that |VAB|, |VWA|, and |VWB| do not exceed VDD-to-GND. INTERFACING The AD5227 contains a three-wire serial input interface. The three inputs are clock (CLK), CS (Chip Select), and up/down control (U/D). These inputs can be controlled digitally for optimum speed and flexibility. Standard logic families work well. On the other hand, they can also be controlled by mechanical means for simple manual operation. The states of the CS and U/D can be selected by the mechanical switches. The CLK input can be controlled by a pushbutton but it should be properly debounced by flip-flops or other suitable means. The negative-edge sensitive CLK input requires clean transitions to avoid clocking multiple pulses into the internal UP/Down counter register. When CS is pulled low, a clock pulse increments or decrements the up/down counter and the direction is determined by the state of REV. Pr F 1/20/2004 Layout and Power Supply Biasing It is always a good practice to employ compact, minimum lead length layout design. The leads to the input should be as direct as possible with a minimum conductor length. Ground paths should have low resistance and low inductance. Similarly, it is also good practice to bypass the power supplies with quality capacitors. Low ESR (Equivalent Series Resistance) 1F to 10F tantalum or electrolytic capacitors should be applied at the 7 Preliminary Technical Data AD5227 supplies to minimize any transient disturbance and filter low frequency ripple. Figure 12 illustrates the basic supply-bypassing configuration for the AD5227 AD5227 Figure 12. Power Supply Bypassing The ground pin of the AD5227 is a digital ground reference. To minimize the digital ground bounce, the AD5227 ground terminal should be joined remotely to the common ground ground, Figure 12 REV. Pr F 1/20/2004 8 Preliminary Technical Data AD5227 In the factory calibration, the one time programmable1 digital pot AD5273 is used to adjust various intensity levels. Once the desirable level is determined, a computer program can program such setting permanently and the system can be shipped to the field. APPLICATIONS Manual Control with Push Button and Toggle Switch When the system is powered up, we may assume the white LED remains at off due to the delay. The photocell sensor senses no intensity and therefore provides high output resistance. The comparator -IN node becomes high and outputs low if this level is higher than the +IN reference level and makes the up/down control digital pot select to the count down direction. AD5227 will decrement at every clock pulse generated by the clock generator U4, R3, and C1. The continued lowering of P1's gate voltage makes it turn on harder to drive the white LED. The operation reverses when the white LED intensity is higher than the reference level. This system is therefore self-regulated. Although the resolution is limited to 1.6%, this system is a simple self-contained close loop control and is adaptive if U1 is made adjustable at the field VCC MR RESET ADM812 AD5227 GND Figure 13. Manual Push Button Up/Down Control Manual Control with Rotary Encorder AD5227 Constant Bias To Retain Resistance Setting RE11CT-V1Y12-EF2CS For users who consider EEMEM pots but cannot justify the additional cost for their designs, they may consider AD5227 as low cost alternatives. They may constantly bias the AD5227 with the supply to retain the resistance setting. AD5227 is designed specifically with low power in mind that allows power conservation even in the battery-operated systems. As shown in Figure 16, a similar low power digital pot is applied in a 3.4V 450mAhour Li-ion cellphone battery. The measurement shows that the device drains negligible power. Constantly bias the pot is not an impractical approach because most of the portable devices nowadays do not require detachable batteries for charging purpose. Although the resistance setting of AD5227 will be lost when the battery needs replacement, such event occurs infrequently that such inconvenience is justified for most applications. And when it happens, user should be provided with a mean to adjust the setting accordingly. Figure 14. Manual Rotary Control Simple Automatic Controller 3.50 3.49 o TA = 25 C Figure 15. Automatic Controller Implemented in white LED driver Battery Voltage (V) 3.48 Figure 15 shows a simple automatic close loop controller that can be used in many different applications. The core of the controller consists of a one time programmable digital pot, a comparator, a 6bit up/down control digital pot, and a Schmitt trigger NAND gate. For illustration purpose, the application shows a conceptual linear control of white LED. Typical white LEDs employ PWM controls for efficiency purpose but the circuit above can be expanded to PWM with an addition of a boost regulator. REV. Pr F 1/20/2004 3.47 3.46 3.45 3.44 3.43 3.42 3.41 3.40 0 2 4 6 8 10 Days Figure 16. Battery Consumption Measurement. 9 12 Preliminary Technical Data AD5227 Outline Dimensions Dimensions shown in inches and (mm) 8 7 6 5 1 2 3 4 1.60 BSC PR04419-0-1/04(PrF) 2.90 BSC 2.80 BSC PIN 1 0.65 BSC 1.95 BSC 0.90 0.84 1.00 MAX 0.36 0.22 0.20 0.12 0.50 0.30 8 0 SEATING PLANE Figure 17. 8-Lead Small Outline Transistor Package [Thin SOT-23] (UJ-8) Dimensions shown in millimeters ESD Caution ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Table 1. Ordering Guide Model1 RAB (k) Temp Range Package Code Package Description Full Container Quantity Brand AD5227BUJZ10-R7 10 -40oC to +105oC UJ SOT23-8 3000 D3G AD5227BUJZ10 10 -40oC to +105oC UJ SOT23-8 250 D3G o o AD5227BUJZ50-R7 50 -40 C to +105 C UJ SOT23-8 3000 D3H AD5227BUJZ50 50 -40oC to +105oC UJ SOT23-8 250 D3H AD5227BUJZ100-R7 100 -40oC to +105oC UJ SOT23-8 3000 D3J UJ SOT23-8 250 D3J AD5227BUJZ100 100 AD5227EVAL 10 o o -40 C to +105 C 1 1. Z=Pb Free Parts The end-to-end resistance RAB is available in 10k, 50k, and 100k. The final three characters of the part number determine the nominal resistance value, e.g., 10k =10. REV. Pr F 1/20/2004 10