TLV5604
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176B – DECEMBER 1997 – REVISED JULY 2002
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Four 10-Bit D/A Converters
D
Programmable Settling Time
of 3 µs or 9 µs Typ
D
TMS320, (Q)SPI, and Microwire
Compatible Serial Interface
D
Internal Power-On Reset
D
Low Power Consumption:
5.5 mW, Slow Mode – 5-V Supply
3.3 mW, Slow Mode – 3-V Supply
D
Reference Input Buffers
D
Voltage Output Range ...2× the Reference
Input Voltage
D
Monotonic Over Temperature
D
Dual 2.7-V to 5.5-V Supply (Separate Digital
and Analog Supplies)
D
Hardware Power Down (10 nA)
D
Software Power Down (10 nA)
D
Simultaneous Update
applications
D
Battery Powered Test Instruments
D
Digital Offset and Gain Adjustment
D
Industrial Process Controls
D
Machine and Motion Control Devices
D
Communications
D
Arbitrary Waveform Generation
description
The TL V5604 is a quadruple 10-bit voltage output
digital-to-analog converter (DAC) with a flexible
4-wire serial interface. The 4-wire serial interface
allows glueless interface to TMS320, SPI, QSPI,
and Microwire serial ports. The TLV5604 is
programmed with a 16-bit serial word comprised
of a DAC address, individual DAC control bits, and
a 10-bit DAC value.
The device has provision for two supplies: one digital supply for the serial interface (via pins DVDD and DGND),
and one for the DACs, reference buffers and output buffers (via pins AVDD and AGND). Each supply is
independent of the other, and can be any value between 2.7 V and 5.5 V. The dual supplies allow a typical
application where the DAC will be controlled via a microprocessor operating on a 3-V supply (also used on pins
DVDD and DGND), with the DACs operating on a 5-V supply . Of course, the digital and analog supplies can be
tied together.
The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer. The buffer features a Class AB
output stage to improve stability and reduce settling time. A rail-to-rail output stage and a power-down mode
makes it ideal for single voltage, battery based applications. The settling time of the DAC is programmable to
allow the designer to optimize speed versus power dissipation. The settling time is chosen by the control bits
within the 16-bit serial input string. A high-impedance buffer is integrated on the REFINAB and REFINCD
terminals to reduce the need for a low source impedance drive to the terminal. REFINAB and REFINCD allow
DACs A and B to have a dif ferent reference voltage then DACs C and D.
The device, implemented with a CMOS process, is available in 16-terminal SOIC and TSSOP packages. The
TLV5604C is characterized for operation from 0°C to 70°C. The TLV5604I is characterized for operation from
–40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
DVDD
PD
LDAC
DIN
SCLK
CS
FS
DGND
AVDD
REFINAB
OUTA
OUTB
OUTC
OUTD
REFINCD
AGND
(TOP VIEW)
D OR PW PACKAGE
SPI and QSPI are trademarks of Motorola, Inc.
Microwire is a trademark of National Semiconductor Corporation.
TLV5604
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176B – DECEMBER 1997 – REVISED JULY 2002
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
AVAILABLE OPTIONS
PACKAGE
TASOIC
(D) TSSOP
(PW)
0°C to 70°C TLV5604CD TLV5604CPW
–40°C to 85°C TLV5604ID TLV5604IPW
functional block diagram
7
5
Power-On
Reset
14-Bit
Data
and
Control
Register
REFINAB
AGND
CS
DIN
DAC A
Serial
Input
Register
6
9
10-Bit
DAC
Latch
2-Bit
Control
Data
Latch Power Down/
Speed Control
_
+
10
22
10
14
OUTA
DAC
Select/
Control
Logic
FS
DAC B
DAC C
DAC D
OUTB
OUTC
OUTD
LDAC PD
DGND
AVDD DVDD
4
15 16 1
8
32
11
12
13
14
REFINCD
SCLK
2
x2
TLV5604
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176B – DECEMBER 1997 – REVISED JULY 2002
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME NO.
I/O
DESCRIPTION
AGND 9 Analog ground
AVDD 16 Analog supply
CS 6 I Chip select. This terminal is active low.
DGND 8 Digital ground
DIN 4 I Serial data input
DVDD 1Digital supply
FS 7 I Frame sync input. The falling edge of the frame sync pulse indicates the start of a serial data frame shifted out
to the TLV5604.
PD 2 I Power-down pin. Powers down all DACs (overriding their individual power down settings), and all output stages.
This terminal is active low.
LDAC 3 I Load DAC. When the LDAC signal is high, no DAC output updates occur when the input digital data is read into
the serial interface. The DAC outputs are only updated when LDAC is low.
REFINAB 15 I Voltage reference input for DACs A and B.
REFINCD 10 I Voltage reference input for DACs C and D.
SCLK 5 I Serial Clock input
OUTA 14 O DAC A output
OUTB 13 O DAC B output
OUTC 12 O DAC C output
OUTD 11 ODAC D output
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, (DVDD, AVDD to GND) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply voltage difference, (AVDD to DVDD) –2.8 V to 2.8 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital input voltage range –0.3 V to DVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference input voltage range –0.3 V to AVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA: TLV5604C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TLV5604I –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
TLV5604
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176B – DECEMBER 1997 – REVISED JULY 2002
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions
MIN NOM MAX UNIT
Su
pp
ly voltage AVDD DVDD
5-V supply 4.5 5 5.5
V
Supply
voltage
,
AV
DD,
DV
DD 3-V supply 2.7 3 3.3
V
High level digital in
p
ut voltage VIH
DVDD = 2.7 V 2
V
High
-
level
digital
input
voltage
,
V
IH DVDD = 5.5 V 2.4
V
Low level digital in
p
ut voltage VIL
DVDD = 2.7 V 0.6
V
Low
-
level
digital
input
voltage
,
V
IL DVDD = 5.5 V 1
V
Reference voltage V fto REFINAB REFINCD terminal
5-V supply (see Note 1) 0 2.048 AVDD–1.5
V
Reference
voltage
,
V
ref
to
REFINAB
,
REFINCD
terminal
3-V supply (see Note 1) 0 1.024 AVDD–1.5
V
Load resistance, RL2 10 kΩ
Load capacitance, CL100 pF
Serial clock rate, SCLK 20 MHz
O
p
erating free air tem
p
erature
TLV5604C 0 70 °
C
Operating
free
-
air
temperature
TLV5604I –40 85
°C
NOTE 1: V oltages greater than AVDD/2 will cause output saturation for large DAC codes.
electrical characteristics over recommended operating free-air temperature range
(unless otherwise noted)
static DAC specifications
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Resolution 10 bits
Integral nonlinearity (INL), end point adjusted See Note 2 ±1 LSB
Differential nonlinearity (DNL) See Note 3 ±0.1 ±1 LSB
EZS Zero scale error (offset error at zero scale) See Note 4 ±12 mV
Zero scale error temperature coefficient See Note 5 10 ppm/°C
EGGain error See Note 6 ±0.6 %of FS
voltage
Gain error temperature coefficient See Note 7 10 ppm/°C
PSRR
Power su
pp
ly rejection ratio
Zero scale gain
See Notes 8 and 9
–80
dB
PSRR
Power
supply
rejection
ratio
Gain
See
Notes
8
and
9
–80
dB
NOTES: 2. The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error , is the maximum deviation of the output
from the line between zero and full scale excluding the effects of zero code and full-scale errors.
3. The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal
1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains
constant) as a change in the digital input code.
4. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.
5. Zero-scale-error temperature coef ficient is given by: EZS TC = [EZS (Tmax) – EZS (Tmin)]/Vref × 106/(Tmax – Tmin).
6. Gain error is the deviation from the ideal output (2Vref – 1 LSB) with an output load of 10 kΩ excluding the ef fects of the zero-error .
7. Gain temperature coefficient is given by: EG TC = [EG(Tmax) – EG (Tmin)]/Vref × 106/(Tmax – Tmin).
8. Zero-scale-error rejection ratio (EZS–RR) is measured by varying the AVDD from 5 ±0.5 V and 3 ±0.3 V dc, and measuring the
proportion of this signal imposed on the zero-code output voltage.
9. Gain-error rejection ratio (EG-RR) is measured by varying the AVDD from 5 ±0.5 V and 3 ±0.3 V dc and measuring the proportion
of this signal imposed on the full-scale output voltage after subtracting the zero scale change.
TLV5604
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176B – DECEMBER 1997 – REVISED JULY 2002
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range
(unless otherwise noted) (continued)
individual DAC output specifications
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOV oltage output RL = 10 kΩ0AVDD–0.4 V
Output load regulation accuracy RL = 2 kΩ vs 10 kΩ0.1 0.25 % of FS
voltage
reference input (REFINAB, REFINCD)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIInput voltage range See Note 10 0AVDD–1.5 V
RIInput resistance 10 MΩ
CIInput capacitance 5 pF
Reference feed through REFIN = 1 Vpp at 1 kHz + 1.024 V dc
(see Note 11) –75 dB
p
REFIN = 0 2 V + 1 024 V dc
Slow 0.5
MHz
REFIN
=
0
.
2
V
pp +
1
.
024
V
dc
Fast 1
MHz
NOTES: 10. Reference input voltages greater than VDD/2 will cause output saturation for large DAC codes.
11. Reference feedthrough is measured at the DAC output with an input code = 000 hex and a Vref(REFINAB or REFINCD)
input = 1.024 Vdc + 1 Vpp at 1 kHz.
digital inputs (D0–D11, CS, WEB, LDAC, PD)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IIH High-level digital input current VI = DVDD ±1µA
IIL Low-level digital input current VI = 0 V ±1µA
CIInput capacitance 3 pF
power supply
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
5Vsu
pp
ly No load Clock running
Slow 1.4 2.2
mA
IDD
Power su
pp
ly current
5
-
V
supply
,
No
load
,
Clock
running
Fast 3.5 5.5
mA
I
DD
Power
supply
current
3Vsu
pp
ly No load Clock running
Slow 1 1.5
mA
3
-
V
supply
,
No
load
,
Clock
running
Fast 3 4.5
mA
Power down supply current,
See Figure 12 10 nA
TLV5604
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176B – DECEMBER 1997 – REVISED JULY 2002
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range
(unless otherwise noted) (continued)
analog output dynamic performance
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SR
Out
p
ut slew rate
CL = 100 pF, RL = 10 kΩ,
VO10% to 90%
Fast 5 V/µs
SR
Output
slew
rate
V
O =
10%
t
o
90%
,
Vref = 2.048 V, 1024 V Slow 1 V/µs
t
Out
p
ut settling time
To ±0.5 LSB, C
L
= 100 pF, Fast 2.5 4
µs
t
s
Output
settling
time
,L,
RL = 10 kΩ, See Notes 12 and 14 Slow 8.5 18 µ
s
t()
Out
p
ut settling time code to code
To ±0.5 LSB, C
L
= 100 pF, Fast 1
µs
t
s(c)
Output
settling
time
,
code
to
code
,L,
RL = 10 kΩ, See Note 13 Slow 2 µ
s
Glitch energy Code transition from 7FF to 800 10 nV-sec
SNR Signal-to-noise ratio Sinewave generated by DAC,
R f l 1 024 3 V d 2 048 5 V
68
S/(N+D) Signal to noise + distortion Reference voltage = 1.024 at 3 V and 2.048 at 5 V,
f
s
= 4
00
K
S
P
S,
65
dB
THD Total harmonic Distortion
fs
=
400
KSPS
,
fOUT = 1.1 kHz sinewave,
CL= 100
p
FR
L=10kΩ
–68 dB
SFDR Spurious free dynamic range
CL
=
100
pF
,
RL
=
10
kΩ
,
BW = 20 kHz 70
NOTES: 12. Settling time is the time for the output signal to remain within ±0.5LSB of the final measured value for a digital input code change
of 020 hex to 3FF hex or 3FF hex to 020 hex.
13. Settling time is the time for the output signal to remain within ±0.5LSB of the final measured value for a digital input code change
of one count, 1FF hex to 200 hex.
14. Limits are ensured by design and characterization, but are not production tested.
TLV5604
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176B – DECEMBER 1997 – REVISED JULY 2002
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range
(unless otherwise noted) (continued)
digital input timing requirements
MIN NOM MAX UNIT
tsu(CS–FS) Setup time, CS low before FS↓10 ns
tsu(FS–CK) Setup time, FS low before first negative SCLK edge 8 ns
tsu(C16–FS) Setup time, sixteenth negative SCLK edge after FS low on which bit D0 is sampled before
rising edge of FS 10 ns
tsu(C16–CS) Setup time. The first positive SCLK edge after D0 is sampled before CS rising edge. If FS
is used instead of the SCLK positive edge to update the DAC, then the setup time is between
the FS rising edge and CS rising edge. 10 ns
twH Pulse duration, SCLK high 25 ns
twL Pulse duration, SCLK low 25 ns
tsu(D) Setup time, data ready before SCLK falling edge 8 ns
th(D) Hold time, data held valid after SCLK falling edge 5 ns
twH(FS) Pulse duration, FS high 20 ns
PARAMETER MEASUREMENT INFORMATION
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
123451516
D15 D14 D13 D12 D1 D0
tsu(FS-CK)
tsu(CS-FS)
twH(FS)
th(D)
tsu(D)
twH
twL
tsu(C16-CS)
tsu(C16-FS)
SCLK
DIN
CS
FS
Figure 1. Timing Diagram
TLV5604
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176B – DECEMBER 1997 – REVISED JULY 2002
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 2
0.20
0.10
0.05
00 0.02 0.04 0.1 0.2 0.4 1
– Output Voltage – V
0.25
0.30
Load Current – mA
LOAD REGULATION
0.35
24
0.15
VO
VDD = 5 V,
VREF = 2 V,
VO = Full Scale
5 V Slow Mode, Sink
5 V Fast Mode, Sink
0.8
Figure 3
0.10
0.08
0.04
00 0.01 0.02 0.05 0.1 0.2 0.5
0.16
0.18
LOAD REGULATION
0.20
12
0.14
0.12
0.06
0.02
– Output Voltage – V
Load Current – mA
VO
VDD = 3 V,
VREF = 1 V,
VO = Full Scale
3 V Slow Mode, Sink
3 V Fast Mode, Sink
0.8
Figure 4
3.994
3.99
3.986
3.984
3.996
4.00
LOAD REGULATION
4.002
3.998
3.992
3.988
– Output Voltage – V
Load Current – mA
VO
VDD = 5 V,
VREF = 2 V,
VO = Full Scale
5 V Slow Mode, Source
5 V Fast Mode, Source
0 0.02 0.04 0.1 0.2 0.4 1 2 40.8
Figure 5
2.0015
2.0005
1.9995
1.999
2.002
2.0025
LOAD REGULATION
2.003
2.001
2
– Output Voltage – V
Load Current – mA
VO
3 V Slow Mode, Source
3 V Fast Mode, Source
VDD = 3 V,
VREF = 1 V,
VO = Full Scale
0 0.01 0.02 0.05 0.1 0.2 0.5 1 20.8
TLV5604
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176B – DECEMBER 1997 – REVISED JULY 2002
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 6
2.5
2
1.5
0.5
–40 –20 0 20 40 60
– Supply Current – mA
3
3.5
SUPPLY CURRENT
vs
TEMPERATURE
4
1
T – Temperature – °C
IDD
Fast Mode
Slow Mode
VDD = 3 V,
VREF = 1.024 V,
VO = Full Scale
80 100
Figure 7
2.5
2
1.5
0.5
– Supply Current – mA
3
3.5
SUPPLY CURRENT
vs
TEMPERATURE
4
1
T – Temperature – °C
IDD
Fast Mode
Slow Mode
–40 –20 0 20 40 60 80 100
VDD = 5 V,
VREF = 1.024 V,
VO = Full Scale
Figure 8
––40
–50
–70
–80 0 5 10 20
THD – Total Harmonic Distortion – dB
–30
–10
f – Frequency – kHz
TOTAL HARMONIC DISTORTION
vs
FREQUENCY
0
30 50 100
–20
–60
Vref = 1 V dc + 1 V p/p Sinewave,
Output Full Scale
Fast Mode
Figure 9
––40
–50
–70
–80 0 5 10 20
THD – Total Harmonic Distortion – dB
–30
–10
f – Frequency – kHz
TOTAL HARMONIC DISTORTION
vs
FREQUENCY
0
30 50 100
–20
–60
Vref = 1 V dc + 1 V p/p Sinewave,
Output Full Scale
Slow Mode
TLV5604
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176B – DECEMBER 1997 – REVISED JULY 2002
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 10
––40
–50
–70
–80 0 5 10 20
THD – Total Harmonic Distortion And Noise – dB
–30
–10
f – Frequency – kHz
TOTAL HARMONIC DISTORTION AND NOISE
vs
FREQUENCY
0
30 50 100
–20
–60
Vref = 1 V dc + 1 V p/p Sinewave,
Output Full Scale
Fast Mode
Figure 11
––40
–50
–70
–80 0 5 10 20
–30
–10
f – Frequency – kHz
TOTAL HARMONIC DISTORTION AND NOISE
vs
FREQUENCY
0
30 50 100
–20
–60
Vref = 1 V dc + 1 V p/p Sinewave,
Output Full Scale
THD – Total Harmonic Distortion And Noise – dB
Slow Mode
2000
1500
1000
00 200 400 600
– Supply Current –
3000
3500
t – Time – ns
SUPPLY CURRENT
vs
TIME
(WHEN ENTERING POWER-DOWN MODE)
4000
800 1000
2500
500
IDD Aµ
Figure 12
TLV5604
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176B – DECEMBER 1997 – REVISED JULY 2002
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
–0.6 0 64 128 192 256 320 384
0
576 640 768 832
0.2
–0.2
–0.4
448 512 704
INL – Integral Nonlinearity – LSB
896 960
VDD = 5 V, Vref = 2 V,
CLK = 1 MHz
INTEGRAL NONLINEARITY
Digital Code
1024
Figure 13
0
–0.1 0 64 128 192 256 384 512
DNL – Differential Nonlinearity – LSB
0.05
0.1
Digital Code
DIFFERENTIAL NONLINEARITY
0.15
576 640 704 768
–0.05
320 448 832 896 960
VDD = 5 V, Vref = 2 V,
CLK = 1 MHz
1024
Figure 14
TLV5604
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176B – DECEMBER 1997 – REVISED JULY 2002
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
general function
The TLV5604 is a 10-bit single supply DAC based on a resistor string architecture. The device consists of a serial
interface, speed and power-down control logic, a reference input buffer , a resistor string, and a rail-to-rail output
buffer.
The output voltage (full scale determined by external reference) is given by:
2REFCODE
2n[V]
Where REF is the reference voltage and CODE is the digital input value within the range of 010 to 2n–1, where
n=10 (bits). The 16-bit data word, consisting of control bits and the new DAC value, is illustrated in the data
format section. A power-on reset initially resets the internal latches to a defined state (all bits zero).
serial interface
Explanation of data transfer: First, the device has to be enabled with CS set to low. Then, a falling edge of FS
starts shifting the data bit-per-bit (starting with the MSB) to the internal register on the falling edges of SCLK.
After 16 bits have been transferred or FS rises, the content of the shift register is moved to the DAC latch, which
updates the voltage output to the new level.
The serial interface of the TLV5604 can be used in two basic modes:
D
Four wire (with chip select)
D
Three wire (without chip select)
Using chip select (four wire mode), it is possible to have more than one device connected to the serial port of
the data source (DSP or microcontroller). The interface is compatible with the TMS320 family . Figure 15 shows
an example with two TLV5604s connected directly to a TMS320 DSP.
TMS320
DSPXF0
XF1
FSX
DX
CLKX
TLV5604
CS FS DIN SCLK
TLV5604
CS FS DIN SCLK
Figure 15. TMS320 Interface
TLV5604
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176B – DECEMBER 1997 – REVISED JULY 2002
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
serial interface (continued)
If there is no need to have more than one device on the serial bus, then CS can be tied low. Figure 16 shows
an example of how to connect the TLV5604 to a TMS320, SPI, or Microwire port using only three pins.
TMS320
DSPFSX
DX
CLKX
TLV5604
FS
DIN
SCLK
CS
SPI
SS
MOSI
SCLK
TLV5604
FS
DIN
SCLK
CS
Microwire
I/O
SO
SK
TLV5604
FS
DIN
SCLK
CS
Figure 16. Three-Wire Interface
Notes on SPI and Microwire: Before the controller starts the data transfer , the software has to generate a falling
edge on the I/O pin connected to FS. If the word width is 8 bits (SPI and Microwire), two write operations must
be performed to program the TLV5604. After the write operation(s), the DAC output is updated automatically
on the next positive clock edge following the sixteenth falling clock edge.
serial clock frequency and update rate
The maximum serial clock frequency is given by:
fSCLKmax
+
1
twH(min)
)
twL(min)
+
20 MHz
The maximum update rate is:
fUPDATEmax
+
1
16
ǒ
twH(min)
)
twL(min)
Ǔ+
1.25 MHz
Note that the maximum update rate is a theoretical value for the serial interface since the settling time of the
TLV5604 has to be considered also.
data format
The 16-bit data word for the TLV5604 consists of two parts:
D
Control bits (D15 . . . D12)
D
New DAC value (D11 ...D0)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
A1 A0 PWR SPD New DAC value (10 bits) X X
X: don’t care
SPD: Speed control bit. 1 → fast mode 0 → slow mode
PWR: Power control bit. 1 → power down 0 → normal operation
TLV5604
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176B – DECEMBER 1997 – REVISED JULY 2002
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
In power down mode, all amplifiers within the TLV5604 are disabled. A particular DAC (A, B, C, D) of the
TLV5604 is selected by A1 and A0 within the input word.
A1 A0 DAC
0 0 A
0 1 B
1 0 C
1 1 D
TLV5604 interfaced to TMS320C203 DSP
Hardware interfacing
Figure 17 shows an example of how to connect the TLV5604 to a TMS320C203 DSP. The serial port is
configured in burst mode, with FSX generated by the TMS320C203 to provide the Frame Sync (FS) input to
the TLV5604. Data is transmitted on the DX line, with the serial clock input on the CLKX line. The
general-purpose input/output port bits IO0 and IO1 are used to generate the Chip Select (CS) and DAC Latch
Update (LDAC) inputs to the TLV5604. The active low Power Down (PD) is pulled high all the time to ensure
the DACs are enabled.
DX
CLKX
FSX
I/O 0
I/O 1
TMS320C203
SDIN
SCLK
FS
CS
LDAC
REF
VDD
PD
VOUTA
VOUTB
VOUTC
VOUTD
VSS
TLV5604
REFINAB
REFINCD
Figure 17. TLV5604 Interfaced with TMS320C203
Software
The application example generates a differential in-phase (sine) signal between the VOUTA and VOUTB pins,
and it is quadrature (cosine) signal as the differential signal between VOUTC and VOUTD.
The on-chip timer is used to generate interrupts at a fixed frequency. The related interrupt service routine pulses
LDAC low to update all 4 DACs simultaneously, then fetches and writes the next sample to all 4 DACs. The
samples are stored in a look-up table, which describes two full periods of a sine wave.
The synchronous serial port of the DSP is used in burst mode. In this mode, the processor generates an FS
pulse preceding the MSB of every data word. If multiple, contiguous words are transmitted, a violation of the
tsu(C16-FS) timing requirement will occur. T o avoid this, the program waits until the transmission of the previous
word has been completed.
TLV5604
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176B – DECEMBER 1997 – REVISED JULY 2002
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––;
; Processor: TMS320C203 runnning at 40 MHz;
; Description:
;
; This program generates a differential in-phase (sine) on (OUTA–OUTB) and it’s
; quadrature (cosine) as a differential signal on (OUTC–OUTD).
;
; The DAC codes for the signal samples are stored as a table of 64 12–bit values,
; describing 2 periods of a sine function. A rolling pointer is used to address the
; table location in the first period of this waveform, from which the DAC A samples are
; read. The samples for the other 3 DACs are read at an offset to this rolling pointer:
; DAC Function Offset from rolling pointer;
; A sine 0
; B inverse sine 16
; C cosine 8
; D inverse cosine 24
;
; The on-chip timer is used to generate interrupts at a fixed rate. The interrupt
; service routine first pulses LDAC low to update all DACs simultaneously with the
; values which were written to them in the previous interrupt. Then all 4 DAC values are
; fetched and written out through the synchronous serial interface. Finally, the
; rolling pointer is incremented to address the next sample, ready for the next
; interrupt.
;
; 1998, Texas Instruments Incorporated
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––;
; ––––––––––I/O and memory mapped regs –––––––––––––––––––––––––––––––––––––––––––
.include ”regs.asm”
; ––––––––––––––jump vectors––––––––––––––––––––––––––––––––––––––––––––––––––––––
.ps 0h
b start
b int1
b int23
b timer_isr
;–––––––––––––––––––––– variables ––––––––––––––––––––––––––––––––––––––––––––––––
temp .equ 0060h
r_ptr .equ 0061
iosr_stat .equ 0062h
DACa_ptr .equ 0063h
DACb_ptr .equ 0064h
DACc_ptr .equ 0065h
DACd_ptr .equ 0066h
;––––––––– constants –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; DAC control bits to be OR’ed onto data
; all fast mode
DACa_control .equ 01000h
DACb_control .equ 05000h
DACc_control .equ 09000h
DACd_control .equ 0d000h
;––––––––––– tables –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
.ds 02000h
sinevals
.word 00800h
.word 0097Ch
.word 00AE9h
.word 00C3Ah
.word 00D61h
.word 00E53h
.word 00F07h
.word 00F76h
.word 00F9Ch
.word 00F76h
.word 00F07h
.word 00E53h
.word 00D61h
.word 00C3Ah
TLV5604
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176B – DECEMBER 1997 – REVISED JULY 2002
16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
.word 00AE9h
.word 0097Ch
.word 00800h
.word 00684h
.word 00517h
.word 003C6h
.word 0029Fh
.word 001ADh
.word 000F9h
.word 0008Ah
.word 00064h
.word 0008Ah
.word 000F9h
.word 001ADh
.word 0029Fh
.word 003C6h
.word 00517h
.word 00684h
.word 00800h
.word 0097Ch
.word 00AE9h
.word 00C3Ah
.word 00D61h
.word 00E53h
.word 00F07h
.word 00F76h
.word 00F9Ch
.word 00F76h
.word 00F07h
.word 00E53h
.word 00D61h
.word 00C3Ah
.word 00AE9h
.word 0097Ch
.word 00800h
.word 00684h
.word 00517h
.word 003C6h
.word 0029Fh
.word 001ADh
.word 000F9h
.word 0008Ah
.word 00064h
.word 0008Ah
.word 000F9h
.word 001ADh
.word 0029Fh
.word 003C6h
.word 00517h
.word 00684h
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; Main Program
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
.ps 1000h
.entry
start
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; disable interrupts
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
setc INTM ; disable maskable interrupts
splk #0ffffh, IFR ; clear all interrupts
splk #0004h, IMR ; timer interrupts unmasked
TLV5604
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176B – DECEMBER 1997 – REVISED JULY 2002
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; set up the timer
; timer period set by values in PRD and TDDR
; period = (CLKOUT1 period) × (1+PRD) × (1+TDDR)
; examples for TMS320C203 with 40 MHz main clock
; Timer rate TDDR PRD
; 80 kHz 9 24 (18h)
; 50 kHz 9 39 (27h)
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
prd_val.equ 0018h
tcr_val.equ 0029h
splk #0000h, temp ; clear timer
out temp, TIM
splk #prd_val, temp ; set PRD
out temp, PRD
splk #tcr_val, temp ; set TDDR, and TRB=1 for auto-reload
out temp, TCR
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; Configure IO0/1 as outputs to be :
; IO0 CS – and set high
; IO1 LDAC – and set high
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
in temp, ASPCR ; configure as output
lacl temp
or #0003h
sacl temp
out temp, ASPCR
in temp, IOSR ; set them high
lacl temp
or #0003h
sacl temp
out temp, IOSR
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; set up serial port for
; SSPCR.TXM=1 Transmit mode – generate FSX
; SSPCR.MCM=1 Clock mode – internal clock source
; SSPCR.FSM=1 Burst mode
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
splk #0000Eh, temp
out temp, SSPCR ; reset transmitter
splk #0002Eh, temp
out temp, SSPCR
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; reset the rolling pointer
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
lacl #000h sacl r_ptr
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; enable interrupts
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
clrc INTM
; enable maskable interrupts
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; loop forever!
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
next idle ;wait for interrupt
b next
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; all else fails stop here
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
done b done ;hang there
TLV5604
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176B – DECEMBER 1997 – REVISED JULY 2002
18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; Interrupt Service Routines
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
int1 ret ; do nothing and return
int23 ret ; do nothing and return
timer_isr:
in iosr_stat, IOSR ; store IOSR value into variable space
lacl iosr_stat ; load acc with iosr status
and #0FFFDh ; reset IO1 – LDAC low
sacl temp ;
out temp, IOSR ;
or #0002h ; set IO1 – LDAC high
sacl temp ;
out temp, IOSR ;
and #0FFFEh ; reset IO0 – CS low
sacl temp ;
out temp, IOSR ;
lacl r_ptr ; load rolling pointer to accumulator
add #sinevals ; add pointer to table start
sacl DACa_ptr ; to get a pointer for next DAC a sample
add #08h ; add 8 to get to DAC C pointer
sacl DACc_ptr
add #08h ; add 8 to get to DAC B pointer
sacl DACb_ptr
add #08h ; add 8 to get to DAC D pointer
sacl DACd_ptr
mar *,ar0 ; set ar0 as current AR
; DAC A
lar ar0, DACa_ptr ; ar0 points to DAC a sample
lacl * ; get DAC a sample into accumulator
or #DACa_control ; OR in DAC A control bits
sacl temp ;
out temp, SDTR ; send data
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; We must wait for transmission to complete before writing next word to the SDTR.
; TLV5604 interface does not allow the use of burst mode with the full packet rate, as
; we need a CLKX –ve edge to clock in last bit before FS goes high again, to allow SPI
; compatibility.
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
rpt #016h ; wait long enough for this configuration
nop ; of MCLK/CLKOUT1 rate
; DAC B
lar ar0, DACb_ptr ; ar0 points to DAC a sample
lacl * ; get DAC a sample into accumulator
or #DACb_control ; OR in DAC B control bits
sacl temp ;
out temp, SDTR ; send data
rpt #016h ; wait long enough for this configuration
nop ; of MCLK/CLKOUT1 rate
TLV5604
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176B – DECEMBER 1997 – REVISED JULY 2002
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
; DAC C
lar ar0, DACc_ptr ; ar0 points to DAC a sample
lacl * ; get DAC a sample into accumulator
or #DACc_control ; OR in DAC C control bits
sacl temp ;
out temp, SDTR ; send data
rpt #016h ; wait long enough for this configuration
nop ; of MCLK/CLKOUT1 rate
; DAC D
lar ar0, DACd_ptr ; ar0 points to DAC a sample
lacl * ; get DAC a sample into accumulator
or #DACd_control; OR in DAC D control bits
sacl temp ;
out temp, SDTR ; send data
lacl r_ptr ; load rolling pointer to accumulator
add #1h ; increment rolling pointer
and #001Fh ; count 0–31 then wrap back round
sacl r_ptr ; store rolling pointer
rpt #016h ; wait long enough for this configuration
nop ; of MCLK/CLKOUT1 rate
; now take CS high again
lacl iosr_stat ; load acc with iosr status
or #0001h ; set IO0 – CS high
sacl temp ;
out temp, IOSR ;
clrc intm ; re-enable interrupts
ret ; return from interrupt
.end
TLV5604
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176B – DECEMBER 1997 – REVISED JULY 2002
20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
TLV5604 interfaced to MCS51 microcontroller
hardware interfacing
Figure 18 shows an example of how to connect the TLV5604 to an MCS51 Microcontroller. The serial DAC
input data and external control signals are sent via I/O Port 3 of the controller. The serial data is sent on the RxD
line, with the serial clock output on the TxD line. Port 3 bits 3, 4, and 5 are configured as outputs to provide the
DAC latch update (LDAC), chip select (CS) and frame sync (FS) signals for the TL V5604. The active low power
down pin (PD) of the TLV5604 is pulled high to ensure that the DACs are enabled.
RxD
TxD
P3.3
P3.4
MCS
®
51
SDIN
SCLK
FS
CS
LDAC
REF
VDD
PD
VOUTA
VOUTB
VOUTC
VOUTD
VSS
TLV5604
P3.4
REFINAB
REFINCD
Figure 18. TLV5604 Interfaced with MCS51
software
The example is the same as for the TMS320C203 in this datasheet, but adapted for a MCS51 controller. It
generates a differential in-phase (sine) signal between the VOUTA and VOUTB pins, and it’s quadrature
(cosine) signal as the differential signal between VOUTC and VOUTD.
The on-chip timer is used to generate interrupts at a fixed frequency. The related interrupt service routine pulses
LDAC low to update all 4 DACs simultaneously, then fetches and writes the next sample to all 4 DACs. The
samples are stored as a look-up table, which describes one full period of a sine wave.
The serial port of the controller is used in Mode 0, which transmits 8 bits of data on RxD, accompanied by a
synchronous clock on TxD. Two writes concatenated together are required to write a complete word to the
TLV5604. The CS and FS signals are provided in the required fashion through control of IO port 3, which has
bit addressable outputs.
MCS is a registered trademark of Intel Corporation.
TLV5604
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176B – DECEMBER 1997 – REVISED JULY 2002
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
;––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; Processor: 80C51
;
; Description:
;
; This program generates a differential in–phase (sine) on (OUTA–OUTB) and it’s
; quadrature (cosine) as a differential signal on (OUTC–OUTD).
; 1998, Texas Instruments Incorporated
;––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
NAME GENIQ
MAIN SEGMENT CODE
ISR SEGMENT CODE
SINTBL SEGMENT CODE
VAR1 SEGMENT DATA
STACK SEGMENT IDATA
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; Code start at address 0, jump to start
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
CSEG AT 0
LJMP start ; Execution starts at address 0 on power–up.
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; Code in the timer0 interrupt vector
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
CSEG AT 0BH
LJMP timer0isr ; Jump vector for timer 0 interrupt is 000Bh
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; Global variables need space allocated
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
RSEG VAR1
Temp_ptr: DS 1
rolling_ptr: DS 1
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; Interrupt service routine for timer 0 interrupts
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
RSEG ISR
timer0isr: PUSH PSW
PUSH ACC
CLR INT1 ; pulse LDAC low
SETB INT1 ; to latch all 4 previous values at the same time
; 1st thing done in timer isr => fixed period
CLR T0 ; set CS low
; The signal to be output on each DAC is a sine function.
; One cycle of a sine wave is held in a table @ sinevals as 32 samples of msb,
; lsb pairs (64 bytes). We have one pointer which rolls round this table,
; rolling_ptr, incrementing by 2 bytes (1 sample) on each interrupt (at the end of
; this routine).
; The DAC samples are read at an offset to this rolling pointer:
; DAC Function Offset from rolling_ptr
; A sine 0
; B inverse sine 32
; C cosine 16
; D inverse cosine 48
MOV DPTR,#sinevals ; set DPTR to the start of the table of sine signal values
MOV R7,rolling_ptr ; R7 holds the pointer into the sine table
MOV A,R7 ; get DAC A msb
MOVC A,@A+DPTR ; msb of DAC A is in the ACC
CLR T1 ; transmit it – set FS low
MOV SBUF,A ; send it out the serial port
INC R7 ; increment the pointer in R7
MOV A,R7 ; to get the next byte from the table
MOVC A,@A+DPTR ; which is the lsb of this sample, now in ACC
TLV5604
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176B – DECEMBER 1997 – REVISED JULY 2002
22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
A_MSB_TX:
JNB TI,A_MSB_TX ; wait for transmit to complete
CLR TI ; clear for new transmit
MOV SBUF,A ; and send out the lsb of DAC A
; DAC C next
; DAC C codes should be taken from 16 bytes (8 samples) further on in the sine table
; – this gives a cosine function
MOV A,R7 ; pointer in R7
ADD A,#0FH ; add 15 – already done one INC
ANL A,#03FH ; wrap back round to 0 if > 64
MOV R7,A ; pointer back in R7
MOVC A,@A+DPTR ; get DAC C msb from the table
ORL A,#01H ; set control bits to DAC C address
A_LSB_TX:
JNB TI,A_LSB_TX ; wait for DAC A lsb transmit to complete
SETB T1 ; toggle FS
CLR T1
CLR TI ; clear for new transmit
MOV SBUF,A ; and send out the msb of DAC C
INC R7 ; increment the pointer in R7
MOV A,R7 ; to get the next byte from the table
MOVC A,@A+DPTR ; which is the lsb of this sample, now in ACC
C_MSB_TX:
JNB TI,C_MSB_TX ; wait for transmit to complete
CLR TI ; clear for new transmit
MOV SBUF,A ; and send out the lsb of DAC C
; DAC B next
; DAC B codes should be taken from 16 bytes (8 samples) further on
; in the sine table – this gives an inverted sine function
MOV A,R7 ; pointer in R7
ADD A,#0FH ; add 15 – already done one INC
ANL A,#03FH ; wrap back round to 0 if > 64
MOV R7,A ; pointer back in R7
MOVC A,@A+DPTR ; get DAC B msb from the table
ORL A,#02H ; set control bits to DAC B address
C_LSB_TX:
JNB TI,C_LSB_TX ; wait for DAC C lsb transmit to complete
SETB T1 ; toggle FS
CLR T1
CLR TI ; clear for new transmit
MOV SBUF,A ; and send out the msb of DAC B
; get DAC B LSB
INC R7 ; increment the pointer in R7
MOV A,R7 ; to get the next byte from the table
MOVC A,@A+DPTR ; which is the lsb of this sample, now in ACC
B_MSB_TX:
JNB TI,B_MSB_TX ; wait for transmit to complete
CLR TI ; clear for new transmit
MOV SBUF,A ; and send out the lsb of DAC B
TLV5604
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176B – DECEMBER 1997 – REVISED JULY 2002
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
; DAC D next
; DAC D codes should be taken from 16 bytes (8 samples) further on in the sine table
; – this gives an inverted cosine function
MOV A,R7 ; pointer in R7
ADD A,#0FH ; add 15 – already done one INC
ANL A,#03FH ; wrap back round to 0 if > 64
MOV R7,A ; pointer back in R7
MOVC A,@A+DPTR ; get DAC D msb from the table
ORL A,#03H ; set control bits to DAC D address
B_LSB_TX:
JNB TI,B_LSB_TX ; wait for DAC B lsb transmit to complete
SETB T1 ; toggle FS
CLR T1
CLR TI ; clear for new transmit
MOV SBUF,A ; and send out the msb of DAC D
INC R7 ; increment the pointer in R7
MOV A,R7 ; to get the next byte from the table
MOVC A,@A+DPTR ; which is the lsb of this sample, now in ACC
D_MSB_TX:
JNB TI,D_MSB_TX ; wait for transmit to complete
CLR TI ; clear for new transmit
MOV SBUF,A ; and send out the lsb of DAC D
; increment the rolling pointer to point to the next sample
; ready for the next interrupt
MOV A,rolling_ptr
ADD A,#02H ; add 2 to the rolling pointer
ANL A,#03FH ; wrap back round to 0 if > 64
MOV rolling_ptr,A ; store in memory again
D_LSB_TX:
JNB TI,D_LSB_TX ; wait for DAC D lsb transmit to complete
CLR TI ; clear for next transmit
SETB T1 ; FS high
SETB T0 ; CS high
POP ACC
POP PSW
RETI
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; Stack needs definition
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
RSEG STACK
DS 10h ; 16 Byte Stack!
TLV5604
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176B – DECEMBER 1997 – REVISED JULY 2002
24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; Main program code
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
RSEG MAIN
start: MOV SP,#STACK–1 ; first set Stack Pointer
CLR A
MOV SCON,A ; set serial port 0 to mode 0
MOV TMOD,#02H ; set timer 0 to mode 2 – auto-reload
MOV TH0,#038H ; set TH0 for 5 kHs interrupts
SETB INT1 ; set LDAC = 1
SETB T1 ; set FS = 1
SETB T0 ; set CS = 1
SETB ET0 ; enable timer 0 interrupts
SETB EA ; enable all interrupts
MOV rolling_ptr,A ; set rolling pointer to 0
SETB TR0 ; start timer 0
always:
JMP always ; while(1) !
RET
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; Table of 32 sine wave samples used as DAC data
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
RSEG SINTBL
sinevals:
DW 01000H
DW 0903EH
DW 05097H
DW 0305CH
DW 0B086H
DW 070CAH
DW 0F0E0H
DW 0F06EH
DW 0F039H
DW 0F06EH
DW 0F0E0H
DW 070CAH
DW 0B086H
DW 0305CH
DW 05097H
DW 0903EH
DW 01000H
DW 06021H
DW 0A0E8H
DW 0C063H
DW 040F9H
DW 080B5H
DW 0009FH
DW 00051H
DW 00026H
DW 00051H
DW 0009FH
DW 080B5H
DW 040F9H
DW 0C063H
DW 0A0E8H
DW 06021H
END
TLV5604
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176B – DECEMBER 1997 – REVISED JULY 2002
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
4040047/D 10/96
0.228 (5,80)
0.244 (6,20)
0.069 (1,75) MAX 0.010 (0,25)
0.004 (0,10)
1
14
0.014 (0,35)
0.020 (0,51)
A
0.157 (4,00)
0.150 (3,81)
7
8
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.010 (0,25)
PINS **
0.008 (0,20) NOM
A MIN
A MAX
DIM
Gage Plane
0.189
(4,80)
(5,00)
0.197
8
(8,55)
(8,75)
0.337
14
0.344
(9,80)
16
0.394
(10,00)
0.386
0.004 (0,10)
M
0.010 (0,25)
0.050 (1,27)
0°–8°
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
TLV5604
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176B – DECEMBER 1997 – REVISED JULY 2002
26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
4040064/E 08/96
14 PIN SHOWN
Seating Plane
1,20 MAX
1
A
7
14
0,19
4,50
4,30
8
6,20
6,60
0,30
0,75
0,50
0,25
Gage Plane
0,15 NOM
0,65 M
0,10
0°–8°
0,10
PINS **
A MIN
A MAX
DIM
2,90
3,10
8
4,90
5,10
14
6,60
6,404,90
5,10
16
7,70
20
7,90
24
9,60
9,80
28
0,15
0,05
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TLV5604CD ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5604CDG4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5604CDR ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5604CDRG4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5604CPW ACTIVE TSSOP PW 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5604CPWG4 ACTIVE TSSOP PW 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5604CPWR ACTIVE TSSOP PW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5604CPWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5604ID ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5604IDG4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5604IPW ACTIVE TSSOP PW 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5604IPWG4 ACTIVE TSSOP PW 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5604IPWR ACTIVE TSSOP PW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5604IPWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
PACKAGE OPTION ADDENDUM
www.ti.com 27-Aug-2009
Addendum-Page 1
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 27-Aug-2009
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TLV5604CDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
TLV5604CPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
TLV5604IPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 25-Sep-2009
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLV5604CDR SOIC D 16 2500 346.0 346.0 33.0
TLV5604CPWR TSSOP PW 16 2000 346.0 346.0 29.0
TLV5604IPWR TSSOP PW 16 2000 346.0 346.0 29.0
PACKAGE MATERIALS INFORMATION
www.ti.com 25-Sep-2009
Pack Materials-Page 2
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