Features * Incorporates the ARM7TDMITM ARM(R) Thumb(R) Processor Core * * * * * * * * * * * * - High-performance 32-bit RISC Architecture - High-density 16-bit Instruction Set - Leader in MIPS/Watt - Embedded ICE (In-Circuit Emulation) 8K Bytes of On-chip SRAM - 32-bit Data Bus - Single-clock Cycle Access 128K Bytes of On-chip ROM - 32-bit Data Bus - Single-clock Cycle Access Fully-programmable External Bus Interface (EBI) - Maximum External Address Space of 64M Bytes - Up to 8 Chip Selects - Software Programmable 8-/16-bit External Data Bus 8-level Priority, Individually Maskable, Vectored Interrupt Controller - 4 External Interrupts, Including a High-priority Low-latency Interrupt Request 32 Programmable I/O Lines 3-channel 16-bit Timer/Counter - 3 External Clock Inputs - 2 Multi-purpose I/O Pins per Channel 2 USARTs - 2 Dedicated Peripheral Data Controller (PDC) Channels per USART Programmable Watchdog Timer Advanced Power-saving Features - CPU and Peripherals Can be Deactivated Individually Fully Static Operation: 0 Hz to 33 MHz Internal Frequency Range at 3.0 V, 85C 1.8V to 3.6V Operating Range Available in a 100-lead TQFP Package AT91 ARM(R) Thumb(R) Microcontroller s AT91M40807 Electrical Characteristics Description The AT91M40807 microcontroller is a member of the Atmel AT91 16-/32-bit microcontroller family, which is based on the ARM7TDMI processor core. This processor has a high-performance 32-bit RISC architecture with a high-density 16-bit instruction set and very low power consumption. In addition, a large number of internally banked registers result in very fast exception handling, making the device ideal for real-time control applications. The AT91M40807 microcontroller features a direct connection to off-chip memory, including Flash, through the fully-programmable External Bus Interface (EBI). An eight-level priority vectored interrupt controller, in conjunction with the Peripheral Data Controller, significantly improves the real-time performance of the device. The device is manufactured using Atmel's high-density CMOS technology. By combining the ARM7TDMI processor core with an on-chip high-speed SRAM and ROM memor y and a wide range of peripheral functions on a monolithic chip, the AT91M40807 is a powerful microcontroller that offers a flexible, cost-effective solution to many compute-intensive embedded control applications. Rev. 1391B-01/02 1 Absolute Maximum Ratings* Operating Temperature (Industrial)................. -40C to + 85C *NOTICE: Storage Temperature ................................... -60C to + 150C Voltage on Any Input Pin with Respect to Ground...........................-0.5V to + 3.9V Maximum Operating Voltage.....................................4.6V Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Output Current...................................................6 mA DC Characteristics The following characteristics are applicable to the Operating Temperature range: TA = -40C to 85C, unless otherwise specified and are certified for a Junction Temperature up to TJ = 100C Table 1. DC Characteristics Symbol Parameter VDD DC Supply VIL Input Low Voltage VIH Max Units 1.8 3.6 V VDD = 3.0V to 3.6V -0.3 0.3 x VDD V Input High Voltage VDD = 3.0V to 3.6V 0.7 x VDD VDD + 0.3 V VOL Output Low Voltage IOL = 0.3 mA, VDD = 3.0V 0.1 V VOH Output High Voltage IOH = 0.3 mA, VDD = 3.0V ILEAK Input Leakage Current IPULL Input Pull-up Current CIN Input Capacitance ISC Conditions Min Typ VDD - 0.1 VDD = 3.6V, VIN = 0V V 390 nA 350 A 6.8 pF VDD = 3.6V; MCKI = 0 Hz TA = 25C 40 All inputs driven TMS, TDI, TCK, NRST = 1 TA = 85C 320 A Static Current . 2 AT91M40807 1391B-01/02 AT91M40807 Power Consumption The values in the following tables are measured values in the operating conditions indicated (i.e., VDD = 3.3V or 2.0V, TA = 25C) on the AT91EB40 Evaluation Board. Table 2. Power Consumption VDD Mode 2.0V 3.3V 0.05 0.10 Fetch in ARM mode out of Internal SRAM All peripheral clocks activated 1.52 4.89 Fetch in ARM mode out of Internal SRAM All peripheral clocks deactivated 1.12 3.55 All peripheral clocks activated 0.69 2.18 All peripheral clocks deactivated 0.2 0.72 Conditions Reset Unit Normal mW/MHz Idle Table 3. Power Consumption per Peripheral VDD Peripheral 2.0V 3.3V PIO Controller 0.01 0.21 Timer/Counter Channel 0.01 0.23 Timer/Counter Block (3 Channels) 0.02 0.36 USART 0.03 0.48 Unit mW/MHz 3 1391B-01/02 Thermal and Reliability Considerations Thermal Data In Table 4, the device Lifetime is estimated with the MIL-217 standard in the "moderately controlled" environmental model (this model is described as corresponding to an installation in a permanent rack with adequate cooling air), depending on the device Junction Temperature. (For details see the section "Junction Temperature" on page 5.) Note that the user must be extremely cautious with this MTBF calculation: as the MIL-217 model is pessimistic with respect to observed values due to the way the data/models are obtained (test under severe conditions). The life test results that have been measured are always better than the predicted ones. Table 4. MTBF Versus Junction Temperature Junction Temperature (TJ) (C) Estimated Lifetime (MTBF) (Year) 100 32 125 17 150 9 175 6 Table 5 summarizes the thermal resistance data related to the package of interest. Table 5. Thermal Resistance Data Reliability Data Symbol Parameter JA= Junction-to-ambient thermal resistance JC Junction-to-case thermal resistance Condition Package Typ Still Air TQFP100 40 TQFP100 6.4 Unit C/W The number of gates and the device die size are provided for the user to calculate reliability data with another standard and/or in another environmental model. Table 6. Reliability Data 4 Parameter Data Unit Number of Logic Gates 272 K gates Number of Memory Gates 990 K gates Device Die Size 23.2 mm2 AT91M40807 1391B-01/02 AT91M40807 Junction Temperature The average chip-junction temperature TJ in C can be obtained from the following: 1. T J = T A + ( P D x JA ) 2. T J = T A + ( P D x ( HEATSINK + JC ) ) Where: * JA = package thermal resistance, Junction-to-ambient (C/W), provided in Table 5 on page 4. * JC = package thermal resistance, Junction-to-case thermal resistance (C/W), provided in Table 5 on page 4. * HEAT SINK = cooling device thermal resistance (C/W), provided in the device datasheet. * PD = device power consumption (W) estimated from data provided in the section "Power Consumption" on page 3. * TA = ambient temperature (C). From the first equation, the user can derive the estimated lifetime of the chip and thereby decide if a cooling device is necessary or not. If a cooling device is to be fitted on the chip, the second equation should be used to compute the resulting average chip-junction temperature TJ in C. 5 1391B-01/02 Conditions Timing Results The delays are given as typical values in the following conditions: * VDD = 3.3V * Ambient Temperature = 25C * Load Capacitance is 0 pF * The output level change detection is (0.5 x VDD). * The input level is (0.3 x VDD) for a low-level detection and is (0.7 x VDD) for a high level detection. The minimum and maximum values given in the AC characteristic tables of this datasheet take into account the process variation and the design. In order to obtain the timing for other conditions, the following equation should be used: t = T x VDD x ( t DATASHEET + ( C SIGNAL x CSIGNAL ) ) where * T is the derating factor in temperature given in the Figure 1 on page 7. * VDD is the derating factor for the Power Supply given in Figure 2 on page 7. * tdatasheet is the minimum or maximum timing value given in this datasheet for a load capacitance of 0 pF. * CSignal is the capacitance load on the considered output pin.(1) * CSignal is the load derating factor depending on the capacitance load on the related output pins given in Min and Max in this datasheet. The input delays are given as typical value. Note: 6 1. The user must take into account the package capacitance load contribution (CIN) described in Table 1 on page 2. AT91M40807 1391B-01/02 AT91M40807 Temperature Derating Factor Figure 1. Derating Curve for Different Operating Temperatures 1.3 Derating Factor 1.2 1.1 1 0.9 Typ Case Derating Factor is 1 0.8 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 Operating Temperature/deg (C) Figure 2. Derating Curve for Different Core Supply Voltages Derating Factor Voltage Derating Factor 1.70 1.65 1.60 1.55 1.50 1.45 1.40 1.35 1.30 1.25 1.20 1.15 1.10 1.05 1.00 0.95 0.90 Typ Case Derating Factor is 1 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 Supply Voltage (V) Note: This derating factor is applicable only to timings related to output pins. 7 1391B-01/02 Clock Waveforms Table 7. Clock Waveform Parameters Symbol Parameter 1/(tCP) Oscillator Frequency tCP Oscillator Period 26.1 tCH High Half-period 0.45 x tCP 0.55 x tCP ns tCL Low Half-period 0.45 x tCP 0.55 x tCP ns tr MCKI Rising Edge TBD ns tf MCKI Falling Edge TBD ns Note: Conditions Min Max Units 38.3 MHz ns 1. Applicable only for Chip Select programmed with zero wait states. Table 8. Clock Propagation Times Symbol Parameter tCDLH Rising Edge Propagation Time tCDHL Falling Edge Propagation Time Conditions Min Max Units CMCKO = 0 pF 3.8 6.0 ns 0.032 0.05 ns/pF 4.5 7.0 ns 0.033 0.051 ns/pF CMCKO derating CMCKO = 0 pF CMCKO derating Figure 3. Clock Waveform tr tCH 0.7 VDD tf 0.3 VDD MCKI tCL tCP 0.5 VDD MCKO tCDLH 8 0.5 VDD tCDHL AT91M40807 1391B-01/02 AT91M40807 Table 9. NRST to MCKO Symbol Parameter tD NRST Rising Edge to MCKO Valid Time Min Max Units 3(tCP/2) 7(tCP/2) ns Figure 4. MCKO Relative to NRST NRST tD MCKO 9 1391B-01/02 AC Characteristics EBI Signals Relative to MCKI The following tables show timings relative to operating condition limits defined in the section "Conditions" on page 6. See Figure 5 on page 14. Table 10. General-purpose EBI Signals Symbol Parameter EBI1 MCKI Falling to NUB Valid EBI2 MCKI Falling to NLB/A0 Valid EBI3 MCKI Falling to A1 - A23 Valid EBI4 MCKI Falling to Chip Select Change EBI5 NWAIT Setup before MCKI Rising 1.0 ns EBI6 NWAIT Hold after MCKI Rising 3.1 ns 10 Conditions Min Max Units CNUB = 0 pF 4.9 12.5 ns 0.032 0.05 ns/pF 4.2 10.1 ns 0.032 0.051 ns/pF 4.0 11.9 ns 0.032 0.051 ns/pF 4.3 11.8 ns 0.032 0.051 ns/pF CNUB derating CNLB = 0 pF CNLB derating CADD = 0 pF CADD derating CNCS = 0 pF CNCS derating AT91M40807 1391B-01/02 AT91M40807 Table 11. EBI Write Signals Symbol Parameter Conditions Min Max Units MCKI Rising to NWR Active (No Wait States) CNWR = 0 pF 4.0 6.8 ns EBI7 0.033 0.051 ns/pF MCKI Rising to NWR Active (Wait States) 4.7 7.9 ns EBI8 0.033 0.051 ns/pF MCKI Falling to NWR Inactive (No Wait States) 4.3 7.4 ns EBI9 0.032 0.05 ns/pF MCKI Rising to NWR Inactive (Wait States) 4.4 7.5 ns EBI10 0.032 0.05 ns/pF 4.4 12.0 ns EBI11 MCKI Rising to D0 - D15 Out Valid 0.031 0.051 ns/pF 2.8 7.1 ns EBI12 NWR High to NUB Change 0.032 0.05 ns/pF 3.0 5.1 ns EBI13 NWR High to NLB/A0 Change CNLB derating 0.033 0.051 ns/pF 6.9 ns NWR High to A1 - A23 Change CADD = 0 pF 2.8 EBI14 0.033 0.051 ns/pF 2.9 6.6 ns EBI15 NWR High to Chip Select Inactive 0.032 0.051 ns/pF EBI16 Data Out Valid before NWR High (No Wait States) (1) CNWR derating CNWR = 0 pF CNWR derating CNWR = 0 pF CNWR derating CNWR = 0 pF CNWR derating CDATA = 0 pF CDATA derating CNUB = 0 pF CNUB derating CNLB = 0 pF CADD derating CNCS = 0 pF CNCS derating C = 0 pF tCH - 5.2 ns CDATA derating -0.051 ns/pF CNWR derating 0.05 ns/pF n x tCP - 5.1 (2) ns CDATA derating -0.051 ns/pF CNWR derating 0.05 ns/pF 4.8 ns CNWR = 0 pF tCH - 0 ns CNWR derating -0.001 C = 0 pF Data Out Valid before NWR High (Wait States) (1) EBI17 EBI18 Data Out Valid after NWR High EBI19 NWR Minimum Pulse Width (No Wait States) (1) NWR Minimum Pulse Width (Wait States) (1) EBI20 Notes: CNWR = 0 pF CNWR derating n x tCP - 1.0 -0.001 ns/pF (2) ns ns/pF 1. The derating factor is not to be applied to tCH or tCP. 2. n = number of standard Wait States inserted. 11 1391B-01/02 Table 12. EBI Read Signals Symbol Parameter EBI21 MCKI Falling to NRD Active (1) EBI22 MCKI Rising to NRD Active (2) EBI23 MCKI Falling to NRD Inactive (1) EBI24 MCKI Falling to NRD Inactive (2) Max Units CNRD = 0 pF 4.7 10.2 ns 0.033 0.051 ns/pF 3.8 9.6 ns 0.033 0.051 ns/pF 4.6 8.9 ns 0.032 0.05 ns/pF 4.3 6.7 ns 0.032 0.05 ns/pF CNRD = 0 pF CNRD derating CNRD = 0 pF CNRD derating CNRD = 0 pF CNRD derating D0-D15 In Setup before MCKI Falling EBI26 D0-D15 In Hold after MCKI Falling (5) EBI27 NRD High to NUB Change EBI28 NRD High to NLB/A0 Change EBI29 NRD High to A1-A23 Change EBI30 NRD High to Chip Select Inactive EBI31 Data Setup before NRD High (5) EBI32 Data Hold after NRD High (5) (5) CNUB = 0 pF CNUB derating CNLB = 0 pF CNLB derating CADD = 0 pF CADD derating CNCS = 0 pF CNCS derating NRD Minimum Pulse Width (1) (3) NRD Minimum Pulse Width (2) (3) 3.4 ns 3.0 7.1 ns 0.032 0.05 ns/pF 3.0 4.7 ns 0.033 0.051 ns/pF 2.8 6.5 ns 0.033 0.051 ns/pF 2.9 6.3 ns 0.032 0.051 ns/pF ns CNRD derating 0.05 ns/pF CNRD = 0 pF -2.1 ns CNRD = 0 pF CNRD = 0 pF CNRD derating 1. 2. 3. 4. 5. ns 7.3 CNRD derating EBI34 -1.0 CNRD = 0 pF CNRD derating EBI33 12 Min CNRD derating EBI25 Notes: Conditions -0.032 (n +1) x tCP - 2.9 ns/pF (4) -0.001 n x tCP + (tCH - 2.9) -0.001 ns ns/pF (4) ns ns/pF Early Read Protocol. Standard Read Protocol. The derating factor is not to be applied to tCH nor tCP. n = number of Wait States inserted. Only one of these two timings needs to be met. AT91M40807 1391B-01/02 AT91M40807 Table 13. EBI Read and Write Control Signals. Capacitance Limitation Symbol Parameter TCPLNRD(1) Master Clock Low Due to NRD Capacitance TCPLNWR(2) Master CLock Low Due to NWR Capacitance Notes: Conditions Min Max Units CNRD = 0 pF 9.8 ns CNRD derating 0.05 ns/pF CNWR = 0 pF 8.5 ns CNWR derating 0.05 ns/pF 1. If this condition is not met, the action depends on the read protocol intended for use. * Early Read Protocol: Programing an additional tDF (Data Float Output Time) cycle. * Standard Read Protocol: Programming an additional tDF Cycle and an additional wait state. 2. Applicable only for chip select programmed with 0 wait state. If this condition is not met, at least one wait state must be programmed. 13 1391B-01/02 Figure 5. EBI Signals Relative to MCKI MCKI EBI4 EBI4 NCS CS EBI3 A1 - A23 EBI5 EBI6 NWAIT EBI1/EBI2 NUB/NLB/A0 EBI21 EBI23 EBI27-30 EBI33 NRD(1) EBI24 EBI22 EBI34 NRD(2) EBI32 EBI31 EBI25 EBI26 D0 - D15 Read EBI9 EBI7 EBI12-15 EBI19 NWR (No Wait States) EBI8 EBI10 EBI20 NWR (Wait States) EBI17 EBI11 EBI16 EBI18 EBI18 D0 - D15 to Write No Wait Notes: 14 Wait 1. Early Read Protocol. 2. Standard Read Protocol. AT91M40807 1391B-01/02 AT91M40807 Peripheral Signals Relative to MCKI USART Signals The inputs have to meet the minimum pulse width and period constraints as shown in Table 14 and Table 15, and represented in Figure 6. Table 14. USART Input Minimum Pulse Width Symbol Parameter US1 SCK/RXD Minimum Pulse Width Min Pulse Width Units 5(tCP/2) ns Min Input Period Units 9(tCP/2) ns Table 15. USART Minimum Input Period Symbol Parameter US2 SCK Minimum Input Period Figure 6. USART Signals US1 RXD US2 US1 SCK 15 1391B-01/02 Timer/Counter Signals Due to internal synchronization of input signals, there is a delay between an input event and a corresponding output event. This delay is 3(tCP) in Waveform Event Detection mode and 4(tCP) in Waveform Total-count Detection mode. The inputs have to meet the minimum pulse width and minimum input period shown in Table 16 and Table 17, and as represented in Figure 7. Table 16. Timer Input Minimum Pulse Width Symbol Parameter TC1 TCLK/TIOA/TIOB Minimum Pulse Width Min Pulse Width Units 3(tCP/2) ns Min Input Period Units 5(tCP/2) ns Table 17. Timer Input Minimum Input Period Symbol Parameter TC2 TCLK/TIOA/TIOB Minimum Input Period Figure 7. Timer Input 3(tCP /2) TC2 3(tCP /2) MCKI TC1 TIOA/ TIOB/ TCLK Reset Signals A minimum pulse width is necessary, as shown in Table 18 and as represented in Figure 8. Table 18. Reset Minimum Pulse Width Symbol Parameter RST1 NRST Minimum Pulse Width Min Pulse Width Units 10(tCP) ns Figure 8. Reset Signal RST1 NRST Only the NRST rising edge is synchronized with MCKI. The falling edge is asynchronous. 16 AT91M40807 1391B-01/02 AT91M40807 Advanced Interrupt Controller Signals Inputs have to meet the minimum pulse width and minimum input period shown in Table 19 and Table 20 and represented in Figure 9. Table 19. AIC Input Minimum Pulse Width Symbol Parameter AIC1 FIQ/IRQ0/IRQ1/IRQ2/IRQ3 Minimum Pulse Width Min Pulse Width Units 3(tCP/2) ns Min Input Period Units 5(tCP/2) ns Table 20. AIC Input Minimum Input Period Symbol Parameter AIC2 AIC Minimum Input Period Figure 9. AIC Signals AIC2 MCKI AIC1 0/IRQ1/IRQ2/IRQ3 Input Parallel I/O Signals The inputs have to meet the minimum pulse width shown in Table 21 and represented in Figure 10. Table 21. PIO Input Minimum Pulse Width Symbol Parameter PIO1 PIO Input Minimum Pulse Width Min Pulse Width Units 3(tCP/2) ns Figure 10. PIO Signal PIO1 PIO Inputs 17 1391B-01/02 ICE Interface Signals Table 22. ICE Interface Timing Specifications Symbol Parameter Conditions Min ICE0 NTRST Minimum Pulse Width 18.8 ns ICE1 NTRST High Recovery to TCK High 1.2 ns ICE2 NTRST High Removal from TCK High -0.2 ns ICE3 TCK Low Half-period 41.7 ns ICE4 TCK High Half-period 40.9 ns ICE5 TCK Period 82.5 ns ICE6 TDI, TMS, Setup before TCK High 0.2 ns ICE7 TDI, TMS, Hold after TCK High 0.9 ns 5.6 ns ICE8 TDO Hold Time 0 ns/pF ICE9 TCK Low to TDO Valid CTDO = 0 pF CTDO derating Max Units CTDO = 0 pF 10.9 ns CTDO derating 0.05 ns/pF Figure 11. ICE Interface Signal ICE0 NTRST ICE1 ICE2 ICE5 TCK ICE3 ICE4 TMS/TDI ICE6 ICE7 TDO ICE8 ICE9 18 AT91M40807 1391B-01/02 Atmel Headquarters Atmel Operations Corporate Headquarters Memory 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 487-2600 Europe Atmel SarL Route des Arsenaux 41 Casa Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500 Asia Atmel Asia, Ltd. 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