ST7536CFNTR - STMicroelectronics - Datasheet.Directory

ST7536

POWER LINE MODEM

November 1998

.HALFDUPLEX SYNCHRONOUS FSK MODEM

- TWO PROGRAMMABLE CHANNELS FOR

600BPSDATARATE

- TWO PROGRAMMABLE CHANNELS FOR

1200BPSDATARATE

.AUTOMATICALLYTUNEDRxANDTxFILTERS

.TX CARRIER FREQUENCIES SYNTHESIZED

FROMEXTERNAL CRYSTAL

.LOW DISTORTION Tx SIGNAL(S/H2 ≥50dB)

.AUTOMATICLEVELCONTROLONTxSIGNAL

.Rx SENSITIVITY: 2mVRMS (600bps)

3mVRMS (1200bps)

.Rx CLOCKRECOVERY

.POWER-DOWN MODE

.SUITABLETO APPLICATIONIN ACCORDANCE

WITH DH028/29 ENEL, EN50065-1 CENELEC

ANDFCCSPECIFICATIONS

DESCRIPTION

The ST7536 is a half duplex synchronous FSK

MODEM designed for power line communication

networkapplications.

It operatesfrom a dualpowersupply +5V and -5V,

and requires an external interfacefor the coupling

to the powerline. It offerstwoprogrammable data

ratewith two programmablechannels each.

PLCC28

(Plastic Leaded Chip Carrier Package)

ORDER CODE : ST7536CFN

Rx/Tx

11 19

VDD

DVSS

DVDD

ATO

ALCI

TxFI

RxFO

RAI

AGND

DEMI

IFO

AFCF

BRS

CHS

RESET

TEST4

TEST3

TEST2

TEST1

CLR/T

RxD

RxDEM

DGND

TxD

XTAL2

XTAL1

7536-01.EPS

PIN CONNECTIONS

1/9

PIN DESCRIPTION

Number Name Type Description

1 Rx/Tx Digital Rx or Tx mode selection input

2 RESET Digital Logic reset and power-down mode input. Active when low.

3 TEST4 Digital Testinput whichselects the Tx band-pass filterinput (TxFI)when high.

4 TEST3 Digital Testinput which gives an access to theclock recovery input stage. This input is selected

when TEST1 ishigh.

5 RxD Digital Synchronous receive data output

6 CLR/T Digital Rx or Tx clock according to the functional mode

7 RxDEM Digital Demodulated data output

8 DGND Supply Digital ground

9DV

DD Supply Digital positive supply voltage: 5V ±5%

10 TEST1 Digital Test input which cancels the Tx to Rx mode automatic switching and validates TEST3

input. Active when high.

11 TEST2 Digital Testinput which reduces the Tx to Rxmode automaticswitching time. Active when high.

12 TxD Digital Transmitdata input

13 XTAL2 Digital Crystal oscillator output

14 XTAL1 Digital Crystal oscillator input

15 CHS Digital Channel selection input

16 BRS Digital Baud rate selection input

17 AFCF Analog Automatic frequency control output for connecting compensation network.

18 DVSS Supply Digital negative supply voltage : -5V ±5%

19 IFO Analog Intermediate frequency filter output

20 DEMI Analog FSK demodulator input

21 AVSS Supply Analog negative supplyvoltage :-5V ±5%

22 AGND Supply Analog ground : 0V

23 AVDD Supply Analog positive supply voltage : 5V ± 5%

24 RAI Analog Receive analog input

25 RxFO Analog Receive filter output

26 TxFI Analog Transmitfilter input (selected when TEST4 ishigh)

27 ALCI Analog Automatic level control input

28 ATO Analog Analogtransmit output

7536-01.TBL

ST7536

2/9

POST-DEMO

S.C. FILTER CORRELATOR

18 23

TEST

LOGIC

REFERENCE

VOLTAGE

CLOCK

RECOVERY

FSK

MODULATOR

20dB

GAIN

AFC

ALC

TIME BASEAND

CONTROLLOGIC 2

FSK DEMODULATOR

IFO

XTAL2

XTAL1

Rx/Tx

RESET

BRS

CHS

TxD

TxFI

DEMI

RAI

AFCF

ATO

ALCI

RxDEM

RxD

CLR/T

TEST1

TEST2

TEST3

TEST4

RxFO DGND AGND

DVDD AVSS

DVSS

RX BAND-PASS

S.C. FILTER

SMT. FILTER

A.A. FILTER

I.F. BAND-PASS

S.C. FILTER

SMT. FILTER

A.A. FILTER

AVDD

TX BAND-PASS

S.C. FILTER

A.A. FILTER

MUX

4ST7536

7536-02.EPS

BLOCKDIAGRAM

ST7536

3/9

FUNCTIONAL DESCRIPTION

1 - TransmitSection

The transmitmode isset whenRx/Tx = 0, ifRx/Tx

isheldat0longerthan3s, thenthedeviceswitches

automatically in the Rx mode. A new activation of

the Txmode requiresRx/Tx to bereturnedto 1 for

a minimum2µs periodbefore being set to 0.

The Transmit Data (TxD)is sampled on a positive

edgeofCLR/Twhich deliversthe transmitbit clock

when the transmit mode is selected. This data

entersa FSKmodulatorwhose twobasicfrequen-

cies are selected by the Baud Rate Selection pin

(BRS) and the Channel Selection pin (CHS) ac-

cordingto the Table1.

CLR/T

TxD DATA VALID

7536-03.EPS

Figure 1 : Tx Data Input Timing

Table1

BRS CHS Baud Rate

(Baud) Tx Frequencies (kHz)

TxD=1 - TxD=0

0 0 600 81.75 - 82.35

0 1 600 67.2 - 67.8

1 0 1200 71.4 - 72.6

1 1 1200 85.95 - 87.15

These frequencies are synthesized from a

11.0592MHzcrystaloscillator; theirprecisionisthe

same as the crystal one’s (100 ppm).

ThemodulatedsignalcomingoutoftheFSKmodu-

lator is filtered by a switched-capacitorband-pass

filter (Tx band-pass) in order to limit the output

spectrumandto reducethe levelofharmoniccom-

ponents.

The output stage of the Tx path consists of an

AutomaticLevelControl(ALC)systemwhich keeps

the output signal (ATO) amplitude independantof

thelineimpedancevariations.ThisALCisa variable

gain system(with 32 discrete values)controlled by

ananalogfeed-backsignalALCI (seeFigure 2).

The ALC gain range is 0dB to -26dB and gain

change is clocked at 7200Hz. Gain steps are of

magnitude0.84dBtypically.

Aperiod of this clock is decomposedinto a 34.7µs

gain settlinglatency and a 104.2µs peakdetecting

time. The gain change is related to the result of a

peak detection obtained by making a direct com-

parison of ALCI maximum value (during detecting

time)with two thresholdvoltagesVT1 andVT2 (see

Figure2).

- max (VALCI) < VT1 - The next gain is increased

by 0.84dB,

-V

T1 ≤max(VALCI) ≤VT2 - No gain change,

-V

T2 < max (VALCI) - The next gain is decreased

by 0.84dB.

Amplitude

modification

due to an

external cause

High Gain

Low Gain Correct Gain Correct

Gain

latency 34.7µs

Gain setting

Peak detecting

time 104.2µs

VT2

VT1

ALCI SIGNAL ENVELOP

ALCCLOCK

7536-04.EPS

Figure 2 : AutomaticLevel Control Timing Chart

ST7536

4/9

2 - Receive Section

Thereceive section is active when Rx/Tx = 1.

The baud rate and channel selectionis also made

according to Table 1.

The Rx signal is applied on RAI with a common

mode voltage of 0V and filtered by a band-pass

switched capacitor filter (Rx band-pass) centered

onthereceivedcarrierfrequencyand whoseband-

width is around 6kHz. The input voltage range on

RAI is 2mVRMS -2V

RMS.

TheRxfilteroutputisamplifiedbya20dBgainstage

whichprovidessymmetricallimitationsforlargevolt-

age. The resulting signal is down-converted by a

mixer which receives a local oscillator synthesized

bytheFSKmodulatorblock.Finallyanintermediate

frequency band-pass filter (IF band-pass) whose

central frequency is 2.7kHz when BRS = 0 and

5.4kHzwhen BRS = 1 improvesthe signalto noise

ratio before entering the FSK demodulator. The

couplingof theintermediatefrequencyfilter output

(IFO)totheFSKdemodulatorinput(DEMI)ismade

byanexternalcapacitorC5(1µF±10%,10V)which

cancelsthe Rx path offsetvoltage.

A clock recovery circuit extracts the receive clock

(CLR/T) from the demodulated output (RxDEM)

and delivers synchronousdata (RxD) on the posi-

tiveedge of CLR/T.

FUNCTIONAL DESCRIPTION(continued)

3 - Additional Digital and Analog Functions

Areset intput (RESET) initializesthe device.

When RESET = 0, the device is in power-down

mode and all the internal logic is reset. When

RESET= 1, the device is active.

A time base section delivers all the internalclocks

from a crystal oscillator (11.0592MHz).The crystal

isconnectedbetweenXTAL1andXTAL2 pins and

needs twoexternalcapacitorsC3 and C4 depend-

ing on the crystal characteristic typically

22pF ±10%for properoperation.It isalso possible

to provide directly the clock on pin XTAL1 ; in this

caseC3 and C4 should be removed.

An Automatic Frequency Control (AFC) Section

adjusts the central frequency of Rx and Tx band-

pass filter to the carrier central frequency. The

stability of the AFC loop is ensured by an external

compensationnetworkC1(470nF±10%,10V), C2

CLR/T

RxD DATA VALID

7536-05.EPS

Figure 3 : RxDataOutputTiming

(47nF±10%,10V)and R1 (1.5kΩ±5%) connected

topin AFCF.

17 C1

AFCF AGND

7536-06.EPS

Figure 4 : AutomaticFrequencyLoop Filter

4 - Testing Features

- Anadditionnalamplifierallowstheobservationof

the Rx band-pass filter outputon pin RxFO.

- A direct input to the Tx band-passfilter (TxFI) is

availableand selected when TEST4 = 1.

- The 3 second normal duration of the Tx to Rx

mode automaticswitching is reducedto 1.48ms

when TEST2 = 1.

- When TEST1 = 1 the Tx to Rx mode automatic

switchingis desactivatedandthefunctionalmode

ofthecircuitiscontrolledbyRx/Txasfollow:when

Rx/Tx = 0 the circuit is transmitting continuously,

whenRx/Tx= 1theclockrecoveryblockisdiscon-

nectedfromtheFSK demodulatorfortestingpur-

pose,inthisconfigurationTEST3isthedatainput

oftheclockrecoveryblock,RxDEMfollowTEST3

andRxD deliverstheresynchronizeddata.

5 - PowerSupplies Wiring and Decoupling

Precautions

The ST7536 has two positive power supply pins,

two negative power supply pins and two ground

pinsinordertoseparateinternalanaloganddigital

supplies.The analog and digital terminals of each

supply pair must be connectedtogetherexternally

and require special routing precautionsin order to

get the best receivesensitivity performances.

The three major routing requirementsare :

- The ground impedance should be as low as

possible, for this purpose the AGND an DGND

terminalscan be connectedvia a local plane.

- Thepositiveandnegativepowersupplies(AVDD,

DVDD,AV

SS,DV

SS) should be star-connected,

avoidingcommoncurrent pathfor the digitaland

analog powersupplies terminals.

- Five decoupling capacitors located as close as

possibleto thepowersupplyterminalsshouldbe

used. Two 2.2µF tantalum and two 100nF ce-

ramic capacitors perform the main decoupling

function in the vicinity of the analog power sup-

pliesanda100nFceramiccapacitorinthevicinity

of the positive digital power supply is used to

reduce the high frequency perturbations gener-

ated by the logic part of the circuit.

ST7536

5/9

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

AVDD/DVDD Positive Supply Voltage (1) -0.3, +7 V

AVSS/DVSS Negative Supply Voltage (1) -7, +0.3 V

VAGND/DGND Voltage between AGND and DGND -0.3, +0.3 V

VIDigital Input Voltage DGND-0.3, DVDD+0.3 V

VODigital Output Voltage DGND-0.3, DVDD+0.3 V

IODigital Output Current -5, +5 mA

ViAnalog Input Voltage AVSS-0.3, AVDD+0.3 V

VoAnalog Output Voltage AVSS-0.3, AVDD+0.3 V

IoAnalog Output Current -5, +5 mA

PDPower Dissipation 500 mW

Toper Operating Temperature - 25, + 70 oC

Tstg Storage Temperature - 65, + 150 oC

Notes : 1. The voltages are referenced to AGND andDGND.

2. Latch-up problems can be overcome with 2 reverse biased schottky diodes connectedrespectively between A/DVDD & A/DGND

andA/DVSS &A/DGND.

3. Absolutemaximum ratings are values beyondwhich damage todevice may occur.Functional operationunder theseconditions is

not implied.

7536-02.TBL

GENERAL ELECTRICAL CHARACTERISTICS

Thetest conditionsare A/DVDD = +5V,A/DVSS = -5V,A/DGND = 0V,

Tamb = -10to 70oC unless otherwisespecified

Symbol Parameter Test Conditions Min. Typ. Max. Unit

AVDD/DVDD Positive Supply Voltage 4.75 5 5.25 V

AVSS/DVSS Negative Supply Voltage -5.25 -5 -4.75 V

AIDD +DI

DD Positive Supply Current in Tx Mode RESET = 1, RX/Tx = 0 30 35 mA

AIDD +DI

DD Positive Supply Current in Rx Mode RESET = 1, RX/Tx = 1 29 34 mA

AISS +DI

SS Negative Supply Current in Tx Mode RESET = 1, RX/Tx = 0 - 34 - 29 mA

AISS +DI

SS Negative Supply Current in Rx Mode RESET = 1, RX/Tx = 1 - 33 - 28 mA

AIDD +DI

DD Positive Power-down Current RESET = 0, RX/Tx = 1

XTAL1= 1 1.2 mA

AISS +DI

SS Negative Power-down Current - 1.2 mA

VIH High LevelInput Voltage Digital inputs except XTAL1 2.2 V

VIL Low Level Input Voltage Digital inputs 0.8 V

VOH High LevelOutput Voltage Digital outputs, IOH = - 400µA 2.4 V

VOL Low Level Output Voltage Digital outputs, IOL = 1.6mA 0.4 V

VIH High LevelInput Voltage XTAL1input 3.6 V

DC XTAL1 Clock Duty Cycle External clock 40 60 %

7536-03.TBL

ST7536

6/9

TRANSMITTER ELECTRICAL CHARACTERISTICS

Thetest conditionsare A/DVDD = +5V,A/DGND= 0V,A/DVSS =-5V,

Tamb = -10to +70oC unless othewisespecified

Symbol Parameter Test Conditions Min. Typ. Max. Unit

VTAC Max Carrier Output ACVoltage RL=2kΩ,V

ALCI <V

T1 2.8 3.2 3.7 VPP

HD2 Second Harmonic Distortion RL=2kΩ,V

ALCI <V

T1 0.32 %

FD FSK Peak-to-peak Deviation BRS = 0

BRS = 1 600

1200 Hz

TRxTx CarrierActivation Time After Rx/Tx 1 →0 transition 1 ms

TALC Carrier Stabilisation Time ALC maximum settlingtime, 32 gain steps 5 ms

DRNG ALC Dynamic Range 25 26 27 dB

VT1 ALC Low Threshold Voltage 1.81 1.87 V

VT2 ALC High Threshold Voltage 2.12 2.18 V

GST ALC Gain Step 0.84 dB

PSRR1

PSRR2 Power supply rejection ratio on ATO

(see Note 1) VIN = 200mVPP,f

IN = 50Hz on VDD or VSS 35

10 dB

Note 1 : This characteristic is guaranteed by correlation.

7536-04.TBL

RECEIVERELECTRICAL CHARACTERISTICS

Thetest conditionsare A/DVDD = +5V,A/DGND= 0V,A/DVSS =-5V,

Tamb = -10to +70oC unless othewisespecified

Symbol Parameter Test Conditions Min. Typ. Max. Unit

VIN Maximum Input Signal 2V

RMS

RIN Input Impedance 100 kΩ

RCJ Recovered Clock Jitter Percentage of the nominal clock - 5 + 5 %

PSRR1

PSRR2 Power supply rejection ratio on

RxFO (see Note 1) VIN = 200mVPP,f

IN = 50Hz on VDD or VSS 35

10 dB

VIN0

VIN1

Rx sensitivity (see Note 1) Typical measured BER < 10-5

BRS = 0

BRS = 1 2

mVRMS

BER1

BER2

Bit error rate at minimum Rx

signal (seeNote 1) White Noise, S/N = 15dB

RAI = 2mVRMS, BRS = 0

RAI = 3mVRMS, BRS = 1 2⋅10-5

3⋅10-4 10-3

10-3

BER3 Bit error rateat maximum Rx sig-

nal (see Note 1) RAI = 2VRMS, White Noise, S/N =25dB 10-7 10-3

BER4 Bit error rate at medium Rx signal

(see Note 1) RAI= 0.6VRMS, S/N= 15dB 10-6 10-3

BER5 Bit error rate with impulsive noise

(see Note 1) RAI = 90mVRMS,N=5V

PP pulsewave,

f = 100Hz, duty cycle = 10% 10-3

BER6

BER7

Bit error rate with modulated

sinusoidal noise Ns (see Note 1) S+ Ns < 0.2VRMS, Ns = sinecarrier with

80% AM modul.,fm= 1kHz, See Figure 5

Smin = 2mVRMS, BRS = 0

Smin = 3mVRMS, BRS = 1 10-3

10-3

Note 1 : This characteristic is guaranteed by correlation

7536-05.TBL

ST7536

7/9

-10

-20

-30

-40

-500 0.5 1 1.5 2

Frequency (f/fc)

B = 20kHzat 600 Bit/s (BRS = 0)

B = 40kHz at 1200 Bit/s-BRS = 1) fc : Central Carrier Frequency

S/N (dB)

7536-07.EPS

Figure 5 : S/N Maskfor 80% AM Sine Noise

FILTER TEMPLATES

Frequency

(kHz) Test

Conditions Amplitude (dB)

Min. Typ. Max.

RECEIVE AND TRANSMIT FILTER

BRS = 0,

CHS = 0

-35

79.05 - 4 - 3 - 2

Ref 82.05 0

85.05 - 4 - 3 - 2

123 - 35

44.4

BRS = 0,

CHS = 1

-35

65 -4 -3 -2

Ref 67.46 0

69.93 - 4 - 3 - 2

101.13 - 35

47.57

BRS = 1,

CHS = 0

-35

69.64 - 4 - 3 - 2

Ref 72.28 0

74.92 - 4 - 3 - 2

108.36 - 35

57.08

BRS = 1,

CHS = 1

-35

83.57 - 4 - 3 - 2

Ref 86.74 0

89.91 - 4 - 3 - 2

130.03 - 35

Frequency

(kHz) Test

Conditions Amplitude (dB)

Min. Typ. Max.

INTERMEDIATEFREQUENCY FILTER

1.2

BRS = 0

-35

2.15 - 5 - 3 - 2

Ref 2.7 0

3.25 - 5 - 3 - 2

5.8 - 35

2.4

BRS = 1

-35

4.3 -5 -3 -2

Ref 5.4 0

6.5 -5 -3 -2

11.6 - 35

7536-06.TBL

ST7536

8/9

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consequences of use of such information nor for any infringement of patents or other rights of third parties whichmay result from

its use. No licence is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications

mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information

previouslysupplied. STMicroelectronics productsare not authorizedfor useas criticalcomponentsin lifesupport devicesor systems

without express written approval of STMicroelectronics.

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Purchase of I2C Components of STMicroelectronics, conveys a licenseunder the PhilipsI2C Patent.

Rights to use these components in a I2C system,is granted provided that the system conforms to

the I2C StandardSpecifications as defined by Philips.

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PMPLCC28.EPS

PACKAGE MECHANICAL DATA

28 PINS - PLASTICLEADED CHIP CARRIER (PLCC)

Dimensions Millimeters Inches

Min. Typ. Max. Min. Typ. Max.

A 12.32 12.57 0.485 0.495

B 11.43 11.58 0.450 0.456

D 4.2 4.57 0.165 0.180

D1 2.29 3.04 0.090 0.120

D2 0.51 0.020

E 9.91 10.92 0.390 0.430

e 1.27 0.050

e3 7.62 0.300

F 0.46 0.018

F1 0.71 0.028

G 0.101 0.004

M 1.24 0.049

M1 1.143 0.045

PLCC28.TBL

ST7536

9/9