Isolated Sigma-Delta Modulator
Data Sheet
AD7401A
Rev. D Document Feedback
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FEATURES
20 MHz maximum external clock rate
Second-order modulator
16 bits, no missing codes
±2 LSB INL typical at 16 bits
1 µV/°C typical offset drift
On-board digital isolator
On-board reference
±250 mV analog input range
Low power operation: 17 mA typical at 5.5 V
−40°C to +125°C operating range
16-lead SOIC package
Internal clock version: AD7400A
Safety and regulatory approvals
UL recognition
5000 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice #5A
VDE Certificate of Conformity
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 891 V peak
Qualified for Automotive Applications
APPLICATIONS
AC motor controls
Shunt current monitoring
Data acquisition systems
Analog-to-digital and opto-isolator replacements
GENERAL DESCRIPTION
The AD7401A1 is a second-order, sigma-delta (Σ-Δ) modulator
that converts an analog input signal into a high speed, 1-bit data
stream with on-chip digital isolation based on the Analog
Devices, Inc., iCoupler® technology. The AD7401A operates
from a 5 V power supply and accepts a pseudo-differential input
signal of ±250 mV (±320 mV full scale). The analog input is
continuously sampled by the analog modulator, eliminating the
need for external sample-and-hold circuitry. The input
information is contained in the output stream as a density of
ones with a data rate of up to 20 MHz. The original information
can be reconstructed with an appropriate digital filter. The
serial I/O can use a 5 V or a 3.3 V supply (VDD2).
The serial interface is digitally isolated. High speed CMOS,
combined with Analog Devices, Inc., iCoupler® technology ,
means the on-chip isolation provides outstanding performance
characteristics, superior to alternatives such as optocoupler
devices. The device contains an on-chip reference. The
AD7401A is offered in a 16-lead SOIC and has an operating
temperature range of −40°C to +125°C.
FUNCTIONAL BLOCK DIAGRAM
VIN+
VDD1 VDD2
VIN–Σ-Δ ADC
CONTROL LOGIC
AD7401A
BUF
T/H
REF
WATCHDOG
GND1GND2
MDAT
MCLKIN
DECODE
ENCODE DECODE
ENCODE
UPDATE
WATCHDOG
UPDATE
07332-001
Figure 1.
1 Protected by U.S. Patents 5,952,849; 6,873,065; and 7,075,329. Other patents pending.
AD7401A Data Sheet
Rev. D | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Timing Specifications .................................................................. 5
Insulation and Safety-Related Specifications ............................ 6
Regulatory Information ............................................................... 6
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 Insulation
Characteristics .............................................................................. 7
Absolute Maximum Ratings ............................................................ 8
ESD Caution .................................................................................. 8
Pin Configuration and Function Descriptions ............................. 9
Typical Performance Characteristics ........................................... 10
Terminology .................................................................................... 13
Theory of Operation ...................................................................... 14
Circuit Information .................................................................... 14
Analog Input ............................................................................... 14
Differential Inputs ...................................................................... 15
Current Sensing Applications ................................................... 15
Voltage Sensing Applications .................................................... 15
Digital Filter ................................................................................ 16
Applications Information .............................................................. 18
Grounding and Layout .............................................................. 18
Evaluating the AD7401A Performance ................................... 18
Insulation Lifetime ..................................................................... 18
Outline Dimensions ....................................................................... 19
Ordering Guide .......................................................................... 19
Automotive Product ................................................................... 19
REVISION HISTORY
1/2018—Rev. C to Rev. D
Changes to Features and General Description ............................. 1
Change to Power Dissipation Parameter, Table 1 ......................... 4
Changes to Table 3 and Table 4 ....................................................... 6
Changes to Absolute Maximum Rating Section ........................... 8
Changes to Table 8 ............................................................................ 9
Changes to Terminology Section.................................................. 13
Changes to Ordering Guide .......................................................... 19
Added Automotive Product Section ............................................ 19
7/2011—Rev. B to Rev. C
Changes to Minimum External Air Gap (Clearance) Parameter,
Table 3 and Minimum External Tracking (Creepage) Parameter,
Table 3 ................................................................................................ 6
Changes to Figure 5; Pin 1 Description, Table 8; and Pin 7
Description, Table 8 .......................................................................... 9
3/2011—Rev. A to Rev. B
Change to General Description Section ........................................ 1
Changes to Table 1 ............................................................................ 3
1/2011—Rev. 0 to Rev. A
Change to Features, UL Recognition Value ................................... 1
Change to Table 3, Input-to-Output Momentary Withstand
Voltage Value .................................................................................................. 6
Changes to Table 4, Isolation Voltage Value, and Endnote 1 ....... 6
7/2008—Revision 0: Initial Version
Data Sheet AD7401A
Rev. D | Page 3 of 20
SPECIFICATIONS
VDD1 = 4.5 V to 5.5 V, V DD2 = 3 V to 5.5 V, VIN+ = −200 mV to +200 mV, and VIN− = 0 V (single-ended); TA = −40°C to +125°C, fMCLKIN =
16 MHz maximum,1 tested with sinc3 filter, 256 decimation rate, as defined by Verilog code, unless otherwise noted.
Table 1.
Parameter
Y Version1, 2
Unit Test Conditions/Comments
Min Typ Max
STATIC PERFORMANCE
Resolution 16 Bits Filter output truncated to 16 bits
Integral Nonlinearity (INL)3 ±1.5 ±7 LSB VIN+ = ±200 mV, TA = −40°C to +85°C, fMCLKIN = 20 MHz max1
±2
±13
LSB
VIN+ = ±250 mV, TA = −40°C to +85°C, fMCLKIN = 20 MHz max1
±1.5 ±11 LSB VIN+ = ±200 mV, TA = −40°C to +125°C, fMCLKIN = 20 MHz max1
±2 ±46 LSB VIN+ = ±250 mV, TA = −40°C to +125°C, fMCLKIN = 20 MHz max1
Differential Nonlinearity (DNL)3 ±0.9 LSB Guaranteed no missed codes to 16 bits,
fMCLKIN = 20 MHz max,1 VIN+ = −250 mV to +250 mV
Offset Error3 ±.025 ±0.5 mV fMCLKIN = 20 MHz max,1 VIN+ = −250 mV to +250 mV
Offset Drift vs. Temperature3 1 3.5 µV/°C
Offset Drift vs. VDD13 120 µV/V
Gain Error3
0.07
±1.5
mV
±1 mV fMCLKIN = 20 MHz max,1 VIN+ = −250 mV to +250 mV
Gain Error Drift vs. Temperature3 23 µV/°C
Gain Error Drift vs. VDD13 110 µV/V
ANALOG INPUT
Input Voltage Range ±200 ±250 mV For specified performance; full range ±320 mV
Dynamic Input Current ±13 ±18 µA VIN+ = 500 mV, VIN− = 0 V, fMCLKIN = 20 MHz max1
±10 ±15 µA VIN+ = 400 mV, VIN− = 0 V, fMCLKIN = 20 MHz max1
0.08 µA VIN+ = 0 V, VIN− = 0 V, fMCLKIN = 20 MHz max1
DC Leakage Current ±0.01 ±0.6 µA
Input Capacitance 10 pF
DYNAMIC SPECIFICATIONS VIN+ = 5 kHz
Signal-to-(Noise + Distortion) Ratio (SINAD)3 76 82 dB VIN+ = ±200 mV, TA = −40°C to +85°C,
fMCLKIN = 5 MHz to 20 MHz1
71
82
dB
V
IN
+ = ±250 mV, T
A
= −40°C to +85°C,
fMCLKIN = 5 MHz to 20 MHz1
72 82 dB VIN+ = ±200 mV, TA = −40°C to +125°C,
fMCLKIN = 5 MHz to 20 MHz1
82 dB VIN+ = ±250 mV, TA = −40°C to +125°C,
fMCLKIN = 5 MHz to 20 MHz1
Signal-to-Noise Ratio (SNR)3 81 83 dB VIN+ = ±250 mV, TA = −40°C to +125°C,
fMCLKIN = 5 MHz to 20 MHz1
80 82 dB VIN+ = ±200 mV, TA = −40°C to +125°C,
fMCLKIN = 5 MHz to 20 MHz1
Total Harmonic Distortion (THD)3
−90
dB
fMCLKIN = 20 MHz max1, VIN+ = −250 mV to +250 mV
Peak Harmonic or Spurious Noise (SFDR)3 −92 dB
Effective Number of Bits (ENOB)3 12.3 13.3 Bits
Isolation Transient Immunity3 25 30 kV/µs
LOGIC INPUTS
Input High Voltage, VIH 0.8 × VDD2 V
Input Low Voltage, VIL 0.2 × VDD2 V
Input Current, I
IN
±0.5
µA
Floating State Leakage Current 1 µA
Input Capacitance, CIN 4 10 pF
AD7401A Data Sheet
Rev. D | Page 4 of 20
Parameter
Y Version1, 2
Unit Test Conditions/Comments
Min Typ Max
LOGIC OUTPUTS
Output High Voltage, VOH VDD2 − 0.1 V IO = −200 µA
Output Low Voltage, V
OL
0.4
V
I
O
= +200 µA
POWER REQUIREMENTS
VDD1 4.5 5.5 V
V
DD2
3
5.5
V
IDD15 10 12 mA VDD1 = 5.5 V
IDD26 7 9 mA VDD2 = 5.5 V
3 4 mA VDD2 = 3.3 V
POWER DISSIPATION (SEE Figure 17) 93.5 mW VDD1 = VDD2 = 5.5 V
1 For fMCLK > 16 MHz to 20 MHz, mark space ratio is 48/52 to 52/48, VDD1 = VDD2 = 5 V ± 5%, and TA = −40°C to +85°C.
2 All voltages are relative to their respective ground.
3 See the Terminology section.
4 Sample tested during initial release to ensure compliance.
5 See Figure 15.
6 See Figure 17.
Data Sheet AD7401A
Rev. D | Page 5 of 20
TIMING SPECIFICATIONS
VDD1 = 4.5 V to 5.5 V, V DD2 = 3 V to 5.5 V, TA = −40°C to +125°C, unless otherwise noted.
Table 2.
Parameter1 Limit at TMIN, TMAX Unit Description
fMCLKIN2, 3 20 MHz max Master clock input frequency
5 MHz min Master clock input frequency
t14 25 ns max Data access time after MCLKIN rising edge
t24 15 ns min Data hold time after MCLKIN rising edge
t3 0.4 × tMCLKIN ns min Master clock low time
t4 0.4 × tMCLKIN ns min Master clock high time
1 Sample tested during initial release to ensure compliance.
2 Mark space ratio for clock input is 40/60 to 60/40 for fMCLKIN ≤ 16 MHz and 48/52 to 52/48 for 16 MHz < fMCLKIN < 20 MHz.
3 VDD1 = VDD2 = 5 V ± 5% for fMCLKIN > 16 MHz to 20 MHz.
4 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V.
200µAIOL
200µAIOH
1.6V
TO OUTPUT
PIN CL
25pF
07332-002
Figure 2. Load Circuit for Digital Output Timing Specifications
MCLKIN
MDAT
t1t2
t4
t3
07332-003
Figure 3. Data Timing
AD7401A Data Sheet
Rev. D | Page 6 of 20
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 3.
Parameter Symbol Value Unit Conditions
Input-to-Output Momentary Withstand Voltage
V
ISO
5000 min
V
1-minute duration
Minimum External Air Gap (Clearance) L(I01) 7.8 min1, 2 mm Measured from input terminals to output
terminals, shortest distance through air
Minimum External Tracking (Creepage) L(I02) 7.8 min1,2 mm Measured from input terminals to output
terminals, shortest distance path along body
Minimum Internal Gap (Internal Clearance) 0.017 min mm Insulation distance through insulation
Tracking Resistance (Comparative Tracking Index)
CTI
> 400
V
DIN IEC 112/VDE 0303 Part 1
3
Isolation Group II Material Group (DIN VDE 0110, 1/89, Table I)3
1 In accordance with IEC 60950-1 guidelines for the measurement of creepage and clearance distances for a pollution degree of 2 and altitudes ≤2000 m.
2 Consideration must be given to pad layout to ensure the minimum required distance for clearance is maintained.
3 CSA CTI rating is >400 and a Material Group II isolation group.
REGULATORY INFORMATION
Table 4.
UL1 CSA VDE2
Recognized Under 1577
Component Recognition Program1
Approved under CSA Component
Acceptance Notice #5A
Certified according to DIN V VDE V 0884-10
(VDE V 0884-10):2006-122
5000 V rms Isolation Voltage Basic insulation per CSA60950-1-07
and IEC 60950-1, 780 Vrms
maximum working voltage.
Reinforced insulation per DIN V VDE V 0884-10 (VDE V
0884-10):2006-12, 891 V peak
Reinforced insulation per
CSA 60950-1-03 and IEC 60950-1,
390 V rms maximum working
voltage
File E214100 File 205078 File 2471900-4880-0001
1 In accordance with UL 1577, each AD7401A is proof tested by applying an insulation test voltage ≥ 6000 V rms for 1 second (current leakage detection limit = 15 µA).
2 In accordance with DIN V VDE V 0884-10, each AD7401A is proof tested by applying an insulation test voltage ≥1671V peak for 1 sec (partial discharge detection limit = 5 pC).
Data Sheet AD7401A
Rev. D | Page 7 of 20
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 INSULATION CHARACTERISTICS
This isolator is suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by
means of protective circuits.
Table 5.
Description Symbol Characteristic Unit
INSTALLATION CLASSIFICATION PER DIN VDE 0110
For Rated Mains Voltage ≤ 300 V rms I to IV
For Rated Mains Voltage ≤ 450 V rms I to II
For Rated Mains Voltage ≤ 600 V rms I to II
CLIMATIC CLASSIFICATION 40/105/21
POLLUTION DEGREE (DIN VDE 0110, TABLE 1) 2
MAXIMUM WORKING INSULATION VOLTAGE VIORM 891 V peak
INPUT-TO-OUTPUT TEST VOLTAGE, METHOD B1
VIORM × 1.875 = VPR, 100% Production Test, tm = 1 sec, Partial Discharge < 5 pC VPR 1671 V peak
INPUT-TO-OUTPUT TEST VOLTAGE, METHOD A VPR
After Environmental Test Subgroup 1 1426 V peak
VIORM × 1.6 = VPR, tm = 60 sec, Partial Discharge < 5 pC
After Input and/or Safety Test Subgroup 2/ Safety Test Subgroup 3 1069 V peak
VIORM × 1.2 = VPR, tm = 60 sec, Partial Discharge < 5 pC
HIGHEST ALLOWABLE OVERVOLTAGE (TRANSIENT OVERVOLTAGE, tTR = 10 sec) VTR 6000 V peak
SAFETY-LIMITING VALUES (MAXIMUM VALUE ALLOWED IN THE EVENT OF A FAILURE, SEE Figure 4)
Case Temperature TS 150 °C
Side 1 Current IS1 265 mA
Side 2 Current IS2 335 mA
INSULATION RESISTANCE AT TS, VIO = 500 V RS >109 Ω
CASE TEMPERATURE (°C)
SAFETY-LIMITING CURRENT (mA)
0
0
350
300
250
200
150
100
50
50 100 150 200
SIDE #1
SIDE #2
07332-004
Figure 4. Thermal Derating Curve, Dependence of Safety-Limiting Values
with Case Temperature per DIN V VDE V 0884-10
AD7401A Data Sheet
Rev. D | Page 8 of 20
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted. All voltages are relative to
their respective grounds.
Table 6.
Parameter Rating
VDD1 to GND1 −0.3 V to +6.5 V
VDD2 to GND2 −0.3 V to +6.5 V
Analog Input Voltage to GND1 −0.3 V to VDD1 + 0.3 V
Digital Input Voltage to GND2 −0.3 V to VDD1 + 0.5 V
Output Voltage to GND2 −0.3 V to VDD2 + 0.3 V
Input Current to Any Pin Except Supplies1 ±10 mA
Operating Temperature Range −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
SOIC Package
θJA Thermal Impedance2 89.2°C/W
θJC Thermal Impedance2 55.6°C/W
Resistance (Input to Output), R
I-O
10
12
Ω
Capacitance (Input to Output), CI-O3 1.7 pF typ
Pb-Free Temperature, Soldering
Reflow 260°C
ESD 1.5 kV
1 Transient currents of up to 100 mA do not cause SCR to latch up.
2 EDEC 2S2P standard board.
3 f = 1 MHz.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Table 7. Maximum Continuous Working Voltage1
Parameter Max Unit Constraint
AC Voltage, Bipolar
Waveform
565 V peak 50-year minimum
lifetime
AC Voltage, Unipolar
Waveform
891 V peak Maximum CSA/VDE
approved working
voltage
DC Voltage 891 V Maximum CSA/VDE
approved working
voltage
1 Refers to continuous voltage magnitude imposed across the isolation
barrier. See the Insulation Lifetime section for more details.
ESD CAUTION
Data Sheet AD7401A
Rev. D | Page 9 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
V
DD1 1
V
IN
+
2
V
IN
–
3
NC
4
GND
2
16
NC
15
V
DD2
14
MCLKIN
13
NC
5
NC
12
NC
6
MDAT
11
V
DD1
/NC
7
NC
10
GND
18
GND
2
9
NC = NO CONNECT
AD7401A
TOP VIEW
(Not to Scale)
07332-005
Figure 5. Pin Configuration
Table 8. Pin Function Descriptions
Pin No. Mnemonic Description
1 VDD1 Supply Voltage, 4.5 V to 5.5 V. This is the supply voltage for the isolated side of the AD7401A and is relative to GND1.
2 VIN+ Positive Analog Input. Specified range of ±250 mV.
3 VIN− Negative Analog Input. Normally connected to GND1.
4 to 6, 10,
12, 15
NC No Connect.
7 VDD1/NC Supply Voltage. Supply voltage (VDD1) 4.5 V to 5.5 V. VDD1 is the supply voltage for the isolated side of the AD7401A
and it is relative to GND1.
No Connect (NC). If desired, Pin 7 may be allowed to float. Do not be tie Pin 7 to ground. The AD7401A will
operate normally provided that the supply voltage is applied to Pin 1.
8 GND1 Ground 1. This is the ground reference point for all circuitry on the isolated side.
9, 16 GND2 Ground 2. This is the ground reference point for all circuitry on the nonisolated side.
11 MDAT
Serial Data Output. The single bit modulator output is supplied to this pin as a serial data stream.
The bits are clocked out on the rising edge of the MCLKIN input and valid on the following MCLKIN rising edge.
13 MCLKIN Master Clock Logic Input. 20 MHz maximum. The bit stream from the modulator is valid on the rising edge of MCLKIN.
14 VDD2 Supply Voltage. 3 V to 5.5 V. This is the supply voltage for the nonisolated side and is relative to GND2.
AD7401A Data Sheet
Rev. D | Page 10 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, using 25 kHz brick-wall filter, unless otherwise noted.
100
0
0 1000
SUPPLY RIPPLE FREQUENCY (kHz)
PSRR (dB)
90
80
70
60
50
40
30
20
10
100 200 300 400 500 600 700 800 900
MCLKIN = 10MHz
MCLKIN = 5MHz
MCLKIN = 16MHz
200mV p-p SINE WAVE ON V
DD1
NO DECOUPLING
V
DD1
= V
DD2
= 5V
1MHz CUTOFF FILTER
07332-006
Figure 6. PSRR vs. Supply Ripple Frequency Without Supply Decoupling
–
90
–50
0 10k
INPUT FREQUENCY (Hz)
SINAD (dB)
–85
–80
–75
–70
–65
–60
–55
1k 2k 3k 4k 5k 6k 7k 8k 9k
V
DD1
= V
DD2
= 5 V
V
DD1
= V
DD2
= 5V
MCLKIN = 16MHz
MCLKIN = 5MHz
MCLKIN = 10MHz
07332-007
Figure 7. SINAD vs. Analog Input Frequency
20
–180
030
FREQUENCY (kHz)
(dB)
0
–20
–40
–60
–80
–100
–120
–140
–160
5 10152025
4096 POINT FFT
f
IN = 5kHz
SINAD = 81.984dB
THD = –96.311dB
DECIMATION BY 256
07332-008
Figure 8. Typical FFT (±200 mV Range)
–
90
–50
0.17 0.33
± INPUT AMPLITUDE (V)
SINAD (dB)
–85
–80
–75
–70
–65
–60
–55
0.18 0.19 0.20 0.21 0.22 0.23 0.24 0.25 0.26 0.27 0.28 0.29 0.30 0.31 0.32
MCLKIN = 16MHz
MCLKIN = 10MHz
V
DD1
= V
DD2
= 5V
07332-009
Figure 9. SINAD vs. VIN
0.4
–0.5
0 60k
CODE
DNL ERROR (LSB)
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
10k 20k 30k 40k 50k
V
IN
+ = –200mV TO +200mV
V
IN
– = 0V
07332-010
Figure 10. Typical DNL (±200 mV Range)
0.8
–0.4
060k
CODE
INL ERROR (LSB)
07332-011
0.6
0.4
0.2
0
–0.2
10k 20k 30k 40k 50k
V
IN
+ = –200mV TO +200mV
V
IN
– = 0V
Figure 11. Typical INL (±200 mV Range)
Data Sheet AD7401A
Rev. D | Page 11 of 20
250
–250
–45
TEMPERATURE (°C)
OFFSET (µV)
–35 –25 –15 –5 515 25 35 45 55 65 75 85 95 105
200
150
100
50
0
–50
–100
–150
–200
V
DD1
= V
DD2
= 5V
MCLKIN = 16MHz
V
DD1
= V
DD2
= 4.5V
MCLKIN = 5MHz
V
DD1
= V
DD2
= 4.5V
MCLKIN = 16MHz
V
DD1
= V
DD2
= 4.5V
MCLKIN = 10MHz
V
DD1
= V
DD2
= 5V
MCLKIN = 5MHz
V
DD1
= V
DD2
= 5.25V
MCLKIN = 16MHz
V
DD1
= V
DD2
= 5.25V
MCLKIN = 10MHz
V
DD1
= V
DD2
= 5V
MCLKIN = 10MHz
V
DD1
= V
DD2
= 5.25V
MCLKIN = 5MHz
07332-012
Figure 12. Offset Drift vs. Temperature for Various Supply Voltages
200.5
199.5
–45
TEMPERATURE (°C)
GAIN (mV)
–35 –25 –15 –5 515 25 35 45 55 65 75 85 95 105
200.4
200.3
200.2
200.1
200.0
199.9
199.8
199.7
199.6
V
DD1
= V
DD2
= 5V
MCLKIN = 16MHz
V
DD1
= V
DD2
= 4.5V
MCLKIN = 5MHz
V
DD1
= V
DD2
= 4.5V
MCLKIN = 16MHz
V
DD1
= V
DD2
= 5.25V
MCLKIN = 16MHz
V
DD1
= V
DD2
= 5V
MCLKIN = 10MHz
V
DD1
= V
DD2
= 4.5V
MCLKIN = 10MHz
V
DD1
= V
DD2
= 5V
MCLKIN = 5MHz
V
DD1
= V
DD2
= 5.25V
MCLKIN = 10MHz
V
DD1
= V
DD2
= 5.25V
MCLKIN = 5MHz
07332-013
Figure 13. Gain Error Drift vs. Temperature for Various Supply Voltages
V
IN
DC INPUT VOLTAGE (V)
I
DD1
(A)
–0.33 0.33–0.28 –0.23 –0.18 –0.13 –0.08 –0.03 0.03 0.08 0.13 0.18 0.23 0.28
0.0065
0.0070
0.0075
0.0080
0.0085
0.0090
0.0095
0.0100
0.0105
V
DD1
= V
DD2
= 5V
T
A
= 25°C
MCLKIN = 16MHz
MCLKIN = 10MHz
MCLKIN = 5MHz
07332-014
Figure 14. IDD1 vs. VIN DC Input Voltage
V
IN
DC INPUT VOLTAGE (V)
I
DD1
(A)
–0.33 0.33–0.28 –0.23 –0.18 –0.13 –0.08 –0.03 0.03 0.08 0.13 0.18 0.23 0.28
0.0060
0.0065
0.0070
0.0075
0.0080
0.0085
0.0090
0.0095
0.0100
0.0105
MCLKIN = 16MHz
T
A
= +85°C MCLKIN = 16MHz
T
A
= +105°C
MCLKIN = 16MHz
T
A
= –40°C
MCLKIN = 10MHz
T
A
= –40°C
MCLKIN = 10MHz
T
A
= +105°C
MCLKIN = 10MHz
T
A
= +85°C
MCLKIN = 5MHz
T
A
= +105°C
MCLKIN = 5MHz
T
A
= +85°C
MCLKIN = 5MHz
T
A
= –40°C
V
DD1
= V
DD2
= 5V
07332-015
Figure 15. IDD1 vs. VIN at Various Temperatures
V
IN
DC INPUT VOLTAGE (V)
I
DD2
(A)
–0.325 –0.225 –0.125 –0.025 0.075 0.175
0.325–0.275 –0.175 –0.075 0.025 0.125 0.225
0.275
0.0020
0.0070
V
DD1
= V
DD2
= 5V
T
A
= 25°C
MCLKIN = 16MHz
MCLKIN = 10MHz
MCLKIN = 5MHz
0.0065
0.0060
0.0055
0.0050
0.0045
0.0040
0.0035
0.0030
0.0025
07332-016
Figure 16. IDD2 vs. VIN DC Input Voltage
V
IN
DC INPUT VOLTAGE (V)
I
DD2
(A)
–0.325 –0.225 –0.125 –0.025 0.075 0.175
0.325–0.275 –0.175 –0.075 0.025 0.125 0.225
0.275
0.0020
0.0070
0.0065
0.0060
0.0055
0.0050
0.0045
0.0040
0.0035
0.0030
0.0025
MCLKIN = 16MHz
T
A
= +105°C MCLKIN = 16MHz
T
A
= +85°C
MCLKIN = 16MHz
T
A
= –40°C
MCLKIN = 10MHz
T
A
= –40°C
MCLKIN = 10MHz
T
A
= +105°C
MCLKIN = 10MHz
T
A
= +85°C
MCLKIN = 5MHz
T
A
= +105°C
MCLKIN = 5MHz
T
A
= +85°C
MCLKIN = 5MHz
T
A
= –40°C
V
DD1
= V
DD2
= 5V
07332-017
Figure 17. IDD2 vs. VIN at Various Temperatures
AD7401A Data Sheet
Rev. D | Page 12 of 20
8
–8
–0.35
0.35
V
IN
– DC INPUT (V)
I
IN
(µA)
6
4
2
0
–2
–4
–6
–0.30
–0.25
–0.20
–0.15
–0.10
–0.05
0
0.05
0.10
0.15
0.20
0.25
0.30
V
DD1
= V
DD2
= 4.5V TO 5.25V
MCLKIN = 10MHz
MCLKIN = 5MHz
MCLKIN = 16MHz
07332-018
Figure 18. IIN vs. VIN− DC Input
0
–120
0.1 1000
RIPPLE FREQUENCY (kHz)
CMRR (dB)
–20
–40
–60
–80
–100
1 10 100
V
DD1
= V
DD2
= 5 V
V
DD1
= V
DD2
= 5V
MCLKIN = 16MHz
MCLKIN = 5MHz
MCLKIN = 10MHz
07332-019
Figure 19. CMRR vs. Common-Mode Ripple Frequency
1.0
0
VIN DC INPUT (V)
NOISE (mV)
0.8
0.6
0.4
0.2
VDD1 = VDD2 = 5V
50kHz BRICK-WALL FILTER
MCLKIN = 5MHz
MCLKIN = 10MHz MCLKIN = 16MHz
07332-020
–0.30
–0.25
–0.20
–0.15
–0.10
–0.05
0
0.05
0.10
0.15
0.20
0.25
0.30
Figure 20. RMS Noise Voltage vs. VIN DC Input
Data Sheet AD7401A
Rev. D | Page 13 of 20
TERMINOLOGY
Differential Nonlinearity (DNL)
DNL is the difference between the measured and the ideal 1
LSB change between any two adjacent codes
in the ADC.
Integral Nonlinearity (INL)
INL is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The
endpoints of the transfer function are specified negative full
scale, −250 mV (VIN+ − VIN−), Code 7169 for the 16-bit level,
and specified positive full scale, +250 mV (VIN+ − VIN−), Code
58366 for the 16-bit level.
Offset Error
Offset error is the deviation of the midscale code (32768 for the
16-bit level) from the ideal VIN+ − VIN− (that is, 0 V).
Offset Error Drift vs. Temperature
Offset error drift is a measure of the change in offset error with
a change in temperature. It is expressed in μV/°C.
Offset Error Drift vs. VDD1
Offset error drift is a measure of the change in offset error with
a change in supply voltage. It is expressed in μV/V.
Gain Error
The gain error includes both positive full-scale gain error and
negative full-scale gain error. Positive full-scale gain error is the
deviation of the specified positive full-scale code (58366 for the
16-bit level) from the ideal VIN+ − VIN− (+250 mV) after the
offset error is adjusted out. Negative full-scale gain error is the
deviation of the specified negative full-scale code (7169 for the
16-bit level) from the ideal VIN+ − VIN− (−250 mV) after the
offset error is adjusted out. Gain error includes reference error.
Gain Error Drift vs. Temperature
Gain error drift is a measure of the change in gain error with a
change in temperature. It is expressed in μV/°C.
Gain Error Drift vs. VDD1
Gain error drift is a measure of the change in gain error with a
change in supply voltage. It is expressed in μV/V.
Signal-to-(Noise and Distortion) Ratio (SINAD)
SINAD is the measured ratio of signal-to-noise and distortion
at the output of the ADC. The signal is the rms amplitude of the
fundamental. Noise is the sum of all nonfundamental signals up
to half the sampling frequency (fS/2), excluding dc. The ratio is
dependent on the number of quantization levels in the digitization
process; the more levels, the smaller the quantization noise. The
theoretical signal-to-(noise and distortion) ratio for an ideal
N-bit converter with a sine wave input is given by
Signal-to-(Noise and Distortion) = (6.02N + 1.76) dB
Therefore, for a 12-bit converter, this is 74 dB.
Effective Number of Bits (ENOB)
ENOB is defined by
ENOB = (SINAD − 1.76)/6.02 bits
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of harmonics to the
fundamental. For the AD7401A, it is defined as
1
6
54
32
V
V
VV
V
V
THD
22
22
2
log20
(dB) +
++
+
=
where:
V1 is the rms amplitude of the fundamental.
V2, V3, V4, V5, and V6 are the rms amplitudes of the second
through the sixth harmonics.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2, excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is
determined by the largest harmonic in the spectrum, but
for ADCs where the harmonics are buried in the noise floor,
it is a noise peak.
Common-Mode Rejection Ratio (CMRR)
CMRR is defined as the ratio of the power in the ADC output
at ±250 mV frequency, f, to the power of a 250 mV p-p sine
wave applied to the common-mode voltage of VIN+ and VIN−
of frequency, fS, as
CMRR (dB) = 10 .log(Pf/PfS)
where:
Pf is the power at frequency, f, in the ADC output.
PfS is the power at frequency, fS, in the ADC output.
Power Supply Rejection Ratio (PSRR)
Variations in power supply affect the full-scale transition but
not the linearity of the converter’s linearity. PSRR is the
maximum change in the specified full-scale (±250 mV)
transition point due to a change in power supply voltage from
the nominal value (see Figure 6).
Isolation Transient Immunity
The isolation transient immunity specifies the rate of rise/fall of
a transient pulse applied across the isolation boundary beyond
which clock or data is corrupted. The AD7401A was tested
using a transient pulse frequency of 100 kHz.
AD7401A Data Sheet
Rev. D | Page 14 of 20
THEORY OF OPERATION
CIRCUIT INFORMATION
The AD7401A isolated Σ-Δ modulator converts an analog input
signal into a high speed (20 MHz maximum), single-bit data
stream; the time average single-bit data from the modulators
is directly proportional to the input signal. Figure 23 shows a
typical application circuit where the AD7401A is used to provide
isolation between the analog input, a current sensing resistor,
and the digital output, which is then processed by a digital filter
to provide an N-bit word.
ANALOG INPUT
The differential analog input of the AD7401A is implemented
with a switched capacitor circuit. This circuit implements a
second-order modulator stage that digitizes the input signal
into a 1-bit output stream. The sample clock (MCLKIN)
provides the clock signal for the conversion process as well as
the output data-framing clock. This clock source is external
on the AD7401A. The analog input signal is continuously
sampled by the modulator and compared to an internal
voltage reference. A digital stream that accurately represents
the analog input over time appears at the output of the
converter (see Figure 21).
MODULATOR OUTPUT
+FS ANALOG INPUT
–FS ANALOG INPUT
ANALOG INPUT
07332-021
Figure 21. Analog Input vs. Modulator Output
A differential signal of 0 V results (ideally) in a stream of alter-
nating 1s and 0s at the MDAT output pin. This output is high
50% of the time and low 50% of the time. A differential input of
200 mV produces a stream of 1s and 0s that are high 81.25% of
the time (for a +250 mV input, the output stream is high 89.06% of
the time). A differential input of −200 mV produces a stream of
1s and 0s that are high 18.75% of the time (for a −250 mV
input, the output stream is high 10.94% of the time).
A differential input of 320 mV results in a stream of, ideally, all
1s. This is the absolute full-scale range of the AD7401A, and
200 mV is the specified full-scale range, as shown in Table 9.
Table 9. Analog Input Range
Analog Input Voltage Input
Full-Scale Range +640 mV
Positive Full Scale +320 mV
Positive Typical Input Range +250 mV
Positive Specified Input Range +200 mV
Zero 0 mV
Negative Specified Input Range −200 mV
Negative Typical Input Range −250 mV
Negative Full Scale −320 mV
To reconstruct the original information, this output needs to be
digitally filtered and decimated. A sinc3 filter is recommended
because this is one order higher than that of the AD7401A modu-
lator. If a 256 decimation rate is used, the resulting 16-bit word
rate is 62.5 kHz, assuming a 16 MHz external clock frequency.
Figure 22 shows the transfer function of the AD7401A relative
to the 16-bit output.
65535
53248
SPECIFIED RANGE
ANALOG INPUT
ADC CODE
12288
–320mV –200mV +200mV +320mV
0
07332-022
Figure 22. Filtered and Decimated 16-Bit Transfer Characteristic
Σ-∆
MOD/
ENCODER
INPUT
CURRENT
NONISOL
A
TED
5V/3V
ISO
L
A
TED
5V
V
DD1
R
SHUNT
V
IN
+
V
IN
–
GND
1
V
DD
GND
V
DD2
MDAT MDAT
SINC3 FILTER*
AD7401A
MCLKIN
SDAT
CS
SCLK
MCLK
GND
2
DECODER
DECODER
+
ENCODER
07332-023
*THIS FILTER IS I MP LEM ENT ED
WITHAN FPGA OR DSP.
Figure 23. Typical Application Circuit
Data Sheet AD7401A
Rev. D | Page 15 of 20
DIFFERENTIAL INPUTS
The analog input to the modulator is a switched capacitor
design. The analog signal is converted into charge by highly
linear sampling capacitors. A simplified equivalent circuit
diagram of the analog input is shown in Figure 24. A signal
source driving the analog input must be able to provide the
charge onto the sampling capacitors every half MCLKIN cycle
and settle to the required accuracy within the next half cycle.
φA
φB
1kΩ
V
IN
–
φA
φB
φB φB
1kΩ
V
IN
+2pF
2pF
φA φA
MCLKIN
07332-024
Figure 24. Analog Input Equivalent Circuit
Because the AD7401A samples the differential voltage across
its analog inputs, low noise performance is attained with an
input circuit that provides low common-mode noise at each
input. The amplifiers used to drive the analog inputs play a
critical role in attaining the high performance available from the
AD7401A.
When a capacitive load is switched onto the output of an op
amp, the amplitude momentarily drops. The op amp tries to
correct the situation and, in the process, hits its slew rate limit.
This nonlinear response, which can cause excessive ringing,
can lead to distortion. To remedy the situation, a low-pass RC
filter can be connected between the amplifier and the input
to the AD7401A. The external capacitor at each input aids
in supplying the current spikes created during the sampling
process, and the resistor isolates the op amp from the transient
nature of the load.
The recommended circuit configuration for driving the
differential inputs to achieve best performance is shown in
Figure 25. A capacitor between the two input pins sources or
sinks charge to allow most of the charge that is needed by one
input to be effectively supplied by the other input. The series
resistor again isolates any op amp from the current spikes
created during the sampling process. Recommended values for
the resistors and capacitor are 22 Ω and 47 pF, respectively.
R
V
IN
–
R
V
IN
+
CAD7401A
07332-025
Figure 25. Differential Input RC Network
CURRENT SENSING APPLICATIONS
The AD7401A is ideally suited for current sensing applications
where the voltage across a shunt resistor is monitored. The load
current flowing through an external shunt resistor produces a
voltage at the input terminals of the AD7401A. The AD7401A
provides isolation between the analog input from the current
sensing resistor and the digital outputs. By selecting the appro-
priate shunt resistor value, a variety of current ranges can be
monitored.
Choosing RSHUNT
The shunt resistor values used in conjunction with the AD7401A
are determined by the specific application requirements in
terms of voltage, current, and power. Small resistors minimize
power dissipation, while low inductance resistors prevent any
induced voltage spikes, and good tolerance devices reduce
current variations. The final values chosen are a compromise
between low power dissipation and good accuracy. Low value
resistors have less power dissipated in them, but higher value
resistors may be required to utilize the full input range of the
ADC, thus achieving maximum SNR performance.
When the peak sense current is known, the voltage range of the
AD7401A (±200 mV) is divided by the maximum sense current
to yield a suitable shunt value. If the power dissipation in the
shunt resistor is too large, the shunt resistor can be reduced
and less of the ADC input range is used. Using less of the ADC
input range results in performance that is more susceptible to
noise and offset errors because offset errors are fixed and are
thus more significant when smaller input ranges are used.
RSHUNT must be able to dissipate the I2R power losses. If the
power dissipation rating of the resistor is exceeded, its value
may drift or the resistor may be damaged, resulting in an open
circuit. This can result in a differential voltage across the ter-
minals of the AD401A in excess of the absolute maximum
ratings. If ISENSE has a large high frequency component, take
care to choose a resistor with low inductance.
VOLTAGE SENSING APPLICATIONS
The AD7401A can also be used for isolated voltage monitoring.
For example, in motor control applications, it can be used to
sense bus voltage. In applications where the voltage being moni-
tored exceeds the specified analog input range of the AD7401A,
a voltage divider network can be used to reduce the voltage to
be monitored to the required range.
AD7401A Data Sheet
Rev. D | Page 16 of 20
DIGITAL FILTER
The overall system resolution and throughput rate is determined
by the filter selected and the decimation rate used. The higher
the decimation rate, the greater the system accuracy, as illus-
trated in Figure 26. However, there is a tradeoff between accuracy
and throughput rate and, therefore, higher decimation rates
result in lower throughput solutions. Note that for a given
bandwidth requirement, a higher MCLKIN frequency can allow
for higher decimation rates to be used, resulting in higher SNR
performance.
80
70
60
50
40
30
20
10
0
90
10 100 1k1
DECIMATION RATE
SNR (dB)
SINC3
SINC2
SINC1
07332-026
Figure 26. SNR vs. Decimation Rate for Different Filter Types
A sinc3 filter is recommended for use with the AD7401A. This
filter can be implemented on an FPGA or a DSP.
3
1
1
1
)(
Z
Z
zH
DR
where DR is the decimation rate.
The following Verilog code provides an example of a sinc3 filter
implementation on a Xilinx® Spartan-II 2.5 V FPGA. This code
can possibly be compiled for another FPGA, such as an Altera®
device. Note that the data is read on the negative clock edge in
this case, although it can be read on the positive edge, if
preferred.
/*`Data is read on negative clk edge*/
module DEC256SINC24B(mdata1, mclk1, reset,
DATA);
input mclk1; /*used to clk filter*/
input reset; /*used to reset filter*/
input mdata1; /*ip data to be
filtered*/
output [15:0] DATA; /*filtered op*/
integer location;
integer info_file;
reg [23:0] ip_data1;
reg [23:0] acc1;
reg [23:0] acc2;
reg [23:0] acc3;
reg [23:0] acc3_d1;
reg [23:0] acc3_d2;
reg [23:0] diff1;
reg [23:0] diff2;
reg [23:0] diff3;
reg [23:0] diff1_d;
reg [23:0] diff2_d;
reg [15:0] DATA;
reg [7:0] word_count;
reg word_clk;
reg init;
/*Perform the Sinc ACTION*/
always @ (mdata1)
if(mdata1==0)
ip_data1 <= 0; /* change from a 0
to a -1 for 2's comp */
else
ip_data1 <= 1;
/*ACCUMULATOR (INTEGRATOR)
Perform the accumulation (IIR) at the speed
of the modulator.
MCLKIN
IP_DATA1
ACC1+ ACC2+ ACC3+
+
Z
+
Z
+
Z
07332-027
Figure 27. Accumulator
Data Sheet AD7401A
Rev. D | Page 17 of 20
Z = one sample delay
MCLKOUT = modulators conversion bit rate
*/
always @ (posedge mclk1 or posedge reset)
if (reset)
begin
/*initialize acc registers on reset*/
acc1 <= 0;
acc2 <= 0;
acc3 <= 0;
end
else
begin
/*perform accumulation process*/
acc1 <= acc1 + ip_data1;
acc2 <= acc2 + acc1;
acc3 <= acc3 + acc2;
end
/*DECIMATION STAGE (MCLKOUT/ WORD_CLK)
*/
always @ (negedge mclk1 or posedge reset)
if (reset)
word_count <= 0;
else
word_count <= word_count + 1;
always @ (word_count)
word_clk <= word_count[7];
/*DIFFERENTIATOR ( including decimation
stage)
Perform the differentiation stage (FIR) at a
lower speed.
WORD_CLK
ACC3
DIFF1DIFF3
+
–
+
–
DIFF2
Z
–1
–
+
–
Z
–1
Z
–1
07332-028
Figure 28. Differentiator
Z = one sample delay
WORD_CLK = output word rate
*/
always @ (posedge word_clk or posedge reset)
if(reset)
begin
acc3_d2 <= 0;
diff1_d <= 0;
diff2_d <= 0;
diff1 <= 0;
diff2 <= 0;
diff3 <= 0;
end
else
begin
diff1 <= acc3 - acc3_d2;
diff2 <= diff1 - diff1_d;
diff3 <= diff2 - diff2_d;
acc3_d2 <= acc3;
diff1_d <= diff1;
diff2_d <= diff2;
end
/* Clock the Sinc output into an output
register
WORD_CLK
DATADIFF3
07332-029
Figure 29. Clocking Sinc Output into an Output Register
WORD_CLK = output word rate
*/
always @ (posedge word_clk)
begin
DATA[15] <= diff3[23];
DATA[14] <= diff3[22];
DATA[13] <= diff3[21];
DATA[12] <= diff3[20];
DATA[11] <= diff3[19];
DATA[10] <= diff3[18];
DATA[9] <= diff3[17];
DATA[8] <= diff3[16];
DATA[7] <= diff3[15];
DATA[6] <= diff3[14];
DATA[5] <= diff3[13];
DATA[4] <= diff3[12];
DATA[3] <= diff3[11];
DATA[2] <= diff3[10];
DATA[1] <= diff3[9];
DATA[0] <= diff3[8];
end
endmodule
AD7401A Data Sheet
Rev. D | Page 18 of 20
APPLICATIONS INFORMATION
GROUNDING AND LAYOUT
Supply decoupling with a value of 100 nF is recommended on
both VDD1 and VDD2. In applications involving high common-
mode transients, care should be taken to ensure that board
coupling across the isolation barrier is minimized. Further-
more, the board layout should be designed so that any coupling
that occurs equally affects all pins on a given component side.
Failure to ensure this may cause voltage differentials between
pins to exceed the absolute maximum ratings of the device,
thereby leading to latch-up or permanent damage. Any decoupling
used should be placed as close to the supply pins as possible.
Series resistance in the analog inputs should be minimized to
avoid any distortion effects, especially at high temperatures. If
possible, equalize the source impedance on each analog input to
minimize offset. Beware of mismatch and thermocouple effects
on the analog input PCB tracks to reduce offset drift.
EVALUATING THE AD7401A PERFORMANCE
An AD7401A evaluation board is available with split ground
planes and a board split beneath the AD7401A package to
ensure isolation. This board allows access to each pin on the
device for evaluation purposes.
The evaluation board package includes a fully assembled and
tested evaluation board, documentation, and software for
controlling the board from the PC via the EVAL-CED1Z. The
software also includes a sinc3 filter implemented on an FPGA.
The evaluation board is used in conjunction with the EVAL-
CED1Z board and can also be used as a standalone board. The
software allows the user to perform ac (fast Fourier transform)
and dc (histogram of codes) tests on the AD7401A. The soft-
ware and documentation are on a CD that is shipped with the
evaluation board.
INSULATION LIFETIME
All insulation structures, subjected to sufficient time and/or
voltage, are vulnerable to breakdown. In addition to the testing
performed by the regulatory agencies, Analog Devices has
carried out an extensive set of evaluations to determine the
lifetime of the insulation structure within the AD7401A.
These tests subjected devices to continuous cross-isolation
voltages. To accelerate the occurrence of failures, the selected
test voltages were values exceeding those of normal use. The
time-to-failure values of these units were recorded and used
to calculate acceleration factors. These factors were then used
to calculate the time-to-failure under normal operating
conditions. The values shown in Table 7 are the lesser of the
following two values:
• The value that ensures at least a 50-year lifetime of
continuous use.
• The maximum CSA/VDE approved working voltage.
It should also be noted that the lifetime of the AD7401A varies
according to the waveform type imposed across the isolation
barrier. The iCoupler insulation structure is stressed differently
depending on whether the waveform is bipolar ac, unipolar ac,
or dc. Figure 30, Figure 31, and Figure 32 illustrate the different
isolation voltage waveforms.
0V
RATED PEAK VOLTAGE
07332-030
Figure 30. Bipolar AC Waveform
0V
RATED PEAK VOLTAGE
07332-031
Figure 31. Unipolar AC Waveform
0V
RATED PEAK VOLTAGE
07332-032
Figure 32. DC Waveform
Data Sheet AD7401A
Rev. D | Page 19 of 20
OUTLINE DIMENSIONS
CONTROLLINGDIMENSIONS ARE IN MILLIMETERS;INCH DIMENSIONS
(IN PARENT
HESES) ARE ROUNDED-OFFMILLIMETER EQUIVALENTS FOR
REFERENCE ONLYANDARE NOT APPROPRIATEFORUSE IN DESIGN.
COMPLIANTTO JEDEC STANDARDSMS-013-AA
10.50 (0.4134)
10.10(0.3976)
0.30 (0.0118)
0.10 (0.0039)
2.65 (0.1043)
2.35 (0.0925)
10.65 (0.4193)
10.00 (0.3937)
7.60 (0.2992)
7.40 (0.2913)
0.75(0.0295)
0.25(0.0098)
45°
1.27 (0.0500)
0.40(0.0157)
COPLANARITY
0.100.33 (0.0130)
0.20 (0.0079)
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
8°
0°
16 9
8
1
1.27 (0.0500)
BSC
03-27-2007-B
Figure 33. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-16)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
AD7401AYRWZ −40°C to +125°C 16-Lead Standard Small Outline Package (SOIC_W) RW-16
AD7401AYRWZ-RL −40°C to +125°C 16-Lead Standard Small Outline Package (SOIC_W) RW-16
ADW70015Z-0RL −40°C to +125°C 16-Lead Standard Small Outline Package (SOIC_W) RW-16
EVAL-AD7401AEDZ
Evaluation Board
EVAL-CED1Z Development Board
1 Z = RoHS Compliant Part.
AUTOMOTIVE PRODUCT
The ADW70015Z model is available with controlled manufacturing to support the quality and reliability requirements of automotive
applications. Note that this automotive model may have specifications that differ from the commercial models; therefore, designers
should review the Specifications section of this data sheet carefully. Only the automotive grade product shown is available for use in
automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to
obtain the specific Automotive Reliability reports for this model.
