Rev.2.40 Aug 25, 2006 page 1 of 88
REJ03B0003-0240
M16C/6N Group (M16C/6N4)
Renesas MCU
Under development
This document is under development and its contents are subject to change
Specifications written in this manual are believed to be accurate, but are not
guaranteed to be entirely free of error. Specifications in this manual may be
changed for functional or performance improvements. Please make sure your
manual is the latest edition.
REJ03B0003-0240
Rev.2.40
Aug 25, 2006
1. Overview
The M16C/6N Group (M16C/6N4) of MCUs are built using the high-performance silicon gate CMOS process
using the M16C/60 Series CPU core and are packaged in 100-pin plastic molded QFP and LQFP. These
MCUs operate using sophisticated instructions featuring a high level of instruction efficiency. With 1 Mbyte of
address space, they are capable of executing instructions at high speed. Being equipped with two CAN
(Controller Area Network) modules in the M16C/6N Group (M16C/6N4), the MCU is suited to drive automotive
and industrial control systems. The CAN modules comply with the 2.0B specification. In addition, this MCU
contains a multiplier and DMAC which combined with fast instruction processing capability, makes it suitable
for control of various OA, communication, and industrial equipment which requires high-speed arithmetic/
logic operations.
1.1 Applications
• Automotive, industrial control systems and other automobile, other (T/V-ver. product)
• Car audio and industrial control systems, other (Normal-ver. product)
Rev.2.40 Aug 25, 2006 page 2 of 88
REJ03B0003-0240
M16C/6N Group (M16C/6N4) 1. Overview
Under development
This document is under development and its contents are subject to change.
Item Specification
Normal-ver. T/V-ver.
CPU Number of fundamental 91 instructions
instructions
Minimum instruction 41.7 ns (f(BCLK) = 24 MHz, 50.0 ns (f(BCLK) = 20 MHz,
execution time
1/1 prescaler, without software wait) 1/1 prescaler, without software wait)
Operating mode Single-chip, memory expansion, and microprocessor modes
Address space 1 Mbyte
Memory capacity Refer to Table 1.2 Product Information
Peripheral Ports Input/Output: 87 pins, Input: 1 pin
Function Multifunction timers Timer A: 16 bits ✕ 5 channels
Timer B: 16 bits ✕ 6 channels
Three-phase motor control circuit
Serial interfaces 3 channels
Clock synchronous, UART, I2C-bus (1), IEBus (2)
1 channel
Clock synchronous
A/D converter 10-bit A/D converter: 1 circuit, 26 channels
D/A converter 8 bits ✕ 2 channels
DMAC 2 channels
CRC calculation circuit CRC-CCITT
CAN module 2 channels with 2.0B specification
Watchdog timer 15 bits ✕ 1 channel (with prescaler)
Interrupts Internal: 31 sources, External: 9 sources
Software: 4 sources, Priority levels: 7 levels
Clock generation circuits 4 circuits
• Main clock oscillation circuit (*)
• Sub clock oscillation circuit (*)
• On-chip oscillator
• PLL frequency synthesizer
(*) Equipped with on-chip feedback resistor
Oscillation-stopped detector Main clock oscillation stop and re-oscillation detection function
Electrical Supply voltage
VCC = 3.0 to 5.5 V (f(BCLK) = 24 MHz, VCC = 4.2 to 5.5 V (f(BCLK) = 20 MHz,
Characteristics
1/1 prescaler, without software wait) 1/1 prescaler, without software wait)
Consumption Mask ROM 20 mA (f(BCLK) = 24 MHz, 18 mA (f(BCLK) = 20 MHz,
current PLL operation, no division) PLL operation, no division)
Flash memory
22 mA (f(BCLK) = 24 MHz, 20 mA (f(BCLK) = 20 MHz,
PLL operation, no division) PLL operation, no division)
Mask ROM 3 µA
(f(BCLK) = 32 kHz, Wait mode, Oscillation capacity Low)
Flash memory
0.8 µA (Stop mode, Topr = 25°C)
Flash Memory Programming and erasure voltage
3.0 ± 0.3 V or 5.0 ± 0.5 V 5.0 ± 0.5 V
Version
Programming and erasure endurance
100 times
I/O I/O withstand voltage 5.0 V
Characteristics
Output current 5 mA
Operating Ambient Temperature -40 to 85°C T version: -40 to 85°C
V version: -40 to 125°C
(option)
Device Configuration CMOS high-performance silicon gate
Package 100-pin molded-plastic QFP, LQFP
1.2 Performance Overview
Table 1.1 lists the Functions and Specifications for M16C/6N Group (M16C/6N4).
Table 1.1 Functions and Specifications for M16C/6N Group (M16C/6N4)
NOTES:
1. I2C-bus is a trademark of Koninklijke Philips Electronics N.V.
2. IEBus is a trademark of NEC Electronics Corporation.
option: All options are on request basis.
Rev.2.40 Aug 25, 2006 page 3 of 88
REJ03B0003-0240
M16C/6N Group (M16C/6N4) 1. Overview
Under development
This document is under development and its contents are subject to change.
1.3 Block Diagram
Figure 1.1 shows a Block Diagram.
Figure 1.1 Block Diagram
NOTES:
1: ROM size depends on MCU type.
2: RAM size depends on MCU type.
Timer (16 bits)
Output (timer A): 5
Input (timer B): 6
Three-phase motor
control circuit
Internal peripheral functions
Watchdog timer
(15 bits)
A/D converter
(10 bits ✕ 8 channels
Expandable up to 26 channels)
UART or
Clock synchronous serial I/O
(3 channels)
System clock generation circuit
XIN-XOUT
XCIN-XCOUT
PLL frequency synthesizer
On-chip oscillator
Port P0
8
Port P1
8
Port P2
8 8 8 8
Port P6
8
8788
Port P10
Port P9
Port P8_5
Port P8
Port P7
Port P5Port P4Port P3
CRC calculation circuit (CCITT)
(Polynomial: X
16
+X
12
+X
5
+1)
Clock synchronous serial I/O
(8 bits ✕ 1 channel)
CAN module
(2 channels)
DMAC
(2 channels)
D/A converter
(8 bits ✕ 2 channels)
MemoryM16C/60 Series CPU core
R0H R0L
R1H R1L
R2
R3
A0
A1
FB
Multiplier
INTB
PC
USP
ISP
SB
FLG
ROM
(1)
RAM
(2)
Rev.2.40 Aug 25, 2006 page 4 of 88
REJ03B0003-0240
M16C/6N Group (M16C/6N4) 1. Overview
Under development
This document is under development and its contents are subject to change.
1.4 Product Information
Table 1.2 lists the Product Information and Figure 1.2 shows the Type Number, Memory Size, and Packages.
Table 1.2 Product Information As of Aug. 2006
Type No.
M30 6N 4
M C T
-
XXX FP
Package type:
FP : Package PRQP0100JB-A (100P6S-A)
GP: Package PLQP0100KB-A (100P6Q-A)
ROM No.
Omitted on flash memory version
Characteristics
(no): Normal-ver.
T : T-ver. (Automotive 85°C version)
V : V-ver. (Automotive 125°C version)
ROM capacity:
C : 128 Kbytes
G: 256 Kbytes
Memory type:
M: Mask ROM version
F : Flash memory version
Shows the number of CAN module, pin count, etc.
6N Group
M16C Family
(D): Under development
NOTES:
1. Data flash memory provides an additional 4 Kbytes of ROM capacity (block A).
2. The correspondence between new and old package types is as follows.
PRQP0100JB-A: 100P6S-A
PLQP0100KB-A: 100P6Q-A
Type No. ROM Capacity RAM Capacity Package Type (2) Remarks
M306N4FCFP 128 K + 4 Kbytes 5 Kbytes PRQP0100JB-A Flash Normal-ver.
M306N4FCGP PLQP0100KB-A memory
M306N4FGFP 256 K + 4 Kbytes 10 Kbytes PRQP0100JB-A version (1)
M306N4FGGP PLQP0100KB-A
M306N4FCTFP 128 K + 4 Kbytes 5 Kbytes PRQP0100JB-A T-ver.
M306N4FCTGP PLQP0100KB-A
M306N4FGTFP 256 K + 4 Kbytes 10 Kbytes PRQP0100JB-A
M306N4FGTGP PLQP0100KB-A
M306N4FCVFP 128 K + 4 Kbytes 5 Kbytes PRQP0100JB-A V-ver.
M306N4FCVGP PLQP0100KB-A
M306N4FGVFP 256 K + 4 Kbytes 10 Kbytes PRQP0100JB-A
M306N4FGVGP PLQP0100KB-A
M306N4MC-XXXGP 128 Kbytes 5 Kbytes PLQP0100KB-A Mask Normal-ver.
M306N4MG-XXXGP 256 Kbytes 10 Kbytes PLQP0100KB-A ROM
M306N4MCT-XXXFP 128 Kbytes 5 Kbytes PRQP0100JB-A version T-ver.
M306N4MCT-XXXGP PLQP0100KB-A
M306N4MGT-XXXFP 256 Kbytes 10 Kbytes PRQP0100JB-A
M306N4MGT-XXXGP PLQP0100KB-A
M306N4MCV-XXXFP 128 Kbytes 5 Kbytes PRQP0100JB-A V-ver.
M306N4MCV-XXXGP (D) PLQP0100KB-A
M306N4MGV-XXXFP 256 Kbytes 10 Kbytes PRQP0100JB-A
M306N4MGV-XXXGP (D) PLQP0100KB-A
Figure 1.2 Type Number, Memory Size, and Package
Rev.2.40 Aug 25, 2006 page 5 of 88
REJ03B0003-0240
M16C/6N Group (M16C/6N4) 1. Overview
Under development
This document is under development and its contents are subject to change.
1.5 Pin Assignments
Figures 1.3 and 1.4 show the Pin Assignment (Top View). Tables 1.3 and 1.4 list the List of Pin Names.
P4_4/CS0
P4_5/CS1
P4_6/CS2
P4_7/CS3
P5_0/WRL/WR
P5_1/WRH/BHE
P5_2/RD
P5_3/BCLK
P5_4/HLDA
P5_5/HOLD
P5_6/ALE
P5_7/RDY/CLKOUT
P6_0/CTS0/RTS0
P6_1/CLK0
P6_2/RXD0/SCL0
P6_3/TXD0/SDA0
P6_4/CTS1/RTS1/CTS0/CLKS1
P6_5/CLK1
P6_6/RXD1/SCL1
P6_7/TXD1/SDA1
P9_6/ANEX1/CTX0
P9_5/ANEX0/CRX0
P9_4/DA1/TB4IN
P9_3/DA0/TB3IN
P9_2/TB2IN/SOUT3
(1)
P9_1/TB1IN/SIN3
P9_0/TB0IN/CLK3
BYTE
CNVSS
P8_7/XCIN
P8_6/XCOUT
RESET
XOUT
VSS
XIN
VCC1
P8_5/NMI
P8_4/INT2/ZP
P8_3/INT1
P8_2/INT0
P8_1/TA4IN/U
P8_0/TA4OUT/U
P7_7/TA3IN/CRX1
P7_6/TA3OUT/CTX1
P7_5/TA2IN/W
P7_4/TA2OUT/W
P7_3/CTS2/RTS2/TA1IN/V
P7_2/CLK2/TA1OUT/V
(1)
P7_1/RXD2/SCL2/TA0IN/TB5IN
P7_0/TXD2/SDA2/TA0OUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P0_7/AN0_7/D7
P0_6/AN0_6/D6
P0_5/AN0_5/D5
P0_4/AN0_4/D4
P0_3/AN0_3/D3
P0_2/AN0_2/D2
P0_1/AN0_1/D1
P0_0/AN0_0/D0
P10_7/AN7/KI3
P10_6/AN6/KI2
P10_5/AN5/KI1
P10_4/AN4/KI0
P10_3/AN3
P10_2/AN2
P10_1/AN1
AVSS
P10_0/AN0
VREF
AVCC
P9_7/ADTRG
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
10 0
P1_0/D8
P1_1/D9
P1_2/D10
P1_3/D11
P1_4/D12
P1_5/D13/INT3
P1_6/D14/INT4
P1_7/D15/INT5
P2_0/AN2_0/A0(/D0/-)
P2_1/AN2_1/A1(/D1/D0)
P2_2/AN2_2/A2(/D2/D1)
P2_3/AN2_3/A3(/D3/D2)
P2_4/AN2_4/A4(/D4/D3)
P2_5/AN2_5/A5(/D5/D4)
P2_6/AN2_6/A6(/D6/D5)
P2_7/AN2_7/A7(/D7/D6)
VSS
P3_0/A8(/-/D7)
VCC2
P3_1/A9
P3_2/A10
P3_3/A11
P3_4/A12
P3_5/A13
P3_6/A14
P3_7/A15
P4_0/A16
P4_1/A17
P4_2/A18
P4_3/A19
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
M16C/6N Group
(M16C/6N4)
Figure 1.3 Pin Assignments (Top View) (1)
Package: PRQP0100JB-A (100P6S-A)
NOTE:
1. P7_1 and P9_1 are N channel open-drain pins.
Rev.2.40 Aug 25, 2006 page 6 of 88
REJ03B0003-0240
M16C/6N Group (M16C/6N4) 1. Overview
Under development
This document is under development and its contents are subject to change.
Figure 1.4 Pin Assignments (Top View) (2)
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
P0_0/AN0_0/D0
P0_1/AN0_1/D1
P0_2/AN0_2/D2
P0_3/AN0_3/D3
P0_4/AN0_4/D4
P0_5/AN0_5/D5
P0_6/AN0_6/D6
P0_7/AN0_7/D7
P1_0/D8
P1_1/D9
P1_2/D10
P1_3/D11
P1_4/D12
VREF
AVSS
VCC1
XIN
XOUT
VSS
RESET
CNVSS
P8_7/XCIN
P8_6/XCOUT
BYTE P2_0/AN2_0/A0(/D0/-)
P2_1/AN2_1/A1(/D1/D0)
P2_2/AN2_2/A2(/D2/D1)
P2_3/AN2_3/A3(/D3/D2)
P2_4/AN2_4/A4(/D4/D3)
P2_5/AN2_5/A5(/D5/D4)
P2_6/AN2_6/A6(/D6/D5)
P2_7/AN2_7/A7(/D7/D6)
P3_0/A8(/-/D7)
P3_1/A9
P3_2/A10
P3_3/A11
P3_4/A12
P3_5/A13
P3_6/A14
P3_7/A15
P4_0/A16
P4_1/A17
P4_2/A18
P4_3/A19
P7_4/TA2OUT/W
P7_6/TA3OUT/CTX1
P5_6/ALE
P7_7/TA3IN/CRX1
P5_5/HOLD
P5_4/HLDA
P5_3/BCLK
P5_2/RD
VCC2
VSS
P5_7/RDY/CLKOUT
P4_5/CS1
P4_6/CS2
P4_7/CS3
AVCC
P6_3/TXD0/SDA0
P6_5/CLK1
P6_6/RXD1/SCL1
P6_7/TXD1/SDA1
P6_1/CLK0
P6_2/RXD0/SCL0
P10_0/AN0
P10_1/AN1
P10_2/AN2
P10_3/AN3
P9_3/DA0/TB3IN
P9_4/DA1/TB4IN
P9_5/ANEX0/CRX0
P9_6/ANEX1/CTX0
(1)
P9_1/TB1IN/SIN3
P9_2/TB2IN/SOUT3
P8_0/TA4OUT/U
P6_0/CTS0/RTS0
P6_4/CTS1/RTS1/CTS0/CLKS1
P8_2/INT0
P8_3/INT1
P8_5/NMI
P9_7/ADTRG
P4_4/CS0
P5_0/WRL/WR
P5_1/WRH/BHE
P9_0/TB0IN/CLK3
P8_4/INT2/ZP
P7_2/CLK2/TA1OUT/V
P7_1/RXD2/SCL2/TA0IN/TB5IN
(1)
P7_0/TXD2/SDA2/TA0OUT
P7_5/TA2IN/W
P7_3/CTS2/RTS2/TA1IN/V
P1_5/D13/INT3
P1_6/D14/INT4
P1_7/D15/INT5
P10_7/AN7/KI3
P10_6/AN6/KI2
P10_5/AN5/KI1
P10_4/AN4/KI0
P8_1/TA4IN/U
M16C/6N Group
(M16C/6N4)
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
NOTE:
1. P7_1 and P9_1 are N channel open-drain pins.
Package: PLQP0100KB-A (100P6Q-A)
Rev.2.40 Aug 25, 2006 page 7 of 88
REJ03B0003-0240
M16C/6N Group (M16C/6N4) 1. Overview
Under development
This document is under development and its contents are subject to change.
Table 1.3 List of Pin Names (1)
Pin No. Control Port Interrupt Timer Pin UART Pin Analog
CAN Module
Bus Control Pin
FP GP Pin Pin Pin Pin
1 99 P9_6 ANEX1 CTX0
2 100 P9_5 ANEX0 CRX0
3 1 P9_4 TB4IN DA1
4 2 P9_3 TB3IN DA0
5 3 P9_2 TB2IN SOUT3
6 4 P9_1 TB1IN SIN3
7 5 P9_0 TB0IN CLK3
8 6 BYTE
9 7 CNVSS
10 8 XCIN P8_7
11 9 XCOUT P8_6
12 10
____________
RESET
13 11 XOUT
14 12 VSS
15 13 XIN
16 14 VCC1
17 15 P8_5
_______
NMI
18 16 P8_4
________
INT2 ZP
19 17 P8_3 INT1
20 18 P8_2 INT0
21 19 P8_1
___
TA4IN/U
22 20 P8_0 TA4OUT/U
23 21 P7_7 TA3IN CRX1
24 22 P7_6 TA3OUT CTX1
25 23 P7_5
____
TA2IN/W
26 24 P7_4 TA2OUT/W
27 25 P7_3
___
TA1IN/V
__________ __________
CTS2/RTS2
28 26 P7_2 TA1OUT/V CLK2
29 27 P7_1 TA0IN/TB5IN RXD2/SCL2
30 28 P7_0 TA0OUT TXD2/SDA2
31 29 P6_7 TXD1/SDA1
32 30 P6_6 RXD1/SCL1
33 31 P6_5 CLK1
34 32 P6_4
_________ _________ _________
CTS1/RTS1/CTS0/CLKS1
35 33 P6_3 TXD0/SDA0
36 34 P6_2 RXD0/SCL0
37 35 P6_1 CLK0
38 36 P6_0
__________ __________
CTS0/RTS0
39 37 P5_7
________
RDY/CLKOUT
40 38 P5_6 ALE
41 39 P5_5
__________
HOLD
42 40 P5_4
__________
HLDA
43 41 P5_3 BCLK
44 42 P5_2
_____
RD
45 43 P5_1
_________ ________
WRH/BHE
46 44 P5_0
________ ______
WRL/WR
47 45 P4_7
_______
CS3
48 46 P4_6
_______
CS2
49 47 P4_5
_______
CS1
50 48 P4_4
_______
CS0
FP: PRQP0100JB-A (100P6S-A), GP: PLQP0100KB-A (100P6Q-A)
Rev.2.40 Aug 25, 2006 page 8 of 88
REJ03B0003-0240
M16C/6N Group (M16C/6N4) 1. Overview
Under development
This document is under development and its contents are subject to change.
Pin No. Control Port Interrupt Timer Pin UART Pin Analog
CAN Module
Bus Control Pin
FP GP Pin Pin Pin Pin
51 49 P4_3 A19
52 50 P4_2 A18
53 51 P4_1 A17
54 52 P4_0 A16
55 53 P3_7 A15
56 54 P3_6 A14
57 55 P3_5 A13
58 56 P3_4 A12
59 57 P3_3 A11
60 58 P3_2 A10
61 59 P3_1 A9
62 60 VCC2
63 61 P3_0 A8(/-/D7)
64 62 VSS
65 63 P2_7 AN2_7 A7(/D7/D6)
66 64 P2_6 AN2_6 A6(/D6/D5)
67 65 P2_5 AN2_5 A5(/D5/D4)
68 66 P2_4 AN2_4 A4(/D4/D3)
69 67 P2_3 AN2_3 A3(/D3/D2)
70 68 P2_2 AN2_2 A2(/D2/D1)
71 69 P2_1 AN2_1 A1(/D1/D0)
72 70 P2_0 AN2_0 A0(/D0/-)
73 71 P1_7
________
INT5 D15
74 72 P1_6
________
INT4 D14
75 73 P1_5
________
INT3 D13
76 74 P1_4 D12
77 75 P1_3 D11
78 76 P1_2 D10
79 77 P1_1 D9
80 78 P1_0 D8
81 79 P0_7 AN0_7 D7
82 80 P0_6 AN0_6 D6
83 81 P0_5 AN0_5 D5
84 82 P0_4 AN0_4 D4
85 83 P0_3 AN0_3 D3
86 84 P0_2 AN0_2 D2
87 85 P0_1 AN0_1 D1
88 86 P0_0 AN0_0 D0
89 87 P10_7
______
KI3 AN7
90 88 P10_6
______
KI2 AN6
91 89 P10_5
______
KI1 AN5
92 90 P10_4
______
KI0 AN4
93 91 P10_3 AN3
94 92 P10_2 AN2
95 93 P10_1 AN1
96 94 AVSS
97 95 P10_0 AN0
98 96 VREF
99 97 AVCC
100 98 P9_7
_____________
ADTRG
Table 1.4 List of Pin Names (2)
FP: PRQP0100JB-A (100P6S-A), GP: PLQP0100KB-A (100P6Q-A)
Rev.2.40 Aug 25, 2006 page 9 of 88
REJ03B0003-0240
M16C/6N Group (M16C/6N4) 1. Overview
Under development
This document is under development and its contents are subject to change.
1.6 Pin Functions
Tables 1.5 to 1.7 list the Pin Functions.
Table 1.5 Pin Functions (1)
I
I
I
I
I
I/O
I/O
O
I/O
I/O
O
O
O
I
O
I
VCC1, VCC2,
VSS
AVCC, AVSS
_____________
RESET
CNVSS
BYTE
D0 to D7
D8 to D15
A0 to A19
A0/D0 to A7/D7
A1/D0 to A8/D7
_______ _______
CS0 to CS3
_________ ______
WRL/WR
_________ ________
WRH/BHE
______
RD
ALE
__________
HOLD
__________
HLDA
________
RDY
Power supply
input
Analog power
supply input
Reset input
CNVSS
External data
bus width
select input
Bus control
pins
Apply 4.2 to 5.5 V (T/V-ver.), 3.0 to 5.5 V (Normal-ver.) to the VCC1
and VCC2 pins and 0 V to the VSS pin. The VCC apply condition is
that VCC2 = VCC1 (1).
Applies the power supply for the A/D converter. Connect the AVCC
pin to VCC1. Connect the AVSS pin to VSS.
The MCU is in a reset state when applying “L” to the this pin.
Switches processor mode. Connect this pin to VSS to when after
a reset to start up in single-chip mode. Connect this pin to VCC1
to start up in microprocessor mode.
Switches the data bus in external memory space. The data bus
is 16-bit long when the this pin is held “L” and 8-bit long when
the this pin is held “H”. Set it to either one. Connect this pin to
VSS when single-chip mode.
Inputs and outputs data (D0 to D7) when these pins are set as
the separate bus.
Inputs and outputs data (D8 to D15) when external 16-bit data
bus is set as the separate bus.
Output address bits (A0 to A19).
Input and output data (D0 to D7) and output address bits (A0 to
A7) by time-sharing when external 8-bit data bus are set as the
multiplexed bus.
Input and output data (D0 to D7) and output address bits (A1 to
A8) by time-sharing when external 16-bit data bus are set as the
multiplexed bus.
_______ _______ _______ _______
Output CS0 to CS3 signals. CS0 to CS3 are chip-select signals
to specify an external space.
________ _________ ______ ________ _____ ________ _________
Output WRL, WRH, (WR, BHE), RD signals. WRL and WRH or
________ ______
BHE, and WR can be switched by program.
________ _________ _____
• WRL, WRH, and RD are selected
________
The WRL signal becomes “L” by writing data to an even address
in an external memory space.
_________
The WRH signal becomes “L” by writing data to an odd address
in an external memory space.
_____
The RD pin signal becomes “L” by reading data in an external
memory space.
______ ________ _____
• WR, BHE, and RD are selected
______
The WR signal becomes “L” by writing data in an external
memory space.
_____
The RD signal becomes “L” by reading data in an external
memory space.
________
The BHE signal becomes “L” by accessing an odd address.
______ ________ _____
Select WR, BHE, and RD for an external 8-bit data bus.
ALE is a signal to latch the address.
__________
While the HOLD pin is held “L”, the MCU is placed in a hold
state. __________
In a hold state, HLDA outputs a “L” signal.
________
While applying a “L” signal to the RDY pin, the MCU is placed in
a wait state.
Signal Name Pin Name I/O Type Description
I: Input O: Output I/O: Input/Output
NOTE:
1. In this manual, hereafter, VCC refers to VCC1 unless otherwise noted.
Rev.2.40 Aug 25, 2006 page 10 of 88
REJ03B0003-0240
M16C/6N Group (M16C/6N4) 1. Overview
Under development
This document is under development and its contents are subject to change.
Table 1.6 Pin Functions (2)
I
O
I
O
O
O
I
I
I
I/O
I
I
I
O
I
O
I/O
I
I
O
O
O
I/O
I/O
I
I
I
I/O
I
O
I
O
XIN
XOUT
XCIN
XCOUT
BCLK
CLKOUT
________ ________
INT0 to INT5
________
NMI
______ ______
KI0 to KI3
TA0OUT to TA4OUT
TA0IN to TA4IN
ZP
TB0IN to TB5IN
___ ___ ____
U, U, V, V, W, W
__________ __________
CTS0 to CTS2
__________ __________
RTS0 to RTS2
CLK0 to CLK3
RXD0 to RXD2
SIN3
TXD0 to TXD2
SOUT3
CLKS1
SDA0 to SDA2
SCL0 to SCL2
VREF
AN0 to AN7
AN0_0 to AN0_7
AN2_0 to AN2_7
_____________
ADTRG
ANEX0
ANEX1
DA0, DA1
CRX0, CRX1
CTX0, CTX1
Main clock
input
Main clock
output
Sub clock
input
Sub clock
output
BCLK output
Clock output
INT interrupt input
_______
NMI interrupt
input
Key input
interrupt input
Timer A
Timer B
Three-phase motor
control output
Serial interface
I2C mode
Reference
voltage input
A/D converter
D/A converter
CAN module
I/O pins for the main clock oscillation circuit. Connect a ceramic
resonator or crystal oscillator between XIN and XOUT (1).
To use the external clock, input the clock from XIN and leave
XOUT open.
I/O pins for a sub clock oscillation circuit. Connect a crystal
oscillator between XCIN and XCOUT (1).
To use the external clock, input the clock from XCIN and leave
XCOUT open.
Outputs the BCLK signal.
The clock of the same cycle as fC, f8, or f32 is output.
______
Input pins for the INT interrupt.
_______
Input pin for the NMI interrupt.
Input pins for the key input interrupt.
These are timer A0 to timer A4 I/O pins.
These are timer A0 to timer A4 input pins.
Input pin for the Z-phase.
These are timer B0 to timer B5 input pins.
These are Three-phase motor control output pins.
These are transmit control input pins.
These are receive control output pins.
These are transfer clock I/O pins.
These are serial data input pins.
These are serial data input pins.
These are serial data output pins.
These are serial data output pins.
This is output pin for transfer clock output from multiple pins
function.
These are serial data I/O pins.
These are transfer clock I/O pins. (however, SCL2 for the
N-channel open drain output.)
Applies the reference voltage for the A/D converter and D/A
converter.
Analog input pins for the A/D converter.
This is an A/D trigger input pin.
This is the extended analog input pin for the A/D converter,
and is the output in external op-amp connection mode.
This is the extended analog input pin for the A/D converter.
These are the output pins for the D/A converter.
These are the input pins for the CAN module.
These are the output pins for the CAN module.
Signal Name Pin Name I/O Type Description
I: Input O: Output I/O: Input/Output
NOTE:
1. Ask the oscillator maker the oscillation characteristic.
Rev.2.40 Aug 25, 2006 page 11 of 88
REJ03B0003-0240
M16C/6N Group (M16C/6N4) 1. Overview
Under development
This document is under development and its contents are subject to change.
Table 1.7 Pin Functions (3)
8-bit I/O ports in CMOS, having a direction register to select
an input or output.
Each pin is set as an input port or output port. An input port
can be set for a pull-up or for no pull-up in 4-bit unit by
program.
(however, P7_1 and P9_1 for the N-channel open drain
output.)
_______
Input pin for the NMI interrupt.
Pin states can be read by the P8_5 bit in the P8 register.
I/O port
Input port
P0_0 to P0_7
P1_0 to P1_7
P2_0 to P2_7
P3_0 to P3_7
P4_0 to P4_7
P5_0 to P5_7
P6_0 to P6_7
P7_0 to P7_7
P8_0 to P8_4
P8_6, P8_7
P9_0 to P9_7
P10_0 to P10_7
P8_5
I/O
I
Signal Name Pin Name I/O Type Description
I: Input O: Output I/O: Input/Output
Rev.2.40 Aug 25, 2006 page 12 of 88
REJ03B0003-0240
M16C/6N Group (M16C/6N4) 2. Central Processing Unit (CPU)
Under development
This document is under development and its contents are subject to change.
Figure 2.1 CPU Registers
2.1 Data Registers (R0, R1, R2, and R3)
The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to
R3 are the same as R0.
The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers.
R1H and R1L are the same as R0H and R0L. Conversely R2 and R0 can be combined for use as a 32-bit
data register (R2R0). R3R1 is analogous to R2R0.
2.2 Address Registers (A0 and A1)
The A0 register consists of 16 bits, and is used for address register indirect addressing and address
register relative addressing. They also are used for transfers and arithmetic/logic operations. A1 is the
same as A0.
In some instructions, A1 and A0 can be combined for use as a 32-bit address register (A1A0).
2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU Registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1, and FB
configure a register bank. There are two register banks.
SB
USP
ISP
b15 b0
Static Base Register
User Stack Pointer
Interrupt Stack Pointer
b19 b15
INTBLINTBH
The upper 4 bits of INTB are INTBH and the lower 16 bits of INTB are INTBL.
b0
Interrupt Table Register
b19
PC
b0
Program Counter
R0H (R0's high bits) R0L (R0's low bits)
R1H (R1's high bits) R1L (R1's low bits)
R2
R3
b31 b15 b8 b7 b0
R2
R3
A0
A1
FB
Data Registers
(1)
Address Registers
(1)
Frame Base Registers
(1)
NOTE:
1. These registers comprise a register bank. There are two register banks.
b15 b0
Carry Flag
Debug Flag
Zero Flag
Sign Flag
Register Bank Select Flag
Overflow Flag
Interrupt Enable Flag
Stack Pointer Select Flag
Reserved Area
Processor Interrupt Priority Level
Reserved Area
b15 b0
FLG Flag Register
IPL U I O B S Z D C
b7b8
Rev.2.40 Aug 25, 2006 page 13 of 88
REJ03B0003-0240
M16C/6N Group (M16C/6N4) 2. Central Processing Unit (CPU)
Under development
This document is under development and its contents are subject to change.
2.3 Frame Base Register (FB)
FB is configured with 16 bits, and is used for FB relative addressing.
2.4 Interrupt Table Register (INTB)
INTB is configured with 20 bits, indicating the start address of an interrupt vector table.
2.5 Program Counter (PC)
PC is configured with 20 bits, indicating the address of an instruction to be executed.
2.6 User Stack Pointer (USP), Interrupt Stack Pointer (ISP)
Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits.
Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG.
2.7 Static Base Register (SB)
SB is configured with 16 bits, and is used for SB relative addressing.
2.8 Flag Register (FLG)
FLG consists of 11 bits, indicating the CPU status.
2.8.1 Carry Flag (C Flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
2.8.2 Debug Flag (D Flag)
This flag is used exclusively for debugging purpose. During normal use, set to 0.
2.8.3 Zero Flag (Z Flag)
This flag is set to 1 when an arithmetic operation resulted in 0; otherwise, it is 0.
2.8.4 Sign Flag (S Flag)
This flag is set to 1 when an arithmetic operation resulted in a negative value; otherwise, it is 0.
2.8.5 Register Bank Select Flag (B Flag)
Register bank 0 is selected when this flag is 0; register bank 1 is selected when this flag is 1.
2.8.6 Overflow Flag (O Flag)
This flag is set to 1 when the operation resulted in an overflow; otherwise, it is 0.
2.8.7 Interrupt Enable Flag (I Flag)
This flag enables a maskable interrupt.
Maskable interrupts are disabled when the I flag is 0, and are enabled when the I flag is 1. The I flag is set
to 0 when the interrupt request is accepted.
2.8.8 Stack Pointer Select Flag (U Flag)
ISP is selected when the U flag is 0; USP is selected when the U flag is 1.
The U flag is set to 0 when a hardware interrupt request is accepted or an INT instruction for software
interrupt Nos. 0 to 31 is executed.
2.8.9 Processor Interrupt Priority Level (IPL)
IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from level
0 to level 7.
If a requested interrupt has priority greater than IPL, the interrupt request is enabled.
2.8.10 Reserved Area
When white to this bit, write 0. When read, its content is undefined.
Rev.2.40 Aug 25, 2006 page 14 of 88
REJ03B0003-0240
M16C/6N Group (M16C/6N4) 3. Memory
Under development
This document is under development and its contents are subject to change.
3. Memory
Figure 3.1 shows a Memory Map. The address space extends the 1 Mbyte from address 00000h to FFFFFh.
The internal ROM is allocated in a lower address direction beginning with address FFFFFh. For example, a
128-Kbyte internal ROM is allocated to the addresses from E0000h to FFFFFh.
As for the flash memory version, 4-Kbyte space (block A) exists in 0F000h to 0FFFFh. 4-Kbyte space is
mainly for storing data. In addition to storing data, 4-Kbyte space also can store programs.
The fixed interrupt vector table is allocated to the addresses from FFFDCh to FFFFFh. Therefore, store the
start address of each interrupt routine here.
The internal RAM is allocated in an upper address direction beginning with address 00400h. For example, a
5-Kbyte internal RAM is allocated to the addresses from 00400h to 017FFh. In addition to storing data, the
internal RAM also stores the stack used when calling subroutines and when interrupts are generated.
The Special Function Registers (SFRs) are allocated to the addresses from 00000h to 003FFh. Peripheral
function control registers are located here. Of the SFR, any area which has no functions allocated is reserved
for future use and cannot be accessed by user.
The special page vector table is allocated to the addresses from FFE00h to FFFDBh. This vector is used by
the JMPS or JSRS instruction. For details, refer to M16C/60, M16C/20, M16C/Tiny Series Software Manual.
In memory expansion and microprocessor modes, some areas are reserved for future use and cannot be
used by users.
Figure 3.1 Memory Map
00000h
YYYYY
h
FFFFFh
00400h
0FFFFh
10000h
0F000h
27000h
28000h
80000h
XXXXX
h
Internal ROM
(data flash) (3)
Internal ROM
(program area) (4)
SFR
Internal RAM
Reserved area
External area
Reserved area (2)
External area
FFE00h
FFFDCh
FFFFFh
NOTES:
1. During memory expansion mode or microprocessor mode, cannot be used.
2. In memory expansion mode, cannot be used.
3. As for the flash memory version, 4-Kbyte space (block A) exists.
4. When using the masked ROM version, write nothing to internal ROM area.
5. Shown here is a memory map for the case where the PM10 bit in the PM1 register is 1 (block A enabled, addresses 10000h to
26FFFh for CS2 area) and the PM13 bit in the PM1 register is 1 (internal RAM area is expanded over 192 Kbytes).
Undefined instruction
Overflow
BRK instruction
Address match
Single step
Oscillation stop and re-oscillation
detection / watchdog timer
Reset
Special page
vector table
DBC
NMI
Address XXXXX
h
Capacity
Internal RAM
10 Kbytes 02BFF
h
5 Kbytes 017FF
h
Address YYYYY
h
Capacity
Internal ROM (4)
256 Kbytes C0000
h
128 Kbytes E0000
h
Reserved area (1)
Rev.2.40 Aug 25, 2006 page 15 of 88
REJ03B0003-0240
M16C/6N Group (M16C/6N4) 4. Special Function Registers (SFRs)
Under development
This document is under development and its contents are subject to change.
4. Special Function Registers (SFRs)
An SFR (Special Function Register) is a control register for a peripheral function.
Tables 4.1 to 4.16 list the SFR Information.
Table 4.1 SFR Information (1) (3)
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h
0024h
0025h
0026h
0027h
0028h
0029h
002Ah
002Bh
002Ch
002Dh
002Eh
002Fh
0030h
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
Processor Mode Register 0
(1)
Processor Mode Register 1
System Clock Control Register 0
System Clock Control Register 1
Chip Select Control Register
Address Match Interrupt Enable Register
Protect Register
Oscillation Stop Detection Register
(2)
Watchdog Timer Start Register
Watchdog Timer Control Register
Address Match Interrupt Register 0
Address Match Interrupt Register 1
Chip Select Expansion Control Register
PLL Control Register 0
Processor Mode Register 2
DMA0 Source Pointer
DMA0 Destination Pointer
DMA0 Transfer Counter
DMA0 Control Register
DMA1 Source Pointer
DMA1 Destination Pointer
DMA1 Transfer Counter
DMA1 Control Register
PM0
PM1
CM0
CM1
CSR
AIER
PRCR
CM2
WDTS
WDC
RMAD0
RMAD1
CSE
PLC0
PM2
SAR0
DAR0
TCR0
DM0CON
SAR1
DAR1
TCR1
DM1CON
X: Undefined
NOTES:
1. Bits PM00 and PM01 in the PM0 register do not change at software reset, watchdog timer reset and oscillation stop detection reset.
2. Bits CM20, CM21, and CM27 in the CM2 register do not change at oscillation stop detection reset.
3. Blank spaces are reserved. No access is allowed.
Address Register Symbol After Reset
00000000b (CNVSS pin is "L")
00000011b (CNVSS pin is "H")
00001000b
01001000b
00100000b
00000001b
XXXXXX00b
XX000000b
0X000000b
XXh
00XXXXXXb
00h
00h
X0h
00h
00h
X0h
00h
0001X010b
XXX00000b
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
00000X00b
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
00000X00b
Rev.2.40 Aug 25, 2006 page 16 of 88
REJ03B0003-0240
M16C/6N Group (M16C/6N4) 4. Special Function Registers (SFRs)
Under development
This document is under development and its contents are subject to change.
Table 4.2 SFR Information (2) (1)
X: Undefined
NOTE:
1. Blank space is reserved. No access is allowed.
XXXXX000b
XXXXX000b
XXXXX000b
XX00X000b
XXXXX000b
XXXXX000b
XXXXX000b
XX00X000b
XX00X000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XX00X000b
XX00X000b
XX00X000b
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
CAN0/1 Wake-up Interrupt Control Register
CAN0 Successful Reception Interrupt Control Register
CAN0 Successful Transmission Interrupt Control Register
INT3 Interrupt Control Register
Timer B5 Interrupt Control Register
Timer B4 Interrupt Control Register
UART1 Bus Collision Detection Interrupt Control Register
Timer B3 Interrupt Control Register
UART0 Bus Collision Detection Interrupt Control Register
CAN1 Successful Reception Interrupt Control Register
INT5 Interrupt Control Register
CAN1 Successful Transmission Interrupt Control Register
SI/O3 Interrupt Control Register
INT4 Interrupt Control Register
UART2 Bus Collision Detection Interrupt Control Register
DMA0 Interrupt Control Register
DMA1 Interrupt Control Register
CAN0/1 Error Interrupt Control Register
A/D Conversion Interrupt Control Register
Key Input Interrupt Control Register
UART2 Transmit Interrupt Control Register
UART2 Receive Interrupt Control Register
UART0 Transmit Interrupt Control Register
UART0 Receive Interrupt Control Register
UART1 Transmit Interrupt Control Register
UART1 Receive Interrupt Control Register
Timer A0 Interrupt Control Register
Timer A1 Interrupt Control Register
Timer A2 Interrupt Control Register
Timer A3 Interrupt Control Register
Timer A4 Interrupt Control Register
Timer B0 Interrupt Control Register
Timer B1 Interrupt Control Register
Timer B2 Interrupt Control Register
INT0 Interrupt Control Register
INT1 Interrupt Control Register
INT2 Interrupt Control Register
CAN0 Message Box 0: Identifier / DLC
CAN0 Message Box 0: Data Field
CAN0 Message Box 0: Time Stamp
CAN0 Message Box 1: Identifier / DLC
CAN0 Message Box 1: Data Field
CAN0 Message Box 1: Time Stamp
0040h
0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh
0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h
0058h
0059h
005Ah
005Bh
005Ch
005Dh
005Eh
005Fh
0060h
0061h
0062h
0063h
0064h
0065h
0066h
0067h
0068h
0069h
006Ah
006Bh
006Ch
006Dh
006Eh
006Fh
0070h
0071h
0072h
0073h
0074h
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
007Eh
007Fh
C01WKIC
C0RECIC
C0TRMIC
INT3IC
TB5IC
TB4IC
U1BCNIC
TB3IC
U0BCNIC
C1RECIC
INT5IC
C1TRMIC
S3IC
INT4IC
U2BCNIC
DM0IC
DM1IC
C01ERRIC
ADIC
KUPIC
S2TIC
S2RIC
S0TIC
S0RIC
S1TIC
S1RIC
TA0IC
TA1IC
TA2IC
TA3IC
TA4IC
TB0IC
TB1IC
TB2IC
INT0IC
INT1IC
INT2IC
Address Register Symbol After Reset
Rev.2.40 Aug 25, 2006 page 17 of 88
REJ03B0003-0240
M16C/6N Group (M16C/6N4) 4. Special Function Registers (SFRs)
Under development
This document is under development and its contents are subject to change.
Table 4.3 SFR Information (3)
X: Undefined
0080h
0081h
0082h
0083h
0084h
0085h
0086h
0087h
0088h
0089h
008Ah
008Bh
008Ch
008Dh
008Eh
008Fh
0090h
0091h
0092h
0093h
0094h
0095h
0096h
0097h
0098h
0099h
009Ah
009Bh
009Ch
009Dh
009Eh
009Fh
00A0h
00A1h
00A2h
00A3h
00A4h
00A5h
00A6h
00A7h
00A8h
00A9h
00AAh
00ABh
00ACh
00ADh
00AEh
00AFh
00B0h
00B1h
00B2h
00B3h
00B4h
00B5h
00B6h
00B7h
00B8h
00B9h
00BAh
00BBh
00BCh
00BDh
00BEh
00BFh
CAN0 Message Box 2: Identifier / DLC
CAN0 Message Box 2: Data Field
CAN0 Message Box 2: Time Stamp
CAN0 Message Box 3: Identifier / DLC
CAN0 Message Box 3: Data Field
CAN0 Message Box 3: Time Stamp
CAN0 Message Box 4: Identifier / DLC
CAN0 Message Box 4: Data Field
CAN0 Message Box 4: Time Stamp
CAN0 Message Box 5: Identifier / DLC
CAN0 Message Box 5: Data Field
CAN0 Message Box 5: Time Stamp
Address Register Symbol After Reset
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
Rev.2.40 Aug 25, 2006 page 18 of 88
REJ03B0003-0240
M16C/6N Group (M16C/6N4) 4. Special Function Registers (SFRs)
Under development
This document is under development and its contents are subject to change.
Table 4.4 SFR Information (4)
X: Undefined
00C0h
00C1h
00C2h
00C3h
00C4h
00C5h
00C6h
00C7h
00C8h
00C9h
00CAh
00CBh
00CCh
00CDh
00CEh
00CFh
00D0h
00D1h
00D2h
00D3h
00D4h
00D5h
00D6h
00D7h
00D8h
00D9h
00DAh
00DBh
00DCh
00DDh
00DEh
00DFh
00E0h
00E1h
00E2h
00E3h
00E4h
00E5h
00E6h
00E7h
00E8h
00E9h
00EAh
00EBh
00ECh
00EDh
00EEh
00EFh
00F0h
00F1h
00F2h
00F3h
00F4h
00F5h
00F6h
00F7h
00F8h
00F9h
00FAh
00FBh
00FCh
00FDh
00FEh
00FFh
CAN0 Message Box 6: Identifier / DLC
CAN0 Message Box 6: Data Field
CAN0 Message Box 6: Time Stamp
CAN0 Message Box 7: Identifier / DLC
CAN0 Message Box 7: Data Field
CAN0 Message Box 7: Time Stamp
CAN0 Message Box 8: Identifier / DLC
CAN0 Message Box 8: Data Field
CAN0 Message Box 8: Time Stamp
CAN0 Message Box 9: Identifier / DLC
CAN0 Message Box 9: Data Field
CAN0 Message Box 9: Time Stamp
Address Register Symbol After Reset
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
Rev.2.40 Aug 25, 2006 page 19 of 88
REJ03B0003-0240
M16C/6N Group (M16C/6N4) 4. Special Function Registers (SFRs)
Under development
This document is under development and its contents are subject to change.
Table 4.5 SFR Information (5)
X: Undefined
0100h
0101h
0102h
0103h
0104h
0105h
0106h
0107h
0108h
0109h
010Ah
010Bh
010Ch
010Dh
010Eh
010Fh
0110h
0111h
0112h
0113h
0114h
0115h
0116h
0117h
0118h
0119h
011Ah
011Bh
011Ch
011Dh
011Eh
011Fh
0120h
0121h
0122h
0123h
0124h
0125h
0126h
0127h
0128h
0129h
012Ah
012Bh
012Ch
012Dh
012Eh
012Fh
0130h
0131h
0132h
0133h
0134h
0135h
0136h
0137h
0138h
0139h
013Ah
013Bh
013Ch
013Dh
013Eh
013Fh
CAN0 Message Box 10: Identifier / DLC
CAN0 Message Box 10: Data Field
CAN0 Message Box 10: Time Stamp
CAN0 Message Box 11: Identifier / DLC
CAN0 Message Box 11: Data Field
CAN0 Message Box 11: Time Stamp
CAN0 Message Box 12: Identifier / DLC
CAN0 Message Box 12: Data Field
CAN0 Message Box 12: Time Stamp
CAN0 Message Box 13: Identifier / DLC
CAN0 Message Box 13: Data Field
CAN0 Message Box 13: Time Stamp
Address Register Symbol After Reset
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
Rev.2.40 Aug 25, 2006 page 20 of 88
REJ03B0003-0240
M16C/6N Group (M16C/6N4) 4. Special Function Registers (SFRs)
Under development
This document is under development and its contents are subject to change.
Table 4.6 SFR Information (6) (1)
X: Undefined
NOTE:
1. Blank spaces are reserved. No access is allowed.
0140h
0141h
0142h
0143h
0144h
0145h
0146h
0147h
0148h
0149h
014Ah
014Bh
014Ch
014Dh
014Eh
014Fh
0150h
0151h
0152h
0153h
0154h
0155h
0156h
0157h
0158h
0159h
015Ah
015Bh
015Ch
015Dh
015Eh
015Fh
0160h
0161h
0162h
0163h
0164h
0165h
0166h
0167h
0168h
0169h
016Ah
016Bh
016Ch
016Dh
016Eh
016Fh
0170h
0171h
0172h
0173h
0174h
0175h
0176h
0177h
0178h
0179h
017Ah
017Bh
017Ch
017Dh
017Eh
017Fh
CAN0 Message Box 14: Identifier /DLC
CAN0 Message Box 14: Data Field
CAN0 Message Box 14: Time Stamp
CAN0 Message Box 15: Identifier /DLC
CAN0 Message Box 15: Data Field
CAN0 Message Box 15: Time Stamp
CAN0 Global Mask Register
CAN0 Local Mask A Register
CAN0 Local Mask B Register
Address Register Symbol After Reset
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C0GMR
C0LMAR
C0LMBR
Rev.2.40 Aug 25, 2006 page 21 of 88
REJ03B0003-0240
M16C/6N Group (M16C/6N4) 4. Special Function Registers (SFRs)
Under development
This document is under development and its contents are subject to change.
Table 4.7 SFR Information (7) (2)
X: Undefined
NOTES:
1. These registers are included in the flash memory version. Cannot be accessed by users in the mask ROM version.
2. Blank spaces are reserved. No access is allowed.
0180h
0181h
0182h
0183h
0184h
0185h
0186h
0187h
0188h
0189h
018Ah
018Bh
018Ch
018Dh
018Eh
018Fh
0190h
0191h
0192h
0193h
0194h
0195h
0196h
0197h
0198h
0199h
019Ah
019Bh
019Ch
019Dh
019Eh
019Fh
01A0h
01A1h
01A2h
01A3h
01A4h
01A5h
01A6h
01A7h
01A8h
01A9h
01AAh
01ABh
01ACh
01ADh
01AEh
01AFh
01B0h
01B1h
01B2h
01B3h
01B4h
01B5h
01B6h
01B7h
01B8h
01B9h
01BAh
01BBh
01BCh
01BDh
01BEh
01BFh
Flash Memory Control Register 1
(1)
Flash Memory Control Register 0
(1)
Address Match Interrupt Register 2
Address Match Interrupt Enable Register 2
Address Match Interrupt Register 3
FMR1
FMR0
RMAD2
AIER2
RMAD3
Address Register Symbol After Reset
0X00XX0Xb
00000001b
00h
00h
X0h
XXXXXX00b
00h
00h
X0h
Rev.2.40 Aug 25, 2006 page 22 of 88
REJ03B0003-0240
M16C/6N Group (M16C/6N4) 4. Special Function Registers (SFRs)
Under development
This document is under development and its contents are subject to change.
Table 4.8 SFR Information (8) (1)
Timer B3, B4, B5 Count Start Flag
Timer A1-1 Register
Timer A2-1 Register
Timer A4-1 Register
Three-Phase PWM Control Register 0
Three-Phase PWM Control Register 1
Three-Phase Output Buffer Register 0
Three-Phase Output Buffer Register 1
Dead Time Timer
Timer B2 Interrupt Generation Frequency Set Counter
Timer B3 Register
Timer B4 Register
Timer B5 Register
Timer B3 Mode Register
Timer B4 Mode Register
Timer B5 Mode Register
Interrupt Source Select Register 0
Interrupt Source Select Register 1
SI/O3 Transmit/Receive Register
SI/O3 Control Register
SI/O3 Bit Rate Register
UART0 Special Mode Register 4
UART0 Special Mode Register 3
UART0 Special Mode Register 2
UART0 Special Mode Register
UART1 Special Mode Register 4
UART1 Special Mode Register 3
UART1 Special Mode Register 2
UART1 Special Mode Register
UART2 Special Mode Register 4
UART2 Special Mode Register 3
UART2 Special Mode Register 2
UART2 Special Mode Register
UART2 Transmit/Receive Mode Register
UART2 Bit Rate Register
UART2 Transmit Buffer Register
UART2 Transmit/Receive Control Register 0
UART2 Transmit/Receive Control Register 1
UART2 Receive Buffer Register
01C0h
01C1h
01C2h
01C3h
01C4h
01C5h
01C6h
01C7h
01C8h
01C9h
01CAh
01CBh
01CCh
01CDh
01CEh
01CFh
01D0h
01D1h
01D2h
01D3h
01D4h
01D5h
01D6h
01D7h
01D8h
01D9h
01DAh
01DBh
01DCh
01DDh
01DEh
01DFh
01E0h
01E1h
01E2h
01E3h
01E4h
01E5h
01E6h
01E7h
01E8h
01E9h
01EAh
01EBh
01ECh
01EDh
01EEh
01EFh
01F0h
01F1h
01F2h
01F3h
01F4h
01F5h
01F6h
01F7h
01F8h
01F9h
01FAh
01FBh
01FCh
01FDh
01FEh
01FFh
Address Register Symbol After Reset
TBSR
TA11
TA21
TA41
INVC0
INVC1
IDB0
IDB1
DTT
ICTB2
TB3
TB4
TB5
TB3MR
TB4MR
TB5MR
IFSR0
IFSR1
S3TRR
S3C
S3BRG
U0SMR4
U0SMR3
U0SMR2
U0SMR
U1SMR4
U1SMR3
U1SMR2
U1SMR
U2SMR4
U2SMR3
U2SMR2
U2SMR
U2MR
U2BRG
U2TB
U2C0
U2C1
U2RB
000XXXXXb
XXh
XXh
XXh
XXh
XXh
XXh
00h
00h
00111111b
00111111b
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
00XX0000b
00XX0000b
00XX0000b
00XXX000b
00h
XXh
01000000b
XXh
00h
000X0X0Xb
X0000000b
X0000000b
00h
000X0X0Xb
X0000000b
X0000000b
00h
000X0X0Xb
X0000000b
X0000000b
00h
XXh
XXh
XXh
00001000b
00000010b
XXh
XXh
X: Undefined
NOTE:
1. Blank spaces are reserved. No access is allowed.
Rev.2.40 Aug 25, 2006 page 23 of 88
REJ03B0003-0240
M16C/6N Group (M16C/6N4) 4. Special Function Registers (SFRs)
Under development
This document is under development and its contents are subject to change.
X: Undefined
0200h
0201h
0202h
0203h
0204h
0205h
0206h
0207h
0208h
0209h
020Ah
020Bh
020Ch
020Dh
020Eh
020Fh
0210h
0211h
0212h
0213h
0214h
0215h
0216h
0217h
0218h
0219h
021Ah
021Bh
021Ch
021Dh
021Eh
021Fh
0220h
0221h
0222h
0223h
0224h
0225h
0226h
0227h
0228h
0229h
022Ah
022Bh
022Ch
022Dh
022Eh
022Fh
0230h
0231h
0232h
0233h
0234h
0235h
0236h
0237h
0238h
0239h
023Ah
023Bh
023Ch
023Dh
023Eh
023Fh
CAN0 Message Control Register 0
CAN0 Message Control Register 1
CAN0 Message Control Register 2
CAN0 Message Control Register 3
CAN0 Message Control Register 4
CAN0 Message Control Register 5
CAN0 Message Control Register 6
CAN0 Message Control Register 7
CAN0 Message Control Register 8
CAN0 Message Control Register 9
CAN0 Message Control Register 10
CAN0 Message Control Register 11
CAN0 Message Control Register 12
CAN0 Message Control Register 13
CAN0 Message Control Register 14
CAN0 Message Control Register 15
CAN0 Control Register
CAN0 Status Register
CAN0 Slot Status Register
CAN0 Interrupt Control Register
CAN0 Extended ID Register
CAN0 Configuration Register
CAN0 Receive Error Count Register
CAN0 Transmit Error Count Register
CAN0 Time Stamp Register
CAN1 Message Control Register 0
CAN1 Message Control Register 1
CAN1 Message Control Register 2
CAN1 Message Control Register 3
CAN1 Message Control Register 4
CAN1 Message Control Register 5
CAN1 Message Control Register 6
CAN1 Message Control Register 7
CAN1 Message Control Register 8
CAN1 Message Control Register 9
CAN1 Message Control Register 10
CAN1 Message Control Register 11
CAN1 Message Control Register 12
CAN1 Message Control Register 13
CAN1 Message Control Register 14
CAN1 Message Control Register 15
CAN1 Control Register
CAN1 Status Register
CAN1 Slot Status Register
CAN1 Interrupt Control Register
CAN1 Extended ID Register
CAN1 Configuration Register
CAN1 Receive Error Count Register
CAN1 Transmit Error Count Register
CAN1 Time Stamp Register
C0MCTL0
C0MCTL1
C0MCTL2
C0MCTL3
C0MCTL4
C0MCTL5
C0MCTL6
C0MCTL7
C0MCTL8
C0MCTL9
C0MCTL10
C0MCTL11
C0MCTL12
C0MCTL13
C0MCTL14
C0MCTL15
C0CTLR
C0STR
C0SSTR
C0ICR
C0IDR
C0CONR
C0RECR
C0TECR
C0TSR
C1MCTL0
C1MCTL1
C1MCTL2
C1MCTL3
C1MCTL4
C1MCTL5
C1MCTL6
C1MCTL7
C1MCTL8
C1MCTL9
C1MCTL10
C1MCTL11
C1MCTL12
C1MCTL13
C1MCTL14
C1MCTL15
C1CTLR
C1STR
C1SSTR
C1ICR
C1IDR
C1CONR
C1RECR
C1TECR
C1TSR
Address Register Symbol After Reset
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
X0000001b
XX0X0000b
00h
X0000001b
00h
00h
00h
00h
00h
00h
XXh
XXh
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
X0000001b
XX0X0000b
00h
X0000001b
00h
00h
00h
00h
00h
00h
XXh
XXh
00h
00h
00h
00h
Table 4.9 SFR Information (9)
Rev.2.40 Aug 25, 2006 page 24 of 88
REJ03B0003-0240
M16C/6N Group (M16C/6N4) 4. Special Function Registers (SFRs)
Under development
This document is under development and its contents are subject to change.
X: Undefined
NOTE:
1. Blank spaces are reserved. No access is allowed.
XXh
XXh
XXh
XXh
00h
00h
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
CAN0 Acceptance Filter Support Register
CAN1 Acceptance Filter Support Register
Peripheral Clock Select Register
CAN0/1 Clock Select Register
CAN1 Message Box 0: Identifier / DLC
CAN1 Message Box 0: Data Field
CAN1 Message Box 0:Time Stamp
CAN1 Message Box 1: Identifier / DLC
CAN1 Message Box 1: Data Field
CAN1 Message Box 1:Time Stamp
0240h
0241h
0242h
0243h
0244h
0245h
0246h
0247h
0248h
0249h
024Ah
024Bh
024Ch
024Dh
024Eh
024Fh
0250h
0251h
0252h
0253h
0254h
0255h
0256h
0257h
0258h
0259h
025Ah
025Bh
025Ch
025Dh
025Eh
025Fh
0260h
0261h
0262h
0263h
0264h
0265h
0266h
0267h
0268h
0269h
026Ah
026Bh
026Ch
026Dh
026Eh
026Fh
0270h
0271h
0272h
0273h
0274h
0275h
0276h
0277h
0278h
0279h
027Ah
027Bh
027Ch
027Dh
027Eh
027Fh
C0AFS
C1AFS
PCLKR
CCLKR
Address Register Symbol After Reset
Table 4.10 SFR Information (10) (1)
Rev.2.40 Aug 25, 2006 page 25 of 88
REJ03B0003-0240
M16C/6N Group (M16C/6N4) 4. Special Function Registers (SFRs)
Under development
This document is under development and its contents are subject to change.
Table 4.11 SFR Information (11)
X: Undefined
0280h
0281h
0282h
0283h
0284h
0285h
0286h
0287h
0288h
0289h
028Ah
028Bh
028Ch
028Dh
028Eh
028Fh
0290h
0291h
0292h
0293h
0294h
0295h
0296h
0297h
0298h
0299h
029Ah
029Bh
029Ch
029Dh
029Eh
029Fh
02A0h
02A1h
02A2h
02A3h
02A4h
02A5h
02A6h
02A7h
02A8h
02A9h
02AAh
02ABh
02ACh
02ADh
02AEh
02AFh
02B0h
02B1h
02B2h
02B3h
02B4h
02B5h
02B6h
02B7h
02B8h
02B9h
02BAh
02BBh
02BCh
02BDh
02BEh
02BFh
CAN1 Message Box 2: Identifier / DLC
CAN1 Message Box 2: Data Field
CAN1 Message Box 2: Time Stamp
CAN1 Message Box 3: Identifier / DLC
CAN1 Message Box 3: Data Field
CAN1 Message Box 3: Time Stamp
CAN1 Message Box 4: Identifier / DLC
CAN1 Message Box 4: Data Field
CAN1 Message Box 4: Time Stamp
CAN1 Message Box 5: Identifier / DLC
CAN1 Message Box 5: Data Field
CAN1 Message Box 5: Time Stamp
Address Register Symbol After Reset
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
Rev.2.40 Aug 25, 2006 page 26 of 88
REJ03B0003-0240
M16C/6N Group (M16C/6N4) 4. Special Function Registers (SFRs)
Under development
This document is under development and its contents are subject to change.
Table 4.12 SFR Information (12)
X: Undefined
02C0h
02C1h
02C2h
02C3h
02C4h
02C5h
02C6h
02C7h
02C8h
02C9h
02CAh
02CBh
02CCh
02CDh
02CEh
02CFh
02D0h
02D1h
02D2h
02D3h
02D4h
02D5h
02D6h
02D7h
02D8h
02D9h
02DAh
02DBh
02DCh
02DDh
02DEh
02DFh
02E0h
02E1h
02E2h
02E3h
02E4h
02E5h
02E6h
02E7h
02E8h
02E9h
02EAh
02EBh
02ECh
02EDh
02EEh
02EFh
02F0h
02F1h
02F2h
02F3h
02F4h
02F5h
02F6h
02F7h
02F8h
02F9h
02FAh
02FBh
02FCh
02FDh
02FEh
02FFh
CAN1 Message Box 6: Identifier / DLC
CAN1 Message Box 6: Data Field
CAN1 Message Box 6: Time Stamp
CAN1 Message Box 7: Identifier / DLC
CAN1 Message Box 7: Data Field
CAN1 Message Box 7: Time Stamp
CAN1 Message Box 8: Identifier / DLC
CAN1 Message Box 8: Data Field
CAN1 Message Box 8: Time Stamp
CAN1 Message Box 9: Identifier / DLC
CAN1 Message Box 9: Data Field
CAN1 Message Box 9: Time Stamp
Address Register Symbol After Reset
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
Rev.2.40 Aug 25, 2006 page 27 of 88
REJ03B0003-0240
M16C/6N Group (M16C/6N4) 4. Special Function Registers (SFRs)
Under development
This document is under development and its contents are subject to change.
Table 4.13 SFR Information (13)
X: Undefined
0300h
0301h
0302h
0303h
0304h
0305h
0306h
0307h
0308h
0309h
030Ah
030Bh
030Ch
030Dh
030Eh
030Fh
0310h
0311h
0312h
0313h
0314h
0315h
0316h
0317h
0318h
0319h
031Ah
031Bh
031Ch
031Dh
031Eh
031Fh
0320h
0321h
0322h
0323h
0324h
0325h
0326h
0327h
0328h
0329h
032Ah
032Bh
032Ch
032Dh
032Eh
032Fh
0330h
0331h
0332h
0333h
0334h
0335h
0336h
0337h
0338h
0339h
033Ah
033Bh
033Ch
033Dh
033Eh
033Fh
CAN1 Message Box 10: Identifier / DLC
CAN1 Message Box 10: Data Field
CAN1 Message Box 10: Time Stamp
CAN1 Message Box 11: Identifier / DLC
CAN1 Message Box 11: Data Field
CAN1 Message Box 11: Time Stamp
CAN1 Message Box 12: Identifier / DLC
CAN1 Message Box 12: Data Field
CAN1 Message Box 12: Time Stamp
CAN1 Message Box 13: Identifier / DLC
CAN1 Message Box 13: Data Field
CAN1 Message Box 13: Time Stamp
Address Register Symbol After Reset
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
Rev.2.40 Aug 25, 2006 page 28 of 88
REJ03B0003-0240
M16C/6N Group (M16C/6N4) 4. Special Function Registers (SFRs)
Under development
This document is under development and its contents are subject to change.
Table 4.14 SFR Information (14) (1)
X: Undefined
NOTE:
1. Blank spaces are reserved. No access is allowed.
0340h
0341h
0342h
0343h
0344h
0345h
0346h
0347h
0348h
0349h
034Ah
034Bh
034Ch
034Dh
034Eh
034Fh
0350h
0351h
0352h
0353h
0354h
0355h
0356h
0357h
0358h
0359h
035Ah
035Bh
035Ch
035Dh
035Eh
035Fh
0360h
0361h
0362h
0363h
0364h
0365h
0366h
0367h
0368h
0369h
036Ah
036Bh
036Ch
036Dh
036Eh
036Fh
0370h
0371h
0372h
0373h
0374h
0375h
0376h
0377h
0378h
0379h
037Ah
037Bh
037Ch
037Dh
037Eh
037Fh
CAN1 Message Box 14: Identifier / DLC
CAN1 Message Box 14: Data Field
CAN1 Message Box 14: Time Stamp
CAN1 Message Box 15: Identifier / DLC
CAN1 Message Box 15: Data Field
CAN1 Message Box 15: Time Stamp
CAN1 Global Mask Register
CAN1 Local Mask A Register
CAN1 Local Mask B Register
Address Register Symbol After Reset
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
C1GMR
C1LMAR
C1LMBR
Rev.2.40 Aug 25, 2006 page 29 of 88
REJ03B0003-0240
M16C/6N Group (M16C/6N4) 4. Special Function Registers (SFRs)
Under development
This document is under development and its contents are subject to change.
X: Undefined
NOTES:
1. Bits TA2P to TA4P in the UDF register are set to 0 after reset. However, the contents in these bits are undefined when read.
2. Blank spaces are reserved. No access is allowed.
0380h
0381h
0382h
0383h
0384h
0385h
0386h
0387h
0388h
0389h
038Ah
038Bh
038Ch
038Dh
038Eh
038Fh
0390h
0391h
0392h
0393h
0394h
0395h
0396h
0397h
0398h
0399h
039Ah
039Bh
039Ch
039Dh
039Eh
039Fh
03A0h
03A1h
03A2h
03A3h
03A4h
03A5h
03A6h
03A7h
03A8h
03A9h
03AAh
03ABh
03ACh
03ADh
03AEh
03AFh
03B0h
03B1h
03B2h
03B3h
03B4h
03B5h
03B6h
03B7h
03B8h
03B9h
03BAh
03BBh
03BCh
03BDh
03BEh
03BFh
Count Start Flag
Clock Prescaler Reset Flag
One-Shot Start Flag
Trigger Select Register
Up/Down Flag
Timer A0 Register
Timer A1 Register
Timer A2 Register
Timer A3 Register
Timer A4 Register
Timer B0 Register
Timer B1 Register
Timer B2 Register
Timer A0 Mode Register
Timer A1 Mode Register
Timer A2 Mode Register
Timer A3 Mode Register
Timer A4 Mode Register
Timer B0 Mode Register
Timer B1 Mode Register
Timer B2 Mode Register
Timer B2 Special Mode Register
UART0 Transmit/Receive Mode Register
UART0 Bit Rate Register
UART0 Transmit Buffer Register
UART0 Transmit/Receive Control Register 0
UART0 Transmit/Receive Control Register 1
UART0 Receive Buffer Register
UART1 Transmit/Receive Mode Register
UART1 Bit Rate Register
UART1 Transmit Buffer Register
UART1 Transmit/Receive Control Register 0
UART1 Transmit/Receive Control Register 1
UART1 Receive Buffer Register
UART Transmit/Receive Control Register 2
DMA0 Request Source Select Register
DMA1 Request Source Select Register
CRC Data Register
CRC Input Register
TABSR
CPSRF
ONSF
TRGSR
UDF
TA0
TA1
TA2
TA3
TA4
TB0
TB1
TB2
TA0MR
TA1MR
TA2MR
TA3MR
TA4MR
TB0MR
TB1MR
TB2MR
TB2SC
U0MR
U0BRG
U0TB
U0C0
U0C1
U0RB
U1MR
U1BRG
U1TB
U1C0
U1C1
U1RB
UCON
DM0SL
DM1SL
CRCD
CRCIN
Address Register Symbol After Reset
00h
0XXXXXXXb
00h
00h
00h
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
00h
00h
00h
00h
00h
00XX0000b
00XX0000b
00XX0000b
XXXXXX00b
00h
XXh
XXh
XXh
00001000b
00XX0010b
XXh
XXh
00h
XXh
XXh
XXh
00001000b
00XX0010b
XXh
XXh
X0000000b
00h
00h
XXh
XXh
XXh
(1)
Table 4.15 SFR Information (15) (2)
Rev.2.40 Aug 25, 2006 page 30 of 88
REJ03B0003-0240
M16C/6N Group (M16C/6N4) 4. Special Function Registers (SFRs)
Under development
This document is under development and its contents are subject to change.
X: Undefined
NOTES:
1. At hardware reset, the register is as follows:
00000000b where "L" is input to the CNVSS pin
00000010b where "H" is input to the CNVSS pin
At software reset, watchdog timer reset and oscillation stop detection reset, the register is as follows:
00000000b where bits PM01 to PM00 in the PM0 register are 00b (single-chip mode)
00000010b where bits PM01 to PM00 in the PM0 register are 01b (memory expansion mode) or 11b (microprocessor mode)
2. Blank spaces are reserved. No access is allowed.
03C0h
03C1h
03C2h
03C3h
03C4h
03C5h
03C6h
03C7h
03C8h
03C9h
03CAh
03CBh
03CCh
03CDh
03CEh
03CFh
03D0h
03D1h
03D2h
03D3h
03D4h
03D5h
03D6h
03D7h
03D8h
03D9h
03DAh
03DBh
03DCh
03DDh
03DEh
03DFh
03E0h
03E1h
03E2h
03E3h
03E4h
03E5h
03E6h
03E7h
03E8h
03E9h
03EAh
03EBh
03ECh
03EDh
03EEh
03EFh
03F0h
03F1h
03F2h
03F3h
03F4h
03F5h
03F6h
03F7h
03F8h
03F9h
03FAh
03FBh
03FCh
03FDh
03FEh
03FFh
A/D Register 0
A/D Register 1
A/D Register 2
A/D Register 3
A/D Register 4
A/D Register 5
A/D Register 6
A/D Register 7
A/D Control Register 2
A/D Control Register 0
A/D Control Register 1
D/A Register 0
D/A Register 1
D/A Control Register
Port P0 Register
Port P1 Register
Port P0 Direction Register
Port P1 Direction Register
Port P2 Register
Port P3 Register
Port P2 Direction Register
Port P3 Direction Register
Port P4 Register
Port P5 Register
Port P4 Direction Register
Port P5 Direction Register
Port P6 Register
Port P7 Register
Port P6 Direction Register
Port P7 Direction Register
Port P8 Register
Port P9 Register
Port P8 Direction Register
Port P9 Direction Register
Port P10 Register
Port P10 Direction Register
Pull-up Control Register 0
Pull-up Control Register 1
Pull-up Control Register 2
Port Control Register
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
ADCON2
ADCON0
ADCON1
DA0
DA1
DACON
P0
P1
PD0
PD1
P2
P3
PD2
PD3
P4
P5
PD4
PD5
P6
P7
PD6
PD7
P8
P9
PD8
PD9
P10
PD10
PUR0
PUR1
PUR2
PCR
Address Register Symbol After Reset
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
00h
00000XXXb
00h
00h
00h
00h
XXh
XXh
00h
00h
XXh
XXh
00h
00h
XXh
XXh
00h
00h
XXh
XXh
00h
00h
XXh
XXh
00X00000b
00h
XXh
00h
00h
00000000b (1)
00000010b
00h
00h
Table 4.16 SFR Information (16) (2)
Rev.2.40 Aug 25, 2006 page 31 of 88
REJ03B0003-02400
M16C/6N Group (M16C/6N4) 5. Electric Characteristics (T/V-ver.)
Under development
This document is under development and its contents are subject to change.
5. Electrical Characteristics
5.1 Electrical Characteristics (T/V-ver.)
Table 5.1 Absolute Maximum Ratings
option: All options are on request basis.
VCC
AVCC
VI
VO
Pd
Topr
Tstg
V
V
V
V
V
V
mW
°C
°C
Unit
Supply voltage (VCC1 = VCC2)
Analog supply voltage
Input
voltage
Output
voltage
Power dissipation
Operating ambient During MCU operation
temperature
During flash memory program and
erase operation
Storage temperature
Symbol Parameter
_____________
RESET, CNVSS, BYTE,
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0, P7_2 to P7_7, P8_0 to P8_7,
P9_0, P9_2 to P9_7, P10_0 to P10_7,
VREF, XIN
P7_1, P9_1
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0, P7_2 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0, P9_2 to P9_7,
P10_0 to P10_7, XOUT
P7_1, P9_1
Rated Value
–0.3 to 6.5
–0.3 to 6.5
–0.3 to VCC+0.3
–0.3 to 6.5
–0.3 to VCC+0.3
–0.3 to 6.5
700
T version: –40 to 85
V version: –40 to 125
(option)
0 to 60
–65 to 150
Condition
VCC = AVCC
VCC = AVCC
Topr = 25°C
Rev.2.40 Aug 25, 2006 page 32 of 88
REJ03B0003-02400
M16C/6N Group (M16C/6N4) 5. Electric Characteristics (T/V-ver.)
Under development
This document is under development and its contents are subject to change.
Table 5.2 Recommended Operating Conditions (1) (1)
Supply voltage (VCC1 = VCC2)
Analog supply voltage
Supply voltage
Analog supply voltage
HIGH input
voltage
LOW input
voltage
HIGH peak
output current
HIGH average
output current
LOW peak
output current
LOW average
output current
P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7,
P7_0, P7_2 to P7_7, P8_0 to P8_7, P9_0, P9_2 to P9_7,
_____________
P10_0 to P10_7, XIN, RESET, CNVSS, BYTE
P7_1, P9_1
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0
(During single-chip mode)
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0
(Data input during memory expansion and microprocessor modes)
P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7,
P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7,
_____________
XIN, RESET, CNVSS, BYTE
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0
(During single-chip mode)
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0
(Data input during memory expansion and microprocessor modes)
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0,
P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0,
P9_2 to P9_7, P10_0 to P10_7
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0,
P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0,
P9_2 to P9_7, P10_0 to P10_7
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7
5.0
VCC
0
0
V
V
V
V
V
V
V
V
V
V
V
mA
mA
mA
mA
4.2
0.8 VCC
0.8 VCC
0.8 VCC
0.5 VCC
0
0
0
5.5
VCC
6.5
VCC
VCC
0.2 VCC
0.2 VCC
0.16 VCC
–10.0
–5.0
10.0
5.0
VCC
AVCC
VSS
AVSS
VIH
VIL
IOH(peak)
IOH(avg)
IOL(peak)
IOL(avg)
ParameterSymbol Typ.Min.
Standard Unit
Max.
NOTES:
1. Referenced to VCC = 4.2 to 5.5 V at Topr = –40 to 85°C unless otherwise specified.
2. Average output current values during 100 ms period.
3. The total IOL(peak) for ports P0, P1, P2, P8_6, P8_7, P9, and P10 must be 80 mA max.
The total IOL(peak) for ports P3, P4, P5, P6, P7, and P8_0 to P8_4 must be 80 mA max.
The total IOH(peak) for ports P0, P1, and P2 must be –40 mA max.
The total IOH(peak) for ports P3, P4, and P5 must be –40 mA max.
The total IOH(peak) for ports P6, P7, and P8_0 to P8_4 must be –40 mA max.
The total IOH(peak) for ports P8_6, P8_7, P9, and P10 must be –40 mA max.
Rev.2.40 Aug 25, 2006 page 33 of 88
REJ03B0003-02400
M16C/6N Group (M16C/6N4) 5. Electric Characteristics (T/V-ver.)
Under development
This document is under development and its contents are subject to change.
Table 5.3 Recommended Operating Conditions (2) (1)
Main clock input oscillation No wait Mask ROM version VCC = 4.2 to 5.5 V
frequency (2) (3) (4)
Flash memory version
Sub clock oscillation frequency
On-chip oscillation frequency
PLL clock oscillation frequency
CPU operation clock
VCC = 4.2 to 5.5 V
PLL frequency synthesizer stabilization wait time
32.768
1
MHz
kHz
MHz
MHz
MHz
ms
0
16
0
16
50
20
20
20
f(XIN)
f(XCIN)
f(Ring)
f(PLL)
f(BCLK)
tsu(PLL)
ParameterSymbol Typ.Min.
Standard Unit
Max.
NOTES:
1. Referenced to VCC = 4.2 to 5.5 V at Topr = –40 to 85°C unless
otherwise specified.
2. Relationship between main clock oscillation frequency and supply
voltage is shown right.
3. Execute program/erase of flash memory by VCC = 5.0 ± 0.5 V.
4. When using over 16 MHz, use PLL clock. PLL clock oscillation
frequency which can be used is 16 MHz or 20 MHz.
0.0
16.0
5.54.2
VCC [V] (main clock: no division)
f(XIN) operating maximum frequency [MHz]
Main clock input oscillation frequency
(Mask ROM version / Flash memory
version: no wait)
Rev.2.40 Aug 25, 2006 page 34 of 88
REJ03B0003-02400
M16C/6N Group (M16C/6N4) 5. Electric Characteristics (T/V-ver.)
Under development
This document is under development and its contents are subject to change.
Table 5.4 Electrical Characteristics (1) (1)
V
CC
-2.0
V
CC
-0.3
3.0
3.0
0.2
0.2
30
2.0
2.5
1.6
0
0
50
1.5
15
HIGH output
voltage
HIGH output
voltage
HIGH output
voltage
HIGH output
voltage
LOW output
voltage
LOW output
voltage
LOW output
voltage
LOW output
voltage
Hysteresis
Hysteresis
HIGH input
current
LOW input
current
Pull-up
resistance
Feedback resistance
Feedback resistance
RAM retention voltage
VOH
VOH
VOH
VOL
VOL
VOL
VT+-VT-
VT+-VT-
IIH
IIL
RPULLUP
RfXIN
RfXCIN
VRAM
IOH = –5 mA
IOH = –200 µA
IOH = –1 mA
IOH = –0.5 mA
With no load applied
With no load applied
IOL = 5 mA
IOL = 200 µA
IOL = 1 mA
IOL = 0.5 mA
With no load applied
With no load applied
VI = 5 V
VI = 0 V
VI = 0 V
At stop mode
V
V
V
V
V
V
V
V
V
V
µA
µA
kΩ
MΩ
MΩ
V
Measuring Condition
Standard
Min. Unit
VCC
VCC
VCC
VCC
2.0
0.45
2.0
2.0
1.0
2.5
5.0
–5.0
170
Parameter
Symbol
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0, P7_2 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0,
P9_2 to P9_7, P10_0 to P10_7
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0, P7_2 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0,
P9_2 to P9_7, P10_0 to P10_7
XOUT HIGHPOWER
LOWPOWER
XCOUT HIGHPOWER
LOWPOWER
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7
XOUT HIGHPOWER
LOWPOWER
XCOUT HIGHPOWER
LOWPOWER
_________ _______
HOLD, RDY, TA0IN to TA4IN, TB0IN to TB5IN,
________ ________ _______ _____________ _________ _________
INT0 to INT5, NMI, ADTRG, CTS0 to CTS2,
SCL0 to SCL2, SDA0 to SDA2, CLK0 to CLK3,
_____ _____
TA0OUT to TA4OUT, KI0 to KI3,
RXD0 to RXD2, SIN3
_____________
RESET
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7,
____________
XIN, RESET, CNVSS, BYTE
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7,
____________
XIN, RESET, CNVSS, BYTE
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0, P7_2 to P7_7, P8_0 to
P8_4, P8_6, P8_7, P9_0, P9_2 to P9_7,
P10_0 to P10_7
XIN
XCIN
Typ. Max.
NOTES:
1. Referenced to VCC = 4.2 to 5.5 V, VSS = 0 V at Topr = –40 to 85°C, f(BCLK) = 20 MHz unless otherwise specified.
Rev.2.40 Aug 25, 2006 page 35 of 88
REJ03B0003-02400
M16C/6N Group (M16C/6N4) 5. Electric Characteristics (T/V-ver.)
Under development
This document is under development and its contents are subject to change.
Table 5.5 Electrical Characteristics (2) (1)
Mask ROM f(BCLK) = 20 MHz,
PLL operation,
No division
On-chip oscillation,
No division
Flash memory f(BCLK) = 20 MHz,
PLL operation,
No division
On-chip oscillation,
No division
Flash memory f(BCLK) = 10 MHz,
program VCC = 5 V
Flash memory f(BCLK) = 10 MHz,
erase VCC = 5 V
Mask ROM f(BCLK) = 32kHz,
Low power dissipation
mode, ROM (2)
Flash memory f(BCLK) = 32 kHz,
Low power dissipation
mode, RAM (2)
f(BCLK) = 32 kHz,
Low power dissipation
mode,
Flash memory (2)
Mask ROM On-chip oscillation,
Flash memory Wait mode
f(BCLK) = 32 kHz,
Wait mode (3),
Oscillation capacity High
f(BCLK) = 32 kHz,
Wait mode (3),
Oscillation capacity Low
Stop mode,
Topr = 25°C
NOTES:
1. Referenced to VCC = 4.2 to 5.5 V, VSS = 0 V at Topr = –40 to 85°C, f(BCLK) = 20 MHz unless otherwise specified.
2. This indicates the memory in which the program to be executed exists.
3. With one timer operated using fC32.
18
1
20
1.8
15
25
25
25
420
50
8.5
3.0
0.8
Power supply
current
(VCC
= 4.2 to 5.5 V)
ICC mA
mA
mA
mA
mA
mA
µA
µA
µA
µA
µA
µA
µA
Measuring Condition Standard
Min. Unit
32
34
3.0
ParameterSymbol
In single-chip mode,
the output pins are
open and other pins
are VSS.
Typ. Max.
Rev.2.40 Aug 25, 2006 page 36 of 88
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Under development
This document is under development and its contents are subject to change.
Table 5.6 A/D Conversion Characteristics (1)
(NOTE 2)
8
1.0
3
20
1.5
Bits
%
µs
kΩ
mA
Resolution
Absolute accuracy
Setup time
Output resistance
Reference power supply input current
–
–
tsu
RO
IVREF
Symbol Parameter Min.
Standard Unit
Measuring condition
4
Max.
Typ.
10
NOTES:
1. Referenced to VCC = AVCC = VREF = 4.2 to 5.5 V, VSS = AVSS = 0 V, –40 to 85°C unless otherwise specified.
2. φAD frequency must be 10 MHz or less.
3. When sample & hold is disabled, φAD frequency must be 250kHz or more in addition to a limit of NOTE 2.
When sample & hold is enabled, φAD frequency must be 1MHz or more in addition to a limit of NOTE 2.
Table 5.7 D/A conversion Characteristics (1)
NOTES:
1. Referenced to VCC = AVCC = VREF = 4.2 to 5.5 V, VSS = AVSS = 0 V, –40 to 85°C unless otherwise specified.
2. This applies when using one D/A converter, with the DAi register (i = 0, 1) for the unused D/A converter set to 00h.
The resistor ladder of the A/D converter is not included. Also, the IVREF will flow even if VREF is disconnected by the
ADCON1 register.
10
±3
±7
±2
±3
±7
±2
±1
±3
±3
40
VCC
VREF
Bit
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
kΩ
µs
µs
µs
V
V
10
3.3
2.8
0.3
2.0
0
VREF = VCC
VREF
= VCC
= 5 V
VREF = AVCC = VCC = 5 V
VREF
= VCC
= 5 V
VREF = AVCC = VCC = 5 V
VREF = VCC
VREF = VCC = 5 V, φAD = 10 MHz
VREF = VCC = 5 V, φAD = 10 MHz
ANEX0, ANEX1 input, AN0 to AN7 input,
AN0_0 to AN0_7 input, AN2_0 to AN2_7 input
External operation amp connection mode
ANEX0, ANEX1 input, AN0 to AN7 input,
AN0_0 to AN0_7 input, AN2_0 to AN2_7 input
External operation amp connection mode
Resolution
Integral 10 bits
nonlinearity
error
8 bits
Absolute 10 bits
accuracy
8 bits
Differential nonlinearity error
Offset error
Gain error
Resistor ladder
10-bit conversion time,
sample & hold available
8-bit conversion time,
sample & hold available
Sampling time
Reference voltage
Analog input voltage
–
INL
–
DNL
–
–
RLADDER
tCONV
tSAMP
VREF
VIA
Symbol Parameter Min.
Standard Unit
Measuring Condition Max.
Typ.
Rev.2.40 Aug 25, 2006 page 37 of 88
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Under development
This document is under development and its contents are subject to change.
2
150
150
ms
µs
µs
Time for internal power supply stabilization during powering-on
STOP release time
Low power dissipation mode wait mode release time
td(P-R)
td(R-S)
td(W-S)
Symbol Parameter Min.
Standard Unit
Measuring
Condition Max.
Typ.
VCC = 4.2 to 5.5 V
Table 5.8 Power Supply Circuit Timing Characteristics
CPU clock
VCC
td(P-R)
td(P-R)
Time for internal power supply
stabilization during powering-on
td(R-S)
STOP release time
td(W-S)
Low power dissipation mode
wait mode release time
CPU clock
td(W-S)
td(R-S)
(b)
(a)
Interrupt for
(a) Stop mode release
or
(b) Wait mode release
Figure 5.1 Power Supply Circuit Timing Diagram
Rev.2.40 Aug 25, 2006 page 38 of 88
REJ03B0003-02400
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Under development
This document is under development and its contents are subject to change.
15
15
ns
ns
ns
ns
ns
External clock input cycle time
External clock input HIGH pulse width
External clock input LOW pulse width
External clock rise time
External clock fall time
Symbol Parameter Min.
Standard Unit
Max.
62.5
25
25
tC
tw(H)
tw(L)
tr
tf
Timing Requirements
(Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85°C unless otherwise specified)
Table 5.9 External Clock Input (XIN Input)
Table 5.10 Memory Expansion Mode and Microprocessor Mode
(NOTE 1)
(NOTE 2)
(NOTE 3)
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data input access time (for setting with no wait)
Data input access time (for setting with wait)
Data input access time (when accessing multiplexed bus area)
Data input setup time
________
RDY input setup time
__________
HOLD input setup time
Data input hold time
________
RDY input hold time
__________
HOLD input hold time
Symbol Parameter Min.
Standard Unit
Max.
40
30
40
0
0
0
tac1(RD-DB)
tac2(RD-DB)
tac3(RD-DB)
tsu(DB-RD)
tsu(RDY-BCLK)
tsu(HOLD-BCLK)
th(RD-DB)
th(BCLK-RDY)
th(BCLK-HOLD)
NOTES:
1. Calculated according to the BCLK frequency as follows:
0.5 ✕ 109
f(BCLK) – 45 [ns]
2. Calculated according to the BCLK frequency as follows:
(n –0.5) ✕ 109
f(BCLK) – 45 [ns]
n is “2” for 1-wait setting, “3” for 2-wait setting and “4” for 3-wait setting.
3. Calculated according to the BCLK frequency as follows:
(n –0.5) ✕ 109
f(BCLK) – 45 [ns] n is “2” for 2-wait setting, “3” for 3-wait setting.
VCC = 5 V
Rev.2.40 Aug 25, 2006 page 39 of 88
REJ03B0003-02400
M16C/6N Group (M16C/6N4) 5. Electric Characteristics (T/V-ver.)
Under development
This document is under development and its contents are subject to change.
Timing Requirements
(Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85°C unless otherwise specified)
Table 5.11 Timer A Input (Counter Input in Event Counter Mode)
ns
ns
ns
TAiIN input cycle time
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
Symbol Parameter Min.
Standard Unit
Max.
100
40
40
Table 5.12 Timer A Input (Gating Input in Timer Mode)
tc(TA)
tw(TAH)
tw(TAL)
Table 5.13 Timer A Input (External Trigger Input in One-shot Timer Mode)
Table 5.14 Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Table 5.15 Timer A Input (Counter Increment/decrement Input in Event Counter Mode)
ns
ns
ns
TAiIN input cycle time
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
Symbol Parameter Min.
Standard Unit
Max.
400
200
200
tc(TA)
tw(TAH)
tw(TAL)
ns
ns
ns
TAiIN input cycle time
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
Symbol Parameter Min.
Standard Unit
Max.
200
100
100
tc(TA)
tw(TAH)
tw(TAL)
ns
ns
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
Symbol Parameter Min.
Standard Unit
Max.
100
100
tw(TAH)
tw(TAL)
ns
ns
ns
ns
ns
TAiOUT input cycle time
TAiOUT input HIGH pulse width
TAiOUT input LOW pulse width
TAiOUT input setup time
TAiOUT input hold time
Symbol Parameter Min.
Standard Unit
Max.
2000
1000
1000
400
400
tc(UP)
tw(UPH)
tw(UPL)
tsu(UP-TIN)
th(TIN-UP)
Table 5.16 Timer A Input (Two-phase Pulse Input in Event Counter Mode)
ns
ns
ns
TAiIN input cycle time
TAiOUT input setup time
TAiIN input setup time
Symbol Parameter Min.
Standard Unit
Max.
800
200
200
tc(TA)
tsu(TAIN-TAOUT)
tsu(TAOUT-TAIN)
VCC = 5 V
Rev.2.40 Aug 25, 2006 page 40 of 88
REJ03B0003-02400
M16C/6N Group (M16C/6N4) 5. Electric Characteristics (T/V-ver.)
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This document is under development and its contents are subject to change.
ns
ns
ns
ns
ns
ns
TBiIN input cycle time (counted on one edge)
TBiIN input HIGH pulse width (counted on one edge)
TBiIN input LOW pulse width (counted on one edge)
TBiIN input cycle time (counted on both edges)
TBiIN input HIGH pulse width (counted on both edges)
TBiIN input LOW pulse width (counted on both edges)
Symbol Parameter Min.
Standard Unit
Max.
100
40
40
200
80
80
Table 5.18 Timer B Input (Pulse Period Measurement Mode)
tc(TB)
tw(TBH)
tw(TBL)
tc(TB)
tw(TBH)
tw(TBL)
Timing Requirements
(Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85°C unless otherwise specified)
Table 5.17 Timer B Input (Counter Input in Event Counter Mode)
Table 5.19 Timer B Input (Pulse Width Measurement Mode)
Table 5.20 A/D Trigger Input
Table 5.21 Serial Interface
ns
ns
ns
TBiIN input cycle time
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
Symbol Parameter Min.
Standard Unit
Max.
400
200
200
tc(TB)
tw(TBH)
tw(TBL)
ns
ns
ns
TBiIN input cycle time
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
Symbol Parameter Min.
Standard Unit
Max.
400
200
200
tc(TB)
tw(TBH)
tw(TBL)
ns
ns
_____________
ADTRG input cycle time (trigger able minimum)
_____________
ADTRG input LOW pulse width
Symbol Parameter Min.
Standard Unit
Max.
1000
125
tC(AD)
tw(ADL)
80
ns
ns
ns
ns
ns
ns
ns
CLKi input cycle time
CLKi input HIGH pulse width
CLKi input LOW pulse width
TXDi output delay time
TXDi hold time
RXDi input setup time
RXDi input hold time
Symbol Parameter Min.
Standard Unit
Max.
200
100
100
0
70
90
tc(CK)
tw(CKH)
tw(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
_______
Table 5.22 External Interrupt INTi Input
ns
ns
_______
INTi input HIGH pulse width
_______
INTi input LOW pulse width
Symbol Parameter Min.
Standard Unit
Max.
250
250
tw(INH)
tw(INL)
VCC = 5 V
Rev.2.40 Aug 25, 2006 page 41 of 88
REJ03B0003-02400
M16C/6N Group (M16C/6N4) 5. Electric Characteristics (T/V-ver.)
Under development
This document is under development and its contents are subject to change.
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
th(WR-AD)
td(BCLK-CS)
th(BCLK-CS)
td(BCLK-ALE)
th(BCLK-ALE)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
td(DB-WR)
th(WR-DB)
td(BCLK-HLDA)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address output delay time
Address output hold time (in relation to BCLK)
Address output hold time (in relation to RD)
Address output hold time (in relation to WR)
Chip select output delay time
Chip select output hold time (in relation to BCLK)
ALE signal output delay time
ALE signal output hold time
RD signal output delay time
RD signal output hold time
WR signal output delay time
WR signal output hold time
Data output delay time (in relation to BCLK)
Data output hold time (in relation to BCLK) (3)
Data output delay time (in relation to WR)
Data output hold time (in relation to WR) (3)
__________
HLDA output delay time
Symbol Parameter Min.
Standard Unit
Max.
4
0
(NOTE 1)
4
–4
0
0
4
(NOTE 2)
(NOTE 1)
Switching Characteristics
(Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified)
Table 5.23 Memory Expansion Mode and Microprocessor Mode (for setting with no wait)
25
25
15
25
25
40
40
NOTES:
1. Calculated according to the BCLK frequency as follows:
0.5 ✕ 109
f(BCLK) – 10 [ns]
2. Calculated according to the BCLK frequency as follows:
0.5 ✕ 109
f(BCLK) – 40 [ns]
3. This standard value shows the timing when the
output is off, and does not show hold time of
data bus.
Hold time of data bus varies with capacitor volume
and pull-up (pull-down) resistance value.
Hold time of data bus is expressed in
t = – CR ✕ ln (1 – VOL / VCC)
by a circuit of the right figure.
For example, when VOL = 0.2 VCC, C = 30 pF,
R =1 kΩ, hold time of output “L” level is
t = – 30 pF ✕ 1 kΩ ✕ ln (1 – 0.2 VCC / VCC) = 6.7 ns.
Figure 5.2 Port P0 to P10 Measurement Circuit
DBi
R
C
30 pF
P6
P7
P8
P10
P9
P0
P1
P2
P3
P4
P5
Measuring
Condition
Figure 5.2
f(BCLK) is 12.5 MHz or less.
VCC = 5 V
Rev.2.40 Aug 25, 2006 page 42 of 88
REJ03B0003-02400
M16C/6N Group (M16C/6N4) 5. Electric Characteristics (T/V-ver.)
Under development
This document is under development and its contents are subject to change.
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
th(WR-AD)
td(BCLK-CS)
th(BCLK-CS)
td(BCLK-ALE)
th(BCLK-ALE)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
td(DB-WR)
th(WR-DB)
td(BCLK-HLDA)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address output delay time
Address output hold time (in relation to BCLK)
Address output hold time (in relation to RD)
Address output hold time (in relation to WR)
Chip select output delay time
Chip select output hold time (in relation to BCLK)
ALE signal output delay time
ALE signal output hold time
RD signal output delay time
RD signal output hold time
WR signal output delay time
WR signal output hold time
Data output delay time (in relation to BCLK)
Data output hold time (in relation to BCLK) (3)
Data output delay time (in relation to WR)
Data output hold time (in relation to WR) (3)
__________
HLDA output delay time
Symbol Parameter Min.
Standard Unit
Max.
4
0
(NOTE 1)
4
–4
0
0
4
(NOTE 2)
(NOTE 1)
Switching Characteristics
(Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified)
Table 5.24
Memory Expansion Mode and Microprocessor Mode (for 1- to 3-wait setting and external area access)
25
25
15
25
25
40
40
NOTES:
1. Calculated according to the BCLK frequency as follows:
0.5 ✕ 109
f(BCLK) – 10 [ns]
2. Calculated according to the BCLK frequency as follows:
(n – 0.5) ✕ 109n is “1” for 1-wait setting, “2” for 2-wait setting and “3” for 3-wait setting.
f(BCLK) – 40 [ns] When n = 1, f(BCLK) is 12.5 MHz or less.
3. This standard value shows the timing when the
output is off, and does not show hold time of
data bus.
Hold time of data bus varies with capacitor volume
and pull-up (pull-down) resistance value.
Hold time of data bus is expressed in
t = – CR ✕ ln (1 – VOL / VCC)
by a circuit of the right figure.
For example, when VOL = 0.2 VCC, C = 30 pF,
R =1 kΩ, hold time of output “L” level is
t = – 30 pF ✕ 1 kΩ ✕ ln (1 – 0.2 VCC / VCC) = 6.7 ns.
DBi
R
C
Measuring
Condition
Figure 5.2
VCC = 5 V
Rev.2.40 Aug 25, 2006 page 43 of 88
REJ03B0003-02400
M16C/6N Group (M16C/6N4) 5. Electric Characteristics (T/V-ver.)
Under development
This document is under development and its contents are subject to change.
4
(NOTE 1)
(NOTE 1)
4
(NOTE 1)
(NOTE 1)
0
0
4
(NOTE 2)
(NOTE 1)
–4
(NOTE 3)
(NOTE 4)
0
0
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
th(WR-AD)
td(BCLK-CS)
th(BCLK-CS)
th(RD-CS)
th(WR-CS)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
td(DB-WR)
th(WR-DB)
td(BCLK-HLDA)
td(BCLK-ALE)
th(BCLK-ALE)
td(AD-ALE)
th(ALE-AD)
td(AD-RD)
td(AD-WR)
tdZ(RD-AD)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address output delay time
Address output hold time (in relation to BCLK)
Address output hold time (in relation to RD)
Address output hold time (in relation to WR)
Chip select output delay time
Chip select output hold time (in relation to BCLK)
Chip select output hold time (in relation to RD)
Chip select output hold time (in relation to WR)
RD signal output delay time
RD signal output hold time
WR signal output delay time
WR signal output hold time
Data output delay time (in relation to BCLK)
Data output hold time (in relation to BCLK)
Data output delay time (in relation to WR)
Data output hold time (in relation to WR)
__________
HLDA output delay time
ALE signal output delay time (in relation to BCLK)
ALE signal output hold time (in relation to BCLK)
ALE signal output delay time (in relation to Address)
ALE signal output hold time (in relation to Address)
RD signal output delay from the end of Address
WR signal output delay from the end of Address
Address output floating start time
Symbol Parameter Min.
Standard Unit
Max.
Switching Characteristics
(Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified)
Table 5.25 Memory Expansion Mode and Microprocessor Mode
(for 2- to 3-wait setting, external area access and multiplexed bus selection)
25
25
25
25
40
40
15
8
Measuring
Condition
Figure 5.2
NOTES:
1. Calculated according to the BCLK frequency as follows:
0.5 ✕ 109
f(BCLK) – 10 [ns]
2. Calculated according to the BCLK frequency as follows:
(n –0.5) ✕ 109
f(BCLK) – 40 [ns] n is “2” for 2-wait setting, “3” for 3-wait setting.
3. Calculated according to the BCLK frequency as follows:
0.5 ✕ 109
f(BCLK) – 25 [ns]
4. Calculated according to the BCLK frequency as follows:
0.5 ✕ 109
f(BCLK) – 15 [ns]
VCC = 5 V
Rev.2.40 Aug 25, 2006 page 44 of 88
REJ03B0003-02400
M16C/6N Group (M16C/6N4) 5. Electric Characteristics (T/V-ver.)
Under development
This document is under development and its contents are subject to change.
Figure 5.3 Timing Diagram (1)
tsu(D—C)
CLKi
TXDi
RXDi
tc(CK)
tw(CKH)
tw(CKL)
tw(INL)
tw(INH)
td(C—Q) th(C—D)
th(C—Q)
INTi input
tc(TB)
tw(TBH)
tw(TBL)
tc(AD)
tw(ADL)
ADTRG input
TBiIN input
Two-phase pulse input in event counter mode
tsu(TAOUT—TAIN)
tsu(TAOUT—TAIN)
tsu(TAIN—TAOUT)
tC(TA)
tsu(TAIN—TAOUT)
TAiIN input
TAiOUT input
tc(TA)
tw(TAH)
tw(TAL)
tc(UP)
tw(UPH)
tw(UPL)
TAiIN input
TAiOUT input
During event counter mode
TAiIN input
(When count on falling edge
is selected)
TAiIN input
(When count on rising edge
is selected)
TAiOUT input
(Up/down input)
t
h(TIN—UP)
t
su(UP—TIN)
trtr
tc
tw(H) tw(L)
XIN input
VCC = 5 V
Rev.2.40 Aug 25, 2006 page 45 of 88
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Under development
This document is under development and its contents are subject to change.
Figure 5.4 Timing Diagram (2)
Measuring conditions :
VCC = 5 V
Input timing voltage : Determined with V
IL
= 1.0 V, V
IH
= 4.0 V
Output timing voltage: Determined with V
OL
= 2.5 V, V
OH
= 2.5 V
BCLK
HOLD input
HLDA output
P0, P1, P2,
P3, P4,
P5_0 to P5_2
(1)
NOTE:
1.
The above pins are set to high-impedance regardless of the input level of the BYTE pin,
the PM06 bit in the PM0 register, and the PM11 bit in the PM1 register.
Hi–Z
RDY input
BCLK
RD
(Multiplexed bus)
(Multiplexed bus)
WR, WRL, WRH
WR, WRL, WRH
(Separate bus)
RD
(Separate bus)
td(BCLK–HLDA)td(BCLK–HLDA)
th(BCLK–HOLD)tsu(HOLD–BCLK)
tsu(RDY–BCLK) th(BCLK–RDY)
Memory Expansion Mode and Microprocessor Mode
(Effective for setting with wait)
(Common to setting with wait and setting without wait)
VCC = 5 V
Rev.2.40 Aug 25, 2006 page 46 of 88
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M16C/6N Group (M16C/6N4) 5. Electric Characteristics (T/V-ver.)
Under development
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Figure 5.5 Timing Diagram (3)
BCLK
CSi
t
d(BCLK-CS)
25ns.max
ADi
25ns.max
ALE
25ns.max -4ns.min
RD
25ns.max
t
h(BCLK-RD)
0ns.min
t
h(BCLK-AD)
4ns.min
t
h(BCLK-CS)
4ns.min
Hi-Z
DBi
t
h(RD-DB)
0ns.min
0ns.min
t
h(RD-AD)
BHE
tcyc
Read timing
t
d(BCLK-AD)
t
d(BCLK-ALE)
t
h(BCLK-ALE)
t
SU(DB-RD)
t
d(BCLK-RD)
40ns.min
t
ac1(RD-DB)
Memory Expansion Mode and Microprocessor Mode
(For setting with no wait)
WR,WRL,
WRH
25ns.max
t
h(BCLK-WR)
0ns.min
BCLK
CSi
t
d(BCLK-CS)
25ns.max
ADi
t
d(BCLK-AD)
25ns.max
ALE
25ns.max
t
d(BCLK-ALE)
t
h(BCLK-ALE)
-4ns.min
t
h(BCLK-AD)
4ns.min
t
h(BCLK-CS)
4ns.min
tcyc
t
h(WR-AD)
BHE
t
d(BCLK-DB)
40ns.max 4ns.min
t
h(BCLK-DB)
t
d(DB-WR)
(0.5 ✕ tcyc-40)ns.min
t
h(WR-DB)
DBi
Write timing
t
d(BCLK-WR)
Hi-Z
(0.5 ✕ tcyc-45)ns.max
(0.5 ✕ tcyc-10)ns.min
tcyc = 1
f(BCLK)
Measuring conditions :
VCC = 5 V
Input timing voltage : V
IL
= 0.8 V, V
IH
= 2.0 V
Output timing voltage : V
OL
= 0.4 V, V
OH
= 2.4 V
(0.5 ✕ tcyc-10)ns.min
VCC = 5 V
Rev.2.40 Aug 25, 2006 page 47 of 88
REJ03B0003-02400
M16C/6N Group (M16C/6N4) 5. Electric Characteristics (T/V-ver.)
Under development
This document is under development and its contents are subject to change.
Figure 5.6 Timing Diagram (4)
BCLK
CSi
t
d(BCLK-CS)
25ns.max
ADi
t
d(BCLK-AD)
25ns.max
ALE
25ns.max
t
h(BCLK-ALE)
-4ns.min
RD
25ns.max
t
h(BCLK-RD)
0ns.min
t
h(BCLK-AD)
4ns.min
t
h(BCLK-CS)
4ns.min
Hi-Z
DBi
t
SU(DB-RD)
40ns.min
t
h(RD-DB)
0ns.min
tcyc
BHE
Read timing
WR,WRL,
WRH
25ns.max
t
h(BCLK-WR)
0ns.min
BCLK
CSi
t
d(BCLK-CS)
25ns.max
ADi
t
d(BCLK-AD)
25ns.max
ALE
25ns.max
t
d(BCLK-ALE)
t
h(BCLK-ALE)
-4ns.min
t
h(BCLK-AD)
4ns.min
t
h(BCLK-CS)
4ns.min
tcyc
t
h(WR-AD)
BHE
t
d(BCLK-DB)
40ns.max 4ns.min
t
h(BCLK-DB)
t
d(DB-WR)
(0.5 ✕ tcyc-40)ns.min (0.5 ✕ tcyc-10)ns.min
t
h(WR-DB)
DBi
Write timing
t
d(BCLK-ALE)
t
d(BCLK-RD)
t
d(BCLK-WR)
0ns.min
t
h(RD-AD)
t
ac2(RD-DB)
Hi-Z
Memory Expansion Mode and Microprocessor Mode
(For 1-wait setting and external area access)
(1.5 ✕ tcyc-45)ns.max
tcyc = 1
f(BCLK)
Measuring conditions :
VCC = 5 V
Input timing voltage : VIL = 0.8 V, VIH = 2.0 V
Output timing voltage : VOL = 0.4 V, VOH = 2.4 V
(0.5 ✕ tcyc-10)ns.min
VCC = 5 V
Rev.2.40 Aug 25, 2006 page 48 of 88
REJ03B0003-02400
M16C/6N Group (M16C/6N4) 5. Electric Characteristics (T/V-ver.)
Under development
This document is under development and its contents are subject to change.
Figure 5.7 Timing Diagram (5)
Read timing
Write timing
BCLK
CSi
ALE
DBi
ADi
BHE
WR, WRL
WRH
Memory Expansion Mode and Microprocessor Mode
(For 2-wait setting and external area access)
BCLK
CSi
ALE
DBi
ADi
BHE
RD
tcyc
t
d(BCLK-CS)
25ns.max
t
d(BCLK-AD)
25ns.max
t
d(BCLK-ALE)
25ns.max
t
h(BCLK-ALE)
-4ns.min
t
d(BCLK-RD)
25ns.max
Hi-Z
t
SU(DB-RD)
40ns.min
t
h(RD-DB)
0ns.min
t
h(BCLK-RD)
0ns.min
t
h(RD-AD)
0ns.min
t
h(BCLK-AD)
4ns.min
t
h(BCLK-CS)
4ns.min
tcyc
Hi-Z
t
d(BCLK-CS)
25ns.max
t
d(BCLK-AD)
25ns.max
t
d(BCLK-ALE)
25ns.max
t
h(BCLK-ALE)
-4ns.min
t
d(BCLK-WR)
25ns.max
t
h(BCLK-CS)
4ns.min
t
h(BCLK-AD)
4ns.min
t
h(WR-AD)
(0.5 ✕ tcyc-10)ns.min
t
h(BCLK-WR)
0ns.min
t
d(BCLK-DB)
40ns.max
t
d(DB-WR)
(1.5 ✕ tcyc-40)ns.min
t
h(BCLK-DB)
4ns.min
t
h(WR-DB)
(0.5 ✕ tcyc-10)ns.min
t
ac2(RD-DB)
(2.5 ✕ tcyc-45)ns.max
tcyc = 1
f(BCLK)
Measuring conditions :
VCC = 5 V
Input timing voltage : V
IL
= 0.8 V, V
IH
= 2.0 V
Output timing voltage : V
OL
= 0.4 V, V
OH
= 2.4 V
VCC = 5 V
Rev.2.40 Aug 25, 2006 page 49 of 88
REJ03B0003-02400
M16C/6N Group (M16C/6N4) 5. Electric Characteristics (T/V-ver.)
Under development
This document is under development and its contents are subject to change.
Figure 5.8 Timing Diagram (6)
Read timing
Write timing
BCLK
CSi
ALE
DBi
ADi
BHE
WR, WRL
WRH
Memory Expansion Mode and Microprocessor Mode
(For 3-wait setting and external area access)
BCLK
CSi
ALE
DBi
ADi
BHE
RD
tcyc
t
d(BCLK-CS)
25ns.max
t
d(BCLK-AD)
25ns.max
t
d(BCLK-ALE)
25ns.max
t
h(BCLK-ALE)
-4ns.min
t
d(BCLK-RD)
25ns.max
Hi-Z
t
SU(DB-RD)
40ns.min
t
h(RD-DB)
0ns.min
t
h(BCLK-RD)
0ns.min
t
h(RD-AD)
0ns.min
t
h(BCLK-AD)
4ns.min
t
h(BCLK-CS)
4ns.min
tcyc
Hi-Z
t
d(BCLK-CS)
25ns.max
t
d(BCLK-AD)
25ns.max
t
d(BCLK-ALE)
25ns.max
t
h(BCLK-ALE)
-4ns.min
t
d(BCLK-WR)
25ns.max
t
h(BCLK-CS)
4ns.min
t
h(BCLK-AD)
4ns.min
t
h(WR-AD)
(0.5 ✕ tcyc-10)ns.min
t
h(BCLK-WR)
0ns.min
t
d(BCLK-DB)
40ns.max
t
d(DB-WR)
(2.5 ✕ tcyc-40)ns.min
t
h(BCLK-DB)
4ns.min
t
h(WR-DB)
(0.5 ✕ tcyc-10)ns.min
t
ac2(RD-DB)
(3.5 ✕ tcyc-45)ns.max
tcyc = 1
f(BCLK)
Measuring conditions :
VCC = 5 V
Input timing voltage : VIL = 0.8 V, VIH = 2.0 V
Output timing voltage : VOL = 0.4 V, VOH = 2.4 V
VCC = 5 V
Rev.2.40 Aug 25, 2006 page 50 of 88
REJ03B0003-02400
M16C/6N Group (M16C/6N4) 5. Electric Characteristics (T/V-ver.)
Under development
This document is under development and its contents are subject to change.
Figure 5.9 Timing Diagram (7)
Memory Expansion Mode and Microprocessor Mode
(For 1- or 2-wait setting, external area access and multiplexed bus selection)
BCLK
CSi
td(BCLK-CS)
25ns.max
ADi
td(BCLK-AD)
25ns.max
ALE
th(BCLK-ALE)
-4ns.min
RD
25ns.max
th(BCLK-RD)
0ns.min
th(BCLK-AD)
4ns.min
th(BCLK-CS)
4ns.min
tcyc th(RD-CS)
th(RD-AD)
BHE
ADi
/DBi th(RD-DB)
0ns.min
td(AD-ALE)
Read timing
td(BCLK-WR)
25ns.max
th(BCLK-WR)
0ns.min
BCLK
CSi
td(BCLK-CS)
25ns.max
ADi
td(BCLK-AD)
25ns.max
ALE
25ns.max
th(BCLK-ALE)
-4ns.min
th(BCLK-AD)
4ns.min
th(BCLK-CS)
4ns.min
tcyc
th(WR-AD)
BHE
td(BCLK-DB)
40ns.max 4ns.min
th(BCLK-DB)
td(DB-WR) th(WR-DB)
ADi
/DBi
Data output
WR,WRL,
WRH
Write timing
Address
Address
Data input
40ns.min
(0.5 ✕ tcyc-10)ns.min
td(BCLK-ALE)
td(BCLK-RD)
th(WR-CS)
Address
td(AD-ALE)
(0.5 ✕ tcyc-25)ns.min
(1.5 ✕ tcyc-40)ns.min
(0.5 ✕ tcyc-10)ns.min
td(BCLK-ALE)
(0.5 ✕ tcyc-25)ns.min
Address
25ns.max
tSU(DB-RD)
tac3(RD-DB)
(0.5 ✕ tcyc-10)ns.min
td(AD-RD)
0ns.min
tdZ(RD-AD)
8ns.max
td(AD-WR)
0ns.min
th(ALE-AD)
tcyc = 1
f(BCLK)
Measuring conditions :
VCC = 5 V
Input timing voltage : V
IL
= 0.8 V, V
IH
= 2.0 V
Output timing voltage : V
OL
= 0.4 V, V
OH
= 2.4 V
(1.5 ✕ tcyc-45)ns.max
(0.5 ✕ tcyc-10)ns.min
(0.5 ✕ tcyc-10)ns.min
(0.5 ✕ tcyc-15)ns.min
VCC = 5 V
Rev.2.40 Aug 25, 2006 page 51 of 88
REJ03B0003-02400
M16C/6N Group (M16C/6N4) 5. Electric Characteristics (T/V-ver.)
Under development
This document is under development and its contents are subject to change.
Figure 5.10 Timing Diagram (8)
Read timing
Write timing
Memory Expansion Mode and Microprocessor Mode
(For 3-wait setting, external area access and multiplexed bus selection)
BCLK
CSi
ALE
RD
ADi
/DBi
ADi
BHE
BCLK
CSi
ALE
ADi
/DBi
tcyc
t
d(BCLK-AD)
25ns.max
tcyc
Data output
t
h(BCLK-CS)
4ns.min
t
d(BCLK-CS)
25ns.max
t
d(BCLK-ALE)
25ns.max
t
h(BCLK-ALE)
-4ns.min
t
d(BCLK-RD)
25ns.max
t
h(BCLK-RD)
0ns.min
t
SU(DB-RD)
40ns.min
t
h(RD-DB)
0ns.min
t
h(RD-AD)
(0.5 ✕ tcyc-10)ns.min
t
h(BCLK-AD)
4ns.min
t
d(BCLK-CS)
25ns.max
t
d(BCLK-AD)
25ns.max
t
h(BCLK-DB)
4ns.min
t
h(BCLK-WR)
0ns.min
t
h(WR-AD)
(0.5 ✕ tcyc-10)ns.min
t
h(BCLK-AD)
4ns.min
t
h(BCLK-CS)
4ns.min
t
d(BCLK-ALE)
25ns.max
t
d(BCLK-WR)
25ns.max
t
-4ns.min
t
h(WR-DB)
(0.5 ✕ tcyc-10)ns.min
Data input
Address
Address
ADi
BHE
WR, WRL
WRH
t
d(AD-ALE)
(0.5 ✕ tcyc-25)ns.min
t
d(AD-RD)
0ns.min
t
dZ(RD-AD)
8ns.max
t
ac3(RD-DB)
t
d(BCLK-DB)
40ns.max
(0.5 ✕ tcyc-10)ns.min
t
h(WR-CS)
t
d(AD-WR)
0ns.min
t
h(RD-CS)
(0.5 ✕ tcyc-10)ns.min
t
d(AD-ALE)
(0.5 ✕ tcyc-25)ns.min
(2.5 ✕ tcyc-45)ns.max
(no multiplex)
(no multiplex)
tcyc = 1
f(BCLK)
Measuring conditions :
VCC = 5 V
Input timing voltage : V
IL
= 0.8 V, V
IH
= 2.0 V
Output timing voltage : V
OL
= 0.4 V, V
OH
= 2.4 V
td(DB-WR)
(2.5 ✕ tcyc-40)ns.min
h(BCLK-ALE)
(0.5 ✕ tcyc-15)ns.min
th(ALE-AD)
VCC = 5 V
Rev.2.40 Aug 25, 2006 page 52 of 88
REJ03B0003-0240
M16C/6N Group (M16C/6N4) 5. Electric Characteristics (Normal-ver.)
Under development
This document is under development and its contents are subject to change.
5.2 Electrical Characteristics (Normal-ver.)
Table 5.26 Absolute Maximum Ratings
VCC
AVCC
VI
VO
Pd
Topr
Tstg
V
V
V
V
V
V
mW
°C
°C
Unit
Supply voltage (VCC1 = VCC2)
Analog supply voltage
Input
voltage
Output
voltage
Power dissipation
Operating ambient During MCU operation
temperature During flash memory program and
erase operation
Storage temperature
Symbol Parameter
_____________
RESET, CNVSS, BYTE,
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0, P7_2 to P7_7, P8_0 to P8_7,
P9_0, P9_2 to P9_7, P10_0 to P10_7,
VREF, XIN
P7_1, P9_1
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0, P7_2 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0, P9_2 to P9_7,
P10_0 to P10_7, XOUT
P7_1, P9_1
Rated Value
–0.3 to 6.5
–0.3 to 6.5
–0.3 to VCC+0.3
–0.3 to 6.5
–0.3 to VCC+0.3
–0.3 to 6.5
700
–40 to 85
0 to 60
–65 to 150
Condition
VCC = AVCC
VCC = AVCC
Topr = 25°C
Rev.2.40 Aug 25, 2006 page 53 of 88
REJ03B0003-0240
M16C/6N Group (M16C/6N4) 5. Electric Characteristics (Normal-ver.)
Under development
This document is under development and its contents are subject to change.
Table 5.27 Recommended Operating Conditions (1) (1)
Supply voltage (VCC1 = VCC2)
Analog supply voltage
Supply voltage
Analog supply voltage
HIGH input
voltage
LOW input
voltage
HIGH peak
output current
HIGH average
output current
LOW peak
output current
LOW average
output current
P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7,
P7_0, P7_2 to P7_7, P8_0 to P8_7, P9_0, P9_2 to P9_7,
_____________
P10_0 to P10_7, XIN, RESET, CNVSS, BYTE
P7_1, P9_1
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0
(During single-chip mode)
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0
(Data input during memory expansion and microprocessor modes)
P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7,
P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7,
_____________
XIN, RESET, CNVSS, BYTE
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0
(During single-chip mode)
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0
(Data input during memory expansion and microprocessor modes)
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0,
P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0,
P9_2 to P9_7, P10_0 to P10_7
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0,
P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0,
P9_2 to P9_7, P10_0 to P10_7
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7
5.0
VCC
0
0
V
V
V
V
V
V
V
V
V
V
V
mA
mA
mA
mA
3.0
0.8 VCC
0.8 VCC
0.8 VCC
0.5 VCC
0
0
0
5.5
VCC
6.5
VCC
VCC
0.2 VCC
0.2 VCC
0.16 VCC
–10.0
–5.0
10.0
5.0
VCC
AVCC
VSS
AVSS
VIH
VIL
IOH(peak)
IOH(avg)
IOL(peak)
IOL(avg)
ParameterSymbol Typ.Min.
Standard Unit
Max.
NOTES:
1. Referenced to VCC = 3.0 to 5.5 V at Topr = –40 to 85°C unless otherwise specified.
2. Average output current values during 100 ms period.
3. The total IOL(peak) for ports P0, P1, P2, P8_6, P8_7, P9, and P10 must be 80 mA max.
The total IOL(peak) for ports P3, P4, P5, P6, P7, and P8_0 to P8_4 must be 80 mA max.
The total IOH(peak) for ports P0, P1, and P2 must be –40 mA max.
The total IOH(peak) for ports P3, P4, and P5 must be –40 mA max.
The total IOH(peak) for ports P6, P7, and P8_0 to P8_4 must be –40 mA max.
The total IOH(peak) for ports P8_6, P8_7, P9, and P10 must be –40 mA max.
Rev.2.40 Aug 25, 2006 page 54 of 88
REJ03B0003-0240
M16C/6N Group (M16C/6N4) 5. Electric Characteristics (Normal-ver.)
Under development
This document is under development and its contents are subject to change.
Table 5.28 Recommended Operating Conditions (2) (1)
Main clock input oscillation No wait Mask ROM version VCC = 3.0 to 5.5 V
frequency (2) (3) (4)
Flash memory version
Sub clock oscillation frequency
On-chip oscillation frequency
PLL clock oscillation frequency
CPU operation clock
VCC = 3.0 to 5.5 V
PLL frequency synthesizer stabilization wait time
32.768
1
MHz
kHz
MHz
MHz
MHz
ms
0
16
0
16
50
24
24
20
f(XIN)
f(XCIN)
f(Ring)
f(PLL)
f(BCLK)
tsu(PLL)
ParameterSymbol Typ.Min.
Standard Unit
Max.
NOTES:
1. Referenced to VCC = 3.0 to 5.5 V at Topr = –40 to 85°C unless
otherwise specified.
2. Relationship between main clock oscillation frequency and supply
voltage is shown right.
3. Execute program/erase of flash memory by VCC = 3.3 ± 0.3 V or
VCC = 5.0 ± 0.5 V.
4. When using over 16 MHz, use PLL clock. PLL clock oscillation
frequency which can be used is 16 MHz, 20 MHz or 24 MHz.
0.0
16.0
5.53.0
VCC [V] (main clock: no division)
f(XIN) operating maximum frequency [MHz]
Main clock input oscillation frequency
(Mask ROM version / Flash memory
version: no wait)
Rev.2.40 Aug 25, 2006 page 55 of 88
REJ03B0003-0240
M16C/6N Group (M16C/6N4) 5. Electric Characteristics (Normal-ver.)
Under development
This document is under development and its contents are subject to change.
Table 5.29 A/D Conversion Characteristics (1)
(NOTE 2)
8
1.0
3
20
1.5
Bits
%
µs
kΩ
mA
Resolution
Absolute accuracy
Setup time
Output resistance
Reference power supply input current
–
–
tsu
RO
IVREF
Symbol Parameter Min.
Standard Unit
Measuring Condition
4
Max.
Typ.
10
NOTES:
1. Referenced to VCC = AVCC = VREF = 3.3 to 5.5 V, VSS = AVSS = 0 V, –40 to 85°C unless otherwise specified.
2. φAD frequency must be 10 MHz or less.
3. When sample & hold is disabled, φAD frequency must be 250 kHz or more in addition to a limit of NOTE 2.
When sample & hold is enabled, φAD frequency must be 1 MHz or more in addition to a limit of NOTE 2.
Table 5.30 D/A conversion Characteristics (1)
NOTES:
1. Referenced to VCC = AVCC = VREF = 3.3 to 5.5 V, VSS = AVSS = 0 V, –40 to 85°C unless otherwise specified.
2. This applies when using one D/A converter, with the DAi register (i = 0, 1) for the unused D/A converter set to 00h.
The resistor ladder of the A/D converter is not included. Also, the current IVREF always flows even though VREF
may have been set to be unconnected by the ADCON1 register.
10
±3
±7
±5
±7
±2
±3
±7
±5
±7
±2
±1
±3
±3
40
VCC
VREF
Bit
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
kΩ
µs
µs
µs
V
V
10
3.3
2.8
0.3
2.0
0
VREF = VCC
VREF
= VCC
= 5 V
VREF
= VCC
= 3.3 V
VREF = AVCC = VCC = 5.0 V, 3.3 V
VREF
= VCC
= 5 V
VREF
= VCC
= 3.3 V
VREF = AVCC = VCC = 5.0 V, 3.3 V
VREF = VCC
VREF = VCC = 5 V, φAD = 10 MHz
VREF = VCC = 5 V, φAD = 10 MHz
ANEX0, ANEX1 input, AN0 to AN7 input,
AN0_0 to AN0_7 input, AN2_0 to AN2_7 input
External operation amp connection mode
ANEX0, ANEX1 input, AN0 to AN7 input,
AN0_0 to AN0_7 input, AN2_0 to AN2_7 input
External operation amp connection mode
ANEX0, ANEX1 input, AN0 to AN7 input,
AN0_0 to AN0_7 input, AN2_0 to AN2_7 input
External operation amp connection mode
ANEX0, ANEX1 input, AN0 to AN7 input,
AN0_0 to AN0_7 input, AN2_0 to AN2_7 input
External operation amp connection mode
Resolution
Integral 10 bits
nonlinearity
error
8 bits
Absolute 10 bits
accuracy
8 bits
Differential nonlinearity error
Offset error
Gain error
Resistor ladder
10-bit conversion time,
sample & hold available
8-bit conversion time,
sample & hold available
Sampling time
Reference voltage
Analog input voltage
–
INL
–
DNL
–
–
RLADDER
tCONV
tSAMP
VREF
VIA
Symbol Parameter Min.
Standard Unit
Measuring Condition Max.
Typ.
Rev.2.40 Aug 25, 2006 page 56 of 88
REJ03B0003-0240
M16C/6N Group (M16C/6N4) 5. Electric Characteristics (Normal-ver.)
Under development
This document is under development and its contents are subject to change.
2
150
150
ms
µs
µs
Time for internal power supply stabilization during powering-on
STOP release time
Low power dissipation mode wait mode release time
td(P-R)
td(R-S)
td(W-S)
Symbol Parameter Min.
Standard Unit
Measuring
Condition Max.
Typ.
VCC = 3.0 to 5.5 V
Table 5.31 Power Supply Circuit Timing Characteristics
CPU clock
VCC
td(P-R)
td(P-R)
Time for internal power supply
stabilization during powering-on
td(R-S)
STOP release time
td(W-S)
Low power dissipation mode
wait mode release time
CPU clock
td(W-S)
td(R-S)
(b)
(a)
Interrupt for
(a) Stop mode release
or
(b) Wait mode release
Figure 5.11 Power Supply Circuit Timing Diagram
Rev.2.40 Aug 25, 2006 page 57 of 88
REJ03B0003-0240
M16C/6N Group (M16C/6N4) 5. Electric Characteristics (Normal-ver.)
Under development
This document is under development and its contents are subject to change.
Table 5.32 Electrical Characteristics (1) (1)
V
CC
-2.0
V
CC
-0.3
3.0
3.0
0.2
0.2
30
2.0
2.5
1.6
0
0
50
1.5
15
HIGH output
voltage
HIGH output
voltage
HIGH output
voltage
HIGH output
voltage
LOW output
voltage
LOW output
voltage
LOW output
voltage
LOW output
voltage
Hysteresis
Hysteresis
HIGH input
current
LOW input
current
Pull-up
resistance
Feedback resistance
Feedback resistance
RAM retention voltage
VOH
VOH
VOH
VOL
VOL
VOL
VT+-VT-
VT+-VT-
IIH
IIL
RPULLUP
RfXIN
RfXCIN
VRAM
IOH = –5 mA
IOH = –200 µA
IOH = –1 mA
IOH = –0.5 mA
With no load applied
With no load applied
IOL = 5 mA
IOL = 200 µA
IOL = 1 mA
IOL = 0.5 mA
With no load applied
With no load applied
VI = 5 V
VI = 0 V
VI = 0 V
At stop mode
V
V
V
V
V
V
V
V
V
V
µA
µA
kΩ
MΩ
MΩ
V
Measuring Condition
Standard
Min. Unit
VCC
VCC
VCC
VCC
2.0
0.45
2.0
2.0
1.0
2.5
5.0
–5.0
170
Parameter
Symbol
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0, P7_2 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0,
P9_2 to P9_7, P10_0 to P10_7
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0, P7_2 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0,
P9_2 to P9_7, P10_0 to P10_7
XOUT HIGHPOWER
LOWPOWER
XCOUT HIGHPOWER
LOWPOWER
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7
XOUT HIGHPOWER
LOWPOWER
XCOUT HIGHPOWER
LOWPOWER
_________ _______
HOLD, RDY, TA0IN to TA4IN, TB0IN to TB5IN,
________ ________ _______ _____________ _________ _________
INT0 to INT5, NMI, ADTRG, CTS0 to CTS2,
SCL0 to SCL2, SDA0 to SDA2, CLK0 to CLK3,
_____ _____
TA0OUT to TA4OUT, KI0 to KI3,
RXD0 to RXD2, SIN3
_____________
RESET
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7,
____________
XIN, RESET, CNVSS, BYTE
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7,
____________
XIN, RESET, CNVSS, BYTE
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0, P7_2 to P7_7, P8_0 to
P8_4, P8_6, P8_7, P9_0, P9_2 to P9_7,
P10_0 to P10_7
XIN
XCIN
Typ. Max.
NOTES:
1. Referenced to VCC = 4.2 to 5.5 V, VSS = 0 V at Topr = –40 to 85°C, f(BCLK) = 24 MHz unless otherwise specified.
VCC = 5 V
Rev.2.40 Aug 25, 2006 page 58 of 88
REJ03B0003-0240
M16C/6N Group (M16C/6N4) 5. Electric Characteristics (Normal-ver.)
Under development
This document is under development and its contents are subject to change.
Table 5.33 Electrical Characteristics (2) (1)
Mask ROM f(BCLK) = 24 MHz,
PLL operation,
No division
On-chip oscillation,
No division
Flash memory f(BCLK) = 24 MHz,
PLL operation,
No division
On-chip oscillation,
No division
Flash memory f(BCLK) = 10 MHz,
program VCC = 5 V
Flash memory f(BCLK) = 10 MHz,
erase VCC = 5 V
Mask ROM f(BCLK) = 32 kHz,
Low power dissipation
mode, ROM (2)
Flash memory f(BCLK) = 32 kHz,
Low power dissipation
mode, RAM (2)
f(BCLK) = 32 kHz,
Low power dissipation
mode,
Flash memory (2)
Mask ROM On-chip oscillation,
Flash memory Wait mode
f(BCLK) = 32 kHz,
Wait mode (3),
Oscillation capacity High
f(BCLK) = 32 kHz,
Wait mode (3),
Oscillation capacity Low
Stop mode,
Topr = 25°C
NOTES:
1. Referenced to VCC = 3.0 to 5.5 V, VSS = 0 V at Topr = –40 to 85°C, f(BCLK) = 24 MHz unless otherwise specified.
2. This indicates the memory in which the program to be executed exists.
3. With one timer operated using fC32.
20
1
22
1.8
15
25
25
25
420
50
8.5
3.0
0.8
Power supply
current
(VCC
= 3.0 to 5.5 V)
ICC mA
mA
mA
mA
mA
mA
µA
µA
µA
µA
µA
µA
µA
Measuring Condition Standard
Min. Unit
36
38
3.0
ParameterSymbol
In single-chip mode,
the output pins are
open and other pins
are VSS.
Typ. Max.
Rev.2.40 Aug 25, 2006 page 59 of 88
REJ03B0003-0240
M16C/6N Group (M16C/6N4) 5. Electric Characteristics (Normal-ver.)
Under development
This document is under development and its contents are subject to change.
15
15
ns
ns
ns
ns
ns
External clock input cycle time
External clock input HIGH pulse width
External clock input LOW pulse width
External clock rise time
External clock fall time
Symbol Parameter Min.
Standard Unit
Max.
62.5
25
25
tC
tw(H)
tw(L)
tr
tf
Timing Requirements
(Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85°C unless otherwise specified)
Table 5.34 External Clock Input (XIN Input)
Table 5.35 Memory Expansion Mode and Microprocessor Mode
(NOTE 1)
(NOTE 2)
(NOTE 3)
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data input access time (for setting with no wait)
Data input access time (for setting with wait)
Data input access time (when accessing multiplexed bus area)
Data input setup time
________
RDY input setup time
__________
HOLD input setup time
Data input hold time
________
RDY input hold time
__________
HOLD input hold time
Symbol Parameter Min.
Standard Unit
Max.
40
30
40
0
0
0
tac1(RD-DB)
tac2(RD-DB)
tac3(RD-DB)
tsu(DB-RD)
tsu(RDY-BCLK)
tsu(HOLD-BCLK)
th(RD-DB)
th(BCLK-RDY)
th(BCLK-HOLD)
NOTES:
1. Calculated according to the BCLK frequency as follows:
0.5 ✕ 109
f(BCLK) – 45 [ns]
2. Calculated according to the BCLK frequency as follows:
(n –0.5) ✕ 109
f(BCLK) – 45 [ns]
n is “2” for 1-wait setting, “3” for 2-wait setting and “4” for 3-wait setting.
3. Calculated according to the BCLK frequency as follows:
(n –0.5) ✕ 109
f(BCLK) – 45 [ns] n is “2” for 2-wait setting, “3” for 3-wait setting.
VCC = 5 V
Rev.2.40 Aug 25, 2006 page 60 of 88
REJ03B0003-0240
M16C/6N Group (M16C/6N4) 5. Electric Characteristics (Normal-ver.)
Under development
This document is under development and its contents are subject to change.
Timing Requirements
(Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85°C unless otherwise specified)
Table 5.36 Timer A Input (Counter Input in Event Counter Mode)
ns
ns
ns
TAiIN input cycle time
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
Symbol Parameter Min.
Standard Unit
Max.
100
40
40
Table 5.37 Timer A Input (Gating Input in Timer Mode)
tc(TA)
tw(TAH)
tw(TAL)
Table 5.38 Timer A Input (External Trigger Input in One-shot Timer Mode)
Table 5.39 Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Table 5.40 Timer A Input (Counter Increment/decrement Input in Event Counter Mode)
ns
ns
ns
TAiIN input cycle time
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
Symbol Parameter Min.
Standard Unit
Max.
400
200
200
tc(TA)
tw(TAH)
tw(TAL)
ns
ns
ns
TAiIN input cycle time
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
Symbol Parameter Min.
Standard Unit
Max.
200
100
100
tc(TA)
tw(TAH)
tw(TAL)
ns
ns
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
Symbol Parameter Min.
Standard Unit
Max.
100
100
tw(TAH)
tw(TAL)
ns
ns
ns
ns
ns
TAiOUT input cycle time
TAiOUT input HIGH pulse width
TAiOUT input LOW pulse width
TAiOUT input setup time
TAiOUT input hold time
Symbol Parameter Min.
Standard Unit
Max.
2000
1000
1000
400
400
tc(UP)
tw(UPH)
tw(UPL)
tsu(UP-TIN)
th(TIN-UP)
Table 5.41 Timer A Input (Two-phase Pulse Input in Event Counter Mode)
ns
ns
ns
TAiIN input cycle rime
TAiOUT input setup time
TAiIN input setup time
Symbol Parameter Min.
Standard Unit
Max.
800
200
200
tc(TA)
tsu(TAIN-TAOUT)
tsu(TAOUT-TAIN)
VCC = 5 V
Rev.2.40 Aug 25, 2006 page 61 of 88
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M16C/6N Group (M16C/6N4) 5. Electric Characteristics (Normal-ver.)
Under development
This document is under development and its contents are subject to change.
ns
ns
ns
ns
ns
ns
TBiIN input cycle time (counted on one edge)
TBiIN input HIGH pulse width (counted on one edge)
TBiIN input LOW pulse width (counted on one edge)
TBiIN input cycle time (counted on both edges)
TBiIN input HIGH pulse width (counted on both edges)
TBiIN input LOW pulse width (counted on both edges)
Symbol Parameter Min.
Standard Unit
Max.
100
40
40
200
80
80
Table 5.43 Timer B Input (Pulse Period Measurement Mode)
tc(TB)
tw(TBH)
tw(TBL)
tc(TB)
tw(TBH)
tw(TBL)
Timing Requirements
(Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85°C unless otherwise specified)
Table 5.42 Timer B Input (Counter Input in Event Counter Mode)
Table 5.44 Timer B Input (Pulse Width Measurement Mode)
Table 5.45 A/D Trigger Input
Table 5.46 Serial Interface
ns
ns
ns
TBiIN input cycle time
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
Symbol Parameter Min.
Standard Unit
Max.
400
200
200
tc(TB)
tw(TBH)
tw(TBL)
ns
ns
ns
TBiIN input cycle time
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
Symbol Parameter Min.
Standard Unit
Max.
400
200
200
tc(TB)
tw(TBH)
tw(TBL)
ns
ns
_____________
ADTRG input cycle time (trigger able minimum)
_____________
ADTRG input LOW pulse width
Symbol Parameter Min.
Standard Unit
Max.
1000
125
tC(AD)
tw(ADL)
80
ns
ns
ns
ns
ns
ns
ns
CLKi input cycle time
CLKi input HIGH pulse width
CLKi input LOW pulse width
TXDi output delay time
TXDi hold time
RXDi input setup time
RXDi input hold time
Symbol Parameter Min.
Standard Unit
Max.
200
100
100
0
70
90
tc(CK)
tw(CKH)
tw(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
_______
Table 5.47 External Interrupt INTi Input
ns
ns
_______
INTi input HIGH pulse width
_______
INTi input LOW pulse width
Symbol Parameter Min.
Standard Unit
Max.
250
250
tw(INH)
tw(INL)
VCC = 5 V
Rev.2.40 Aug 25, 2006 page 62 of 88
REJ03B0003-0240
M16C/6N Group (M16C/6N4) 5. Electric Characteristics (Normal-ver.)
Under development
This document is under development and its contents are subject to change.
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
th(WR-AD)
td(BCLK-CS)
th(BCLK-CS)
td(BCLK-ALE)
th(BCLK-ALE)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
td(DB-WR)
th(WR-DB)
td(BCLK-HLDA)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address output delay time
Address output hold time (in relation to BCLK)
Address output hold time (in relation to RD)
Address output hold time (in relation to WR)
Chip select output delay time
Chip select output hold time (in relation to BCLK)
ALE signal output delay time
ALE signal output hold time
RD signal output delay time
RD signal output hold time
WR signal output delay time
WR signal output hold time
Data output delay time (in relation to BCLK)
Data output hold time (in relation to BCLK) (3)
Data output delay time (in relation to WR)
Data output hold time (in relation to WR) (3)
__________
HLDA output delay time
Symbol Parameter Min.
Standard Unit
Max.
4
0
(NOTE 1)
4
–4
0
0
4
(NOTE 2)
(NOTE 1)
Switching Characteristics
(Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified)
Table 5.48 Memory Expansion Mode and Microprocessor Mode (for setting with no wait)
25
25
15
25
25
40
40
NOTES:
1. Calculated according to the BCLK frequency as follows:
0.5 ✕ 109
f(BCLK) – 10 [ns]
2. Calculated according to the BCLK frequency as follows:
0.5 ✕ 109
f(BCLK) – 40 [ns]
3. This standard value shows the timing when the
output is off, and does not show hold time of
data bus.
Hold time of data bus varies with capacitor volume
and pull-up (pull-down) resistance value.
Hold time of data bus is expressed in
t = – CR ✕ ln (1 – VOL / VCC)
by a circuit of the right figure.
For example, when VOL = 0.2 VCC, C = 30 pF,
R =1 kΩ, hold time of output “L” level is
t = – 30 pF ✕ 1 kΩ ✕ ln (1 – 0.2 VCC / VCC) = 6.7 ns.
Figure 5.12 Port P0 to P10 Measurement Circuit
DBi
R
C
30 pF
P6
P7
P8
P10
P9
P0
P1
P2
P3
P4
P5
Measuring
Condition
Figure 5.12
f(BCLK) is 12.5 MHz or less.
VCC = 5 V
Rev.2.40 Aug 25, 2006 page 63 of 88
REJ03B0003-0240
M16C/6N Group (M16C/6N4) 5. Electric Characteristics (Normal-ver.)
Under development
This document is under development and its contents are subject to change.
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
th(WR-AD)
td(BCLK-CS)
th(BCLK-CS)
td(BCLK-ALE)
th(BCLK-ALE)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
td(DB-WR)
th(WR-DB)
td(BCLK-HLDA)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address output delay time
Address output hold time (in relation to BCLK)
Address output hold time (in relation to RD)
Address output hold time (in relation to WR)
Chip select output delay time
Chip select output hold time (in relation to BCLK)
ALE signal output delay time
ALE signal output hold time
RD signal output delay time
RD signal output hold time
WR signal output delay time
WR signal output hold time
Data output delay time (in relation to BCLK)
Data output hold time (in relation to BCLK) (3)
Data output delay time (in relation to WR)
Data output hold time (in relation to WR) (3)
__________
HLDA output delay time
Symbol Parameter Min.
Standard Unit
Max.
4
0
(NOTE 1)
4
–4
0
0
4
(NOTE 2)
(NOTE 1)
Switching Characteristics
(Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified)
Table 5.49
Memory Expansion Mode and Microprocessor Mode (for 1- to 3-wait setting and external area access)
25
25
15
25
25
40
40
NOTES:
1. Calculated according to the BCLK frequency as follows:
0.5 ✕ 109
f(BCLK) – 10 [ns]
2. Calculated according to the BCLK frequency as follows:
(n – 0.5) ✕ 109n is “1” for 1-wait setting, “2” for 2-wait setting and “3” for 3-wait setting.
f(BCLK) – 40 [ns] When n = 1, f(BCLK) is 12.5 MHz or less.
3. This standard value shows the timing when the
output is off, and does not show hold time of
data bus.
Hold time of data bus varies with capacitor volume
and pull-up (pull-down) resistance value.
Hold time of data bus is expressed in
t = – CR ✕ ln (1 – VOL / VCC)
by a circuit of the right figure.
For example, when VOL = 0.2 VCC, C = 30 pF,
R =1 kΩ, hold time of output “L” level is
t = – 30 pF ✕ 1 kΩ ✕ ln (1 – 0.2 VCC / VCC) = 6.7 ns.
DBi
R
C
Measuring
Condition
Figure 5.12
VCC = 5 V
Rev.2.40 Aug 25, 2006 page 64 of 88
REJ03B0003-0240
M16C/6N Group (M16C/6N4) 5. Electric Characteristics (Normal-ver.)
Under development
This document is under development and its contents are subject to change.
4
(NOTE 1)
(NOTE 1)
4
(NOTE 1)
(NOTE 1)
0
0
4
(NOTE 2)
(NOTE 1)
–4
(NOTE 3)
(NOTE 4)
0
0
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
th(WR-AD)
td(BCLK-CS)
th(BCLK-CS)
th(RD-CS)
th(WR-CS)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
td(DB-WR)
th(WR-DB)
td(BCLK-HLDA)
td(BCLK-ALE)
th(BCLK-ALE)
td(AD-ALE)
th(ALE-AD)
td(AD-RD)
td(AD-WR)
tdZ(RD-AD)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address output delay time
Address output hold time (in relation to BCLK)
Address output hold time (in relation to RD)
Address output hold time (in relation to WR)
Chip select output delay time
Chip select output hold time (in relation to BCLK)
Chip select output hold time (in relation to RD)
Chip select output hold time (in relation to WR)
RD signal output delay time
RD signal output hold time
WR signal output delay time
WR signal output hold time
Data output delay time (in relation to BCLK)
Data output hold time (in relation to BCLK)
Data output delay time (in relation to WR)
Data output hold time (in relation to WR)
__________
HLDA output delay time
ALE signal output delay time (in relation to BCLK)
ALE signal output hold time (in relation to BCLK)
ALE signal output delay time (in relation to Address)
ALE signal output hold time (in relation to Address)
RD signal output delay from the end of Address
WR signal output delay from the end of Address
Address output floating start time
Symbol Parameter Min.
Standard Unit
Max.
Switching Characteristics
(Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified)
Table 5.50 Memory Expansion Mode and Microprocessor Mode
(for 2- to 3-wait setting, external area access and multiplexed bus selection)
25
25
25
25
40
40
15
8
Measuring
Condition
Figure 5.12
NOTES:
1. Calculated according to the BCLK frequency as follows:
0.5 ✕ 109
f(BCLK) – 10 [ns]
2. Calculated according to the BCLK frequency as follows:
(n –0.5) ✕ 109
f(BCLK) – 40 [ns] n is “2” for 2-wait setting, “3” for 3-wait setting.
3. Calculated according to the BCLK frequency as follows:
0.5 ✕ 109
f(BCLK) – 25 [ns]
4. Calculated according to the BCLK frequency as follows:
0.5 ✕ 109
f(BCLK) – 15 [ns]
VCC = 5 V
Rev.2.40 Aug 25, 2006 page 65 of 88
REJ03B0003-0240
M16C/6N Group (M16C/6N4) 5. Electric Characteristics (Normal-ver.)
Under development
This document is under development and its contents are subject to change.
Figure 5.13 Timing Diagram (1)
tsu(D—C)
CLKi
TXDi
RXDi
tc(CK)
tw(CKH)
tw(CKL)
tw(INL)
tw(INH)
td(C—Q) th(C—D)
th(C—Q)
INTi input
tc(TB)
tw(TBH)
tw(TBL)
tc(AD)
tw(ADL)
ADTRG input
TBiIN input
Two-phase pulse input in event counter mode
tsu(TAOUT—TAIN)
tsu(TAOUT—TAIN)
tsu(TAIN—TAOUT)
tC(TA)
tsu(TAIN—TAOUT)
TAiIN input
TAiOUT input
tc(TA)
tw(TAH)
tw(TAL)
tc(UP)
tw(UPH)
tw(UPL)
TAiIN input
TAiOUT input
During event counter mode
TAiIN input
(When count on falling edge
is selected)
TAiIN input
(When count on rising edge
is selected)
TAiOUT input
(Up/down input)
t
h(TIN—UP)
t
su(UP—TIN)
trtr
tc
tw(H) tw(L)
XIN input
VCC = 5 V
Rev.2.40 Aug 25, 2006 page 66 of 88
REJ03B0003-0240
M16C/6N Group (M16C/6N4) 5. Electric Characteristics (Normal-ver.)
Under development
This document is under development and its contents are subject to change.
Figure 5.14 Timing Diagram (2)
Measuring conditions :
VCC = 5 V
Input timing voltage : Determined with VIL = 1.0 V, VIH = 4.0 V
Output timing voltage: Determined with VOL = 2.5 V, VOH = 2.5 V
BCLK
HOLD input
HLDA output
P0, P1, P2,
P3, P4,
P5_0 to P5_2 (1)
NOTE:
1.
The above pins are set to high-impedance regardless of the input level of the BYTE pin,
the PM06 bit in the PM0 register, and the PM11 bit in the PM1 register.
Hi–Z
RDY input
BCLK
RD
(Multiplexed bus)
(Multiplexed bus)
WR, WRL, WRH
WR, WRL, WRH
(Separate bus)
RD
(Separate bus)
t
d(BCLK–HLDA)
t
d(BCLK–HLDA)
t
h(BCLK–HOLD)
t
su(HOLD–BCLK)
tsu(RDY–BCLK) th(BCLK–RDY)
Memory Expansion Mode and Microprocessor Mode
(Effective for setting with wait)
(Common to setting with wait and setting without wait)
VCC = 5 V
Rev.2.40 Aug 25, 2006 page 67 of 88
REJ03B0003-0240
M16C/6N Group (M16C/6N4) 5. Electric Characteristics (Normal-ver.)
Under development
This document is under development and its contents are subject to change.
Figure 5.15 Timing Diagram (3)
BCLK
CSi
t
d(BCLK-CS)
25ns.max
ADi
25ns.max
ALE
25ns.max -4ns.min
RD
25ns.max
t
h(BCLK-RD)
0ns.min
t
h(BCLK-AD)
4ns.min
t
h(BCLK-CS)
4ns.min
Hi-Z
DBi
t
h(RD-DB)
0ns.min
0ns.min
t
h(RD-AD)
BHE
tcyc
Read timing
t
d(BCLK-AD)
t
d(BCLK-ALE)
t
h(BCLK-ALE)
t
SU(DB-RD)
t
d(BCLK-RD)
40ns.min
t
ac1(RD-DB)
Memory Expansion Mode and Microprocessor Mode
(For setting with no wait)
WR,WRL,
WRH
25ns.max
t
h(BCLK-WR)
0ns.min
BCLK
CSi
t
d(BCLK-CS)
25ns.max
ADi
t
d(BCLK-AD)
25ns.max
ALE
25ns.max
t
d(BCLK-ALE)
t
h(BCLK-ALE)
-4ns.min
t
h(BCLK-AD)
4ns.min
t
h(BCLK-CS)
4ns.min
tcyc
t
h(WR-AD)
BHE
t
d(BCLK-DB)
40ns.max 4ns.min
t
h(BCLK-DB)
t
d(DB-WR)
(0.5 ✕ tcyc-40)ns.min
t
h(WR-DB)
DBi
Write timing
t
d(BCLK-WR)
Hi-Z
(0.5 ✕ tcyc-45)ns.max
(0.5 ✕ tcyc-10)ns.min
tcyc = 1
f(BCLK)
Measuring conditions :
VCC = 5 V
Input timing voltage : V
IL
= 0.8 V, V
IH
= 2.0 V
Output timing voltage : V
OL
= 0.4 V, V
OH
= 2.4 V
(0.5 ✕ tcyc-10)ns.min
VCC = 5 V
Rev.2.40 Aug 25, 2006 page 68 of 88
REJ03B0003-0240
M16C/6N Group (M16C/6N4) 5. Electric Characteristics (Normal-ver.)
Under development
This document is under development and its contents are subject to change.
Figure 5.16 Timing Diagram (4)
BCLK
CSi
t
d(BCLK-CS)
25ns.max
ADi
t
d(BCLK-AD)
25ns.max
ALE
25ns.max
t
h(BCLK-ALE)
-4ns.min
RD
25ns.max
t
h(BCLK-RD)
0ns.min
t
h(BCLK-AD)
4ns.min
t
h(BCLK-CS)
4ns.min
Hi-Z
DBi
t
SU(DB-RD)
40ns.min
t
h(RD-DB)
0ns.min
tcyc
BHE
Read timing
WR,WRL,
WRH
25ns.max
t
h(BCLK-WR)
0ns.min
BCLK
CSi
t
d(BCLK-CS)
25ns.max
ADi
t
d(BCLK-AD)
25ns.max
ALE
25ns.max
t
d(BCLK-ALE)
t
h(BCLK-ALE)
-4ns.min
t
h(BCLK-AD)
4ns.min
t
h(BCLK-CS)
4ns.min
tcyc
t
h(WR-AD)
BHE
t
d(BCLK-DB)
40ns.max 4ns.min
t
h(BCLK-DB)
t
d(DB-WR)
(0.5 ✕ tcyc-40)ns.min (0.5 ✕ tcyc-10)ns.min
t
h(WR-DB)
DBi
Write timing
t
d(BCLK-ALE)
t
d(BCLK-RD)
t
d(BCLK-WR)
0ns.min
t
h(RD-AD)
t
ac2(RD-DB)
Hi-Z
Memory Expansion Mode and Microprocessor Mode
(For 1-wait setting and external area access)
(1.5 ✕ tcyc-45)ns.max
tcyc = 1
f(BCLK)
Measuring conditions :
VCC = 5 V
Input timing voltage : VIL = 0.8 V, VIH = 2.0 V
Output timing voltage : VOL = 0.4 V, VOH = 2.4 V
(0.5 ✕ tcyc-10)ns.min
VCC = 5 V
Rev.2.40 Aug 25, 2006 page 69 of 88
REJ03B0003-0240
M16C/6N Group (M16C/6N4) 5. Electric Characteristics (Normal-ver.)
Under development
This document is under development and its contents are subject to change.
Figure 5.17 Timing Diagram (5)
Read timing
Write timing
BCLK
CSi
ALE
DBi
ADi
BHE
WR, WRL
WRH
Memory Expansion Mode and Microprocessor Mode
(For 2-wait setting and external area access)
BCLK
CSi
ALE
DBi
ADi
BHE
RD
tcyc
t
d(BCLK-CS)
25ns.max
t
d(BCLK-AD)
25ns.max
t
d(BCLK-ALE)
25ns.max
t
h(BCLK-ALE)
-4ns.min
t
d(BCLK-RD)
25ns.max
Hi-Z
t
SU(DB-RD)
40ns.min
t
h(RD-DB)
0ns.min
t
h(BCLK-RD)
0ns.min
t
h(RD-AD)
0ns.min
t
h(BCLK-AD)
4ns.min
t
h(BCLK-CS)
4ns.min
tcyc
Hi-Z
t
d(BCLK-CS)
25ns.max
t
d(BCLK-AD)
25ns.max
t
d(BCLK-ALE)
25ns.max
t
h(BCLK-ALE)
-4ns.min
t
d(BCLK-WR)
25ns.max
t
h(BCLK-CS)
4ns.min
t
h(BCLK-AD)
4ns.min
t
h(WR-AD)
(0.5 ✕ tcyc-10)ns.min
t
h(BCLK-WR)
0ns.min
t
d(BCLK-DB)
40ns.max
t
d(DB-WR)
(1.5 ✕ tcyc-40)ns.min
t
h(BCLK-DB)
4ns.min
t
h(WR-DB)
(0.5 ✕ tcyc-10)ns.min
t
ac2(RD-DB)
(2.5 ✕ tcyc-45)ns.max
tcyc = 1
f(BCLK)
Measuring conditions :
VCC = 5 V
Input timing voltage : V
IL
= 0.8 V, V
IH
= 2.0 V
Output timing voltage : V
OL
= 0.4 V, V
OH
= 2.4 V
VCC = 5 V
Rev.2.40 Aug 25, 2006 page 70 of 88
REJ03B0003-0240
M16C/6N Group (M16C/6N4) 5. Electric Characteristics (Normal-ver.)
Under development
This document is under development and its contents are subject to change.
Figure 5.18 Timing Diagram (6)
Read timing
Write timing
BCLK
CSi
ALE
DBi
ADi
BHE
WR, WRL
WRH
Memory Expansion Mode and Microprocessor Mode
(For 3-wait setting and external area access)
BCLK
CSi
ALE
DBi
ADi
BHE
RD
tcyc
t
d(BCLK-CS)
25ns.max
t
d(BCLK-AD)
25ns.max
t
d(BCLK-ALE)
25ns.max
t
h(BCLK-ALE)
-4ns.min
t
d(BCLK-RD)
25ns.max
Hi-Z
t
SU(DB-RD)
40ns.min
t
h(RD-DB)
0ns.min
t
h(BCLK-RD)
0ns.min
t
h(RD-AD)
0ns.min
t
h(BCLK-AD)
4ns.min
t
h(BCLK-CS)
4ns.min
tcyc
Hi-Z
t
d(BCLK-CS)
25ns.max
t
d(BCLK-AD)
25ns.max
t
d(BCLK-ALE)
25ns.max
t
h(BCLK-ALE)
-4ns.min
t
d(BCLK-WR)
25ns.max
t
h(BCLK-CS)
4ns.min
t
h(BCLK-AD)
4ns.min
t
h(WR-AD)
(0.5 ✕ tcyc-10)ns.min
t
h(BCLK-WR)
0ns.min
t
d(BCLK-DB)
40ns.max
t
d(DB-WR)
(2.5 ✕ tcyc-40)ns.min
t
h(BCLK-DB)
4ns.min
t
h(WR-DB)
(0.5 ✕ tcyc-10)ns.min
t
ac2(RD-DB)
(3.5 ✕ tcyc-45)ns.max
tcyc = 1
f(BCLK)
Measuring conditions :
VCC = 5 V
Input timing voltage : VIL = 0.8 V, VIH = 2.0 V
Output timing voltage : VOL = 0.4 V, VOH = 2.4 V
VCC = 5 V
Rev.2.40 Aug 25, 2006 page 71 of 88
REJ03B0003-0240
M16C/6N Group (M16C/6N4) 5. Electric Characteristics (Normal-ver.)
Under development
This document is under development and its contents are subject to change.
Figure 5.19 Timing Diagram (7)
Memory Expansion Mode and Microprocessor Mode
(For 1- or 2-wait setting, external area access and multiplexed bus selection)
BCLK
CSi
t
d(BCLK-CS)
25ns.max
ADi
t
d(BCLK-AD)
25ns.max
ALE
t
h(BCLK-ALE)
-4ns.min
RD
25ns.max
t
h(BCLK-RD)
0ns.min
t
h(BCLK-AD)
4ns.min
t
h(BCLK-CS)
4ns.min
tcyc
t
h(RD-CS)
t
h(RD-AD)
BHE
ADi
/DBi t
h(RD-DB)
0ns.min
t
d(AD-ALE)
Read timing
t
d(BCLK-WR)
25ns.max
t
h(BCLK-WR)
0ns.min
BCLK
CSi
t
d(BCLK-CS)
25ns.max
ADi
t
d(BCLK-AD)
25ns.max
ALE
25ns.max
t
h(BCLK-ALE)
-4ns.min
t
h(BCLK-AD)
4ns.min
t
h(BCLK-CS)
4ns.min
tcyc
t
h(WR-AD)
BHE
t
d(BCLK-DB)
40ns.max 4ns.min
t
h(BCLK-DB)
t
d(DB-WR)
t
h(WR-DB)
ADi
/DBi
Data output
WR,WRL,
WRH
Write timing
Address
Address
Data input
40ns.min
(0.5 ✕ tcyc-10)ns.min
t
d(BCLK-ALE)
t
d(BCLK-RD)
t
h(WR-CS)
Address
t
d(AD-ALE)
(0.5 ✕ tcyc-25)ns.min
(1.5 ✕ tcyc-40)ns.min
(0.5 ✕ tcyc-10)ns.min
t
d(BCLK-ALE)
(0.5 ✕ tcyc-25)ns.min
Address
25ns.max
t
SU(DB-RD)
t
ac3(RD-DB)
(0.5 ✕ tcyc-10)ns.min
t
d(AD-RD)
0ns.min
t
dZ(RD-AD)
8ns.max
t
d(AD-WR)
0ns.min
t
h(ALE-AD)
tcyc = 1
f(BCLK)
Measuring conditions :
VCC = 5 V
Input timing voltage : VIL = 0.8 V, VIH = 2.0 V
Output timing voltage : VOL = 0.4 V, VOH = 2.4 V
(1.5 ✕ tcyc-45)ns.max
(0.5 ✕ tcyc-10)ns.min
(0.5 ✕ tcyc-10)ns.min
(0.5 ✕ tcyc-15)ns.min
VCC = 5 V
Rev.2.40 Aug 25, 2006 page 72 of 88
REJ03B0003-0240
M16C/6N Group (M16C/6N4) 5. Electric Characteristics (Normal-ver.)
Under development
This document is under development and its contents are subject to change.
Figure 5.20 Timing Diagram (8)
Read timing
Write timing
Memory Expansion Mode and Microprocessor Mode
(For 3-wait setting, external area access and multiplexed bus selection)
BCLK
CSi
ALE
RD
ADi
/DBi
ADi
BHE
BCLK
CSi
ALE
ADi
/DBi
tcyc
t
d(BCLK-AD)
25ns.max
tcyc
Data output
t
h(BCLK-CS)
4ns.min
t
d(BCLK-CS)
25ns.max
t
d(BCLK-ALE)
25ns.max
t
h(BCLK-ALE)
-4ns.min
t
d(BCLK-RD)
25ns.max
t
h(BCLK-RD)
0ns.min
t
SU(DB-RD)
40ns.min
t
h(RD-DB)
0ns.min
t
h(RD-AD)
(0.5 ✕ tcyc-10)ns.min
t
h(BCLK-AD)
4ns.min
t
d(BCLK-CS)
25ns.max
t
d(BCLK-AD)
25ns.max
t
h(BCLK-DB)
4ns.min
t
h(BCLK-WR)
0ns.min
t
h(WR-AD)
(0.5 ✕ tcyc-10)ns.min
t
h(BCLK-AD)
4ns.min
t
h(BCLK-CS)
4ns.min
t
d(BCLK-ALE)
25ns.max
t
d(BCLK-WR)
25ns.max
t
-4ns.min
t
h(WR-DB)
(0.5 ✕ tcyc-10)ns.min
Data input
Address
Address
ADi
BHE
WR, WRL
WRH
t
d(AD-ALE)
(0.5 ✕ tcyc-25)ns.min
t
d(AD-RD)
0ns.min
t
dZ(RD-AD)
8ns.max
t
ac3(RD-DB)
t
d(BCLK-DB)
40ns.max
(0.5 ✕ tcyc-10)ns.min
t
h(WR-CS)
t
d(AD-WR)
0ns.min
t
h(RD-CS)
(0.5 ✕ tcyc-10)ns.min
t
d(AD-ALE)
(0.5 ✕ tcyc-25)ns.min
(2.5 ✕ tcyc-45)ns.max
(no multiplex)
(no multiplex)
tcyc = 1
f(BCLK)
Measuring conditions :
VCC = 5 V
Input timing voltage : VIL = 0.8 V, VIH = 2.0 V
Output timing voltage : VOL = 0.4 V, VOH = 2.4 V
t
d(DB-WR)
(2.5 ✕ tcyc-40)ns.min
h(BCLK-ALE)
(0.5 ✕ tcyc-15)ns.min
t
h(ALE-AD)
VCC = 5 V
Rev.2.40 Aug 25, 2006 page 73 of 88
REJ03B0003-0240
M16C/6N Group (M16C/6N4) 5. Electric Characteristics (Normal-ver.)
Under development
This document is under development and its contents are subject to change.
Table 5.51 Electrical Characteristics (1)
V
CC
-0.5
V
CC
-0.5
V
CC
-0.5
0.2
0.2
50
2.0
2.5
1.6
0
0
100
3.0
25
HIGH output
voltage
HIGH output
voltage
HIGH output
voltage
LOW output
voltage
LOW output
voltage
LOW output
voltage
Hysteresis
Hysteresis
HIGH input
current
LOW input
current
Pull-up
resistance
Feedback resistance
Feedback resistance
RAM retention voltage
VOH
VOH
VOL
VOL
VT+-VT-
VT+-VT-
IIH
IIL
RPULLUP
RfXIN
RfXCIN
VRAM
IOH = –1 mA
IOH = –0.1 mA
IOH = –50 µA
With no load applied
With no load applied
IOL = 1 mA
IOL = 0.1 mA
IOL = 50 µA
With no load applied
With no load applied
VI = 3.3 V
VI = 0 V
VI = 0 V
At stop mode
V
V
V
V
V
V
V
V
µA
µA
kΩ
MΩ
MΩ
V
Measuring Condition
Standard
Min. Unit
VCC
VCC
VCC
0.5
0.5
0.5
0.8
1.8
4.0
–4.0
500
Parameter
Symbol
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0, P7_2 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0,
P9_2 to P9_7, P10_0 to P10_7
XOUT HIGHPOWER
LOWPOWER
XCOUT HIGHPOWER
LOWPOWER
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7
XOUT HIGHPOWER
LOWPOWER
XCOUT HIGHPOWER
LOWPOWER
_________ _______
HOLD, RDY, TA0IN to TA4IN, TB0IN to TB5IN,
________ ________ _______ _____________ _________ _________
INT0 to INT5, NMI, ADTRG, CTS0 to CTS2,
SCL0 to SCL2, SDA0 to SDA2, CLK0 to CLK3,
_____ _____
TA0OUT to TA4OUT, KI0 to KI3,
RXD0 to RXD2, SIN3
_____________
RESET
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7,
____________
XIN, RESET, CNVSS, BYTE
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7,
____________
XIN, RESET, CNVSS, BYTE
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0, P7_2 to P7_7, P8_0 to
P8_4, P8_6, P8_7, P9_0, P9_2 to P9_7,
P10_0 to P10_7
XIN
XCIN
Typ. Max.
NOTES:
1. Referenced to VCC = 3.0 to 3.6 V, VSS = 0 V at Topr = –40 to 85°C, f(BCLK) = 24 MHz unless otherwise specified.
VCC = 3.3 V
Rev.2.40 Aug 25, 2006 page 74 of 88
REJ03B0003-0240
M16C/6N Group (M16C/6N4) 5. Electric Characteristics (Normal-ver.)
Under development
This document is under development and its contents are subject to change.
15
15
ns
ns
ns
ns
ns
External clock input cycle time
External clock input HIGH pulse width
External clock input LOW pulse width
External clock rise time
External clock fall time
Symbol Parameter Min.
Standard Unit
Max.
62.5
25
25
tC
tw(H)
tw(L)
tr
tf
Timing Requirements
(Referenced to VCC = 3.3 V, VSS = 0 V, at Topr = –40 to 85°C unless otherwise specified)
Table 5.52 External Clock Input (XIN Input)
Table 5.53 Memory Expansion Mode and Microprocessor Mode
(NOTE 1)
(NOTE 2)
(NOTE 3)
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data input access time (for setting with no wait)
Data input access time (for setting with wait)
Data input access time (when accessing multiplexed bus area)
Data input setup time
________
RDY input setup time
__________
HOLD input setup time
Data input hold time
________
RDY input hold time
__________
HOLD input hold time
Symbol Parameter Min.
Standard Unit
Max.
50
40
50
0
0
0
tac1(RD-DB)
tac2(RD-DB)
tac3(RD-DB)
tsu(DB-RD)
tsu(RDY-BCLK)
tsu(HOLD-BCLK)
th(RD-DB)
th(BCLK-RDY)
th(BCLK-HOLD)
NOTES:
1. Calculated according to the BCLK frequency as follows:
0.5 ✕ 109
f(BCLK) – 60 [ns]
2. Calculated according to the BCLK frequency as follows:
(n –0.5) ✕ 109
f(BCLK) – 60 [ns]
n is “2” for 1-wait setting, “3” for 2-wait setting and “4” for 3-wait setting.
3. Calculated according to the BCLK frequency as follows:
(n –0.5) ✕ 109
f(BCLK) – 60 [ns] n is “2” for 2-wait setting, “3” for 3-wait setting.
VCC = 3.3 V
Rev.2.40 Aug 25, 2006 page 75 of 88
REJ03B0003-0240
M16C/6N Group (M16C/6N4) 5. Electric Characteristics (Normal-ver.)
Under development
This document is under development and its contents are subject to change.
Timing Requirements
(Referenced to VCC = 3.3 V, VSS = 0 V, at Topr = –40 to 85°C unless otherwise specified)
Table 5.54 Timer A Input (Counter Input in Event Counter Mode)
ns
ns
ns
TAiIN input cycle time
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
Symbol Parameter Min.
Standard Unit
Max.
150
60
60
Table 5.55 Timer A Input (Gating Input in Timer Mode)
tc(TA)
tw(TAH)
tw(TAL)
Table 5.56 Timer A Input (External Trigger Input in One-shot Timer Mode)
Table 5.57 Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Table 5.58 Timer A Input (Counter Increment/decrement Input in Event Counter Mode)
ns
ns
ns
TAiIN input cycle time
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
Symbol Parameter Min.
Standard Unit
Max.
600
300
300
tc(TA)
tw(TAH)
tw(TAL)
ns
ns
ns
TAiIN input cycle time
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
Symbol Parameter Min.
Standard Unit
Max.
300
150
150
tc(TA)
tw(TAH)
tw(TAL)
ns
ns
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
Symbol Parameter Min.
Standard Unit
Max.
150
150
tw(TAH)
tw(TAL)
ns
ns
ns
ns
ns
TAiOUT input cycle time
TAiOUT input HIGH pulse width
TAiOUT input LOW pulse width
TAiOUT input setup time
TAiOUT input hold time
Symbol Parameter Min.
Standard Unit
Max.
3000
1500
1500
600
600
tc(UP)
tw(UPH)
tw(UPL)
tsu(UP-TIN)
th(TIN-UP)
Table 5.59 Timer A Input (Two-phase Pulse Input in Event Counter Mode)
µs
ns
ns
TAiIN input cycle time
TAiOUT input setup time
TAiIN input setup time
Symbol Parameter Min.
Standard Unit
Max.
2
500
500
tc(TA)
tsu(TAIN-TAOUT)
tsu(TAOUT-TAIN)
VCC = 3.3 V
Rev.2.40 Aug 25, 2006 page 76 of 88
REJ03B0003-0240
M16C/6N Group (M16C/6N4) 5. Electric Characteristics (Normal-ver.)
Under development
This document is under development and its contents are subject to change.
ns
ns
ns
ns
ns
ns
TBiIN input cycle time (counted on one edge)
TBiIN input HIGH pulse width (counted on one edge)
TBiIN input LOW pulse width (counted on one edge)
TBiIN input cycle time (counted on both edges)
TBiIN input HIGH pulse width (counted on both edges)
TBiIN input LOW pulse width (counted on both edges)
Symbol Parameter Min.
Standard Unit
Max.
150
60
60
300
120
120
Table 5.61 Timer B Input (Pulse Period Measurement Mode)
tc(TB)
tw(TBH)
tw(TBL)
tc(TB)
tw(TBH)
tw(TBL)
Timing Requirements
(Referenced to VCC = 3.3 V, VSS = 0 V, at Topr = –40 to 85°C unless otherwise specified)
Table 5.60 Timer B Input (Counter Input in Event Counter Mode)
Table 5.62 Timer B Input (Pulse Width Measurement Mode)
Table 5.63 A/D Trigger Input
Table 5.64 Serial Interface
ns
ns
ns
TBiIN input cycle time
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
Symbol Parameter Min.
Standard Unit
Max.
600
300
300
tc(TB)
tw(TBH)
tw(TBL)
ns
ns
ns
TBiIN input cycle time
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
Symbol Parameter Min.
Standard Unit
Max.
600
300
300
tc(TB)
tw(TBH)
tw(TBL)
ns
ns
_____________
ADTRG input cycle time (trigger able minimum)
_____________
ADTRG input LOW pulse width
Symbol Parameter Min.
Standard Unit
Max.
1500
200
tC(AD)
tw(ADL)
160
ns
ns
ns
ns
ns
ns
ns
CLKi input cycle time
CLKi input HIGH pulse width
CLKi input LOW pulse width
TXDi output delay time
TXDi hold time
RXDi input setup time
RXDi input hold time
Symbol Parameter Min.
Standard Unit
Max.
300
150
150
0
100
90
tc(CK)
tw(CKH)
tw(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
_______
Table 5.65 External Interrupt INTi Input
ns
ns
_______
INTi input HIGH pulse width
_______
INTi input LOW pulse width
Symbol Parameter Min.
Standard Unit
Max.
380
380
tw(INH)
tw(INL)
VCC = 3.3 V
Rev.2.40 Aug 25, 2006 page 77 of 88
REJ03B0003-0240
M16C/6N Group (M16C/6N4) 5. Electric Characteristics (Normal-ver.)
Under development
This document is under development and its contents are subject to change.
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
th(WR-AD)
td(BCLK-CS)
th(BCLK-CS)
td(BCLK-ALE)
th(BCLK-ALE)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
td(DB-WR)
th(WR-DB)
td(BCLK-HLDA)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address output delay time
Address output hold time (in relation to BCLK)
Address output hold time (in relation to RD)
Address output hold time (in relation to WR)
Chip select output delay time
Chip select output hold time (in relation to BCLK)
ALE signal output delay time
ALE signal output hold time
RD signal output delay time
RD signal output hold time
WR signal output delay time
WR signal output hold time
Data output delay time (in relation to BCLK)
Data output hold time (in relation to BCLK) (3)
Data output delay time (in relation to WR)
Data output hold time (in relation to WR) (3)
__________
HLDA output delay time
Symbol Parameter Min.
Standard Unit
Max.
4
0
(NOTE 1)
4
–4
0
0
4
(NOTE 2)
(NOTE 1)
Switching Characteristics
(Referenced to VCC = 3.3 V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified)
Table 5.66 Memory Expansion Mode and Microprocessor Mode (for setting with no wait)
30
30
25
30
30
40
40
NOTES:
1. Calculated according to the BCLK frequency as follows:
0.5 ✕ 109
f(BCLK) – 10 [ns]
2. Calculated according to the BCLK frequency as follows:
0.5 ✕ 109
f(BCLK) – 40 [ns]
3. This standard value shows the timing when the
output is off, and does not show hold time of
data bus.
Hold time of data bus varies with capacitor volume
and pull-up (pull-down) resistance value.
Hold time of data bus is expressed in
t = – CR ✕ ln (1 – VOL / VCC)
by a circuit of the right figure.
For example, when VOL = 0.2 VCC, C = 30 pF,
R =1 kΩ, hold time of output “L” level is
t = – 30 pF ✕ 1 kΩ ✕ ln (1 – 0.2 VCC / VCC) = 6.7 ns.
Figure 5.21 Port P0 to P10 Measurement Circuit
DBi
R
C
30 pF
P6
P7
P8
P10
P9
P0
P1
P2
P3
P4
P5
Measuring
Condition
Figure 5.21
f(BCLK) is 12.5 MHz or less.
VCC = 3.3 V
Rev.2.40 Aug 25, 2006 page 78 of 88
REJ03B0003-0240
M16C/6N Group (M16C/6N4) 5. Electric Characteristics (Normal-ver.)
Under development
This document is under development and its contents are subject to change.
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
th(WR-AD)
td(BCLK-CS)
th(BCLK-CS)
td(BCLK-ALE)
th(BCLK-ALE)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
td(DB-WR)
th(WR-DB)
td(BCLK-HLDA)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address output delay time
Address output hold time (in relation to BCLK)
Address output hold time (in relation to RD)
Address output hold time (in relation to WR)
Chip select output delay time
Chip select output hold time (in relation to BCLK)
ALE signal output delay time
ALE signal output hold time
RD signal output delay time
RD signal output hold time
WR signal output delay time
WR signal output hold time
Data output delay time (in relation to BCLK)
Data output hold time (in relation to BCLK) (3)
Data output delay time (in relation to WR)
Data output hold time (in relation to WR) (3)
__________
HLDA output delay time
Symbol Parameter Min.
Standard Unit
Max.
4
0
(NOTE 1)
4
–4
0
0
4
(NOTE 2)
(NOTE 1)
Switching Characteristics
(Referenced to VCC = 3.3 V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified)
Table 5.67
Memory Expansion Mode and Microprocessor Mode (for 1- to 3-wait setting and external area access)
30
30
25
30
30
40
40
NOTES:
1. Calculated according to the BCLK frequency as follows:
0.5 ✕ 109
f(BCLK) – 10 [ns]
2. Calculated according to the BCLK frequency as follows:
(n – 0.5) ✕ 109n is “1” for 1-wait setting, “2” for 2-wait setting and “3” for 3-wait setting.
f(BCLK) – 40 [ns] When n = 1, f(BCLK) is 12.5 MHz or less.
3. This standard value shows the timing when the
output is off, and does not show hold time of
data bus.
Hold time of data bus varies with capacitor volume
and pull-up (pull-down) resistance value.
Hold time of data bus is expressed in
t = – CR ✕ ln (1 – VOL / VCC)
by a circuit of the right figure.
For example, when VOL = 0.2 VCC, C = 30 pF,
R =1 kΩ, hold time of output “L” level is
t = – 30 pF ✕ 1 kΩ ✕ ln (1 – 0.2 VCC / VCC) = 6.7 ns.
DBi
R
C
Measuring
Condition
Figure 5.21
VCC = 3.3 V
Rev.2.40 Aug 25, 2006 page 79 of 88
REJ03B0003-0240
M16C/6N Group (M16C/6N4) 5. Electric Characteristics (Normal-ver.)
Under development
This document is under development and its contents are subject to change.
4
(NOTE 1)
(NOTE 1)
4
(NOTE 1)
(NOTE 1)
0
0
4
(NOTE 2)
(NOTE 1)
–4
(NOTE 3)
(NOTE 4)
0
0
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
th(WR-AD)
td(BCLK-CS)
th(BCLK-CS)
th(RD-CS)
th(WR-CS)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
td(DB-WR)
th(WR-DB)
td(BCLK-HLDA)
td(BCLK-ALE)
th(BCLK-ALE)
td(AD-ALE)
th(ALE-AD)
td(AD-RD)
td(AD-WR)
tdZ(RD-AD)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address output delay time
Address output hold time (in relation to BCLK)
Address output hold time (in relation to RD)
Address output hold time (in relation to WR)
Chip select output delay time
Chip select output hold time (in relation to BCLK)
Chip select output hold time (in relation to RD)
Chip select output hold time (in relation to WR)
RD signal output delay time
RD signal output hold time
WR signal output delay time
WR signal output hold time
Data output delay time (in relation to BCLK)
Data output hold time (in relation to BCLK)
Data output delay time (in relation to WR)
Data output hold time (in relation to WR)
__________
HLDA output delay time
ALE signal output delay time (in relation to BCLK)
ALE signal output hold time (in relation to BCLK)
ALE signal output delay time (in relation to Address)
ALE signal output hold time (in relation to Address)
RD signal output delay from the end of Address
WR signal output delay from the end of Address
Address output floating start time
Symbol Parameter Min.
Standard Unit
Max.
Switching Characteristics
(Referenced to VCC = 3.3 V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified)
Table 5.68 Memory Expansion Mode and Microprocessor Mode
(for 2- to 3-wait setting, external area access and multiplexed bus selection)
50
50
40
40
50
40
25
8
Measuring
Condition
Figure 5.21
NOTES:
1. Calculated according to the BCLK frequency as follows:
0.5 ✕ 109
f(BCLK) – 10 [ns]
2. Calculated according to the BCLK frequency as follows:
(n –0.5) ✕ 109
f(BCLK) – 50 [ns] n is “2” for 2-wait setting, “3” for 3-wait setting.
3. Calculated according to the BCLK frequency as follows:
0.5 ✕ 109
f(BCLK) – 40 [ns]
4. Calculated according to the BCLK frequency as follows:
0.5 ✕ 109
f(BCLK) – 15 [ns]
VCC = 3.3 V
Rev.2.40 Aug 25, 2006 page 80 of 88
REJ03B0003-0240
M16C/6N Group (M16C/6N4) 5. Electric Characteristics (Normal-ver.)
Under development
This document is under development and its contents are subject to change.
Figure 5.22 Timing Diagram (1)
tsu(D—C)
CLKi
TXDi
RXDi
tc(CK)
tw(CKH)
tw(CKL)
tw(INL)
tw(INH)
td(C—Q) th(C—D)
th(C—Q)
INTi input
tc(TB)
tw(TBH)
tw(TBL)
tc(AD)
tw(ADL)
ADTRG input
TBiIN input
Two-phase pulse input in event counter mode
t
su(TAOUT—TAIN)
t
su(TAOUT—TAIN)
t
su(TAIN—TAOUT)
t
C(TA)
t
su(TAIN—TAOUT)
TAiIN input
TAiOUT input
tc(TA)
tw(TAH)
tw(TAL)
tc(UP)
tw(UPH)
tw(UPL)
TAiIN input
TAiOUT input
During event counter mode
TAiIN input
(When count on falling edge
is selected)
TAiIN input
(When count on rising edge
is selected)
TAiOUT input
(Up/down input)
t
h(TIN—UP)
t
su(UP—TIN)
trtr
tc
tw(H) tw(L)
XIN input
VCC = 3.3 V
Rev.2.40 Aug 25, 2006 page 81 of 88
REJ03B0003-0240
M16C/6N Group (M16C/6N4) 5. Electric Characteristics (Normal-ver.)
Under development
This document is under development and its contents are subject to change.
Figure 5.23 Timing Diagram (2)
Measuring conditions :
VCC = 3.3 V
Input timing voltage : Determined with VIL = 0.6 V, VIH = 2.7 V
Output timing voltage: Determined with VOL = 1.65 V, VOH = 1.65 V
BCLK
HOLD input
HLDA output
P0, P1, P2,
P3, P4,
P5_0 to P5_2 (1)
NOTE:
1.
The above pins are set to high-impedance regardless of the input level of the BYTE pin,
the PM06 bit in the PM0 register, and the PM11 bit in the PM1 register.
Hi–Z
RDY input
BCLK
RD
(Multiplexed bus)
(Multiplexed bus)
WR, WRL, WRH
WR, WRL, WRH
(Separate bus)
RD
(Separate bus)
t
d(BCLK–HLDA)
t
d(BCLK–HLDA)
t
h(BCLK–HOLD)
t
su(HOLD–BCLK)
tsu(RDY–BCLK) th(BCLK–RDY)
Memory Expansion Mode and Microprocessor Mode
(Effective for setting with wait)
(Common to setting with wait and setting without wait)
VCC = 3.3 V
Rev.2.40 Aug 25, 2006 page 82 of 88
REJ03B0003-0240
M16C/6N Group (M16C/6N4) 5. Electric Characteristics (Normal-ver.)
Under development
This document is under development and its contents are subject to change.
Figure 5.24 Timing Diagram (3)
BCLK
CSi
t
d(BCLK-CS)
30ns.max
ADi
30ns.max
ALE
30ns.max -4ns.min
RD
30ns.max
t
h(BCLK-RD)
0ns.min
t
h(BCLK-AD)
4ns.min
t
h(BCLK-CS)
4ns.min
Hi-Z
DBi
t
h(RD-DB)
0ns.min
0ns.min
t
h(RD-AD)
BHE
tcyc
Read timing
t
d(BCLK-AD)
t
d(BCLK-ALE)
t
h(BCLK-ALE)
t
SU(DB-RD)
t
d(BCLK-RD)
50ns.min
t
ac1(RD-DB)
Memory Expansion Mode and Microprocessor Mode
(For setting with no wait)
WR,WRL,
WRH
30ns.max
t
h(BCLK-WR)
0ns.min
BCLK
CSi
t
d(BCLK-CS)
30ns.max
ADi
t
d(BCLK-AD)
30ns.max
ALE
30ns.max
t
d(BCLK-ALE)
t
h(BCLK-ALE)
-4ns.min
t
h(BCLK-AD)
4ns.min
t
h(BCLK-CS)
4ns.min
tcyc
t
h(WR-AD)
BHE
t
d(BCLK-DB)
40ns.max 4ns.min
t
h(BCLK-DB)
t
d(DB-WR)
(0.5 ✕ tcyc-40)ns.min
t
h(WR-DB)
DBi
Write timing
t
d(BCLK-WR)
Hi-Z
(0.5 ✕ tcyc-60)ns.max
(0.5 ✕ tcyc-10)ns.min
tcyc = 1
f(BCLK)
Measuring conditions :
VCC = 3.3 V
Input timing voltage : VIL = 0.6 V, VIH = 2.7 V
Output timing voltage : VOL = 1.65 V, VOH = 1.65 V
(0.5 ✕ tcyc-10)ns.min
VCC = 3.3 V
Rev.2.40 Aug 25, 2006 page 83 of 88
REJ03B0003-0240
M16C/6N Group (M16C/6N4) 5. Electric Characteristics (Normal-ver.)
Under development
This document is under development and its contents are subject to change.
Figure 5.25 Timing Diagram (4)
BCLK
CSi
td(BCLK-CS)
30ns.max
ADi
td(BCLK-AD)
30ns.max
ALE
30ns.max
th(BCLK-ALE)
-4ns.min
RD
30ns.max
th(BCLK-RD)
0ns.min
th(BCLK-AD)
4ns.min
th(BCLK-CS)
4ns.min
Hi-Z
DBi
tSU(DB-RD)
50ns.min
th(RD-DB)
0ns.min
tcyc
BHE
Read timing
WR,WRL,
WRH
30ns.max
th(BCLK-WR)
0ns.min
BCLK
CSi
td(BCLK-CS)
30ns.max
ADi
td(BCLK-AD)
30ns.max
ALE
30ns.max
td(BCLK-ALE) th(BCLK-ALE)
-4ns.min
th(BCLK-AD)
4ns.min
th(BCLK-CS)
4ns.min
tcyc
th(WR-AD)
BHE
td(BCLK-DB)
40ns.max 4ns.min
th(BCLK-DB)
td(DB-WR)
(0.5 ✕ tcyc-40)ns.min (0.5 ✕ tcyc-10)ns.min
th(WR-DB)
DBi
Write timing
td(BCLK-ALE)
td(BCLK-RD)
td(BCLK-WR)
0ns.min
th(RD-AD)
tac2(RD-DB)
Hi-Z
Memory Expansion Mode and Microprocessor Mode
(For 1-wait setting and external area access)
(1.5 ✕ tcyc-60)ns.max
tcyc = 1
f(BCLK)
Measuring conditions :
VCC = 3.3 V
Input timing voltage : V
IL = 0.6 V, VIH = 2.7 V
Output timing voltage : VOL = 1.65 V, VOH = 1.65 V
(0.5 ✕ tcyc-10)ns.min
VCC = 3.3 V
Rev.2.40 Aug 25, 2006 page 84 of 88
REJ03B0003-0240
M16C/6N Group (M16C/6N4) 5. Electric Characteristics (Normal-ver.)
Under development
This document is under development and its contents are subject to change.
Figure 5.26 Timing Diagram (5)
Read timing
Write timing
BCLK
CSi
ALE
DBi
ADi
BHE
WR, WRL
WRH
Memory Expansion Mode and Microprocessor Mode
(For 2-wait setting and external area access)
BCLK
CSi
ALE
DBi
ADi
BHE
RD
tcyc
t
d(BCLK-CS)
30ns.max
t
d(BCLK-AD)
30ns.max
t
d(BCLK-ALE)
30ns.max
t
h(BCLK-ALE)
-4ns.min
t
d(BCLK-RD)
30ns.max
Hi-Z
t
SU(DB-RD)
50ns.min
t
h(RD-DB)
0ns.min
t
h(BCLK-RD)
0ns.min
t
h(RD-AD)
0ns.min
t
h(BCLK-AD)
4ns.min
t
h(BCLK-CS)
4ns.min
tcyc
Hi-Z
t
d(BCLK-CS)
30ns.max
t
d(BCLK-AD)
30ns.max
t
d(BCLK-ALE)
30ns.max
t
h(BCLK-ALE)
-4ns.min
t
d(BCLK-WR)
30ns.max
t
h(BCLK-CS)
4ns.min
t
h(BCLK-AD)
4ns.min
t
h(WR-AD)
(0.5 ✕ tcyc-10)ns.min
t
h(BCLK-WR)
0ns.min
t
d(BCLK-DB)
40ns.max
t
d(DB-WR)
(1.5 ✕ tcyc-40)ns.min
t
h(BCLK-DB)
4ns.min
t
h(WR-DB)
(0.5 ✕ tcyc-10)ns.min
t
ac2(RD-DB)
(2.5 ✕ tcyc-60)ns.max
tcyc = 1
f(BCLK)
Measuring conditions :
VCC = 3.3 V
Input timing voltage : VIL = 0.6 V, VIH = 2.7 V
Output timing voltage : VOL = 1.65 V, VOH = 1.65 V
VCC = 3.3 V
Rev.2.40 Aug 25, 2006 page 85 of 88
REJ03B0003-0240
M16C/6N Group (M16C/6N4) 5. Electric Characteristics (Normal-ver.)
Under development
This document is under development and its contents are subject to change.
Figure 5.27 Timing Diagram (6)
Read timing
Write timing
BCLK
CSi
ALE
DBi
ADi
BHE
WR, WRL
WRH
Memory Expansion Mode and Microprocessor Mode
(For 3-wait setting and external area access)
BCLK
CSi
ALE
DBi
ADi
BHE
RD
tcyc
t
d(BCLK-CS)
30ns.max
t
d(BCLK-AD)
30ns.max
t
d(BCLK-ALE)
30ns.max
t
h(BCLK-ALE)
-4ns.min
t
d(BCLK-RD)
30ns.max
Hi-Z
t
SU(DB-RD)
50ns.min
t
h(RD-DB)
0ns.min
t
h(BCLK-RD)
0ns.min
t
h(RD-AD)
0ns.min
t
h(BCLK-AD)
4ns.min
t
h(BCLK-CS)
4ns.min
tcyc
Hi-Z
t
d(BCLK-CS)
30ns.max
t
d(BCLK-AD)
30ns.max
t
d(BCLK-ALE)
30ns.max
t
h(BCLK-ALE)
-4ns.min
t
d(BCLK-WR)
30ns.max
t
h(BCLK-CS)
4ns.min
t
h(BCLK-AD)
4ns.min
t
h(WR-AD)
(0.5 ✕ tcyc-10)ns.min
t
h(BCLK-WR)
0ns.min
t
d(BCLK-DB)
40ns.max
t
d(DB-WR)
(2.5 ✕ tcyc-40)ns.min
t
h(BCLK-DB)
4ns.min
t
h(WR-DB)
(0.5 ✕ tcyc-10)ns.min
t
ac2(RD-DB)
(3.5 ✕ tcyc-60)ns.max
tcyc = 1
f(BCLK)
Measuring conditions :
VCC = 3.3 V
Input timing voltage : V
IL
= 0.6 V, V
IH
= 2.7 V
Output timing voltage : V
OL
= 1.65 V, V
OH
= 1.65 V
VCC = 3.3 V
Rev.2.40 Aug 25, 2006 page 86 of 88
REJ03B0003-0240
M16C/6N Group (M16C/6N4) 5. Electric Characteristics (Normal-ver.)
Under development
This document is under development and its contents are subject to change.
Figure 5.28 Timing Diagram (7)
Memory Expansion Mode and Microprocessor Mode
(For 2-wait setting, external area access and multiplexed bus selection)
BCLK
CSi
t
d(BCLK-CS)
40ns.max
ADi
t
d(BCLK-AD)
40ns.max
ALE
t
h(BCLK-ALE)
-4ns.min
RD
40ns.max
t
h(BCLK-RD)
0ns.min
t
h(BCLK-AD)
4ns.min
t
h(BCLK-CS)
4ns.min
tcyc
t
h(RD-CS)
t
h(RD-AD)
BHE
ADi
/DBi t
h(RD-DB)
0ns.min
t
d(AD-ALE)
Read timing
t
d(BCLK-WR)
40ns.max
t
h(BCLK-WR)
0ns.min
BCLK
CSi
t
d(BCLK-CS)
40ns.max
ADi
t
d(BCLK-AD)
40ns.max
ALE
40ns.max
t
h(BCLK-ALE)
-4ns.min
t
h(BCLK-AD)
4ns.min
t
h(BCLK-CS)
4ns.min
tcyc
t
h(WR-AD)
BHE
t
d(BCLK-DB)
50ns.max 4ns.min
t
h(BCLK-DB)
t
d(DB-WR)
t
h(WR-DB)
ADi
/DBi
Data output
WR,WRL,
WRH
Write timing
Address
Address
Data input
50ns.min
(0.5 ✕ tcyc-10)ns.min
t
d(BCLK-ALE)
t
d(BCLK-RD)
t
h(WR-CS)
Address
t
d(AD-ALE)
(0.5 ✕ tcyc-40)ns.min
(1.5 ✕ tcyc-50)ns.min
(0.5 ✕ tcyc-10)ns.min
t
d(BCLK-ALE)
(0.5 ✕ tcyc-40)ns.min
Address
40ns.max
t
SU(DB-RD)
t
ac3(RD-DB)
(0.5 ✕ tcyc-10)ns.min
t
d(AD-RD)
0ns.min
t
dZ(RD-AD)
8ns.max
t
d(AD-WR)
0ns.min
t
h(ALE-AD)
tcyc = 1
f(BCLK)
Measuring conditions :
VCC = 3.3 V
Input timing voltage : VIL = 0.6 V, VIH = 2.7 V
Output timing voltage : VOL = 1.65 V, VOH = 1.65 V
(1.5 ✕ tcyc-60)ns.max
(0.5 ✕ tcyc-10)ns.min
(0.5 ✕ tcyc-10)ns.min
(0.5 ✕ tcyc-15)ns.min
VCC = 3.3 V
Rev.2.40 Aug 25, 2006 page 87 of 88
REJ03B0003-0240
M16C/6N Group (M16C/6N4) 5. Electric Characteristics (Normal-ver.)
Under development
This document is under development and its contents are subject to change.
Figure 5.29 Timing Diagram (8)
Read timing
Write timing
Memory Expansion Mode and Microprocessor Mode
(For 3-wait setting, external area access and multiplexed bus selection)
BCLK
CSi
ALE
RD
ADi
/DBi
ADi
BHE
BCLK
CSi
ALE
ADi
/DBi
tcyc
td(BCLK-AD)
40ns.max
tcyc
Data output
th(BCLK-CS)
6ns.min
td(BCLK-CS)
40ns.max
td(BCLK-ALE)
40ns.max th(BCLK-ALE)
-4ns.min
td(BCLK-RD)
40ns.max
th(BCLK-RD)
0ns.min
tSU(DB-RD)
50ns.min
th(RD-DB)
0ns.min
th(RD-AD)
(0.5 ✕ tcyc-10)ns.min
th(BCLK-AD)
4ns.min
td(BCLK-CS)
40ns.max
td(BCLK-AD)
40ns.max
th(BCLK-DB)
4ns.min
th(BCLK-WR)
0ns.min
th(WR-AD)
(0.5 ✕ tcyc-10)ns.min
th(BCLK-AD)
4ns.min
th(BCLK-CS)
4ns.min
td(BCLK-ALE)
40ns.max
td(BCLK-WR)
40ns.max
t
-4ns.min
th(WR-DB)
(0.5 ✕ tcyc-10)ns.min
Data input
Address
Address
ADi
BHE
WR, WRL
WRH
td(AD-ALE)
(0.5 ✕ tcyc-40)ns.min
td(AD-RD)
0ns.min
tdZ(RD-AD)
8ns.max tac3(RD-DB)
td(BCLK-DB)
50ns.max
(0.5 ✕ tcyc-10)ns.min
th(WR-CS)
td(AD-WR)
0ns.min
th(RD-CS)
(0.5 ✕ tcyc-10)ns.min
td(AD-ALE)
(0.5 ✕ tcyc-40)ns.min
(2.5 ✕ tcyc-60)ns.max
(no multiplex)
(no multiplex)
tcyc = 1
f(BCLK)
Measuring conditions :
VCC = 3.3 V
Input timing voltage : VIL = 0.6 V, VIH = 2.7 V
Output timing voltage : VOL = 1.65 V, VOH = 1.65 V
td(DB-WR)
(2.5 ✕ tcyc-50)ns.min
h(BCLK-ALE)
(0.5 ✕ tcyc-15)ns.min
th(ALE-AD)
VCC = 3.3 V
Rev.2.40 Aug 25, 2006 page 88 of 88
REJ03B0003-0240
M16C/6N Group (M16C/6N4) Appendix 1. Package Dimensions
Under development
This document is under development and its contents are subject to change.
Appendix 1. Package Dimensions
Terminal cross section
b
1
c
1
b
p
c
2.
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
NOTE)
DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
y
Index mark
x
125
26
50
51
75
76
100
F
*1
*3
*2
Z
E
Z
D
E
D
H
D
H
E
b
p
Detail F
L
1
A
2
A
1
L
A
c
L
1
Z
E
Z
D
c
1
b
1
b
p
A
1
H
E
H
D
y0.08
e0.5
c
0° 8°
x
L0.35 0.5 0.65
0.05 0.1 0.15
A1.7
15.8 16.0 16.2
15.8 16.0 16.2
A
2
1.4
E13.9 14.0 14.1
D13.9 14.0 14.1
Reference
Symbol
Dimension in Millimeters
Min Nom Max
0.15 0.20 0.25
0.09 0.145 0.20
0.08
1.0
1.0
0.18
0.125
1.0
Previous CodeJEITA Package Code RENESAS Code
PLQP0100KB-A 100P6Q-A / FP-100U / FP-100UV
MASS[Typ.]
0.6gP-LQFP100-14x14-0.50
e
0.80.5
0.825
0.575
Z
E
Z
D
b
p
A
1
H
E
H
D
y0.10
e0.65
c
0°10°
L0.4 0.6 0.8
00.1 0.2
A3.05
16.5 16.8 17.1
22.5 22.8 23.1
A
2
2.8
E13.8 14.0 14.2
D19.8 20.0 20.2
Reference
Symbol
Dimension in Millimeters
Min Nom Max
0.25 0.3 0.4
0.13 0.15 0.2
P-QFP100-14x20-0.65 1.6g
MASS[Typ.]
100P6S-APRQP0100JB-A
RENESAS CodeJEITA Package Code Previous Code
y
Index mark
100
81
80 51
50
31
30
1
F
*2
*1
*3
Z
E
Z
D
eb
p
A
H
D
D
E
H
E
c
Detail F
A
1
A
2
L
INCLUDE TRIM OFFSET.
DIMENSION "*3" DOES NOT
NOTE)
DO NOT INCLUDE MOLD FLASH.
DIMENSIONS "*1" AND "*2"1.
2.
REVISION HISTORY M16C/6N Group (M16C/6N4) Data Sheet
Rev. Date Description
Page Summary
A-1
1.00
Jun. 30, 2003
2.00
Nov. 10, 2004
– First edition issued
– Revised edition issued
* Words standardizes (on-chip oscillator)
* 100P6Q-A (100-pin version) is added.
* Revised parts and revised contents are as follows (except for change of a layout
and an expressional change).
1 1. Overview 3rd line: "and LQFP" is added.
2 Table 1.1 Performance outline of M16C/6N Group (M16C/6N4)
• Operation Mode is added.
• Address Space is added.
• Power Consumption is revised.
• "LQFP" is added to Package.
4 Table 1.2 Product List is revised.
Figure 1.2 Type No., Memory Size, and Package:
• "GP: Package 100P6Q-A" is added to Package type.
5 Figure 1.3 Pin Configuration (Top View) (1): "ZP" is added.
6 Figure 1.4 Pin Configuration (Top View) (2) is added. (100P6Q-A)
8 Table 1.4 Pin Description (2): "ZP" is added to Timer A.
12 3. Memory
• 5th to 6th lines: The description about the flash memory version (block A) is added.
Figure 3.1 Memory Map
• Interenal ROM (data area) is added.
• NOTES 3, 4 are added and NOTE 5 is revised.
13 Table 4.1 SFR Information (1)
• The value of After Reset in PM1 register is revised.
• The value of After Reset in CM2 register is revised.
19 Table 4.7 SFR Information (7)
• The value of After Reset in FMR0 register is revised.
27 Table 4.15 SFR Information (15)
• The value of After Reset in U0C1 register is revised.
• The value of After Reset in U1C1 register is revised.
• NOTE 1 is added.
28 Table 4.16 SFR Information (16)
• The value of After Reset in DA0, DA1 registers are revised.
29 Table 5.1 Absolute Maximum Ratings
• "Flash Program Erase" in Operating Ambient Temperature is added.
31 Table 5.3 Recommended Operating Conditions (2)
• Parameters of Power Supply Ripple are added.
• NOTE 4 is revised.
Figure 5.1 Timing of Voltage Fluctuation is added.
32 Table 5.4 Electrical Characteristics (1): Hysteresis
• "CLK4" is revised to "CLK3", and "TA2OUT" is revised to "TA0OUT".
•
____________
Max. of Standard in RESET is revised from "2.2" to "2.5".
• XIN is added.
REVISION HISTORY M16C/6N Group (M16C/6N4) Data Sheet
Rev. Date Description
Page Summary
A-2
34 Table 5.6 A/D Conversion Characteristics: "Tolerance Level Impedance" is added.
35 Table 5.8 Power Supply Circuit Timing Characteristics: "td(M-L)" is deleted.
Figure 5.2 Power Supply Circuit Timing Diagram is added.
36 Table 5.10 Memory Expansion Mode and Microprocessor Mode: "td(BCLK-HLDA)" is deleted.
38 Table 5.21 Serial I/O: Min. of standard in tsu(D-C) is revised from "30" to "70".
39 Table 5.23 Memory Expansion Mode and Microprocessor Mode (for setting with no wait)
• Max. of Standard in td(BCLK-ALE) is revised from "25" to "15".
• td(BCLK-HLDA) is added.
40 Table 5.24 Memory Expansion Mode and Microprocessor Mode (for 1- to 3-wait setting
and external area access)
• Max. of Standard in td(BCLK-ALE) is revised from "25" to "15".
• td(BCLK-HLDA) is added.
41 Table 5.25 Memory Expansion Mode and Microprocessor Mode (for 2- to 3-wait setting,
external area access and multiplexed bus selection)
• td(BCLK-HLDA) is added.
• Max. of Standard in td(BCLK-ALE) is revised from "25" to "15".
42 Figure 5.4 Timing Diagram (1): "XIN input" is added.
44, 45 Figures 5.6 and 5.7 Timing Diagram (3) (4): "DB" in Read timing is revised to "DBi".
46, 47 Figures 5.8 and 5.9 Timing Diagram (5) (6): "DB" in Write timing is revised to "DBi".
49 Figure 5.11 Timing Diagram (8)
• "ADi/DB" in Read/Write timing is revised to "ADi/DBi".
50 Appendix 1. Package Dimensions: 100P6Q-A is added.
– Revised edition issued
* The contents of product are revised. (Normal-ver. is added.)
* Revised parts and revised contents are as follows (except for expressional change).
2 Table 1.1 Performance outline of M16C/6N Group (M16C/6N4)
• Performance outline of Normal-ver. is added.
4 Table 1.2 Product List is revised. (Normal-ver. is added.)
Figure 1.2 Type No., Memory Size, and Package:
• "(no): Normal-ver." is added to Characteristics.
19 Figure 4.7 SFR Information (7): NOTE 1 is revised.
32 Table 5.4 Electrical Characteristics (1)
• Measuring Condition of VOL is revised from “LOL = –200µA” to “LOL = 200µA”.
33 Table 5.5 Electrical Characteristics (2): Mask ROM (5th item)
• “f(XCIN)” is changed to “(f(BCLK)).
34 Table 5.6 A/D Conversion Characteristics: “Tolerance Level Impedance” is deleted.
– Revised edition issued
* Electric Characteristics of Normal-ver. is added.
* Revised parts and revised contents are as follows (except for expressional change).
1 1.1 Applications: Comment of Normal-ver. is added.
4 Table 1.2 Product Information
• Status of development is revised and NOTES 1 and 2 are added.
2.00
Nov. 10, 2004
2.10
Jun. 24, 2005
2.40
Aug. 25, 2006
REVISION HISTORY M16C/6N Group (M16C/6N4) Data Sheet
Rev. Date Description
Page Summary
A-3
7, 8 Tables 1.3 and 1.4 List of Pin Names (1)(2) are added.
9 Table 1.5 Pin Functions (1)
• 3.0 to 5.5 V (Normal-ver.) is added to Description of Power supply input.
22 Table 4.8 SFR Information (8)
• The value of After Reset in IDB0 register is revised.
• The value of After Reset in IDB1 register is revised.
33 Table 5.3 Recommended Operating Conditions (2)
• Power supply ripple is deleted. (three items)
Figure 5.1 Voltage Fluctuation Timing is deleted.
34 Table 5.4 Electrical Characteristics (1): Hysteresis XIN is deleted.
52 to 87 5.2 Electrical Characteristics (Normal-ver.) is added.
2.40
Aug. 25, 2006
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