AT25M02 SPI Serial EEPROM 2-Mbit (262,144 x 8) DATASHEET Features Low-voltage and Standard-voltage Operation Available 1.7V (VCC = 1.7V to 5.5V) 2.5V (VCC = 2.5V to 5.5V) Serial Peripheral Interface (SPI) Compatible Interface Supports SPI Modes 0 (0,0) and 3 (1,1) High Speed Operation 256-byte Page Write Mode Support 5MHz Clock Rate from 1.7V to 5.5V Partial Page Writes Allowed Byte Write Operation Supported Self-timed Write Cycle All Write Operations Complete Within 10ms Max Block Write Protection Ability to Protect the Upper Quarter, Upper Half, or the Entire Memory Array Multiple Write Protection Methods Write Protect (WP) Pin and Write Disable instructions for Both Hardware and Software Data Protection High Reliability Endurance: 1,000,000 Write Cycles Data Retention: 40 Years Green Package Options (Lead-free/Halide-free/RoHS Compliant) 8-lead JEDEC SOIC and 8-ball Thin WLCSP Die Sale Options Wafer form, Waffle Pack, and Bumped Die Available Description The Atmel(R) AT25M02 provides 2,097,152 bits of Serial Electrically Erasable Programmable Read-Only Memory (EEPROM) organized as 262,144 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation is essential. The device is available in space saving 8-lead JEDEC SOIC and 8-ball Thin WLCSP packages. In addition, the device operates from 1.7V to 5.5V. The AT25M02 is enabled through the Chip Select pin (CS) and accessed via a 3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). All programming cycles are completely self-timed and a separate erase cycle is not required before writing to the device. Atmel-8832B-SEEPROM-AT25M02-Datasheet_022016 T a b l e o f C o n te n ts 1. Pin Configurations and Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2. Device Block Diagram and Bus Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3. Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.1 3.2 3.3 3.4 4. Interfacing the AT25M02 on the SPI Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Opcodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hold Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5 6 6 Device Commands and Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.1 4.2 4.3 4.4 Status Register Bit Definition and Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Read Status Register (RDSR) and Low Power Write Poll (LPWP). . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.2.1 Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.2.2 Low Power Write Poll (LPWP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Write Enable (WREN) and Write Disable (WRDI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.3.1 Write Enable Instruction (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.3.2 Write Disable Instruction (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.4.1 Block Write Protect Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.4.2 Write Protect Enable Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5. Read Array Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6. Write Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.1 6.2 7. Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.1 Internal Writing Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.2 Polling Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 13 14 14 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.1 7.2 7.3 7.4 7.5 7.6 7.7 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC and AC Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EEPROM Cell Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-Up Requirements, Reset, and Default Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.7.1 Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.7.2 Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.7.3 Device Default State at Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.7.4 Device Default Condition from Atmel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 15 16 17 18 18 18 18 19 19 19 8. Ordering Code Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 9. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 10. Part Marking Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 11. Packaging Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 11.1 11.2 8S1 -- 8-lead JEDEC SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8U-10 -- 8-ball WLCSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 12. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2 AT25M02 [DATASHEET] Atmel-8832B-SEEPROM-AT25M02-Datasheet_022016 1. Pin Configurations and Pinouts Table 1-1. Pin Description Pin Pin Number Symbol Pin Name and Functional Description 1 2 CS SO Chip Select: Asserting the CS pin selects the device. When the CS pin is deasserted, the device will be deselected and placed in standby mode and the SO pin will be in a high impedance state. When the device is deselected, data will not be accepted on the SI pin. A high-to-low transition on the CS pin is required to start an operation and a low-to-high transition is required to end an operation. When ending the internally self-timed write cycle, the device will not enter the standby mode until the completion of the operation. Serial Data Output: The SO pin is used to shift data out from the device. Data on the SO pin is always clocked out on the falling edge of SCK. The SO pin will be in a high impedance state whenever the device is deselected (CS is deasserted). Write Protect: The Write Protect (WP) pin is used in conjunction with the block protection bits of the Status Register (see Table 4-3 on page 10) to inhibit writing to a portion of, or the entire memory array. Asserted State Pin Type Low Input -- Output Low Input 3 WP 4 GND Ground: The ground reference for the device power supply (VCC). GND should be connected to the system ground. -- Power 5 SI Serial Data Input: Instructions, addresses and data are latched by the AT25M02 on the rising edge of the Serial Clock (SCK) line via the Serial Data Input (SI) pin. -- Input SCK Serial Clock: The Serial Clock (SCK) pin is used to provide a clock to the device and is used to synchronize the flow of data to and from the device. Instructions, addresses and data present on SI pin are always latched in on the rising edge of SCK, while output data on the SO pin is always clocked out on the falling edge of SCK. -- Input 7 HOLD Hold: When the device is selected and a serial sequence is underway, Hold can be used to pause the serial communication with the master device without resetting the serial sequence. To pause, the HOLD pin must be brought low while the SCK pin is low. To resume serial communication, the HOLD pin is brought high while the SCK pin is low (SCK may still toggle during Hold). Inputs to the SI pin will be ignored and the SO pin will be in a high impedance state. Low Input 8 VCC Device Power Supply: The VCC pin is used to supply the source voltage to the device. Operations at invalid VCC voltages may produce spurious results and should not be attempted. -- Power 6 The WP pin can also be used in conjunction with the WPEN bit to prevent inadvertent writing to the Status Register (see Table 4-4 on page 11). The protection is invoked by driving the WP pin to a low state. 8-lead SOIC CS 1 8 8-ball WLCSP VCC SO 2 7 HOLD WP 3 6 SCK GND 4 5 SI Top View VCC 8 HOLD 7 SCK SI 6 5 CS 1 2 SO 3 WP 4 Top View GND Note: Drawings are not to scale. AT25M02 [DATASHEET] Atmel-8832B-SEEPROM-AT25M02-Datasheet_022016 3 2. Device Block Diagram and Bus Connections Figure 2-1. Block Diagram Memory System Control Module CS High Voltage Generation Circuit Power On Reset Generator VCC Suspend Operation Control HOLD Status Register EEPROM Array SO Row Decoder (256 bytes per page x 1024 pages) Full Array WP Range 1 page Half Array WP Range Address Register and Counter Quarter Array WP Range Column Decoder WP SCK Data Register Data Output Buffer Write Protection Control GND Figure 2-2. SI SPI Bus Master Connections to Serial EEPROMs SPI Master: Microcontroller Serial Clock (SPI CK) Data Out (MISO) Data In (MOSI) SI SS3 SS2 SS1 SS0 4 AT25M02 [DATASHEET] Atmel-8832B-SEEPROM-AT25M02-Datasheet_022016 SO SCK SI SO SCK SI SO SCK SI SO SCK Slave 0 AT25xxx Slave 1 AT25xxx Slave 2 AT25xxx Slave 3 AT25xxx CS CS CS CS 3. Device Operation The AT25M02 is controlled by a set of instructions that are sent from a host controller, commonly referred to as the SPI Master. The SPI Master communicates with the AT25M02 via the SPI bus which is comprised of four signal lines: Chip Select (CS), Serial Clock (SCK), Serial Input (SI), and Serial Output (SO). The SPI protocol defines a total of four modes of operation (mode 0, 1, 2, or 3) with each mode differing in respect to the SCK polarity and phase and how the polarity and phase control the flow of data on the SPI bus. The AT25M02 supports the two most common modes, SPI Modes 0 and 3. With SPI Modes 0 and 3, data is always latched in on the rising edge of SCK and always output on the falling edge of SCK. The only difference between SPI Modes 0 and 3 is the polarity of the SCK signal when in the inactive state (when the SPI Master is in standby mode and not transferring any data). SPI Mode 0 is defined as a low SCK while CS is not asserted (at VCC) and SPI Mode 3 has SCK high in the inactive state. The SCK idle state must match when the CS is deasserted both before and after the communication sequence in SPI Mode 0 and 3. The figures in this document depict Mode 0 with a solid line on SCK while CS is inactive and Mode 3 with a dotted line. Figure 3-1. SPI Mode 0 and Mode 3 CS Mode 3 Mode 3 Mode 0 Mode 0 SCK SI MSB SO 3.1 LSB MSB LSB Interfacing the AT25M02 on the SPI Bus Communication to and from the AT25M02 must be initiated by the SPI Master device, such as a microcontroller. The SPI Master device must generate the serial clock for the AT25M02 on the SCK pin. The AT25M02 always operates as a slave due to the fact that the Serial Clock pin (SCK) is always an input. Selecting the Device: The AT25M02 is selected when the CS pin is low. When the device is not selected, data will not be accepted via the SI pin, and the SO pin will remain in a high impedance state. Sending Data to the Device: The AT25M02 uses the Serial Data Input (SI) pin to receive information. All instructions, addresses and data input bytes are clocked into the device with the Most Significant Bit (MSB) first. The SI pin samples on the first rising edge of the SCK line after the CS has been asserted. Receiving Data from the Device: Data output from the device is transmitted on the Serial Data Output (SO) pin, with the MSB output first. The SO data is latched on the first falling edge of SCK after the instruction has been clocked into the device, such as the Read from Memory Array and Read Status Register instructions. See Section 5. "Read Array Operation" on page 12 for more details. 3.2 Device Opcodes Serial Opcode: After the device is selected by driving CS low, the first byte will be received on the SI pin. This byte contains the opcode that defines the operation to be performed. Please refer to Table 4-1 on page 7 for a list of all opcodes that the AT25M02 will respond to. Invalid Opcode: If an invalid opcode is received, no data will be shifted into AT25M02 and the Serial Data Output (SO) pin will remain in a high impedance state until the falling edge of CS is detected again. This will reinitialize the serial communication. AT25M02 [DATASHEET] Atmel-8832B-SEEPROM-AT25M02-Datasheet_022016 5 3.3 Hold Function The HOLD pin is used to pause the serial communication with the device without having to stop or reset the clock sequence. The Hold mode, however, does not have an effect on the internal write cycle. Therefore, if a write cycle is in progress, asserting the HOLD pin will not pause the operation and the write cycle will continue to completion. The Hold mode can only be entered while the CS pin is asserted. The Hold mode is activated by asserting the HOLD pin during the SCK low pulse. If the HOLD pin is asserted during the SCK high pulse, then the Hold mode will not be started until the beginning of the next SCK low pulse. The device will remain in the Hold mode as long as the HOLD pin and CS pin are asserted. While in Hold mode, the SO pin will be in a high impedance state. In addition, both the SI pin and the SCK pin will be ignored. The WP pin, however, can still be asserted or deasserted while in the Hold mode. To end the Hold mode and resume serial communication, the HOLD pin must be deasserted during the SCK low pulse. If the HOLD pin is deasserted during the SCK high pulse, then the Hold mode will not end until the beginning of the next SCK low pulse. If the CS pin is deasserted while the HOLD pin is still asserted, then any operation that may have been started will be aborted and the device will reset the WEL bit in the Status Register back to the Logic 0 state. Figure 3-2. Hold Mode CS SCK HOLD Hold Figure 3-3. Hold Hold Hold Timing CS tCD tCD SCK tHD tHD HOLD tHZ tLZ SO 3.4 Write Protection The Write Protect (WP) pin will allow normal read/write operations when held high. When the WP pin is brought low and WPEN bit is a Logic 1, all write operations to the Status Register are inhibited. The WP pin going low while CS is still low will interrupt a Write to the Status Register. If the internal write cycle has already been initiated, WP going low will have no effect on any write operation to the Status Register. The WP pin function is blocked when the WPEN bit in the Status Register is a Logic 0. This will allow the user to install the AT25M02 device in a system with the WP pin tied to ground and still be able to write to the Status Register. All WP pin functions are enabled when the WPEN bit is set to a Logic 1. 6 AT25M02 [DATASHEET] Atmel-8832B-SEEPROM-AT25M02-Datasheet_022016 4. Device Commands and Addressing The AT25M02 is designed to interface directly with the synchronous Serial Peripheral Interface (SPI) of the 6800 type series of microcontrollers. The AT25M02 utilizes an 8-bit instruction register. The list of instructions and their operation codes are contained in Table 4-1. All instructions, addresses, and data are transferred with the MSB first and start with a high-to-low CS transition. Table 4-1. Instruction Set For the Atmel AT25M02 Instruction Name Instruction Format RDSR 0000 0101 (05h) Read Status Register (SR) Status Register Section 4.2.1 LPWP 0000 1000 (08h) Low Power Write Poll Status Register Section 4.2.2 WREN 0000 0110 (06h) Set Write Enable Latch (WEL) Status Register Section 4.3.1 WRDI 0000 0100 (04h) Reset Write Enable Latch (WEL) Status Register Section 4.3.2 WRSR 0000 0001 (01h) Write Status Register (SR) Status Register Section 4.4 READ 0000 0011 (03h) Read from Memory Array Memory Array Section 5. Write to Memory Array Memory Array Section 6. 0000 0010 (02h) WRITE 4.1 0000 0111 (07h) Operation Description Operates On Refer to Section Status Register Bit Definition and Function The AT25M02 includes an 8-bit Status Register. The Status Register bits modulate various features of the device as shown in Table 4-2. These bits can be changed by specific instructions that are detailed in the following sections. Table 4-2. Status Register Bit Definition Bit Name 7 WPEN 6:4 RFU 3:2 BP1 BP0 Write Protect Enable Reserved for Future Use Block Write Protection Type R/W R R/W 1 WEL Write Enable Latch R/W 0 RDY/BSY Ready/Busy Status R Description 0 See Table 4-4 (Factory Default). 1 See Table 4-4. 0 Reads as zeros when the device is not in a write cycle. 1 Reads as ones when the device is in a write cycle. 00 No array write protection (Factory Default) 01 Quarter memory array protection (see Table 4-3). 10 Half memory array protection (see Table 4-3). 11 Entire memory array protection (see Table 4-3). 0 Device is not write enabled (Power-up Default). 1 Device is write enabled. 0 Device is ready for a new sequence. 1 Device is busy with an internal operation. AT25M02 [DATASHEET] Atmel-8832B-SEEPROM-AT25M02-Datasheet_022016 7 4.2 Read Status Register (RDSR) and Low Power Write Poll (LPWP) 4.2.1 Read Status Register (RDSR) The Read Status Register instruction provides access to the Status Register. The ready/busy and write enable status of the device can be determined by the RDSR instruction. Similarly, the Block Write Protection bits indicate the extent of memory array protection employed. The Status Register is read by asserting the CS pin, followed by sending in a 05h opcode on the SI pin. Upon completion of the opcode, the device will return the 8-bit Status Register value on the SO pin. Figure 4-1. RDSR Waveform CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK RDSR Opcode (05h) SI 0 0 0 0 0 1 0 1 MSB Status Register Data Out High Impedance SO D7 D6 D5 D4 D3 D2 D1 D0 MSB The Status Register can be continuously read for data by continuing to read beyond the first 8-bit value returned. The AT25M02 will update the Status Register value upon the completion of every 8 bits, thereby allowing new Status Register values to be read without having to issue a new RDSR instruction. 4.2.2 Low Power Write Poll (LPWP) The Low Power Write Poll command can be used after any write command as a means to check if the device has completed its internal write cycle. The LPWP command requires an opcode of 08h and will return an FFh value when the part is still busy completing the write cycle. The LPWP command will return a 00h value if the part is no longer in a write cycle. Refer to section Section 6.2.1 on page 14 for a description on implementing a polling routine. Continuous reading of the LPWP state is supported and the value output by the device will be updated every eight bits. Figure 4-2. LPWP Timing CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK LPWP Opcode (08h) SI 0 0 0 0 1 0 0 0 MSB FFh or 00h Data Out High Impedance SO D7 MSB 8 AT25M02 [DATASHEET] Atmel-8832B-SEEPROM-AT25M02-Datasheet_022016 D6 D5 D4 D3 D2 D1 D0 4.3 Write Enable (WREN) and Write Disable (WRDI) Enabling and disabling writing to the Status Register and EEPROM array is accomplished through the Write Enable Instruction (WREN) and the Write Disable Instruction (WRDI). These functions change the status of the WEL bit in the Status Register. 4.3.1 Write Enable Instruction (WREN) The Write Enable Latch (WEL) bit of the Status Register must be set to a Logic 1 prior to each WRSR and WRITE instruction. This is accomplished by sending a WREN (06h) command to the AT25M02. First, the CS pin is driven low to select the device and then a 06h instruction value is clocked in on the SI pin. Then the CS pin can be driven high and the WEL bit will be updated in the Status Register to a Logic 1. The device will power-up in the write disable state (WEL = 0). Figure 4-3. WREN Timing CS 0 1 2 3 4 5 6 7 SCK WREN Opcode (06h) SI 0 0 0 0 0 1 1 0 MSB High Impedance SO 4.3.2 Write Disable Instruction (WRDI) To protect the device against inadvertent writes, the Write Disable instruction (opcode 04h) disables all programming modes by setting the WEL bit to a Logic 0. The WRDI instruction is independent of the status of the WP pin. Figure 4-4. WRDI Timing CS 0 1 2 3 4 5 6 7 SCK WRDI Opcode (04h) SI 0 0 0 0 0 1 0 0 MSB High Impedance SO AT25M02 [DATASHEET] Atmel-8832B-SEEPROM-AT25M02-Datasheet_022016 9 4.4 Write Status Register (WRSR) The Write Status Register (WRSR) instruction enables the SPI Master to change selected bits of the Status Register. Before a WRSR sequence can be initiated, a WREN instruction must be executed to set the WEL to Logic 1. Upon completion of a WREN sequence, a WRSR sequence can be executed. Note: The WRSR function has no effect on bit 6, bit 5, bit 4, bit 1 and bit 0 of the Status Register. Only bit 7, bit 3 and bit 2 can be changed via the WRSR sequence. These modifiable bits are the Write Protect Enable (WPEN) bit and Block Protect (BP1, BP0) bits. These three bits are non-volatile cells that have the same properties and functions as regular EEPROM cells. Their values are retained while power is removed from the device. The AT25M02 will not respond to commands other than a RDSR after a WRSR sequence until the self-timed internal write cycle has completed. When the write cycle is completed, the WEL bit in the Status Register is reset to Logic 0. 4.4.1 Block Write Protect Function The WRSR instruction allows the user to select one of four possible combinations as to how the memory array will be inhibited from writing through changing the Block Write Protect bits (BP1, BP0). The four levels of array protection are: None of the memory array is protected. Upper quarter (1/4) address range is write protected meaning the highest order 512-Kbits are read-only. Upper half (1/2) address range is write protected meaning the highest order 1-Mbits are read-only. All of the memory array is write protected meaning all addresses are read-only. The Block Write Protection levels and corresponding Status Register control bits are shown in Table 4-3. Table 4-3. Block Write Protect Bits Status Register Bits <3:2> 10 Level BP1 BP0 Writeable Address Range Write Protected / Read-Only Address Range 0 0 0 00000h - 3FFFFh None 1 (1/4) 0 1 00000h - 2FFFFh 30000h - 3FFFFh 2 (1/2) 1 0 00000h - 1FFFFh 20000h - 3FFFFh 3 (All) 1 1 None 00000h - 3FFFFh AT25M02 [DATASHEET] Atmel-8832B-SEEPROM-AT25M02-Datasheet_022016 4.4.2 Write Protect Enable Function The WRSR instruction also allows the user to enable or disable the Write Protect (WP) pin through the use of the Write Protect Enable (WPEN) bit. When the WPEN bit is set to Logic 0, the writability of the EEPROM array is dictated by the values of the Block Write Protect bits. The writability of the Status Register is controlled by the WEL bit. When the WPEN bit is set to Logic 1, the Status Register is read-only. Hardware Write Protection is enabled when both the WP pin is at GND and the WPEN bit has been set to one. When the device is Hardware Write Protected, all writing to the Status Register, including the Block Write Protection bits, the WEL and the WPEN bit, and to the sections in the memory array selected by the Block Write Protection bits are disabled. When Hardware Write Protection is enabled, writes are only allowed to sections of the memory that are not block protected. Hardware Write Protection is disabled when either the WP pin is at VCC or the WPEN bit is zero. When Hardware Write Protection is disabled, writes are only allowed to sections of the memory that are not block protected. Note: When the WPEN bit is hardware write protected, it cannot be changed back to zero, as long as the WP pin is held at GND. Table 4-4. WPEN Operation WPEN WP Pin WEL Protected Blocks Unprotected Blocks Status Register 0 X 0 Protected Protected Protected 0 X 1 Protected Writable Writable 1 GND 0 Protected Protected Protected 1 GND 1 Protected Writable Protected X VCC 0 Protected Protected Protected X VCC 1 Protected Writable Writable Figure 4-5. WRSR Waveform CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK Status Register Data In WRSR Opcode (01h) SI 0 MSB 0 0 0 0 0 0 1 D7 X X X D3 D2 X X MSB High Impedance SO AT25M02 [DATASHEET] Atmel-8832B-SEEPROM-AT25M02-Datasheet_022016 11 5. Read Array Operation Reading the AT25M02 via the SO pin requires the following sequence. After the CS line is pulled low to select a device, the Read opcode 03h is transmitted via the SI line followed by the 24-bit address to be read. Note: Address bits A23 through A18 are don't care bits as they do not fall within the 2-Mbit addressable range. Upon completion of the 24-bit address, any data on the SI line will be ignored. The data (D7 - D0) at the specified address is then shifted out onto the SO line. If only one byte is to be read, the CS line should be driven high after the data comes out. The Read sequence can be continued since the byte address is automatically incremented and data will continue to be shifted out. When the highest address is reached (3FFFFh), the address counter will roll over to the lowest address (00000h) allowing the entire memory to be read in one continuous read cycle regardless of the starting address. Figure 5-1. Read Array CS 0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 35 36 37 38 39 40 41 SCK Opcode SI 0 0 0 0 0 Address Bits A23-A0 0 MSB 1 1 A A A A A A A A A MSB Data Byte 1 SO High-impedance D MSB 12 AT25M02 [DATASHEET] Atmel-8832B-SEEPROM-AT25M02-Datasheet_022016 D D D D D D D D MSB D 6. Write Commands In order to program the AT25M02, two separate instructions must be executed. First, the device must be write enabled via the Write Enable instruction (WREN). Then, one of the two possible Write instructions described in Section 6.1 may be executed. The address of the memory location(s) to be programmed must be outside the protected address field location selected by the block write protection level. During an internal write cycle, all commands will be ignored except the RDSR instruction. Note: 6.1 If the device is not Write Enabled (WREN), the device will ignore the Write instruction and will return to the standby state when CS is brought high. A new CS assertion is required to re-initiate communication. Byte Write A Byte Write instruction requires the following sequence and is depicted in Figure 6-1. After the CS line is pulled low to select the device, the Write opcode (02h) is transmitted via the SI line followed by the 24-bit address and the data (D7 - D0) to be programmed. Programming will start after the CS pin is brought high. The low-to-high transition of the CS pin must occur during the SCK low time (Mode 0) and SCK high time (Mode 3) immediately after clocking in the D0 (LSB) data bit. The AT25M02 is automatically returned to the Write Disable state (Status Register bit WEL = 0) at the completion of a write cycle. Figure 6-1. Byte Write CS 0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 35 36 37 38 39 SCK Opcode SI 0 0 0 0 Address Bits A23-A0 0 0 1 SO 6.2 A 0 MSB A A A A A Data In A A A D7 D6 D5 D4 D3 D2 D1 D0 MSB MSB High-impedance Page Write A Page Write sequence allows up to 256 bytes to be written in the same write cycle, provided that all bytes are in the same row of the memory array (where addresses A17 through A8 are the same). Partial Page Writes of less than 256 bytes are allowed. After each byte of data is received, the eight lowest order address bits are internally incremented by one and the remaining address bits will remain constant. If more bytes of data are transmitted that what will fit to the end of that memory row, the address counter will "roll over" to the beginning of the same row. Due to the Internal Writing Methodology utilized in the device (see Section 6.2.1), creating a roll over event should be avoided as data in the page could become unintentionally altered during the write cycle. The AT25M02 is automatically returned to the Write Disable state (WEL = 0) at the completion of a write cycle. Figure 6-2. Page Write CS 0 1 2 3 4 5 6 7 8 9 29 30 31 32 33 34 35 36 37 38 39 SCK Opcode SI 0 0 0 0 0 MSB SO Address Bits A23-A0 0 1 0 A MSB A A A A Data In Byte 1 A D MSB D D D D D Data In Byte n D D D D D D D D D D MSB High-impedance AT25M02 [DATASHEET] Atmel-8832B-SEEPROM-AT25M02-Datasheet_022016 13 6.2.1 Internal Writing Methodology The AT25M02 incorporates a built in error detection and correction (EDC) logic scheme. The EEPROM array is internally organized as a group of four connected 8-bit bytes plus an additional six ECC (Error Correction Code) bits of EEPROM. These 38 bits are referred to as the internal physical data word. During a read sequence, the EDC logic compares each 4-byte physical data word with its corresponding six ECC bits. If a single bit out of the 4-byte region happens to read incorrectly, the EDC logic will detect the bad bit and replace it with a correct value before the data is serially clocked out. This architecture significantly improves the reliability of the AT25M02 compared to an implementation that does not utilize EDC. It is important to note that data is always physically written to the part at the internal physical data word level, regardless of the number of bytes written. Writing single bytes is still possible with the Byte Write operation, but internally, the other three bytes within the 4-byte location where the single byte was written, along with the six ECC bits will be updated. Due to this architecture, the AT25M02 EEPROM write endurance is rated at the internal physical data word level (4-byte word). The system designer needs to optimize the application writing algorithms to observe these internal word boundaries in order to reach the 1,000,000 cycle endurance rating. 6.2.2 Polling Routine An polling routine can be implemented to optimize time sensitive applications that would not prefer to wait the fixed maximum write cycle time (tWC). This method allows the application to know immediately when the Serial EEPROM write cycle has completed to start a subsequent operation. Once the internally timed write cycle has started, a polling routine can be initiated. This involves repeatedly sending Read Status Register (RDSR) command to determine if the device has completed its self timed internal write cycle. If the RDY/BSY bit (Bit 0) = 1, the write cycle is still in progress. If Bit 0 = 0, the write cycle has ended. If the RDY/BSY bit = 1, repeated RDSR commands can be executed until the RDY/BSY bit = 0, signaling that the device is ready to execute a new instruction. Only the Read Status Register instruction is enabled during the write programming cycle. Figure 6-3. Polling Flow Chart Send Valid Write Protocol Deassert CS to VCC to Initiate a Write Cycle Send RDSR Instruction to the Device Does RDY/BSY = 0? NO 14 AT25M02 [DATASHEET] Atmel-8832B-SEEPROM-AT25M02-Datasheet_022016 YES Continue to Next Operation 7. Electrical Specifications 7.1 Absolute Maximum Ratings* Temperature under Bias. . . . . . . . -55C to +125C Storage Temperature . . . . . . . . . . -65C to +150C Supply Voltage with respect to ground . . . . . . . . . . -0.5V to +6.25V Voltage on any pin with respect to ground . . . . . . . . . . . -1.0V to +7.0V DC Output Current . . . . . . . . . . . . . . . . . . . . 5.0mA 7.2 Functional operation at the "Absolute Maximum Ratings" or any other conditions beyond those indicated in Section 7-1 is not implied or guaranteed. Stresses beyond those listed under "Absolute Maximum Ratings" and/or exposure to the "Absolute Maximum Ratings" for extended periods may affect device reliability and cause permanent damage to the device. The voltage extremes referenced in the "Absolute Maximum Ratings" are intended to accommodate short duration undershoot/overshoot pulses that the device may be subjected to during the course of normal operation and does not imply or guarantee functional device operation at these levels for any extended period of time. DC and AC Operating Range Table 7-1. DC and AC Operating Range AT25M02 Operating Temperature (Case) VCC Power Supply Industrial High Temperature -40C to +85C Low Voltage Grade 1.7V to 5.5V Standard Voltage Grade 2.5V to 5.5V AT25M02 [DATASHEET] Atmel-8832B-SEEPROM-AT25M02-Datasheet_022016 15 7.3 DC Characteristics Table 7-2. DC Characteristics Parameter are applicable over operating range in Section 7-1, unless otherwise noted. Symbol Parameter VCC1 Supply Voltage VCC2 Supply Voltage Test Condition Min Max Units 1.7 5.5 V 2.5 5.5 V (2) Supply Current (Read) ICC1 VCC = 1.8V , SCK = 1MHz, SO = Open 0.3 1.0 mA VCC = 1.8V(2), SCK = 5MHz, SO = Open 0.5 1.0 mA VCC = 5.0V, SCK = 1MHz, SO = Open 1.0 2.0 mA VCC = 5.0V, SCK = 5MHz, SO = Open 2.0 3.0 mA VCC = 1.8V , SO = Open During tWC, CS = VCC 0.3 2.0 mA VCC = 5.0V, SO = Open During tWC, CS = VCC 0.5 3.0 mA VCC = 1.8V(2), CS = VCC 0.08 1.0 A VCC = 2.5V, CS = VCC 0.08 2.0 A VCC = 5.5V, CS = VCC 0.15 3.0 A (2) Supply Current (Write) ICC2 ISB IIL Input Leakage VIN = 0V to VCC -3.0 3.0 A IOL Output Leakage VIN = 0V to VCC, TAC = 0C to 70C -3.0 3.0 A VIL(2) Input Low-voltage -1.0 VCC x 0.3 V VIH(2) Input High-voltage VCC x 0.7 VCC + 0.5 V VOL1 Output Low-voltage 0.4 V VOH1 Output High-voltage VOL2 Output Low-voltage VOH2 Output High-voltage Notes: 16 Standby Current Typical(1) 1. 2. 3.6 VCC 5.5V 1.8V VCC 3.6V IOL = 3.0mA IOH = 1.6mA VCC -0.8 IOL = 0.15mA IOH = 100A 0.2 VCC -0.2 Typical values characterized at TA = +25C unless otherwise noted. This parameter is characterized but is not 100% tested in production. AT25M02 [DATASHEET] Atmel-8832B-SEEPROM-AT25M02-Datasheet_022016 V V V 7.4 AC Characteristics Table 7-3. AC Characteristics Applicable over recommended operating range: TAI= -40C to +85C, CL=1 TTL Gate and 30pF (unless otherwise noted). VCC = 1.7V to 5.5V Symbol Parameter Min Max Units fSCK SCK Clock Frequency 0 5 MHz tRI Input Rise Time -- 80 ns tFI(1) Input Fall Time -- 80 ns tWH SCK High Time 80 -- ns tWL SCK Low Time 80 -- ns tCS CS High Time 200 -- ns tCSS CS Setup Time 200 -- ns tCSH CS Hold Time 200 -- ns tSU Data In Setup Time 20 -- ns tH Data In Hold Time 20 -- ns tHD Hold Setup Time 20 -- ns tCD Hold Hold Time 20 -- ns tV Output Valid 0 80 ns tHO Output Hold Time 0 -- ns tLZ Hold to Output Valid -- 100 ns tHZ Hold to Output High Z -- 100 ns tDIS Output Disable Time -- 100 ns tWC Write Cycle Time -- 10 ms (1) Note: 1. Figure 7-1. This parameter is ensured by characterization only. Synchronous Data Timing tCS VIH CS VIL tCSS tCSH VIH tWH SCK tWL VIL tSU tH VIH SI Valid Data In VIL tV VOH SO VOL High Impedance tHO tDIS High Impedance AT25M02 [DATASHEET] Atmel-8832B-SEEPROM-AT25M02-Datasheet_022016 17 7.5 Pin Capacitance Pin Capacitance(1) Table 7-4. Applicable over recommended operating range from TA = 25C, f = 1.0MHz, VCC = 5.0V (unless otherwise noted). Symbol Test Conditions COUT CIN Note: 7.6 1. Max Units Conditions Output Capacitance (SO) 8 pF VOUT = 0V Input Capacitance (CS, SCK, SI, WP, HOLD) 6 pF VIN = 0V Min Max Units 1,000,000 -- Write Cycles 100 -- Years This parameter is characterized and is not 100% tested. EEPROM Cell Performance Characteristics Table 7-5. EEPROM Cell Performance Characteristics Operation Test Condition Write Endurance(1) Data Retention(3) Notes: 1. 2. 3. 7.7 TA = 25C, VCC(min)< VCC < VCC(max) Byte(2) or Page Write Mode TA = 55C, VCC(min)< VCC < VCC(max) Write endurance performance is determined through characterization and the qualification process. Due to the memory array architecture, the Write Cycle Endurance is specified for writes in groups of four data bytes. The beginning of any 4-byte boundaries can be determined by multiplying any integer (N) by four (i.e 4*N). The end address can be found by adding three to the beginning value (i.e. 4*N+3). See Section 6.2.1 "Internal Writing Methodology" on page 14 for more details on this implementation. The data retention capability is determined through qualification and is checked on each device in production. Power-Up Requirements, Reset, and Default Conditions During a power-up sequence, the VCC supplied to the AT25M02 should monotonically rise from GND to the minimum VCC level as specified in Section 7-1 on page 15, with a slew rate no greater than of 1V/s. 7.7.1 Device Reset To prevent inadvertent write operations or other spurious events from happening during a power-up sequence, the AT25M02 includes a power-on-reset (POR) circuit. Upon power-up, the device will not respond to any commands until the VCC level crosses the internal voltage threshold (VPOR) that brings the device out of reset and into standby mode. The system designer must ensure that no instruction is sent to the device until the VCC supply has reached a stable value greater than the minimum VCC level. Once the VCC has surpassed the minimum level, the SPI Master must wait at least tVCSL before asserting the CS pin. See Table 7-6 for the values associated with these power-up parameters. 18 AT25M02 [DATASHEET] Atmel-8832B-SEEPROM-AT25M02-Datasheet_022016 Table 7-6. Power-up Conditions(1) Symbol Parameter Min tVCSL Minimum VCC to Chip Select Low Time 100 VPOR Power-On Reset Threshold Voltage tPOFF Minimum time at VCC = 0V between power cycles Note: 1. Max Units s 1.5 1 V ms These parameters are characterized but are not 100% tested in production. If an event occurs in the system where the VCC level supplied to the AT25M02 drops below the maximum VPOR level specified, it is recommended that a full power cycle sequence be performed by first driving the VCC pin to GND, waiting at least the minimum tPOFF time, and then performing a new power-up sequence in compliance with the requirements defined in this section. 7.7.2 Software Reset The SPI interface of the AT25M02 can be reset by toggling the CS input. If the CS line is already in the active state, it must a complete transition from the inactive state ( VIH)to the active state ( VIL), and then back to the inactive state ( VIH) without sending clocks on the SCK line. Upon completion of this sequence, the device will be ready to receive a new opcode on the SI line. 7.7.3 Device Default State at Power-up The AT25M02 default state upon power-up consists of: 7.7.4 Standby Power mode. Write Enable Latch (WEL) bit in the Status Register = 0. Ready/Busy bit in the Status Register = 0, indicating the device is ready to accept a new command. Device is not selected. Not in Hold condition. WPEN, BP1 and BP0 bits in the Status Register are unchanged from their previous state due to the fact that they are non-volatile values. Device Default Condition from Atmel The AT25M02 is shipped from Atmel to the customer with the EEPROM array set to an all FFh data pattern (Logic 1 state). The Write Protection Enable bit in the Status Register is set to Logic 0 (the ability of the EEPROM array to write is dictated by the values of the Block Write Protect bits while the SR ability to write is controlled by the WEL bit). The Block Write Protection bits in the Status Register are set to Logic 0 (no write protection selected). AT25M02 [DATASHEET] Atmel-8832B-SEEPROM-AT25M02-Datasheet_022016 19 8. Ordering Code Detail AT2 5 M 0 2 - S S H M x x - T Atmel Designator Shipping Carrier Option T = Tape and Reel B = Bulk (Tubes) Product Family Product Variation / Customer Specific Option 25 = SPI Serial EEPROM xx = Applies to selecte packages only. See ordering table for details. Device Density M = Megabit Family 02 = 2 Megabit Operating Voltage M = 1.7V to 5.5V D = 2.5V to 5.5V Package Device Grade or Wafer/Die Thickness U = Green, SnAgCu WLCSP Ball Industrial Temperature Range (-40C to +85C) H = Green, NiPdAu Lead Finish Industrial Temperature Range (-40C to +85C) 11 = 11mil wafer thickness Package Option SS = JEDEC SOIC U1 = 8-ball, 4x4 Grid Array, WLCSP WWU = Wafer Unsawn 9. Ordering Information Additional package types that are not listed below may be available for order. Please contact Atmel for availability details. Delivery Information Atmel Ordering Code Lead Finish Package AT25M02-SSHM-T 1.7V to 5.5V AT25M02-SSHM-B NiPdAu AT25M02-SSHD-T (Lead-free/Halogen-free) 8S1 2.5V to 5.5V AT25M02-SSHD-B AT25M02-U1UM0B-T(1) SnAgCu (Lead-free/Halogen-free) AT25M02-WWU11M(2) Notes: Voltage n/a 8U-10 1.7V to 5.5V Wafer Sale Quantity Tape and Reel 4,000 per Reel Bulk (Tubes) 100 per Tube Tape and Reel 4,000 per Reel Bulk (Tubes) 100 per Tube Tape and Reel 5,000 per Reel Operation Range Industrial Temperature (-40C to 85C) Note 2 1. WLCSP Package: This device includes a backside coating to increase product robustness. CAUTION: Exposure to ultraviolet (UV) light can degrade the data stored in EEPROM cells. Therefore, customers who use a WLCSP package must ensure that exposure to ultraviolet light does not occur. 2. For wafer sales, please contact Atmel Sales. Package Type 8S1 8-lead, 0.150" wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8U-10 4-ball, 4x4 Grid Array, Wafer Level Chip Scale Package (WLCSP) 20 Form AT25M02 [DATASHEET] Atmel-8832B-SEEPROM-AT25M02-Datasheet_022016 10. Part Marking Scheme AT25M02: Package Marking Information 8-ball WLCSP 8-lead SOIC ATMLHYWW ## % @ AAAAAAAA ATMLUYWW ## % @ AAAAAAAA Note 1: designates pin 1 Note 2: Package drawings are not to scale Catalog Number Truncation AT25M02 Date Codes Y = Year 2: 2012 3: 2013 4: 2014 5: 2015 Truncation Code ##: 5H Voltages 6: 2016 7: 2017 8: 2018 9: 2019 M = Month A: January B: February ... L: December WW = Work Week of Assembly 02: Week 2 04: Week 4 ... 52: Week 52 Country of Assembly Lot Number @ = Country of Assembly AAA...A = Atmel Wafer Lot Number Trace Code % = Minimum Voltage M: 1.7V min D: 2.5V min Grade/Lead Finish Material U: Industrial/SnAgCu H: Industrial/NiPdAu Atmel Truncation XX = Trace Code (Atmel Lot Numbers Correspond to Code) Example: AA, AB.... YZ, ZZ AT: Atmel ATM: Atmel ATML: Atmel 5/6/15 TITLE Package Mark Contact: DL-CSO-Assy_eng@atmel.com 25M02SM, AT25M02 Standard Package Marking Information DRAWING NO. REV. 25M02SM C AT25M02 [DATASHEET] Atmel-8832B-SEEPROM-AT25M02-Datasheet_022016 21 11. Packaging Information 11.1 8S1 -- 8-lead JEDEC SOIC C 1 E E1 L N O TOP VIEW END VIEW e b COMMON DIMENSIONS (Unit of Measure = mm) A A1 D SIDE VIEW Notes: This drawing is for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. MIN NOM MAX - - 1.75 A1 0.10 - 0.25 b 0.31 - 0.51 C 0.17 - 0.25 SYMBOL A D 4.90 BSC E 6.00 BSC E1 3.90 BSC e 1.27 BSC L 0.40 - 1.27 O 0 - 8 NOTE 3/6/2015 Package Drawing Contact: packagedrawings@atmel.com 22 TITLE 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) AT25M02 [DATASHEET] Atmel-8832B-SEEPROM-AT25M02-Datasheet_022016 GPC SWB DRAWING NO. REV. 8S1 H 11.2 8U-10 -- 8-ball WLCSP TOP VIEW BOTTOM SIDE k 12 A1 CORNER 0.015 (4X) A 34 43 A A B B 21 e1 E C C D D D e d1 d2 B SIDE VIEW A A1 CORNER db v A2 d0.015 m C d0.05 m C A B SEATING PLANE C k COMMON DIMENSIONS (Unit of Measure = mm) A1 0.20 C PIN ASSIGNMENT MATRIX SYMBOL MIN TYP MAX A 0.313 0.334 0.355 A1 -- 0.094 -- 1 2 3 4 A2 -- 0.240 -- A n/a VCC CS n/a D B n/a HOLD n/a SO d1 1.00 BSC d2 1.40 BSC C SCK n/a n/a WP D n/a SI GND n/a E 3 Contact Atmel for details Contact Atmel for details e 0.50 BSC e1 2.10 BSC b NOTE 0.170 0.185 0.200 Note: 1. Dimensions are NOT to scale. 2. Solder ball composition is 95.5Sn-4.0Ag-0.5Cu. 3. Product offered with Back Side Coating 9/22/15 Package Drawing Contact: packagedrawings@atmel.com TITLE 8U-11, 8-ball 4x4 Array, Custom Pitch Wafer Level Chip Scale Package (WLCSP) GPC DRAWING NO. REV. GAC 8U-10 E AT25M02 [DATASHEET] Atmel-8832B-SEEPROM-AT25M02-Datasheet_022016 23 12. 24 Revision History Doc. Rev. Date Comments 8832B 02/2016 Removed preliminary status and updated 8U-10 package drawing. 8832A 05/2015 Initial document release. AT25M02 [DATASHEET] Atmel-8832B-SEEPROM-AT25M02-Datasheet_022016 XXXXXX Atmel Corporation 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 | www.atmel.com (c) 2016 Atmel Corporation. / Rev.: Atmel-8832B-SEEPROM-AT25M02-Datasheet_022016. Atmel(R), Atmel logo and combinations thereof, Enabling Unlimited Possibilities(R), and others are registered trademarks or trademarks of Atmel Corporation in U.S. and other countries. Other terms and product names may be trademarks of others. DISCLAIMER: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. 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