Dual, 500kSPS, 12-Bit, 2 + 2 Channel,
Simultaneous Sampling
ANALOG-TO-DIGITAL CONVERTER
FEATURES
●4 INPUT CHANNELS
●FULLY DIFFERENTIAL INPUTS
●2µs TOTAL THROUGHPUT PER CHANNEL
●NO MISSING CODES
●1MHz EFFECTIVE SAMPLING RATE
●LOW POWER: 40mW
●SSI SERIAL INTERFACE
●OPERATING TEMPERATURE RANGE:
–40°C to +125°C
APPLICATIONS
● MOTOR CONTROL
● MULTI-AXIS POSITIONING SYSTEMS
● 3-PHASE POWER CONTROL
DESCRIPTION
The ADS7861 is a dual, 12-bit, 500kSPS, Analog-to-Digital
(A/D) converter with four fully differential input channels
grouped into two pairs for high speed, simultaneous signal
acquisition. Inputs to the sample-and-hold amplifiers are fully
differential and are maintained differential to the input of the
A/D converter. This provides excellent common-mode rejec-
tion of 80dB at 50kHz which is important in high noise
environments.
The ADS7861 offers a high-speed, dual serial interface and
control inputs to minimize software overhead. The output data
for each channel is available as a 12-bit word. The ADS7861
is offered in both an SSOP-24 and a QFN-32 package and is
fully specified over the –40°C to +125°C operating range.
SAR
Serial
Interface
COMP
CLOCK
A0
M1
M0
CONVST
CS
RD
BUSY
SERIAL DATA B
SERIAL DATA A
CDAC
Internal
2.5V
Reference
SHA
CH A0–
CH A0+
REF
IN
CH A1–
CH A1+
SAR
COMP
CDAC
SHA
CH B0–
CH B0+
CH B1–
CH B1+
REF
OUT
ADS7861
SBAS110D – DECEMBER 1998 – REVISED AUGUST 2007
www.ti.com
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1998-2007, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
ADS7861
ADS7861
All trademarks are the property of their respective owners.
ADS7861
2SBAS110D
ABSOLUTE MAXIMUM RATINGS(1)
Analog Inputs to AGND, Any Channel Input ........ –0.3V to (+VD + 0.3V)
REFIN ..................................................................... –0.3V to (+VD + 0.3V)
Digital Inputs to DGND.......................................... –0.3V to (+VD + 0.3V)
Ground Voltage Differences: AGND, DGND ................................... ±0.3V
+VD to AGND......................... –0.3V to +6V
Power Dissipation .......................................................................... 325mW
Maximum Junction Temperature................................................... +150°C
Operating Temperature Range ......................................–40°C to +125°C
Storage Temperature Range .........................................–65°C to +150°C
NOTE: (1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods may degrade
device reliability.
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instruments
recommends that all integrated circuits be handled with appropriate
precautions. Failure to observe proper handling and installation proce-
dures can cause damage.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
BASIC CIRCUIT CONFIGURATION
M0 M1 A0 TWO-CHANNEL/FOUR-CHANNEL OPERATION DATA ON SERIAL OUTPUTS CHANNELS CONVERTED
0 0 0 Two Channel A and B A0, B0
0 0 1 Two Channel A and B A1, B1
0 1 0 Two Channel A Only A0, B0
0 1 1 Two Channel A Only A1, B1
1 0 X Four Channel A and B Sequential
1 1 X Four Channel A Only Sequential
X = Don’t Care.
TRUTH TABLE
DGND
CH B1+
CH B1–
CH B0+
CH B0–
CH A1+
CH A1–
CH A0+
CH A0–
REF
IN
REF
OUT
AGND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
+V
D
SERIAL DATA A
SERIAL DATA B
BUSY
CLOCK
CS
RD
CONVST
A0
M0
M1
+V
A
BUSY Output
Clock Input
Chip Select
Read Input
Conversion Start
A0 Address Select
M0 Address Select
M1 Address Select
ADS7861
10µF
+0.1µF+5V Analog Supply
+
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see
the TI website at www.ti.com.
PACKAGE/ORDERING INFORMATION
ADS7861 3
SBAS110D
ELECTRICAL CHARACTERISTICS
Over recommended operating free-air temperature range at TA = –40°C to +125 °C, +VA + VD = +5V, VREF = internal +2.5V, fCLK = 8MHz, and fSAMPLE = 500kSPS,
unless otherwise noted.
ADS7861I, E ADS7861IB, EB
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
RESOLUTION 12 ✻Bits
ANALOG INPUT
Input Voltage Range-Bipolar VCENTER = Internal VREF at 2.5V –VREF +VREF ✻✻V
Input Capacitance 15 ✻pF
Input Leakage Current ±1✻µA
SYSTEM PERFORMANCE
No Missing Codes 12 ✻Bits
Integral Linearity ±0.75 ±2±0.5 ±1 LSB
Integral Linearity Match 0.5 ±1✻✻LSB
Differential Linearity ±1±0.5 ±1 LSB
Bipolar Offset Error TA = –40°C to +85°C±0.5 ±3✻✻LSB
TA = –40°C to +125°C±0.5 ±3.5 ✻✻LSB
Bipolar Offset Error Match 3 2 LSB
Positive Gain Error Referenced to REFIN ±0.15 ±0.75 ±0.10 ±0.50 % of FSR
Positive Gain Error Match 2 1 LSB
Negative Gain Error Referenced to REFIN ±0.15 ±0.75 ±0.10 ±0.50 % of FSR
Negative Gain Error Match 2 1 LSB
Common-Mode Rejection Ratio At DC 80 ✻dB
VIN = ±1.25VPP at 50kHz 80 ✻dB
Noise 120 ✻µVrms
Power Supply Rejection Ratio 0.5 2 ✻✻LSB
SAMPLING DYNAMICS
Conversion Time per A/D 1.625 ✻µs
Acquisition Time 0.375 ✻µs
Throughput Rate 500 ✻kSPS
Aperture Delay 3.5 ✻ns
Aperture Delay Matching 100 ✻ps
Aperture Jitter 50 ✻ps
Small-Signal Bandwidth 40 ✻MHz
DYNAMIC CHARACTERISTICS (VIN = ±2.5VPP at 100kHz)
Total Harmonic Distortion TA = –40°C to +85°C–72 –76 dB
TA = –40°C to +125°C–71 –75 dB
SINAD 70 ✻dB
Spurious Free Dynamic Range TA = –40°C to +85°C72 76 dB
TA = –40°C to +125°C71 75 dB
Channel-to-Channel Isolation –80 ✻dB
VOLTAGE REFERENCE
Internal 2.475 2.5 2.525 ✻✻✻V
Internal Drift ±25 ✻ppm/°C
Internal Noise 50 ✻µVPP
Internal Source Current 2✻mA
Internal Load Rejection 0.005 ✻mV/µA
Internal PSRR 80 ✻dB
External Voltage Range 1.2 2.5 2.6 ✻✻✻V
Input Current 0.05 1 ✻✻µA
Input Capacitance 5✻pF
DIGITAL INPUT/OUTPUT
Logic Family CMOS ✻
Logic Levels: VIH IIH = +5µA 3.0
+VDD + 0.3
✻✻V
VIL IIL = +5µA–0.3 1 ✻✻V
VOH IOH = –0.5mA 3.5 ✻V
VOL IOL = –0.5mA 0.4 ✻V
External Clock, Optional 0.2 8 ✻✻MHz
Data Format Binary Two's Complement ✻
POWER SUPPLY REQUIREMENTS
Power Supply Voltage, +V 4.75 5 5.25 ✻✻✻V
Quiescent Current, +VATA = –40°C to +85°C58✻✻mA
TA = –40°C to +125°C 5 8.5 ✻✻mA
Power Dissipation TA = –40°C to +85°C2540✻✻mW
TA = –40°C to +125°C 25 42.5 ✻✻mW
✻ Specifications same as ADS7861I, ADS7861E.
ADS7861
4SBAS110D
DGND
CH B1+
CH B1–
CH B0+
CH B0–
CH A1+
CH A1–
CH A0+
CH A0–
REF
IN
REF
OUT
AGND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
+V
D
SERIAL DATA A
SERIAL DATA B
BUSY
CLOCK
CS
RD
CONVST
A0
M0
M1
+V
A
ADS7861
PIN CONFIGURATIONS
Top View SSOP Top View QFN
SSOP QFN
PIN PIN NAME DESCRIPTION
1 28 DGND Digital Ground. Connect directly to analog ground (pin 12).
2 1 CH B1+ Noninverting Input Channel B1
3 2 CH B1–Inverting Input Channel B1
4 3 CH B0+ Noninverting Input Channel B0
5 4 CH B0–Inverting Input Channel B0
6 5 CH A1+ Noninverting Input Channel A1
7 6 CH A1–Inverting Input Channel A1
8 7 CH A0+ Noninverting Input Channel A0
9 8 CH A0–Inverting Input Channel A0
10 9 REFIN Reference Input
11 10 REFOUT 2.5V Reference Output
12 12 AGND Analog Ground. Connect directly to digital ground (pin 1).
13 13 +VAAnalog Power Supply, +5VDC. Connect directly to digital power supply (pin 24). Decouple to analog ground with a 0.1µF ceramic capacitor
and a 10µF tantalum capacitor.
14 16 M1 Selects between the Serial Outputs. When M1 is LOW, both Serial Output A and Serial Output B are selected for data transfer. When M1
is HIGH, Serial output A is configured for both Channel A data and Channel B data; Serial Output B goes into tri-state (i.e., high impedance).
15 17 M0 Selects between two-channel and four-channel operation. When M0 is LOW, two-channel operation is selected and operates in
conjunction with A0. When A0 is HIGH, Channel A1 and Channel B1 are being converted. When A0 is LOW, Channel A0 and Channel
B0 are being converted. When M0 is HIGH, four-channel operation is selected. In this mode, all four channels are converted in sequence
starting with Channels A0 and B0, followed by Channels A1 and B1.
16 18 A0 A0 operates in conjunction with M0. With M0 LOW and A0 HIGH, Channel A1 and Channel B1 are converted. With M0 LOW and A0 LOW,
Channel A0 and Channel B0 are converted.
17 19 CONVST Convert Start. When CONVST switches from LOW to HIGH, the device switches from the sample to hold mode, independent of the status
of the external clock.
18 20 RD Synchronization Pulse for the Serial Output.
19 21 CS Chip Select. When LOW, the Serial Output A and Serial Output B outputs are active; when HIGH, the serial outputs are tri-stated.
20 22 CLOCK An external CMOS-compatible clock can be applied to the CLOCK input to synchronize the conversion process to an external source.
The CLOCK pin controls the sampling rate by the equation: CLOCK = 16 • fSAMPLE.
21 23 BUSY BUSY goes HIGH during a conversion and returns LOW after the third LSB has been transmitted on either the Serial A or Serial B output
pin.
22 24 SERIAL The Serial Output data word is comprised of channel information and 12 bits of data. In operation, data is valid on the falling edge of
DCLOCK for 16 edges after the rising edge of RD.
23 25 SERIAL The Serial Output data word is comprised of channel information and 12 bits of data. In operation, data is valid on the falling edge of
DCLOCK for 16 edges after the rising edge of RD. When M1 is HIGH, both Channel A data and Channel B data are available.
24 27 +VDDigital Power Supply, +5VDC. Connect directly to pin 13. Must be ≤ +VA.
PIN DESCRIPTIONS
DATA A
DATA B
CH B1+
CH B1−
CH B0+
CH B0−
CH A1+
CH A1−
CH A0+
CH A0−
SERIAL DATA B
BUSY
CLOCK
CS
RD
CONVST
A0
M0
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
ADS7861
(1)
NC
(2)
NC
(2)
NC
(2)
NC
(2)
DGND
+V
D
NC
(2)
SERIAL DATA A
32
31
30
29
28
27
26
25
REF
IN
REF
OUT
NC
(2)
AGND
+V
A
NC
(2)
NC
(2)
M1
9
10
11
12
13
14
15
16
NOTE: (1) The thermal pad is internally connected to the substrate.
This pad can be connected to the analog ground or left floating.
Keep the thermal pad separate from the digital ground, if possible.
(2) NC = Not Connected.
ADS7861 5
SBAS110D
TYPICAL CHARACTERISTICS
At TA = +25°C, +VA + VD = +5V, and VREF = internal +2.5V, fCLK = 8MHz, fSAMPLE = 500kSPS, unless otherwise noted.
FREQUENCY SPECTRUM
(4096 Point FFT; f
IN
= 99.9kHz, –0.5dB)
Frequency (kHz)
0
–20
–40
–60
–80
–100
–120
Amplitude (dB)
0 62.5 125 250187.5
FREQUENCY SPECTRUM
(4096 Point FFT; f
IN
= 199.9kHz, –0.5dB)
Frequency (kHz)
0
–20
–40
–60
–80
–100
–120
Amplitude (dB)
0 62.5 125 250187.5
CHANGE IN POSITIVE GAIN MATCH
vs TEMPERATURE
(Maximum Deviation for All Four Channels)
Temperature (°C)
0.6
0.5
0.4
0.3
0.2
0.1
0
Change in Positive Gain Match (LSB)
–40 25 85 150
CHANGE IN SIGNAL-TO-NOISE RATIO
AND SIGNAL-TO-(NOISE+DISTORTION)
vs TEMPERATURE
Temperature (°C)
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
–0.1
Delta from +25°C (dB)
–40 25 85
SNR SINAD
CHANGE IN SPURIOUS FREE DYNAMIC RANGE
AND TOTAL HARMONIC DISTORTION
vs TEMPERATURE
Temperature (°C)
7
6
5
4
3
2
1
0
–1
+1
0
–0.5
–1
–1.5
–2
–2.5
–3
–3.5
SFDR Delta from +25°C (dB)
THD Delta from +25°C (dB)
–40 25 85
THD
SFDR
SIGNAL-TO-NOISE RATIO and
SIGNAL-TO-(NOISE+DISTORTION)
vs INPUT FREQUENCY
10k 100k1k 1M
Input Frequency (Hz)
SNR and SINAD (dB)
74
72
70
68
66
64
76
SINAD
SNR
ADS7861
6SBAS110D
INTEGRAL LINEARITY ERROR vs CODE
Hex BTC Code
Typical of All Four Channels
1
0.75
0.5
0.25
0
–0.25
–0.5
–0.75
–1
ILE (LSB)
800 000 7FF
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, +VA + VD = +5V, and VREF = internal +2.5V, fCLK = 8MHz, fSAMPLE = 500kSPS, unless otherwise noted.
CHANGE IN NEGATIVE GAIN MATCH
vs TEMPERATURE
(Maximum Deviation for All Four Channels)
Temperature (°C)
0.2
0.18
0.16
0.14
0.12
0.1
0.08
0.06
0.04
0.02
0
Change in Negative Gain Match (LSB)
–40 25 85 150
CHANGE IN REFERENCE VOLTAGE
vs TEMPERATURE
Temperature (°C)
2.51
2.505
2.5
2.495
2.49
2.485
Change in Reference (V)
–40 25 85 150
CHANGE IN BIPOLAR ZERO
vs TEMPERATURE
Temperature (°C)
0.75
0.5
0.25
0
–0.25
–0.5
–0.75
Change in Bipolar Zero (LSB)
–40 25
A Channel
B Channel
85 150
CHANGE IN CMRR vs TEMPERATURE
Temperature (°C)
86
85
84
83
82
81
80
79
78
Change in CMRR (dB)
–40 –5255585
CHANGE IN BPZ MATCH vs TEMPERATURE
Temperature (°C)
1
0.75
0.5
0.25
0
Change in Bipolar Match (LSB)
–40 25 85 150
ADS7861 7
SBAS110D
DIFFERENTIAL LINEARITY ERROR vs CODE
Hex BTC Code
Typical of All Four Channels
1
0.75
0.5
0.25
0
–0.25
–0.5
–0.75
–1
DLE (LSB)
800 000 7FF
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, +VA + VD = +5V, and VREF = internal +2.5V, fCLK = 8MHz, fSAMPLE = 500kSPS, unless otherwise noted.
DIFFERENTIAL LINEARITY ERROR
vs TEMPERATURE
Temperature (°C)
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
DLE Error (LSB)
–40 25
Positive DLE
Negative DLE
85 150
INTEGRAL LINEARITY ERROR MATCH
vs CODE CHANNEL A0/CHANNEL A1
(Same Converter, Different Channels)
Hex BTC Code
0.25
0.2
0.15
0.1
0.05
0
–0.05
–0.1
–0.15
–0.2
–0.25
ILE (LSB)
800 000 7FF
INTEGRAL LINEARITY ERROR MATCH
vs CODE CHANNEL A0/CHANNEL B1
(Different Converter, Different Channels)
Hex BTC Code
0.25
0.2
0.15
0.1
0.05
0
–0.05
–0.1
–0.15
–0.2
–0.25
ILE (LSB)
800 000 7FF
INTEGRAL LINEARITY ERROR vs TEMPERATURE
Positive ILE
Negative ILE
Temperature (°C)
0.8
0.7
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
Change in ILE (LSB)
–40 25 85 150
INTEGRAL LINEARITY ERROR MATCH
vs TEMPERATURE
Channel A0/Channel B0
(Different Converter, Different Channels)
Temperature (°C)
0.47
0.46
0.45
0.44
0.43
0.42
0.41
0.40
0.39
0.38
Change in INL Match (LSB)
–40 25 85 150
ADS7861
8SBAS110D
REFERENCE
Under normal operation, the REFOUT pin should be directly
connected to the REFIN pin to provide an internal +2.5V
reference to the ADS7861. The ADS7861 can operate,
however, with an external reference in the range of 1.2V to
2.6V for a corresponding full-scale range of 2.4V to 5.2V.
The internal reference of the ADS7861 is double-buffered.
If the internal reference is used to drive an external load, a
buffer is provided between the reference and the load ap-
plied to pin 2 (the internal reference can typically source
2mA of current load—capacitance should not exceed 100pF).
If an external reference is used, the second buffer provides
isolation between the external reference and the CDAC.
This buffer is also used to recharge all of the capacitors of
both CDACs during conversion.
ANALOG INPUT
The analog input is bipolar and fully differential. There are
two general methods of driving the analog input of the
ADS7861: single-ended or differential (see Figures 1 and 2).
When the input is single-ended, the –IN input is held at the
common-mode voltage. The +IN input swings around the
same common voltage and the peak-to-peak amplitude is the
(common-mode +VREF) and the (common-mode –VREF).
The value of VREF determines the range over which the
common-mode voltage may vary (see Figure 3).
When the input is differential, the amplitude of the input is the
difference between the +IN and –IN input, or (+IN) – (–IN).
The peak-to-peak amplitude of each input is ±1/2VREF around
this common voltage. However, since the inputs are 180° out
of phase, the peak-to-peak amplitude of the differential volt-
age is +VREF to –VREF. The value of VREF also determines the
range of the voltage that may be common to both inputs (see
Figure 4).
INTRODUCTION
The ADS7861 is a high-speed, low power, dual, 12-bit A/D
converter that operates from a single +5V supply. The input
channels are fully differential with a typical common-mode
rejection of 80dB. The part contains dual, 2µs successive
approximation ADCs, two differential sample-and-hold am-
plifiers, an internal +2.5V reference with REFIN and REFOUT
pins and a high-speed parallel interface. The ADS7861
requires an external clock. In order to achieve the maximum
throughput rate of 500kSPS, the master clock must be set at
8MHz. A minimum of 16 clock cycles are required for each
12-bit conversion.
There are four analog inputs that are grouped into two chan-
nels (A and B). Channel selection is controlled by the M0, M1
and A0 pins. Each channel has two inputs (A0 and A1 and B0
and B1) that can be sampled and converted simultaneously,
thus preserving the relative phase information of the signals on
both analog inputs. The part accepts an analog input voltage in
the range of –VREF to +VREF, centered around the internal
+2.5V reference. The part will also accept bipolar input ranges
when a level shift circuit is used at the front end (see Fi gure 7).
All conversions are initiated on the ADS7861 by bringing
the CONVST pin HIGH for a minimum of 15ns. CONVST
HIGH places both sample-and-hold amplifiers in the hold
state simultaneously and the conversion process is started on
both channels. The RD pin can be connected to CONVST to
simplify operation. Depending on the status of the M0, M1
and A0 pins, the ADS7861 will (a) operate in either two-
channel or four-channel mode and (b) output data on both
the Serial A and Serial B output or both channels can be
transmitted on the A output only.
NOTE: See the Timing and Control section of this data sheet
for more information.
SAMPLE-AND-HOLD SECTION
The sample-and-hold amplifiers on the ADS7861 allow the
ADCs to accurately convert an input sine wave of full-scale
amplitude to 12-bit accuracy. The input bandwidth of the
sample-and-hold is greater than the Nyquist rate (Nyquist
equals one-half of the sampling rate) of the ADC even when
the ADC is operated at its maximum throughput rate of
500kSPS. The typical small-signal bandwidth of the sample-
and-hold amplifiers is 40MHz.
Typical aperture delay time or the time it takes for the
ADS7861 to switch from the sample to the hold mode
following the CONVST pulse is 3.5ns. The average delta of
repeated aperture delay values is typically 50ps (also known
as aperture jitter). These specifications reflect the ability of
the ADS7861 to capture AC input signals accurately at the
exact same moment in time.
ADS7861
ADS7861
Single-Ended Input
Common
Voltage
–VREF to +VREF
peak-to-peak
Differential Input
Common
Voltage
VREF
peak-to-peak
VREF
peak-to-peak
FIGURE 1. Methods of Driving the ADS7861 Single-Ended
or Differential.
ADS7861 9
SBAS110D
FIGURE 3. Single-Ended Input: Common-Mode Voltage
Range vs VREF.
1.0 1.5
1.2
2.0 2.5
2.6
3.0
V
REF
(V)
Common Voltage Range (V)
–1
0
1
2
3
4
5
2.7
2.3
4.1
0.9
V
CC
= 5V
Single-Ended Input
Differential Input
1.0 1.5
1.2
2.0 2.5
2.6
3.0
V
REF
(V)
Common Voltage Range (V)
–1
0
1
2
3
4
54.7
0.3
V
CC
= 5V
4.0
1.0
FIGURE 2. Using the ADS7861 in the Single-Ended and Differential Input Modes.
FIGURE 4. Differential Input: Common-Mode Voltage
Range vs V
REF
.
In each case, care should be taken to ensure that the output
impedance of the sources driving the +IN and –IN inputs are
matched. Otherwise, this may result in offset error, gain
error and linearity error which will change with both tem-
perature and input voltage.
The input current on the analog inputs depend on a number
of factors: sample rate, input voltage, and source impedance.
Essentially, the current into the ADS7861 charges the inter-
nal capacitor array during the sampling period. After this
capacitance has been fully charged, there is no further input
current. The source of the analog input voltage must be able
to charge the input capacitance (15pF) to a 12-bit settling
level within 2 clock cycles. When the converter goes into the
hold mode, the input impedance is greater than 1GΩ.
Care must be taken regarding the absolute analog input
voltage. The +IN input should always remain within the
range of GND – 300mV to VDD + 0.3V.
CM
+V
REF
+V
REF
–V
REF
Single-Ended Inputs t
+IN
CM
Voltage
CM
–V
REF
CM
+1/2V
REF
Differential Inputs
NOTES: Common-Mode Voltage (Differential Mode) = Common-Mode Voltage (Single-Ended Mode) = IN–.
(IN+) + (IN–)
2
The maximum differential voltage between +IN and –IN of the ADS7861 is V
REF
. See Figures 3 and 4 for a further
explanation of the common voltage range for single-ended and differential inputs.
t
+IN
–IN
CM
Voltage
CM
–1/2V
REF
–IN = CM Voltage
+V
REF
–V
REF
ADS7861
10 SBAS110D
Code (decimal)
8000
7000
6000
5000
4000
3000
2000
1000
0
Number of Conversions
2044 2045 2046 2047 2048
FIGURE 5. Histogram of 8,000 Conversions of a DC Input.
FIGURE 6. Test Circuits for Timing Specifications. FIGURE 7. Level Shift Circuit for Bipolar Input Ranges.
TRANSITION NOISE
Figure 5 shows a histogram plot for the ADS7861 following
8,000 conversions of a DC input. The DC input was set at
output code 2046. All but one of the conversions had an
output code result of 2046 (one of the conversions resulted
in an output of 2047). The histogram reveals the excellent
noise performance of the ADS7861.
BIPOLAR INPUTS
The differential inputs of the ADS7861 were designed to
accept bipolar inputs (–VREF and +VREF) around the internal
reference voltage (2.5V), which corresponds to a 0V to 5V
input range with a 2.5V reference. By using a simple op amp
circuit featuring a single amplifier and four external resis-
tors, the ADS7861 can be configured to except bipolar
inputs. The conventional ±2.5V, ±5V, and ±10V input
ranges can be interfaced to the ADS7861 using the resistor
values shown in Figure 7.
TIMING AND CONTROL
The operation of the ADS7861 can be configured in four
different modes by using the address pins M0, M1 and A0.
The M0 pin selects between two- and four-channel operation
(in two-channel operation, the A0 pin selects between Chan-
nels 0 and 1; in four-channel operation the A0 pin is ignored
and the channels are switched automatically after each
conversion). The M1 pin selects between having serial data
transmitted simultaneously on both the Serial A data output
and the Serial B data output or having both channels output
data through the Serial A port. The A0 pin selects either
Channel 0 or Channel 1 (see Pin Descriptions and Serial
Output Truth Table for more information).
The next four sections will explain the four different modes
of operation.
Mode I (M0 = 0, M1 = 0)
With the M0 and M1 pins both set to ‘0’, the ADS7861 will
operate in two-channel operation (the A0 pin must be used
to switch between Channels A and B). A conversion is
initiated by bringing CONVST HIGH for a minimum of
15ns. It is very important that CONVST be brought HIGH
a minimum of 10ns prior to a rising edge of the external
clock or 5ns after the rising edge. If CONVST is brought
R
1
R
2
+IN
–IN
REF
OUT
2.5V
4kΩ
20kΩ
Bipolar Input
BIPOLAR INPUT R
1
R
2
±10V 1kΩ5kΩ
±5V 2kΩ10kΩ
±2.5V 4kΩ20kΩ
OPA132
ADS7861
DATA
1.4V
Test Point
3kΩ
100pF
CLOAD
tR
DATA
Voltage Waveforms for DATA Rise and Fall Times tR, and tF.
VOH
VOL
tF
DESCRIPTION ANALOG INPUT
Full-Scale Input Span –VREF to +VREF(1)
Least Significant (–VREF to +VREF)/4096(2)
Bit (LSB)
+Full Scale 4.99878V 0111 1111 1111 7FF
Midscale 2.5V 0000 0000 0000 000
Midscale – 1 LSB 2.49878V 1111 1111 1111 FFF
–Full Scale 0V 1000 0000 0000 800
NOTES: (1) –VREF to +VREF around VREF. With a 2.5V reference, this corre-
sponds to a 0V to 5V input span. (2) 1.22mV with a 2.5V reference.
TABLE I. Ideal Input Voltages and Output Codes.
DIGITAL OUTPUT
BINARY TWO’S COMPLEMENT
BINARY CODE HEX CODE
ADS7861 11
SBAS110D
FIGURE 8. Conversion Mode.
HIGH within this window, it is then uncertain as to when the
ADS7861 will initiate conversion (see Figure 8 for a more
detailed description). Sixteen clock cycles are required to
perform a single conversion. Immediately following
CONVST switching to HIGH, the ADS7861 will switch
from the sample mode to the hold mode asynchronous to the
external clock. The BUSY output pin will then go HIGH and
remain HIGH for the duration of the conversion cycle. On
the falling edge of the first cycle of the external clock, the
ADS7861 will latch in the address for the next conversion
cycle depending on the status of the A0 pin (HIGH =
Channel 1, LOW = Channel 0). The address must be selected
15ns prior to the falling edge of cycle one of the external clock
and must remain ‘held’ for 15ns following the clock edge. For
maximum throughput time, the CONVST and RD pins should
be tied together. CS must be brought LOW to enable the two
serial outputs. Data will be valid on the falling edge of all 16
clock cycles per conversion. The first bit of data will be a
status flag for either Channel 0 or 1, the second bit will be a
second status flag for either Channel A or B. The subsequent
data will be MSB-first through the LSB, followed by two
zeros (see Table II and Figures 9 and 10).
SYMBOL DESCRIPTION MIN TYP MAX UNITS COMMENTS
tCONV Conversion Time 1.75 µs When TCKP = 125ns
tACQ Acquisition Time 0.25 µs When TCKP = 125ns
tCKP Clock Period 125 5000 ns
tCKL Clock LOW 40 ns
tCKH Clock HIGH 40 ns
tFDOUT Fall Time 25 ns
tRDOUT Rise Time 30 ns
t1CONVST HIGH 15 ns
t2Address Setup Time 15 ns Address latched on falling edge of CLK cycle ‘2’
t3Address Hold Time 15
t4RD Setup Time 15 ns Before falling edge of CLOCK
t5RD to CS Hold Time 15 ns After falling edge of CLOCK
t6CONVST LOW 20 ns
t7RD LOW 20 ns
t8CS to Data Valid 25 ns
t9CLOCK to Data Valid Delay 30 ns Maximum delay following rising edge of CLOCK
t10 Data Valid After CLOCK(1) 1 ns Time data is valid after second rising edge of CLOCK
NOTE: (1) ‘n – 1’ data will remain valid 1ns after rising edge of next CLOCK cycle.
TIMING SPECIFICATIONS
CLOCK CYCLE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
SERIAL DATA
CH0 OR CH1 CHA OR CHB
DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0
TABLE II. Serial Data Output Format.
NOTE: All CONVST commands which occur more than 10ns before the rising edge of cycle ‘1’ of the external clock
(Region ‘A’) will initiate a conversion on the rising edge of cycle ‘1’. All CONVST commands which occur 5ns after
the rising edge of cycle ‘1’ or 10ns before the rising edge of cycle 2 (Region ‘B’) will initiate a conversion on the
rising edge of cycle ‘2’. All CONVST commands which occur 5ns after the rising edge of cycle ‘2’ (Region ‘C’) will
initiate a conversion on the rising edge of the next clock period. The CONVST pin should never be switched from
LOW to HIGH in the region 10ns prior to the rising edge of the CLOCK and 5ns after the rising edge (gray areas). If
CONVST is toggled in this gray area, the conversion could begin on either the same rising edge of the CLOCK or
the following edge.
CLOCK
CONVST
Cycle 1 Cycle 2
tCKP
125ns
10ns
5ns
10ns
5ns
A B C
ADS7861
12 SBAS110D
Mode II (M0 = 0, M1 = 1)
With M1 set to ‘1’, the ADS7861 will output data on the
Serial Data A pin only. All other pins function in the same
manner as Mode I except that the Serial Data B output will
tri-state (i.e., high impedance) after a conversion following
M1 going HIGH. Another difference in this mode involves
the CONVST pin. Since it takes 32 clock cycles to output
the results from both A/D converters (rather than 16 when
M1 = 0), the ADS7861 will take 4µs to complete a
conversion on both A/Ds (See Figure 11).
Mode III (M0 = 1, M1 = 0)
With M0 set to ‘1’, the ADS7861 will cycle through Chan-
nels 0 and 1 sequentially (the A0 pin is ignored). At the same
time, setting M1 to ‘0’ places both Serial Outputs, A and B,
in the active mode (See Figure 12).
Mode IV (M0 = 1, M1 = 1)
Similar to Mode II, Mode IV uses the Serial A output line to
transmit data exclusively. Following the first conversion
after M1 goes HIGH, the serial B output will go into tri-
state. See Figure 13. As in Mode II, the second CONVST
command is always ignored when M1 = 1.
READING DATA
In all four timing diagrams, the CONVST pin and the RD
pins are tied together. If so desired, the two lines can be
separated. Data on the Serial Output pins (A and B) will
become valid following the third rising SCLK edge follow-
ing RD rising edge. Refer to Table II for data output format.
LAYOUT
For optimum performance, care should be taken with the
physical layout of the ADS7861 circuitry. This is particu-
larly true if the CLOCK input is approaching the maximum
throughput rate.
The basic SAR architecture is sensitive to glitches or sudden
changes on the power supply, reference, ground connections
and digital inputs that occur just prior to latching the output
of the analog comparator. Thus, driving any single conver-
sion for an n-bit SAR converter, there are n “windows” in
which large external transient voltages can affect the conver-
sion result. Such glitches might originate from switching
power supplies, nearby digital logic or high power devices.
The degree of error in the digital output depends on the
reference voltage, layout, and the exact timing of the exter-
nal event. Their error can change if the external event
changes in time with respect to the CLOCK input.
With this in mind, power to the ADS7861 should be clean
and well-bypassed. A 0.1µF ceramic bypass capacitor should
be placed as close to the device as possible. In addition, a
1µF to 10µF capacitor is recommended. If needed, an even
larger capacitor and a 5Ω or 10Ω series resistor may be used
to low pass filter a noisy supply. On average, the ADS7861
draws very little current from an external reference as the
reference voltage is internally buffered. However, glitches
from the conversion process appear at the VREF input and the
reference source must be able to handle this. Whether the
reference is internal or external, the VREF pin should be
bypassed with a 0.1µF capacitor. An additional larger ca-
pacitor may also be used, if desired. If the reference voltage
is external and originates from an op amp, make sure that it
can drive the bypass capacitor or capacitors without oscilla-
tion. No bypass capacitor is necessary when using the
internal reference (tie pin 10 directly to pin 11).
The GND pin should be connected to a clean ground point.
In many cases, this will be the ‘analog’ ground. Avoid
connections which are too near the grounding point of a
microcontroller or digital signal processor. If required, run a
ground trace directly from the converter to the power supply
entry point. The ideal layout will include an analog ground
plane dedicated to the converter and associated analog
circuitry.
ADS7861 13
SBAS110D
FIGURE 9. Mode I with Timing Specifications.
FIGURE 10. Mode I, Timing Diagram for M0 = 0 and M1 = 0.
A0
RD
CS
BUSY
SERIAL
DATA A
1CLOCK
CONVST
2345 768910111213141516123456
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 D11 D10 D9 D8
00
SERIAL
DATA B D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 D11 D10 D9 D800
t3
t1
tCONV
Conversion 1 Start of Conversion 2
tACQ tCONV
t7
t10
t9
t6
tCKH
tCKL
0
t2
t4
t8
t5
1
CLOCK
CONVST
A0
RD
CS
SERIAL
DATA A
SERIAL
DATA B
BUSY
TIME 0 1µs2µs3µs4µs5µs6µs
Time (seconds)
Conversion of Chx
12-Bit Data of Chx
12-Bit Data of Chx
12-Bit Data of ChA1
12-Bit Data of ChB1
Conversion of Ch0
16
CS HIGH, Outputs in Tri-State
Conversion of Ch1
A0 HIGH, Next Conversion: Ch1 A0 LOW, Next Conversion: Ch0
Conversion of Ch0
Conversion of Ch1
RD Connected to CONVST
ADS7861
14 SBAS110D
FIGURE 12. Mode III, Timing Diagram for M0 = 1 and M1 = 0.
FIGURE 11. Mode II, Timing Diagram for M0 = 0 and M1 = 1.
CLOCK
CONVST
A0
RD
M1
CS
SERIAL
DATA A
SERIAL
DATA B
BUSY
0TIME 5µs10µs
Time (seconds)
M1 = 1 Serial Data B in Tri-state
C
h
B
C
h
A
C
h
B
C
h
A
Conversion of Chx M1 = 1 and 1
st
CONVST
Conversion
A0 HIGH
Next Conversion Ch1
RD Connected with CONVST
12-Bit Data of ChAx
12-Bit Data of ChBx
M1 = 1 and 1
st
CONVST
Data of ChA M1 = 1 and 2
nd
CONVST
Data of ChB M1 = 1 and 1
st
CONVST
Data of ChA M1 = 1 and 2
nd
CONVST
Data of ChB
Conversion of Chx
M1 = 1 and 1
st
CONVST
Conversion M1 = 1 and 2
nd
CONVST
No Conversion M1 = 1 and 1
st
CONVST
Conversion M1 = 1 and 2
nd
CONVST
No Conversion
CS LOW Output Active
A0 LOW
Next Conversion Ch0 A0 LOW
Next Conversion Ch0
M1 = 1 and 2
nd
CONVST
No Conversion M1 = 1 and 1
st
CONVST
Conversion M1 = 1 and 2
nd
CONVST
No Conversion
161
M1 HIGH
Only Serial Data A Used as Output Starting with 1
st
Conversion
1
CLOCK
CONVST
A0
RD
M0
CS
SERIAL
DATA A
SERIAL
DATA B
BUSY
TIME 0 1µs2µs3µs4µs5µs6µs
Time (seconds)
12-Bit Data of ChAx
12-Bit Data of ChBx
12-Bit Data of ChA0
12-Bit Data of ChB0 12-Bit Data of ChB1
C
h
1
12-Bit Data of ChA1
C
h
1
C
h
0
C
h
0
16
CS LOW, Output is Active
M0 = 1 A0 Ignored
4-Ch Operation and 1
st
Conversion Ch0 4-Ch Operation and 2
nd
Conversion Ch1
RD Connected with CONVST
M0 = 1, 4-Ch Operation Starts with Next Conversion
ADS7861 15
SBAS110D
FIGURE 13. Mode IV, Timing Diagram for M0 = 1 and M1 = 1.
CLOCK
CONVST
A0
RD
M0
CS
SERIAL
DATA A
SERIAL
DATA B
BUSY
0TIME 5µs10µs
Time (seconds)
M1 = 1 Serial Data B in Tri-state
C
h
B
C
h
0
C
h
A
C
h
1
C
h
B
C
h
1
C
h
A
C
h
0
Conversion of Chx M1 = 1 and 1st CONVST
Conversion
M0 HIGH
4-Ch Operation Starts, A0 Ignored
M0 HIGH
4-Ch Operation Starts M0 = 1 and 1st Active CONVST
Ch0 M0 = 1 and 2nd Active CONVST
Ch1
M1 M1 HIGH
Only Serial Data A Used as Output Starting with 1st Conversion
RD Connected with CONVST
12-Bit Data of ChAx
12-Bit Data of ChBx
M1 = 1 and 1
st
CONVST
Data of ChA0 M1 = 1 and 2
nd
CONVST
Data of ChB0 M1 = 1 and 1
st
CONVST
Data of ChA1 M1 = 1 and 2
nd
CONVST
Data of ChB1
Conversion of Chx
M1 = 1 and 1
st
CONVST
Conversion M1 = 1 and 2
nd
CONVST
No Conversion M1 = 1 and 1
st
CONVST
Conversion M1 = 1 and 2
nd
CONVST
No Conversion
CS LOW Output Active
M1 = 1 and 2nd CONVST
No Conversion M1 = 1 and 1st CONVST
Conversion M1 = 1 and 2nd CONVST
No Conversion
116
ADS7861
16 SBAS110D
DATE REVISION PAGE SECTION DESCRIPTION
D 6 Pin Configuration Added Note (1) to QFN package.
1 Entire Document Changed Throughput Rate from 500kHz to 500kSPS throughout document.
1 Features Added Operating Temperature Range: –40°C to +125°C.
1 Description Changed Operating Temperature Range upper limit from +85°C to +125°C.
2 Absolute Maximum Ratings Changed Operating Temperature Range upper limit from +85°C to +125°C.
Changed top-of-page header condition to begin with:
"Over recommended operating free-air temperature range at..."
Changed "TMIN to TMAX" to "TA = –40°C to +125°C" in several locations.
Added TA = –40°C to +85°C to conditions for these parameters:
Bipolar Offset Error, Total Harmonic Distortion, Spurious-Free Dynamic
Range, Quiescent Current, and Power Dissipation.
Added new row for TA = –40°C to +125°C condition for these parameters:
Bipolar Offset Error, Total Harmonic Distortion, Spuriouse-Free Dynamic
Range, Quiescent Current, and Power Dissipation.
Moved "VIN = ±2.5VPP at 100kHz" from conditions of Dynamic Characteristics to
section header.
Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
C
8/06
Electrical Characteristics
3
8/07
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
ADS7861E ACTIVE SSOP/
QSOP DBQ 24 56 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS7861E/2K5 ACTIVE SSOP/
QSOP DBQ 24 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS7861E/2K5G4 ACTIVE SSOP/
QSOP DBQ 24 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS7861EB ACTIVE SSOP/
QSOP DBQ 24 56 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS7861EB/2K5 ACTIVE SSOP/
QSOP DBQ 24 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS7861EB/2K5G4 ACTIVE SSOP/
QSOP DBQ 24 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS7861EBG4 ACTIVE SSOP/
QSOP DBQ 24 56 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS7861EG4 ACTIVE SSOP/
QSOP DBQ 24 56 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS7861IBRHBR ACTIVE QFN RHB 32 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS7861IBRHBRG4 ACTIVE QFN RHB 32 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS7861IBRHBT ACTIVE QFN RHB 32 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS7861IBRHBTG4 ACTIVE QFN RHB 32 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS7861IRHBR ACTIVE QFN RHB 32 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS7861IRHBRG4 ACTIVE QFN RHB 32 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS7861IRHBT ACTIVE QFN RHB 32 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS7861IRHBTG4 ACTIVE QFN RHB 32 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
PACKAGE OPTION ADDENDUM
www.ti.com 10-Aug-2007
Addendum-Page 1
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 10-Aug-2007
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
ADS7861E ACTIVE SSOP DBQ 24 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS7861E/2K5 ACTIVE SSOP DBQ 24 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS7861E/2K5G4 ACTIVE SSOP DBQ 24 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS7861EB ACTIVE SSOP DBQ 24 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS7861EB/2K5 ACTIVE SSOP DBQ 24 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS7861EB/2K5G4 ACTIVE SSOP DBQ 24 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS7861EBG4 ACTIVE SSOP DBQ 24 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS7861EG4 ACTIVE SSOP DBQ 24 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS7861IBRHBR ACTIVE QFN RHB 32 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS7861IBRHBRG4 ACTIVE QFN RHB 32 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS7861IBRHBT ACTIVE QFN RHB 32 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS7861IBRHBTG4 ACTIVE QFN RHB 32 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS7861IRHBR ACTIVE QFN RHB 32 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS7861IRHBRG4 ACTIVE QFN RHB 32 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS7861IRHBT ACTIVE QFN RHB 32 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS7861IRHBTG4 ACTIVE QFN RHB 32 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 2
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
ADS7861E/2K5 SSOP DBQ 24 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
ADS7861EB/2K5 SSOP DBQ 24 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
ADS7861IBRHBR QFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2
ADS7861IBRHBT QFN RHB 32 250 180.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2
ADS7861IRHBR QFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2
ADS7861IRHBT QFN RHB 32 250 180.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ADS7861E/2K5 SSOP DBQ 24 2500 367.0 367.0 38.0
ADS7861EB/2K5 SSOP DBQ 24 2500 367.0 367.0 38.0
ADS7861IBRHBR QFN RHB 32 3000 367.0 367.0 35.0
ADS7861IBRHBT QFN RHB 32 250 210.0 185.0 35.0
ADS7861IRHBR QFN RHB 32 3000 367.0 367.0 35.0
ADS7861IRHBT QFN RHB 32 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 2
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