ADC12138CIMSAXNOPB - NATIONAL SEMICONDUCTOR

ADC12130,ADC12132,ADC12138

ADC12130/ADC12132/ADC12138 Self-Calibrating 12-Bit Plus Sign Serial I/O

A/D Converters with MUX and Sample/Hold

Literature Number: SNAS098F

September 8, 2008

ADC12130/ADC12132/ADC12138

Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters

with MUX and Sample/Hold

General Description

NOTE: Some device/package combinations are obsolete

and are described and shown here for reference only. See

our web site for product availability.

The ADC12130, ADC12132 and ADC12138 are 12-bit plus

sign successive approximation Analog-to-Digital converters

with serial I/O and configurable input multiplexer. The

ADC12132 and ADC12138 have a 2 and an 8 channel mul-

tiplexer, respectively. The differential multiplexer outputs and

ADC inputs are available on the MUXOUT1, MUXOUT2,

A/DIN1 and A/DIN2 pins. The ADC12130 has a two channel

multiplexer with the multiplexer outputs and ADC inputs in-

ternally connected. The ADC12130 family is tested and spec-

ified with a 5 MHz clock. On request, these ADCs go through

a self calibration process that adjusts linearity, zero and full-

scale errors to typically less than ±1 LSB each.

The analog inputs can be configured to operate in various

combinations of single-ended, differential, or pseudo-differ-

ential modes. A fully differential unipolar analog input range

(0V to +5V) can be accommodated with a single +5V supply.

In the differential modes, valid outputs are obtained even

when the negative inputs are greater than the positive be-

cause of the 12-bit plus sign output data format.

The serial I/O is configured to comply with NSC MI-

CROWIRE™. For voltage references, see the LM4040,

LM4050 or LM4041.

Features

■Serial I/O (MICROWIRE, SPI and QSPI Compatible)

■Power down mode

■Programmable acquisition time

■Variable digital output word length and format

■No zero or full scale adjustment required

■0V to 5V analog input range with single 5V power supply

Key Specifications

Resolution 12-bit plus sign

■ 12-Bit plus sign conversion time 8.8 µs (max)

■ 12-Bit plus sign throughput time 14 µs (max)

■ Integral Linearity Error ±2 LSB (max)

■ Single Supply 3.3V or 5V ±10%

■ Power Consumption

+3.3V 15 mW (max)

+3.3V power down 40 μW (typ)

+5V 33 mW (max)

+5V power down 100 μW (typ)

Applications

■Pen-based computers

■Digitizers

■Global positioning systems

TRI-STATE® is a registered trademark of National Semiconductor Corporation.

ADC12130/ADC12132/ADC12138 Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with

MUX and Sample/Hold

ADC12138 Simplified Block Diagram

1207901

Connection Diagrams

16-Pin Dual-In-Line and

Wide Body SO Packages

1207902

Top View

20-Pin SSOP Package

1207947

Top View

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ADC12130/ADC12132/ADC12138

28-Pin Dual-In-Line, SSOP and

Wide Body SO Packages

1207903

Top View

Ordering Information

Industrial Temperature Range

−40°C ≤ TA ≤ +85°C NS Package Number

ADC12130CIN N16E, Dual-In-Line

ADC12130CIWM M16B, Wide Body SO

ADC12130CIWMX M16B, Wide Body SO - Tape & Reel

ADC12132CIMSA MSA20, SSOP

ADC12132CIMSAX MSA20, SSOP - Tape & Reel

ADC12138CIN N28B, Dual-In-Line

ADC12138CIWM M28B

ADC12138CIWMX M28B - Tape & Reel

ADC12138CIMSA MSA28, SSOP

ADC12138CIMSA MSA28, SSOP - Tape & Reel

Some of these product/package combinations are obsolete and are shown here for reference only. Check the National web site

for availability.

Pin Descriptions

Pin Name Pin Description

CH0 thru CH7

Analog Inputs to the MUX (multiplexer). A channel input is selected by the address information at the DI pin,

which is loaded at the rising edge of SCLK into the address register (see Table 2 and Table 3). The voltage

applied to these inputs should not exceed VA+ or go below VA- or below GND. Exceeding this range on an

unselected channel may corrupt the reading of a selected channel.

COM Analog input pin that is used as a pseudo ground when the analog multiplexer is single-ended.

MUXOUT1

MUXOUT2

Multiplexer Output pins. If the multiplexer is used, these pins should be connected to the A/DIN pins, directly

or through an amplifier and/of filter.

A/DIN1

A/DIN2

Converter Input pins. MUXOUT1 is usually tied to A/DIN1. MUXOUT2 is usually tied to A/DIN2. If external

circuitry is placed between MUXOUT1 and A/DIN1, or MUXOUT2 and A/DIN2, it may be necessary to protect

these pins against voltage overload. The voltage at these pins should not exceed VA+ or go below AGND (see

Figure 6).

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ADC12130/ADC12132/ADC12138

Pin Name Pin Description

Data Output pin. This pin is an active push/pull output when CS is low. When CS is high, this output is TRI-

STATE®. The conversion result (DB0–DB12) and converter status data are clocked out at the falling edge of

SCLK on this pin. The word length and format of this result can vary (see Table 1). The word length and format

are controlled by the data shifted into the multiplexer address and mode select register (see Table 4).

Serial Data Input pin. The data applied to this pin is shifted at the rising edge of SCLK into the multiplexer

address and mode select register. Table 2 through Table 4 show the assignment of the multiplexer address

and the mode select data.

EOC

This pin is an active push/pull output which indicates the status of the ADC12130/2/8.A logic low on this pin

indicates that the ADC is busy with a conversion, Auto Calibration, Auto Zero or power down cycle. The rising

edge of EOC signals the end of one of these cycles

CONV

A logic low is required at this pin to program any mode or to change the ADC's configuration as listed in Mode

Programming (Table 4). When this pin is high, the ADC is placed in the read data only mode. While in the read

data only mode, bringing CS low and pulsing SCLK will only clock out the data stored in the ADCs output shift

mode and/or configuration previously programmed. Read data only cannot be performed while a conversion,

Auto Cal or Auto Zero are in progress.

Chip Select input pin. When a logic low is applied to this pin, the rising edge of SCLK shifts the data at the DI

input into the address register and brings DO out of TRI-STATE. With CS low, the falling edge of SCLK shifts

the data resulting from the previous ADC conversion out at the DO output, with the exception of the first bit of

data. When CS is low continuously, the first bit of the data is clocked out on the rising edge of EOC (end of

conversion). When CS is toggled, the falling edge of CS always clocks out the first bit of data. CS should be

brought low while SCLK is low. The falling edge of CS interrupts a conversion in progress and starts the

sequence for a new conversion. When CS is brought low during a conversion, that conversion is prematurely

terminated and the data in the output latches may be corrupted. Therefore, when CS is brought low during a

conversion in progress, the data output at that time should be ignored. CS may also be left continuously low.

In this case, it is imperative that the correct number of SCLK pulses be applied to the ADC in order to remain

synchronous. After the ADC supply power is applied, the device expects to see 13 clock pulses for each I/O

sequence. The number of clock pulses the ADC expects is the same as the digital output word length. This

word length can be modified by the data shifted in at the DO pin. Table 4 details the data required.

DOR Data Output Ready pin. This pin is an active push/pull output which is low when the conversion result is being

shifted out and goes high to signal that all the data has been shifted out.

SCLK

Serial Data Clock input. The clock applied to this input controls the rate at which the serial data exchange occurs.

The rising edge loads the information at the DI pin into the multiplexer address and mode select shift register.

This address controls which channel of the analog input multiplexer (MUX) is selected and the mode of operation

for the ADC. With CS low, the falling edge of SCLK shifts the data resulting from the previous ADC conversion

out on DO, with the exception of the first bit of data. When CS is low continuously, the first bit of the data is

clocked out on the rising edge of EOC (end of conversion). When CS is toggled, the falling edge of CS always

clocks out the first bit of data. CS should be brought low when SCLK is low. The rise and fall times of the clock

edges should not exceed 1 μs.

CCLK Conversion Clock input. The clock applied to this input controls the successive approximation conversion time

interval and the acquisition time. The rise and fall times of the clock edges should not exceed 1 μs.

VREF+

Positive analog voltage reference input. In order to maintain accuracy, the voltage range of VREF (VREF = VREF

+ − VREF−) is 1.0 VDC to 5.0 VDC and the voltage at VREF+ cannot exceed VA+. See Figure 5 for recommended

bypassing.

VREF-The negative analog voltage reference input. In order to maintain accuracy, the voltage at this pin must not go

below GND or exceed VREF+. (See Figure 5).

PD Power Down pin. When PD is high the ADC is powered down; when PD is low the ADC is powered up, or active.

The ADC takes a maximum of 700 μs to power up after the command is given.

VA+

VD+

These are the analog and digital power supply pins. VA+ and VD+ are not connected together on the chip. These

pins should be tied to the same supply voltage and bypassed separately (see Figure 5). The operating voltage

range of VA+ and VD+ is 3.0 VDC to 5.5 VDC.

DGND The digital ground pin (see Figure 5).

AGND The analog ground pin (see Figure 5).

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ADC12130/ADC12132/ADC12138

Absolute Maximum Ratings

(Notes 1, 2)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Positive Supply Voltage

(V+ = VA+ = VD+) 6.5V

Voltage at Inputs and Outputs

except CH0–CH7 and COM −0.3V to V+ +0.3V

Voltage at Analog Inputs

CH0–CH7 and COM GND −5V to V+ +5V

|VA+ − VD+| 300 mV

Input Current at Any Pin (Note 3) ±30 mA

Package Input Current (Note 3) ±120 mA

Package Dissipation at

TA = 25°C (Note 4) 500 mW

ESD Susceptibility (Note 5)

Human Body Model 1500V

Soldering Information

N Packages (10 seconds) 260°C

SO Package (Note 6):

Vapor Phase (60 seconds) 215°C

Infrared (15 seconds) 220°C

Storage Temperature −65°C to +150°C

Operating Ratings (Notes 1, 2)

Operating Temperature Range TMIN ≤ TA ≤ TMAX

−40°C ≤ TA ≤ +85°C

Supply Voltage (V+ = VA+ = VD+) +3.0V to +5.5V

|VA+ − VD+| ≤ 100 mV

VREF+ 0V to VA+

VREF− 0V to (VREF+ −1V)

VREF (VREF+ − VREF−) 1V to VA+

VREF Common Mode Voltage Range

[(VREF+) − (VREF−)] / 2 0.1 VA+ to 0.6 VA+

A/DIN1, A/DIN2, MUXOUT1

and MUXOUT2 Voltage Range 0V to VA+

ADC IN Common Mode Voltage

Range

[(VIN+) − (VIN−)] / 2 0V to VA+

Package Thermal Resistance

Part Number Thermal Resistance

(θJA)

ADC12130CIN 53°C/W

ADC12130CIWM 70°C/W

ADC12132CIMSA 134°C/W

ADC12132CIWM 64°C/W

ADC121038CIN 40°C/W

ADC121038CIMSA 97°C/W

ADC12138CIWM 50°C/W

Some of these product/package combinations are obsolete

and are shown here for reference only. Check the National

web site for availability.

Converter Electrical Characteristics

The following specifications apply for (V+ = VA+ = VD+ = +5V, VREF+ = +4.096V, and fully differential input with fixed 2.048V common-

mode voltage) or (V+ = VA+ = VD+ = 3.3V, VREF+ = 2.5V and fully-differential input with fixed 1.250V common-mode voltage), VREF

− = 0V, 12-bit + sign conversion mode, source impedance for analog inputs, VREF− and VREF+ ≤ 25Ω, fCK = fSK = 5 MHz, and 10

(tCK) acquisition time unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25°

C. (Notes 7, 8, 9)

Symbol Parameter Conditions Typical

(Note 10)

Limits

(Note 11)

Units

(Limits)

STATIC CONVERTER CHARACTERISTICS

Resolution with No Missing Codes 12 + sign Bits (min)

ILE Integral Linearity Error After Auto Cal (Notes 12, 18) ±1/2 ±2 LSB (max)

DNL Differential Non-Linearity After Auto Cal ±1.5 LSB (max)

Positive Full-Scale Error After Auto Cal (Notes 12, 18) ±1/2 ±3.0 LSB (max)

Negative Full-Scale Error After Auto Cal (Notes 12, 18) ±1/2 ±3.0 LSB (max)

Offset Error After Auto Cal (Notes 5, 18)

VIN(+) = VIN(−) = 2.048V ±1/2 ±2 LSB (max)

DC Common Mode Error After Auto Cal (Note 15) ±2 LSB (max)

TUE Total Unadjusted Error After Auto Cal (Notes 12, 13, 14) ±1 LSB

Multiplexer Chan-to-Chan Matching V+ = +5V ±10%, VREF = +4.096V ±0.05 LSB

Power Supply Sensitivity

Offset Error

+ Full-Scale Error

− Full-Scale Error

Integral Linearity Error

±0.5

LSB

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ADC12130/ADC12132/ADC12138

Symbol Parameter Conditions Typical

(Note 10)

Limits

(Note 11)

Units

(Limits)

UNIPOLAR DYNAMIC CONVERTER CHARACTERISTICS

S/(N+D) Signal-to-Noise Plus Distortion Ratio

fIN = 1 kHz, VIN = 5 VPP, VREF+ = 5.0V 69.4 dB

fIN = 20 kHz, VIN = 5 VPP, VREF+ = 5.0V 68.3 dB

fIN = 40 kHz, VIN = 5 VPP, VREF+ = 5.0V 65.7 dB

−3 dB Full Power Bandwidth VIN = 5 VPP, where S/(N+D) drops 3 dB 31 kHz

DIFFERENTIAL DYNAMIC CONVERTER CHARACTERISTICS

fIN = 1 kHz, VIN = ±5V, VREF+ = 5.0V 77.0 dB

S/(N+D) Signal-to-Noise Plus Distortion Ratio fIN = 20 kHz, VIN = ±5V, VREF+ = 5.0V 73.9 dB

fIN = 40 kHz, VIN = ±5V, VREF+ = 5.0V 67.0 dB

−3 dB Full Power Bandwidth VIN = ±5V, where S/(N+D) drops 3 dB 40 kHz

REFERENCE INPUT, ANALOG INPUTS AND MULTIPLEXER CHARACTERISTICS

CREF Reference Input Capacitance 85 pF

CA/D

A/DIN1 and A/DIN2 Analog Input

Capacitance 75 pF

A/DIN1 and A/DIN2 Analog Input

Leakage Current VIN = +5.0V or VIN = 0V ±0.1 μA

CH0–CH7 and COM Input Voltage GND − 0.05

(VA+) + 0.05 V (min)

V (max)

CCH

CH0–CH7 and COM Input

Capacitance 10 pF

CMUXOUT MUX Output Capacitance 20 pF

Off Channel Leakage (Note 16)

CH0–CH7 and COM Pins

On Channel = 5V and

Off Channel = 0V −0.01 μA

On Channel = 0V and

Off Channel = 5V 0.01 μA

On Channel Leakage (Note 16)

CH0–CH7 and COM Pins

On Channel = 5V and

Off Channel = 0V 0.01 μA

On Channel = 0V and

Off Channel = 5V −0.01 μA

MUXOUT1 and MUXOUT2 Leakage

Current VMUXOUT = 5.0V or VMUXOUT = 0V 0.01 μA

RON MUX On Resistance VIN = 2.5V and

VMUXOUT = 2.4V 850 1900 Ω (max)

RON Matching Channel to Channel VIN = 2.5V and

VMUXOUT = 2.4V 5 %

Channel-to-Channel Crosstalk VIN = 5 VPP, fIN = 40 kHz −72 dB

MUX Bandwidth 90 kHz

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ADC12130/ADC12132/ADC12138

DC and Logic Electrical Characteristics

The following specifications apply for (V+ = VA+ = VD+ = +5V, VREF+ = +4.096V, and fully-differential input with fixed 2.048V

common-mode voltage) or (V+ = VA+ = VD+ = +3.3V, VREF+ = +2.5V and fully-differential input with fixed 1.250V common-mode

voltage), VREF− = 0V, 12-bit + sign conversion mode, source impedance for analog inputs, VREF− and VREF+ ≤ 25Ω, fCK = fSK = 5

MHz, and 10 (tCK) acquisition time unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits

TA = TJ = 25°C. (Notes 7, 8, 9)

Symbol Parameter Conditions Typical

(Note 10)

V+ = VA+ =

VD+ = 3.3V

Limits (Note

11)

V+ = VA+ =

VD+ = 5V

Limits (Note

11)

Units

(Limits)

CCLK, CS, CONV, DI, PD AND SCLK INPUT CHARACTERISTICS

VIN(1) Logical “1” Input Voltage VA+ = VD+ = V+ +10% 2.0 2.0 V (min)

VIN(0) Logical “0” Input Voltage VA+ = VD+ = V+ −10% 0.8 0.8 V (max)

IIN(1) Logical “1” Input Current VIN = V+0.005 1.0 1.0 μA (max)

IIN(0) Logical `“0” Input Current VIN = 0V −0.005 −1.0 −1.0 μA (min)

DO, EOC AND DOR DIGITAL OUTPUT CHARACTERISTICS

VOUT(1) Logical “1” Output Voltage

VA+ = VD+ = V+ − 10%,

IOUT = −360 μA 2.4 2.4 V (min)

VA+ = VD+ = V+ − 10%,

IOUT = −10 μA 2.9 4.25 V (min)

VOUT(0) Logical “0” Output Voltage VA+ = VD+ = V+ − 10%

IOUT = 1.6 mA 0.4 0.4 V (max)

IOUT TRI-STATE Output Current VOUT = 0V

VOUT = V+

−0.1

−3.0

3.0

−3.0

3.0

μA (max)

+ISC Output Short Circuit Source Current VOUT = 0V −14 mA

−ISC Output Short Circuit Sink Current VOUT = VD+16 mA

POWER SUPPLY CHARACTERISTICS

ID+Digital Supply Current

Awake (Active) 1.5 2.5 mA (max)

CS = HIGH, Powered Down,

CCLK on 600 μA

CS = HIGH, Powered Down,

CCLK off 20 μA

IA+Positive Analog Supply Current

Awake (Active) 3.0 4.0 mA (max)

CS = HIGH, Powered Down,

CCLK on

10 μA

CS = HIGH, Powered Down,

CCLK off

0.1 μA

IREF Reference Input Current

CS = HIGH, Powered Down,

CCLK on 70 μA

CS = HIGH, Powered Down,

CCLK off 0.1 μA

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ADC12130/ADC12132/ADC12138

AC Electrical Characteristics

The following specifications apply for (V+ = VA+ = VD+ = +5V, VREF+ = +4.096V, and fully-differential input with fixed 2.048V

common-mode voltage) or (V+ = VA+ = VD+ = +3.3V, VREF+ = +2.5V and fully-differential input with fixed 1.250V common-mode

voltage), VREF− = 0V, 12-bit + sign conversion mode, source impedance for analog inputs, VREF− and VREF+ ≤ 25Ω, fCK = fSK = 5

MHz, and 10 (tCK) acquisition time unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits

TA = TJ = 25°C. (Note 17)

Symbol Parameter Conditions Typical

(Note 10) Limits (Note 11) Units (Limits)

fCK Conversion Clock (CCLK) Frequency 10

5MHz (max)

MHz (min)

fSK Serial Data Clock SCLK Frequency 10

5MHz (max)

Hz (min)

Conversion Clock Duty Cycle 40

% (min)

% (max)

Serial Data Clock Duty Cycle 40

% (min)

% (max)

tCConversion Time 12-Bit + Sign or 12-Bit 44(tCK)44(tCK)(max)

8.8 μs (max)

tAAcquisition Time (Note 19)

6 Cycles Programmed

6(tCK)6(tCK)(min)

7(tCK)(max)

1.2 μs (min)

1.4 μs (max)

10 Cycles Programmed

10(tCK)10(tCK)(min)

11(tCK)(max)

2.0 μs (min)

2.2 μs (max)

18 Cycles Programmed

18(tCK)18(tCK)(min)

19(tCK)(max)

3.6 μs (min)

3.8 μs (max)

34 Cycles Programmed

34(tCK)34(tCK)(min)

35(tCK)(max)

6.8 μs (min)

7.0 μs (max)

tCAL Self-Calibration Time 4944(tCK)4944(tCK)(max)

988.8 μs (max)

tAZ Auto Zero Time 76(tCK)76(tCK)(max)

15.2 μs (max)

tSYNC

Self-Calibration or Auto Zero

Synchronization Time from DOR

2(tCK)2(tCK)(min)

3(tCK)(max)

0.40 μs (min)

0.60 μs (max)

tDOR

DOR High Time when CS is Low

Continuously for Read Data and Software

Power Up/Down

9(tSK)9(tSK)(max)

1.8 μs (max)

tCONV CONV Valid Data Time 8(tSK)8(tSK)(max)

1.6 μs (max)

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ADC12130/ADC12132/ADC12138

AC Electrical Characteristics

The following specifications apply for (V+ = VA+ = VD+ = +5V, VREF+ = +4.096V, and fully-differential input with fixed 2.048V

common-mode voltage) or (V+ = VA+ = VD+ = +3.3V, VREF+ = +2.5V and fully-differential input with fixed 1.250V common-mode

voltage), VREF− = 0V, 12-bit + sign conversion mode, source impedance for analog inputs, VREF− and VREF+ ≤ 25Ω, fCK = fSK = 5

MHz, and 10 (tCK) acquisition time unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits

TA = TJ = 25°C. (Note 17) (Continued)

Symbol Parameter Conditions Typical (Note

10)

Limits (Note

11)

Units

(Limits)

tHPU

Hardware Power-Up Time, Time from PD

Falling Edge to EOC Rising Edge 500 700 μs (max)

tSPU

Software Power-Up Time, Time from Serial

Data Clock Falling Edge to EOC Rising Edge 500 700 μs (max)

tACC

Access Time Delay from CS Falling Edge to

DO Data Valid 25 60 ns (max)

tSET-UP

Set-Up Time of CS Falling Edge to Serial Data

Clock Rising Edge 50 ns (min)

tDELAY

Delay from SCLK Falling Edge to CS Falling

Edge 0 5ns (min)

t1H, t0H Delay from CS Rising Edge to DO TRI-STATE RL = 3k, CL = 100 pF 70 100 ns (max)

tHDI

DI Hold Time from Serial Data Clock Rising

Edge 5 15 ns (max)

tSDI

DI Set-Up Time from Serial Data Clock Rising

Edge 5 10 ns (min)

tHDO

DO Hold Time from Serial Data Clock Falling

Edge RL = 3k, CL = 100 pF 35 65

ns (max)

ns (min)

tDDO

Delay from Serial Data Clock Falling Edge to

DO Data Valid 50 90 ns (max)

tRDO

DO Rise Time, TRI-STATE to High DO Rise

Time, Low to High RL = 3k, CL = 100 pF 10

ns (max)

tFDO

DO Fall Time, TRI-STATE to Low DO Fall

Time, High to Low RL = 3k, CL = 100 pF 15

ns (max)

tCD

Delay from CS Falling Edge to DOR Falling

Edge 45 80 ns (max)

tSD

Delay from Serial Data Clock Falling Edge to

DOR Rising Edge 45 80 ns (max)

CIN Capacitance of Logic Inputs 20 pF

COUT Capacitance of Logic Outputs 20 pF

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is

functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed

specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test

conditions.

Note 2: All voltages are measured with respect to GND, unless otherwise specified.

Note 3: When the input voltage (VIN) at any pin exceeds the power supplies (VIN < GND or VIN > VA+ or VD+), the current at that pin should be limited to 30 mA.

The 120 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 30 mA to four.

Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax, θJA and the ambient temperature, TA. The maximum

allowable power dissipation at any temperature is PD = (TJmax − TA)/θJA or the number given in the Absolute Maximum Ratings, whichever is lower. For this

device, TJmax = 150°C.

Note 5: The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin.

Note 6: See AN450 “Surface Mounting Methods and Their Effect on Product Reliability” or the section titled “Surface Mount” found in any post 1986 National

Semiconductor Linear Data Book for other methods of soldering surface mount devices.

Note 7: Two on-chip diodes are tied to each analog input through a series resistor as shown below. Input voltage magnitude up to 5V above VA+ or 5V below

GND will not damage this device. However, errors in conversion can occur (if these diodes are forward biased by more than 50 mV) if the input voltage magnitude

of selected or unselected analog input go above VA+ or below GND by more than 50 mV. As an example, if VA+ is 4.5 VDC, full-scale input voltage must be

≤4.55 VDC to ensure accurate conversions.

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ADC12130/ADC12132/ADC12138

1207904

Note 8: To guarantee accuracy, it is required that the VA+ and VD+ be connected together to the same power supply with separate bypass capacitors at each

V+ pin.

Note 9: With the test condition for VREF (VREF+ − VREF−) given as +4.096V, the 12-bit LSB is 1.0 mV. For VREF = 2.5V, the 12-bit LSB is 610 μV.

Note 10: Typical figures are at TJ = TA = 25°C and represent most likely parametric norm.

Note 11: Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level).

Note 12: Positive integral linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive full-

scale and zero. For negative integral linearity error, the straight line passes through negative full-scale and zero (see Figure 2 and Figure 3).

Note 13: Offset or Zero error is a measure of the deviation from the mid-scale voltage (a code of zero), expressed in LSB. It is the average value of the code

transitions between −1 to 0 and 0 to +1 (see Figure 4).

Note 14: Total unadjusted error includes offset, full-scale, linearity and multiplexer errors.

Note 15: The DC common-mode error is measured in the differential multiplexer mode with the assigned positive and negative input channels shorted together.

Note 16: Channel leakage current is measured after the channel selection.

Note 17: Timing specifications are tested at the TTL logic levels, VOL = 0.4V for a falling edge and VOL = 2.4V for a rising edge. TRI-STATE output voltage is

forced to 1.4V.

Note 18: The ADC12130 family's self-calibration technique ensures linearity and offset errors as specified, but noise inherent in the self-calibration process will

result in a maximum repeatability uncertainty of 0.2 LSB.

Note 19: If SCLK and CCLK are driven from the same clock source, then tA is 6, 10, 18 or 34 clock periods minimum and maximum.

Note 20: The “12-Bit Conversion of Offset” and “12-Bit Conversion of Full-Scale” modes are intended to test the functionality of the device. Therefore, the output

data from these modes are not an indication of the accuracy of a conversion result.

1207905

FIGURE 1. Transfer Characteristic

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ADC12130/ADC12132/ADC12138

1207906

FIGURE 2. Simplified Error Curve vs. Output Code without Auto Calibration or Auto Zero Cycles

1207907

FIGURE 3. Simplified Error Curve vs. Output Code after Auto Calibration Cycle

1207908

FIGURE 4. Offset or Zero Error Voltage

11 www.national.com

ADC12130/ADC12132/ADC12138

Typical Performance Characteristics The following curves apply for 12-bit + sign mode after Auto

Calibration unless otherwise specified.

Linearity Error Change

vs. Clock Frequency

1207953

Linearity Error Change

vs. Temperature

1207954

Linearity Error Change

vs. Reference Voltage

1207955

Linearity Error Change

vs. Supply Voltage

1207956

Full-Scale Error Change

vs. Clock Frequency

1207957

Full-Scale Error Change

vs. Temperature

1207958

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ADC12130/ADC12132/ADC12138

Full-Scale Error Change

vs. Reference Voltage

1207959

Full-Scale Error Change

vs. Supply Voltage

1207960

Offset or Zero Error Change

vs. Clock Frequency

1207961

Offset or Zero Error Change

vs. Temperature

1207962

Offset or Zero Error Change

vs. Reference Voltage

1207963

Offset or Zero Error Change

vs. Supply Voltage

1207964

13 www.national.com

ADC12130/ADC12132/ADC12138

Analog Supply Current

vs. Temperature

1207965

Digital Supply Current

vs. Clock Frequency

1207966

Digital Supply Current

vs. Temperature

1207967

Linearity Error Change

vs. Temperature

1207968

Full-Scale Error Change

vs. Temperature

1207969

Full-Scale Error Change

vs. Supply Voltage

1207970

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ADC12130/ADC12132/ADC12138

Offset or Zero Error Change

vs. Temperature

1207971

Offset or Zero Error Change

vs. Supply Voltage

1207972

Analog Supply Current

vs. Temperature

1207973

Digital Supply Current

vs. Temperature

1207974

15 www.national.com

ADC12130/ADC12132/ADC12138

Typical Dynamic Performance Characteristics

The following curves apply for 12-bit + sign mode after Auto Calibration unless otherwise specified.

Bipolar Spectral Response

with 1 kHz Sine Wave Input

1207975

Bipolar Spectral Response

with 10 kHz Sine Wave Input

1207976

Bipolar Spectral Response

with 20 kHz Sine Wave Input

1207977

Bipolar Spectral Response

with 30 kHz Sine Wave Input

1207978

Bipolar Spectral Response

with 40 kHz Sine Wave Input

1207979

Bipolar Spectral Response

with 50 kHz Sine Wave Input

1207980

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ADC12130/ADC12132/ADC12138

Bipolar Spurious Free

Dynamic Range

1207981

Unipolar Signal-to-Noise Ratio

vs. Input Frequency

1207982

Unipolar Signal-to-Noise

+ Distortion Ratio

vs. Input Frequency

1207983

Unipolar Signal-to-Noise

+ Distortion Ratio

vs. Input Signal Level

1207984

Unipolar Spectral Response

with 1 kHz Sine Wave Input

1207985

Unipolar Spectral Response

with 10 kHz Sine Wave Input

1207986

17 www.national.com

ADC12130/ADC12132/ADC12138

Unipolar Spectral Response

with 20 kHz Sine Wave Input

1207987

Unipolar Spectral Response

with 30 kHz Sine Wave Input

1207988

Unipolar Spectral Response

with 40 kHz Sine Wave Input

1207989

Unipolar Spectral Response

with 50 kHz Sine Wave Input

1207990

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ADC12130/ADC12132/ADC12138

Test Circuits

DO “TRI-STATE” (t1H, t0H)

1207913

DO except “TRI-STATE”

1207914

Leakage Current

1207915

Timing Diagrams

DO Falling and Rising Edge

1207916

DO “TRI-STATE” Falling and Rising Edge

1207917

DI Data Input Timing

1207918

19 www.national.com

ADC12130/ADC12132/ADC12138

DO Data Output Timing Using CS

1207919

DO Data Output Timing with CS Continuously Low

1207920

ADC12138 Auto Cal or Auto Zero

1207921

Note: DO output data is not valid during this cycle.

www.national.com 20

ADC12130/ADC12132/ADC12138

ADC12138 Read Data without Starting a Conversion Using CS

1207922

ADC12138 Read Data without Starting a Conversion with CS Continuously Low

1207923

21 www.national.com

ADC12130/ADC12132/ADC12138

ADC12138 Conversion Using CS with 16-Bit Digital Output Format

1207924

ADC12138 Conversion with CS Continuously Low and 16-Bit Digital Output Format

1207925

www.national.com 22

ADC12130/ADC12132/ADC12138

ADC12138 Software Power Up/Down Using CS with 16-Bit Digital Output Format

1207926

ADC12138 Software Power Up/Down with CS Continuously Low and 16-Bit Digital Output Format

1207927

23 www.national.com

ADC12130/ADC12132/ADC12138

ADC12138 Hardware Power Up/Down

1207928

Note: Hardware power up/down may occur at any time. If PD is high while a conversion is in progress that conversion will be corrupted and erroneous data will

be stored in the output shift register.

ADC12138 Configuration Modification—Example of a Status Read

1207929

1207931

*Tantalum

**Monolithic Ceramic or better

FIGURE 5. Recommended Power Supply Bypassing and Grounding

www.national.com 24

ADC12130/ADC12132/ADC12138

1207930

FIGURE 6. Protecting the MUXOUT1, MUXOUT2, A/DIN1 and A/DIN2 Analog Pins

Format and Set-Up Tables

TABLE 1. Data Out Formats

DO Formats DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB 10 DB 11 DB 12 DB 13 DB 14 DB 15 DB 16

with

Sign

MSB

First

Bits X X X X Sign MSB 10 9 8 7 6 5 4 3 2 1 LSB

Bits Sing MSB 10 9 8 7 6 5 4 3 2 1 LSB

LSB

First

Bits LSB 1 2 3 4 5 6 7 8 9 10 MSB Sign X X X X

Bits LSB 1 2 3 4 5 6 7 8 9 10 MSB Sign

with-

out

Sign

MSB

First

Bits 0 0 0 0 MSB 10 9 8 7 6 5 4 3 2 1 LSB

Bits MSB 10 9 8 7 6 5 4 3 2 1 LSB

LSB

First

Bits LSB 1 2 3 4 5 6 7 8 9 10 MSB 0 0 0 0

Bits LSB 1 2 3 4 5 6 7 8 9 10 MSB

X = High or Low state.

25 www.national.com

ADC12130/ADC12132/ADC12138

TABLE 2. ADC12138 Multiplexer Addressing

MUX Address

Analog Channel Addressed and Assignment

with A/DIN1 tied to MUXOUT1 and A/DIN2 tied to

MUXOUT2

ADC Input

Polarity

Assignment

Multiplexer Output

Channel Assignment Mode

DI0 DI1 DI2 DI3 CH

7COM A/DIN1 A/DIN2 MUXOUT1 MUXOUT2

L L L L + − + −CH0 CH1

Differential

L L L H + − + −CH2 CH3

L L H L + − + −CH4 CH5

L L H H + − + −CH6 CH7

L H L L −+ −+ CH0 CH1

L H L H −+ −+ CH2 CH3

L H H L −+ −+ CH4 CH5

L H H H −+ −+ CH6 CH7

H L L L + −+−CH0 COM

Single-Ended

H L L H + −+−CH2 COM

H L H L + −+−CH4 COM

H L H H + −+−CH6 COM

H H L L + −+−CH1 COM

H H L H + −+−CH3 COM

H H H L + −+−CH5 COM

H H H H + −+−CH7 COM

TABLE 3. ADC12130 and ADC12132 Multiplexer Addressing

MUX Address

Analog Channel Addressed and Assignment

with A/DIN1 tied to MUXOUT1 and A/DIN2 tied

to MUXOUT2

ADC Input Polarity

Assignment

Multiplexer Output

Channel Assignment Mode

DI0 DI1 CH0 CH1 COM A/DIN1 A/DIN2 MUXOUT1 MUXOUT2

L L + − + −CH0 CH1 Differential

L H −+ −+ CH0 CH1

H L + −+−CH0 COM Single-Ended

H H + −+−CH1 COM

Note: ADC12130 do not have A/DIN1, A/DIN2, MUXOUT1 and MUXOUT2 pins.

www.national.com 26

ADC12130/ADC12132/ADC12138

TABLE 4. Mode Programming

ADC12138 DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7

Mode Selected

(Current)

DO Format

(next Conversion

Cycle)

ADC12130

and

ADC12132

DI0 DI1 DI2 DI3 DI4 DI5

See Table 2 or Table 3 L L L L 12 Bit Conversion 12 or 13 Bit MSB First

See Table 2 or Table 3 L L L H 12 Bit Conversion 16 or 17 Bit MSB First

See Table 2 or Table 3 L H L L 12 Bit Conversion 12 or 13 Bit LSB First

See Table 2 or Table 3 L H L H 12 Bit Conversion 16 or 17 Bit LSB First

L L L L H L L L Auto Cal No Change

L L L L H L L H Auto Zero No Change

L L L L H L H L Power Up No Change

L L L L H L H H Power Down No Change

L L L L H H L L Read Status Register No Change

L L L L H H L H Data Out without Sign No Change

H L L L H H L H Data Out with Sign No Change

L L L L H H H L Acquisition Time—6 CCLK Cycles No Change

L H L L H H H L Acquisition Time—10 CCLK Cycles No Change

H L L L H H H L Acquisition Time—18 CCLK Cycles No Change

H H L L H H H L Acquisition Time—34 CCLK Cycles No Change

L L L L H H H H User Mode No Change

H X X X H H H H Test Mode

(CH1–CH7 become Active Outputs) No Change

Note: The ADC powers up with no Auto Cal, no Auto Zero, 10 CCLK acquisition time, 12-bit + sign conversion, power up, 12- or 13-bit MSB First, and user mode.

X = Don't Care

TABLE 5. Conversion/Read Data Only Mode Programming

CS CONV PD Mode

L L L See Table 4 for Mode

L H L Read Only (Previous DO Format). No Conversion.

H X L Idle

X X H Power Down

X = Don't Care

TABLE 6. Status Register

Status Bit DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8

Location

Status Bit PU PD Cal 12 or 13 16 or 17 Sign Justification Test Mode

Device Status DO Output Format Status

Function “High”

indicates a

Power Up

Sequence

is in

progress

“High”

indicates a

Power

Down

Sequence

is in

progress

“High”

indicates

an Auto Cal

Sequence

is in

progress

Not used “High”

indicates a

12 or 13 bit

format

“High”

indicates a

16 or 17 bit

format

“High”

indicates

that the

sign bit is

included.

When

“Low” the

sign bit is

not

included.

When “High”

the conversion

result will be

output MSB

first. When

“Low” the

result will be

output LSB

first.

When

“High” the

device is in

test mode.

When

“Low” the

device is in

user mode.

27 www.national.com

ADC12130/ADC12132/ADC12138

Application Information

NOTE: Some of the device/package combinations are ob-

solete and are shown and described here for reference

only. Please see the National web site for availability.

1.0 DIGITAL INTERFACE

1.1 Interface Concepts

The example in Figure 7 shows a typical sequence of events

after the power is applied to the ADC12130/2/8:

1207932

FIGURE 7. Typical Power Supply Power Up Sequence

The first instruction input to the ADC via DI initiates Auto Cal.

The data output on DO at that time is meaningless and is

completely random. To determine whether the Auto Cal has

been completed, a read status instruction should be issued to

the ADC. Again the data output at that time has no signifi-

cance since the Auto Cal procedure modifies the data in the

output shift register. To retrieve the status information, an ad-

ditional read status instruction should be issued to the ADC.

At this time the status data is available on DO. If the Cal signal

in the status word is low, Auto Cal has been completed.

Therefore, the next instruction issued can start a conversion.

The data output at this time is again status information.

To keep noise from corrupting the conversion, status can not

be read during a conversion. If CS is strobed and is brought

low during a conversion, that conversion is prematurely end-

ed. EOC can be used to determine the end of a conversion

or the ADC controller can keep track in software of when it

would be appropriate to communicate to the ADC again. Once

it has been determined that the ADC has completed a con-

version, another instruction can be transmitted to the ADC.

The data from this conversion can be accessed when the next

instruction is issued to the ADC.

Note, when CS is low continuously it is important to transmit

the exact number of SCLK cycles, as shown in the timing di-

agrams. Not doing so will desynchronize the serial commu-

nication to the ADC. (See Section 1.3 CS Low Continuously

Considerations.)

1.2 Changing Configuration

The configuration of the ADC12130/2/8 on power up defaults

to 12-bit plus sign resolution, 12- or 13-bit MSB First, 10 CCLK

acquisition time, user mode, no Auto Cal, no Auto Zero, and

power up mode. Changing the acquisition time and turning

the sign bit on and off requires an 8-bit instruction to be issued

to the ADC. This instruction will not start a conversion. The

instructions that select a multiplexer address and format the

output data do start a conversion. Figure 8 describes an ex-

ample of changing the configuration of the ADC12130/2/8.

During I/O sequence 1, the instruction at DI configures the

ADC to do a conversion with 12-bit +sign resolution. Notice

that, when the 6 CCLK Acquisition and Data Out without Sign

instructions are issued to the ADC, I/O sequences 2 and 3, a

new conversion is not started. The data output during these

instructions is from conversion N, which was started during

I/O sequence 1. The Configuration Modification timing dia-

gram describes in detail the sequence of events necessary

for a Data Out without Sign, Data Out with Sign, or 6/10/18/34

CCLK Acquisition time mode selection. Table 4 describes the

actual data necessary to be loaded into the ADC to accom-

plish this configuration modification. The next instruction,

shown in Figure 8, issued to the ADC starts conversion N+1

with 16-bit format and 12 bits of resolution formatted MSB

first. Again the data output during this I/O cycle is the data

from conversion N.

The number of SCLKs applied to the ADC during any con-

version I/O sequence should vary in accord with the data out

word format chosen during the previous conversion I/O se-

quence. The various formats and resolutions available are

shown in Table 1. In Figure 8, since 16-bit without sign MSB

first format was chosen during I/O sequence 4, the number of

SCLKs required during I/O sequence 5 is sixteen. In the fol-

lowing I/O sequence the format changes to 12-bit without sign

MSB first; therefore the number of SCLKs required during

I/O sequence 6 changes accordingly to 12.

1.3 CS Low Continuously Considerations

When CS is continuously low, it is important to transmit the

exact number of SCLK pulses that the ADC expects. Not do-

ing so will desynchronize the serial communications to the

ADC. When the supply power is first applied to the ADC, it will

expect to see 13 SCLK pulses for each I/O transmission. The

number of SCLK pulses that the ADC expects to see is the

same as the digital output word length. The digital output word

length is controlled by the Data Out (DO) format. The DO for-

mat maybe changed any time a conversion is started or when

the sign bit is turned on or off. The table below details out the

number of clock periods required for different DO formats:

DO Format

Number of

SCLKs

Expected

12-Bit MSB or LSB First SIGN OFF 12

SIGN ON 13

16-Bit MSB or LSB first SIGN OFF 16

SIGN ON 17

If erroneous SCLK pulses desynchronize the communica-

tions, the simplest way to recover is by cycling the power

supply to the device. Not being able to easily resynchronize

the device is a shortcoming of leaving CS low continuously.

The number of clock pulses required for an I/O exchange may

be different for the case when CS is left low continuously vs.

the case when CS is cycled. Take the I/O sequence detailed

in Figure 7 (Typical Power Supply Sequence) as an example.

The table below lists the number of SCLK pulses required for

each instruction:

Instruction CS Low

Continuously CS Strobed

Auto Cal 13 SCLKs 8 SCLKs

Read Status 13 SCLKs 8 SCLKs

12-Bit + Sign Conv 1 13 SCLKs 8 SCLKs

12-Bit + Sign Conv 2 13 SCLKs 13 SCLKs

1.4 Analog Input Channel Selection

The data input at DI also selects the channel configuration

(see Table 2, Table 3 and Table 4). In Figure 8 the only times

when the channel configuration could be modified would be

during I/O sequences 1, 4, 5 and 6. Input channels are rese-

lected before the start of each new conversion. Shown below

www.national.com 28

ADC12130/ADC12132/ADC12138

is the data bit stream required at DI during I/O sequence

number 4 in Figure 8 to set CH1 as the positive input and CH0

as the negative input for the different ADC versions.

Part

Number

DI Data

DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7

ADC12130

and

ADC12132

L H L L H L X X

ADC12138 L H L L L L H L

Where X can be a logic high (H) or low (L).

1.5 Power Up/Down

The ADC may be powered down by taking the PD pin HIGH

or by the instruction input at DI (see Table 4 and Table 5, and

the Power Up/Down timing diagrams). When the ADC is pow-

ered down in this way, the ADC conversion circuitry is deac-

tivated but the digital I/O circuitry is kept active.

Hardware power up/down is controlled by the state of the PD

pin. Software power-up/down is controlled by the instruction

issued to the ADC. If a software power up instruction is issued

to the ADC while a hardware power down is in effect (PD pin

high) the device will remain in the power-down state. If a soft-

ware power down instruction is issued to the ADC while a

hardware power up is in effect (PD pin low), the device will

power down. When the device is powered down by software,

it may be powered up by either issuing a software power up

instruction or by taking PD pin high and then low. If the power

down command is issued during a conversion, that conver-

sion is interrupted, so the data output after power up cannot

be relied upon.

1207933

FIGURE 8. Changing the ADC's Conversion Configuration

1.6 User Mode and Test Mode

An instruction may be issued to the ADC to put it into test

mode, which is used by the manufacturer to verify complete

functionality of the device. During test mode CH0–CH7 be-

come active outputs. If the device is inadvertently put into the

test mode with CS continuously low, the serial communica-

tions may be desynchronized. Synchronization may be re-

gained by cycling the power supply voltage to the device.

Cycling the power supply voltage will also set the device into

user mode. If CS is used in the serial interface, the ADC may

be queried to see what mode it is in. This is done by issuing

a “read STATUS register” instruction to the ADC. When bit 9

of the status register is high, the ADC is in test mode; when

bit 9 is low the ADC, is in user mode. As an alternative to

cycling the power supply, an instruction sequence may be

used to return the device to user mode. This instruction se-

quence must be issued to the ADC using CS. The following

table lists the instructions required to return the device to user

mode. Note that this entire sequence, including both Test

Mode and User Mode values, should be sent to recover from

the test mode.

Instruction DI Data

DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7

TEST MODE H X X X H H H H

Reset

Test Mode

Instructions

L L L L H H H L

L L L L H L H L

L L L L H L H H

USER MODE L L L L H H H H

Power Up L L L L H L H L

Set DO with or

without Sign

H or

LL L L H H L H

Set Acquisition

Time

H or

LL L H H H L

Start a

Conversion

H or

LLH or

H or

X = Don't Care

The power up, data with or without sign, and acquisition time

instructions should be resent after returning to the user mode.

This is to ensure that the ADC is in the required state before

a conversion is started.

29 www.national.com

ADC12130/ADC12132/ADC12138

1.7 Reading the Data Without Starting a Conversion

The data from a particular conversion may be accessed with-

out starting a new conversion by ensuring that the CONV line

is taken high during the I/O sequence. See the Read Data

timing diagrams. Table 5 describes the operation of the

CONV pin. It is not necessary to read the data as soon as

DOR goes low. The data will remain in the output register if

CS is brought high right after DOR goes high. A single con-

version may be read as many times as desired before CS is

brought low.

1.8 Brown Out Conditions

When the supply voltage dips below about 2.7V, the internal

registers, including the calibration coefficients and all of the

other registers, may lose their contents. When this happens

the ADC will not perform as expected or not at all after power

is fully restored. While writing the desired information to all

registers and performing a calibration might sometimes cause

recovery to full operation, the only sure recovery method is to

reduce the supply voltage to below 0.5V, then reprogram the

ADC and perform a calibration after power is fully restored.

2.0 THE ANALOG MULTIPLEXER

For the ADC12138, the analog input multiplexer can be con-

figured with 4 differential channels or 8 single ended channels

with the COM input as the zero reference or any combination

thereof (see Figure 9). The difference between the voltages

at the VREF+ and VREF− pins determines the input voltage span

(VREF). The analog input voltage range is 0 to VA+. Negative

digital output codes result when VIN− > VIN+. The actual volt-

age at VIN− or VIN+ cannot go below AGND.

4 Differential

Channels

1207934

8 Single-Ended Channels

with COM

as Zero Reference

1207935

FIGURE 9. Input Multiplexer Options

Differential

Configuration

1207936

A/DIN1 and A/DIN2 can be assigned as the + or − input

Single-Ended

Configuration

1207937

A/DIN1 is + input

A/DIN2 is − input

FIGURE 10. MUXOUT connections for multiplexer option

CH0, CH2, CH4, and CH6 can be assigned to the MUXOUT1

pin in the differential configuration, while CH1, CH3, CH5, and

CH7 can be assigned to the MUXOUT2 pin. In the differential

configuration, the analog inputs are paired as follows: CH0

with CH1, CH2 with CH3, CH4 with CH5 and CH6 with CH7.

The A/DIN1 and A/DIN2 pins can be assigned positive or

negative polarity.

With the single-ended multiplexer configuration, CH0 through

CH7 can be assigned to the MUXOUT1 pin. The COM pin is

always assigned to the MUXOUT2 pin. A/DIN1 is assigned as

the positive input; A/DIN2 is assigned as the negative input.

(See Figure 10).

The Multiplexer assignment tables for these ADCs (Table 2

and Table 3) summarize the aforementioned functions for the

different versions of ADCs.

2.1 Biasing for Various Multiplexer Configurations

Figure 11 is an example of device connections for single-

ended operation. The sign bit is always low. The digital output

range is 0 0000 0000 0000 to 0 1111 1111 1111. One LSB is

equal to 1 mV (4.1V/4096 LSBs).

www.national.com 30

ADC12130/ADC12132/ADC12138

1207938

FIGURE 11. Single-Ended Biasing

For pseudo-differential signed operation, the circuit of shows

a signal AC coupled to the ADC. This gives a digital output

range of −4096 to +4095. With a 2.5V reference, 1 LSB is

equal to 610 μV. Although the ADC is not production tested

with a 2.5V reference, when VA+ and VD+ are +5.0V, linearity

error typically will not change more than 0.1 LSB (see the

curves in the Typical Electrical Characteristics Section). With

the ADC set to an acquisition time of 10 clock periods, the

input biasing resistor needs to be 600Ω or less. Notice though

that the input coupling capacitor needs to be made fairly large

to bring down the high pass corner. Increasing the acquisition

time to 34 clock periods (with a 5 MHz CCLK frequency) would

allow the 600Ω to increase to 6k, which would set the high

pass corner at 26 Hz. Increasing R, to 6k would allow R2 to

be 2k with a 1 μF coupling capacitor.

1207939

FIGURE 12. Pseudo-Differential Biasing with the Signal Source AC Coupled Directly into the ADC

An alternative method for biasing pseudo-differential opera-

tion is to use the +2.5V from the LM4040 to bias any amplifier

circuits driving the ADC as shown in Figure 13. The value of

the resistor pull-up biasing the LM4040-2.5 will depend upon

the current required by the op amp biasing circuitry.

In the circuit of Figure 13, some voltage range is lost since the

amplifier will not be able to swing to +5V and GND with a

single +5V supply. Using an adjustable version of the LM4041

to set the full scale voltage at exactly 2.048V and a lower

grade LM4040D-2.5 to bias up everything to 2.5V as shown

in Figure 14 will allow the use of all the ADC's digital output

range of −4096 to +4095 while leaving plenty of head room

for the amplifier.

Fully differential operation is shown in Figure 15. One LSB for

this case is equal to (4.1V/4096) = 1 mV.

31 www.national.com

ADC12130/ADC12132/ADC12138

1207940

FIGURE 13. Alternative Pseudo-Differential Biasing

1207941

FIGURE 14. Pseudo-Differential Biasing without the Loss of Digital Output Range

www.national.com 32

ADC12130/ADC12132/ADC12138

1207942

FIGURE 15. Fully Differential Biasing

3.0 REFERENCE VOLTAGE

The difference in the voltages applied to the VREF+ and

VREF− defines the analog input span (the difference between

the voltage applied between two multiplexer inputs or the

voltage applied to one of the multiplexer inputs and analog

ground) over which 4095 positive and 4096 negative codes

exist. The voltage sources driving VREF+ and VREF− must have

very low output impedance and noise. The circuit in

Figure 16 is an example of a very stable reference appropriate

for use with the device.

1207943

*Tantalum

FIGURE 16. Low Drift Extremely

Stable Reference Circuit

The ADC12130/2/8 can be used in either ratiometric or ab-

solute reference applications. In ratiometric systems, the ana-

log input voltage is proportional to the voltage used for the

ADC's reference voltage. When this voltage is the system

power supply, the VREF+ pin is connected to VA+ and VREF− is

connected to ground. This technique relaxes the system ref-

erence stability requirements because the analog input volt-

age and the ADC reference voltage move together. This

maintains the same output code for given input conditions.

For absolute accuracy, where the analog input voltage varies

between very specific voltage limits, a time and temperature

stable voltage source can be connected to the reference in-

puts. Typically, the reference voltage magnitude will require

an initial adjustment to null reference voltage induced full-

scale errors.

Below are recommended references along with some key

specifications.

Part Number

Output

Voltage

Tolerance

Temperature

Coefficient

LM4041CI-Adj ±0.5% ±100ppm/°C

LM4040AI-4.1 ±0.1% ±100ppm/°C

LM4120AI-4.1 ±0.2% ±50ppm/°C

LM4121AI-4.1 ±0.2% ±50ppm/°C

LM4050AI-4.1 ±0.1% ±50ppm/°C

LM4030AI-4.1 ±0.05% ±10ppm/°C

LM4040AI-4.1 ±0.1% ±3.0ppm/°C

Circuit of Figure 16 Adjustable ±2ppm/°C

The reference voltage inputs are not fully differential. The

ADC12130/2/8 will not generate correct conversions or com-

parisons if VREF+ is taken below VREF−. Correct conversions

result when VREF+ and VREF− differ by 1V or more and remain

at all times between ground and VA+. The VREF common mode

range, (VREF+ + VREF−)/2, is restricted to (0.1 × VA+) to (0.6 ×

VA+). Therefore, with VA+ = 5V, the center of the reference

ladder should not go below 0.5V or above 3.0V. Figure 17 is

a graphic representation of the voltage restrictions on VREF+

and VREF−.

33 www.national.com

ADC12130/ADC12132/ADC12138

1207944

FIGURE 17. VREF Operating Range

4.0 ANALOG INPUT VOLTAGE RANGE

The ADC12130/2/8's fully differential ADC generate a two's

complement output that is found by using the equation shown

below:

for (12-bit) resolution the Output Code =

Round off to the nearest integer value between −4096 to 4095

if the result of the above equation is not a whole number.

Examples are shown in the table below:

VREF+VREF−VIN+VIN−Code Output

Digital

+2.5V +1V +1.5V 0V 0,1111,1111,1111

+4.096V 0V +3V 0V 0,1011,1011,1000

+4.096V 0V +2.499V +2.500V 1,1111,1111,1111

+4.096V 0V 0V +4.096V 1,0000,0000,0000

5.0 INPUT CURRENT

At the start of the acquisition window (tA) a charging current

flows into or out of the analog input pins (A/DIN1 and A/DIN2)

depending upon the input voltage polarity. The analog input

pins are CH0–CH7 and COM when A/DIN1 is tied to

MUXOUT1 and A/DIN2 is tied to MUXOUT2. The peak value

of this input current will depend upon the actual input voltage

applied, the source impedance and the internal multiplexer

switch on resistance. With MUXOUT1 tied to A/DIN1 and

MUXOUT2 tied to A/DIN2 the internal multiplexer switch on

resistance is typically 1.6 kΩ. The A/DIN1 and A/DIN2 mux

on resistance is typically 750Ω.

6.0 INPUT SOURCE RESISTANCE

For low impedance voltage sources (<600Ω), the input charg-

ing current will decay, before the end of the S/H's acquisition

time of 2 μs (10 CCLK periods with fCK = 5 MHz), to a value

that will not introduce any conversion errors. For high source

impedances, the S/H's acquisition time can be increased to

18 or 34 CCLK periods. For less ADC accuracy and/or slower

CCLK frequencies the S/H's acquisition time may be de-

creased to 6 CCLK periods. To determine the number of clock

periods (Nc) required for the acquisition time with a specific

source impedance for the various resolutions the following

equations can be used:

12 Bit + Sign NC = [RS + 2.3] × fCK × 0.824

Where fCK is the conversion clock (CCLK) frequency in MHz

and RS is the external source resistance in kΩ. As an exam-

ple, operating with a resolution of 12 Bits + sign, a 5 MHz clock

frequency and maximum acquisition time of 34 conversion

clock periods the ADC's analog inputs can handle a source

impedance as high as 6 kΩ. The acquisition time may also be

extended to compensate for the settling or response time of

external circuitry connected between the MUXOUT and

A/DIN pins.

An acquisition starts at a falling edge of SCLK and ends at a

rising edge of CCLK (see timing diagrams). If SCLK and

CCLK are asynchronous, one extra CCLK clock period may

be inserted into the programmed acquisition time for synchro-

nization. Therefore, with asynchronous SCLK and CCLK, the

acquisition time will change from conversion to conversion.

7.0 INPUT BYPASS CAPACITANCE

External capacitors (0.01 μF–0.1 μF) can be connected be-

tween the analog input pins, CH0–CH7, and analog ground

to filter any noise caused by inductive pickup associated with

long input leads. These capacitors will not degrade the con-

version accuracy.

8.0 NOISE

The leads to each of the analog multiplexer input pins should

be kept as short as possible. This will minimize input noise

and clock frequency coupling that can cause conversion er-

rors. Input filtering can be used to reduce the effects of the

noise sources.

9.0 POWER SUPPLIES

Noise spikes on the VA+ and VD+ supply lines can cause con-

version errors; the comparator will respond to the noise. The

ADC is especially sensitive to any power supply spikes that

occur during the Auto Zero or linearity correction. The mini-

mum power supply bypassing capacitors recommended are

low inductance tantalum capacitors of 10 μF or greater par-

alleled with 0.1 μF monolithic ceramic capacitors. More or

different bypassing may be necessary depending upon the

overall system requirements. Separate bypass capacitors

should be used for the VA+ and VD+ supplies and placed as

close as possible to these pins.

10.0 GROUNDING

The ADC12130/2/8's performance can be maximized through

proper grounding techniques. These include the use of sep-

arate analog and digital areas of the board with analog and

digital components and traces located only in their respective

areas. Bypass capacitors of 0.01 µF and 0.1 µF surface mount

capacitors and a 10 µF are recommended at each of the pow-

er supply pins for best performance. These capacitors should

be located as close to the bypassed pin as practical, espe-

cially the smaller value capacitors.

11.0 CLOCK SIGNAL LINE ISOLATION

The ADC12130/2/8's performance is optimized by routing the

analog input/output and reference signal conductors as far as

possible from the conductors that carry the clock signals to

the CCLK and SCLK pins. Maintaining a separation of at least

7 to 10 times the height of the clock trace above its reference

plane is recommended.

www.national.com 34

ADC12130/ADC12132/ADC12138

12.0 THE CALIBRATION CYCLE

A calibration cycle needs to be started after the power sup-

plies, reference, and clock have been given enough time to

stabilize after initial turn-on. During the calibration cycle, cor-

rection values are determined for the offset voltage of the

sampled data comparator and any linearity and gain errors.

These values are stored in internal RAM and used during an

analog-to-digital conversion to bring the overall full-scale, off-

set, and linearity errors down to the specified limits. Full-scale

error typically changes ±0.4 LSB over temperature and lin-

earity error changes even less; therefore, it should be neces-

sary to go through the calibration cycle only once after power

up if the Power Supply Voltage and the ambient temperature

do not change significantly (see the curves in the Typical Per-

formance Characteristics).

13.0 THE Auto Zero CYCLE

To correct for any change in the zero (offset) error of the ADC,

the Auto Zero cycle can be used. It may be desirable to do an

Auto Zero cycle whenever the ambient temperature or the

power supply voltage change significantly. (See the curves

titled "Offset or Zero Error Change vs. Ambient Temperature”

and “Offset or Zero Error Change vs. Supply Voltage” in the

Typical Performance Characteristics.)

14.0 DYNAMIC PERFORMANCE

Many applications require the converter to digitize AC signals,

but the standard DC integral and differential nonlinearity

specifications will not accurately predict the converter's per-

formance with AC input signals. The important specifications

for AC applications reflect the converter's ability to digitize AC

signals without significant spectral errors and without adding

noise to the digitized signal. Dynamic characteristics such as

signal-to-noise (S/N), signal-to-noise + distortion ratio or

S/(N + D), effective bits, full power bandwidth, aperture time

and aperture jitter are quantitative measures of the

converter's capability.

An ADC's AC performance can be measured using Fast

Fourier Transform (FFT) methods. A sinusoidal waveform is

applied to the ADC's input, and the transform is then per-

formed on the digitized waveform. S/(N + D) and S/N are

calculated from the resulting FFT data, and a spectral plot

may also be obtained. Typical values for S/N are shown in the

table of Electrical Characteristics, and spectral plots of

S/(N + D) are included in the typical performance curves.

The ADC's noise and distortion levels will change with the

frequency of the input signal, with more distortion and noise

occurring at higher signal frequencies. This can be seen in

the S/(N + D) versus frequency curves. These curves will also

give an indication of the full power bandwidth (the frequency

at which the S/(N + D) or S/N drops 3 dB).

Effective number of bits can also be useful in describing the

ADC's noise and distortion performance. An ideal ADC will

have some amount of quantization noise, determined by its

resolution, and no distortion, which will yield an optimum

S/(N + D) ratio given by the following equation:

S/(N + D) = (6.02 × n + 1.76) dB

where "n" is the ADC's resolution in bits.

The effective bits of an actual ADC can be found by:

n(effective) = ENOB = (S/(N + D) - 1.76) / 6.02

As an example, this device with a differential signed 5V, 1 kHz

sine wave input signal will typically have a S/(N + D) of 77 dB,

which is equivalent to 12.5 effective bits.

15.0 AN RS232 SERIAL INTERFACE

Shown on the following page is a schematic for an RS232

interface to any IBM and compatible PCs. The DTR, RTS, and

CTS RS232 signal lines are buffered via level translators and

connected to the ADC12138's DI, SCLK, and DO pins, re-

spectively. The D flip-flop is used to generate the CS signal.

1207946

Note: VA+, VD+, and VREF+ on the ADC12138 each have 0.01 μF and 0.1 μF chip caps, and 10 μF tantalum caps. All logic devices are bypassed with 0.1 μF caps.

The assignment of the RS232 port is shown below

B7 B6 B5 B4 B3 B2 B1 B0

COM1 Input Address 3FE X X X CTS X X X X

Output Address 3FC X X X 0 X X RTS DTR

35 www.national.com

ADC12130/ADC12132/ADC12138

A sample program, written in Microsoft QuickBasic, is shown

on the next page. The program prompts for data mode select

instruction to be sent to the ADC. This can be found from the

Mode Programming table shown earlier. The data should be

entered in “1”s and “0”s as shown in the table with DI0 first.

Next, the program prompts for the number of SCLK cycles

required for the programmed mode select instruction. For in-

stance, to send all “0”s to the ADC, selects CH0 as the +input,

CH1 as the −input, 12-bit conversion, and 13-bit MSB first

data output format (if the sign bit was not turned off by a pre-

vious instruction). This would require 13 SCLK periods since

the output data format is 13 bits.

The ADC powers up with No Auto Cal, No Auto Zero, 10

CCLK Acquisition Time, 12-bit conversion, data out with sign,

power up, 12- or 13-bit MSB First, and user mode. Auto Cal,

Auto Zero, Power Up and Power Down instructions do not

change these default settings. The following power up se-

quence should be followed:

1. Run the program

2. Prior to responding to the prompt apply the power to the

ADC12138

3. Respond to the program prompts

It is recommended that the first instruction issued to the

ADC12138 be Auto Cal (See Section 1.1 Interface Con-

cepts).

www.national.com 36

ADC12130/ADC12132/ADC12138

Code Listing:

'variables DOL=Data Out word length, DI=Data string for the DI input,

' DO=ADC result string

'SET CS# HIGH

OUT &H3FC, (&H2 OR INP (&H3FC) 'set RTS HIGH

OUT &H3FC, (&HFE AND INP(&H3FC) 'SET DTR LOW

OUT &H3FC, (&HFD AND INP (&H3FC) 'SET RTS LOW

OUT &H3FC, (&HEF AND INP(&H3FC)) 'set B4 low

LINE INPUT “DI data for ADC12138 (see Mode Table on data sheet)”; DI$

INPUT “ADC12138 output word length (12,13,16 or 17)”; DOL

'SET CS# HIGH

OUT &H3FC, (&H2 OR INP (&H3FC) 'set RTS HIGH

OUT &H3FC, (&HFE AND INP(&H3FC) 'SET DTR LOW

OUT &H3FC, (&HFD AND INP (&H3FC) 'SET RTS LOW

'SET CS# LOW

OUT &H3FC, (&H2 OR INP (&H3FC) 'set RTS HIGH

OUT &H3FC, (&H1 OR INP(&H3FC) 'SET DTR HIGH

OUT &H3FC, (&HFD AND INP (&H3FC) 'SET RTS LOW

DO$=“ ” 'reset DO variable

OUT &H3FC, (&H1 OR INP(&H3FC) 'SET DTR HIGH

OUT &H3FC, (&HFD AND INP(&H3FC)) 'SCLK low

FOR N = 1 TO 8

Temp$ = MID$(DI$, N, 1)

IF Temp$=“0” THEN

OUT &H3FC, (&H1 OR INP(&H3FC))

ELSE OUT &H3FC, (&HFE AND INP(&H3FC))

END IF 'out DI

OUT &H3FC, (&H2 OR INP(&H3FC)) 'SCLK high

IF (INP(&H3FE) AND 16) = 16 THEN

DO$ = DO$ + “0”

ELSE

DO$ = DO$ + “1”

END IF 'Input DO

OUT &H3FC, (&H1 OR INP(&H3FC) 'SET DTR HIGH

OUT &H3FC, (&HFD AND INP(&H3FC)) 'SCLK low

NEXT N

IF DOL > 8 THEN

FOR N=9 TO DOL

OUT &H3FC, (&H1 OR INP(&H3FC) 'SET DTR HIGH

OUT &H3FC, (&HFD AND INP(&H3FC)) 'SCLK low

OUT &H3FC, (&H2 OR INP(&H3FC)) 'SCLK high

IF (INP(&H3FE) AND &H1O) = &H1O THEN

DO$ = DO$ + “0”

ELSE

DO$ = DO$ + “1”

END IF

NEXT N

END IF

OUT &H3FC, (&HFA AND INP(&H3FC)) 'SCLK low and DI high

FOR N = 1 TO 500

NEXT N

PRINT DO$

INPUT “Enter “C” to convert else “RETURN” to alter DI data”; s$

IF s$ = “C” OR s$ = “c” THEN

GOTO 20

ELSE

GOTO 10

END IF

END

37 www.national.com

ADC12130/ADC12132/ADC12138

Physical Dimensions inches (millimeters) unless otherwise noted

Order Number ADC12130CIWM

NS Package Number M16B

Order Number ADC12138CIWM

NS Package Number M28B

www.national.com 38

ADC12130/ADC12132/ADC12138

Order Number ADC12132CIMSA

NS Package Number MSA20

Order Number ADC12138CIMSA

NS Package Number MSA28

39 www.national.com

ADC12130/ADC12132/ADC12138

Order Number ADC12130CIN

NS Package Number N16E

Order Number ADC12138CIN

NS Package Number N28B

www.national.com 40

ADC12130/ADC12132/ADC12138

Notes

41 www.national.com

ADC12130/ADC12132/ADC12138

Notes

ADC12130/ADC12132/ADC12138 Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with

MUX and Sample/Hold

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