LT4250L/LT4250H
1
4250lhfa
TYPICAL APPLICATION
DESCRIPTION
Negative 48V
Hot Swap Controller
Voltage Step on Input Supply
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. Hot Swap is a
trademark of Linear Technology Corporation.
FEATURES
APPLICATIONS
n Allows Safe Board Insertion and Removal from a
Live –48V Backplane
n Circuit Breaker Immunity to Voltage Steps and
Current Spikes
n Programmable Inrush and Short-Circuit Current
Limits
n Pin Compatible With LT1640L/LT1640H
n Operates from –18V to –80V
n Programmable Overvoltage Protection
n Programmable Undervoltage Lockout
n Power Good Control Output
n Bell-Core Compatible ON/OFF Threshold
n Central Office Switching
n –48V Distributed Power Systems
n Negative Power Supply Control
The LT
®
4250L/LT4250H are 8-pin, negative 48V Hot Swap™
controllers that allow a board to be safely inserted and
removed from a live backplane. Inrush current is limited
to a programmable value by controlling the gate voltage
of an external N-channel pass transistor. The pass tran-
sistor is turned off if the input voltage is less than the
programmable undervoltage threshold or greater than
the overvoltage threshold. A programmable current limit
protects the system against shorts. After a 500μs timeout
the current limit activates the electronic circuit breaker.
The PWRGD (LT4250L) or PWRGD (LT4250H) signal can
be used to directly enable a power module. The LT4250L
is designed for modules with a low enable input and the
LT4250H for modules with a high enable input.
The LT4250L/LT4250H are available in 8-pin PDIP and
SO packages
VEE
VDD
LT4250L
SENSE
C1†
470nF
25V
C2†
15nF
100V
C3
0.1μF
100V
C4
100μF
100V
Q1
IRF530
R2
10Ω
5%
R3†
1k, 5%
R4†
549k
1%
R6†
10k
1%
R1†
0.02Ω
5%
4
OV
–48V RTN
–48V RTN
(SHORT PIN)
3
2
OV =
71V
*
* DIODES INC. SMAT70A
† THESE COMPONENTS ARE APPLICATION
SPECIFIC AND MUST BE SELECTED BASED
UPON OPERATING CONDITIONS AND DESIRED
PERFORMANCE. SEE APPLICATIONS
INFORMATION.
UV =
38.5V UV
56
8
7
1
GATE DRAIN
PWRGD
4250 TA01a
VOUT+
SENSE+
TRIM
SENSE–
VOUT–
VIN–
ON/OFF
LUCENT
JW050A1-E
VIN+
2
95V
8
7
6
5
1
4
+C5
100μF
16V
+
–48V
INPUT 1
–48V
INPUT 2
UV
RELEASE
AT 43V
R5†
6.49k
1%
0.1μF
10V
VEE AND
DRAIN
20V/DIV
ID(Q1)
5A/DIV
500μs/DIV 4250 TA01b
LT4250L/LT4250H
2
4250lhfa
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (VDD – VEE) ...................... –0.3V to 100V
PWRGD, PWRGD Pins ............................. –0.3V to 100V
SENSE, GATE Pins ..................................... –0.3V to 20V
UV, OV Pins ................................................ –0.3V to 60V
DRAIN Pin ................................................... –2V to 100V
Maximum Junction Temperature........................... 125°C
(Note 1), All Voltages Referred to VEE
1
2
3
4
8
7
6
5
TOP VIEW
VDD
DRAIN
GATE
SENSE
PWRGD
OV
UV
VEE
N8 PACKAGE
8-LEAD PDIP
S8 PACKAGE
8-LEAD PLASTIC SO
TJMAX = 125°C, θJA = 120°C/W (N8)
TJMAX = 125°C, θJA = 150°C/W (S8)
1
2
3
4
8
7
6
5
TOP VIEW
VDD
DRAIN
GATE
SENSE
PWRGD
OV
UV
VEE
N8 PACKAGE
8-LEAD PDIP
S8 PACKAGE
8-LEAD PLASTIC SO
TJMAX = 125°C, θJA = 120°C/W (N8)
TJMAX = 125°C, θJA = 150°C/W (S8)
ORDER INFORMATION
Operating Temperature Range
LT4250LC/LT4250HC ............................... 0°C to 70°C
LT4250LI/LT4250HI .............................. –40°C to 85°C
Storage Temperature Range ................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec) .................. 300°C
LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LT4250LCN8#PBF LT4250LCN8#TRPBF 4250L 8-Lead PDIP 0°C to 70°C
LT4250LCS8#PBF LT4250LCS8#TRPBF 4250L 8-Lead PLASTIC SO 0°C to 70°C
LT4250LIN8#PBF LT4250LIN8#TRPBF 4250LI 8-Lead PDIP –40°C to 85°C
LT4250LIS8#PBF LT4250LIS8#TRPBF 4250LI 8-Lead PLASTIC SO –40°C to 85°C
LT4250HCN8#PBF LT4250HCN8#TRPBF 4250H 8-Lead PDIP 0°C to 70°C
LT4250HCS8#PBF LT4250HCS8#TRPBF 4250H 8-Lead PLASTIC SO 0°C to 70°C
LT4250HIN8#PBF LT4250HIN8#TRPBF 4250HI 8-Lead PDIP –40°C to 85°C
LT4250HIS8#PBF LT4250HIS8#TRPBF 4250HI 8-Lead PLASTIC SO –40°C to 85°C
Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based fi nish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/
LT4250L/LT4250H
3
4250lhfa
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
DC
VDD Supply Voltage Operating Range l18 80 V
IDD Supply Current UV = 3V, OV = VEE, SENSE = VEE l1.6 5 mA
VUVL Undervoltage Lockout 15.4 V
VCL Current Limit Trip Voltage VCL = (VSENSE – VEE)l40 50 60 mV
IPU GATE Pin Pull-Up Current Gate Drive On, VGATE = VEE l–30 –45 –60 μA
IPD GATE Pin Pull-Down Current Gate Drive OFF 24 50 70 mA
ISENSE SENSE Pin Current VSENSE = 50mV –20 μA
ΔVGATE External Gate Drive (VGATE – VEE), 18V ≤ VDD ≤ 80V l10 13.5 18 V
VUVH UV Pin High Threshold Voltage UV Increasing l1.24 1.255 1.27 V
VUVL UV Pin Low Threshold Voltage UV Decreasing l1.105 1.125 1.145 V
VUVHY UV Pin Hysteresis 130 mV
IINUV UV Pin Input Current VUV = VEE l–0.02 –0.5 μA
VOVH OV Pin High Threshold Voltage OV Increasing l1.235 1.255 1.275 V
VOVL OV Pin Low Threshold Voltage OV Decreasing l1.21 1.235 1.255 V
VOVHY OV Pin Hysteresis 20 mV
IINOV OV Pin Input Current VOV = VEE l–0.03 –0.5 μA
VDL DRAIN Low Threshold VDRAIN – VEE, DRAIN Decreasing 1.1 1.6 2.3 V
VGH GATE High Threshold ΔVGATE – VGATE Decreasing 1.3 V
IDRAIN Drain Input Bias Current VDRAIN = 48V l10 80 500 μA
VOL PWRGD Output Low Voltage PWRGD (LT4250L), (VDRAIN – VEE) < VDL
IOUT = 1mA
IOUT = 5mA
l
l
0.48
1.2
0.8
3
V
V
PWRGD Output Low Voltage
(PWRGD – DRAIN)
PWRGD (LT4250H), VDRAIN = 5V
IOUT = 1mA l0.75 1V
IOH Output Leakage PWRGD (LT4250L), VDRAIN = 48V, VPWRGD = 80V
PWRGD (LT4250H), VDRAIN = 0V, VPWRGD = 80V
l
l
0.05
0.05
10
10
μA
μA
AC
tPHLOV OV High to GATE Low Figures 1a, 2 1.7 μs
tPHLUV UV Low to GATE Low Figures 1a, 3 1.5 μs
tPLHOV OV Low to GATE High Figures 1a, 2 5.5 μs
tPLHUV UV High to GATE High Figures 1a, 3 6.5 μs
tPHLSENSE SENSE High to Gate Low Figures 1a, 4a 1 3 μs
tPHLCB Current Limit to GATE Low Figures 1b, 4b 500 μs
tPHLDL DRAIN Low to PWRGD Low
DRAIN Low to (PWRGD – DRAIN) High
(LT4250L) Figures 1a, 5a
(LT4250H) Figures 1a, 5a
1
1
μs
μs
tPHLGH GATE High to PWRGD Low
GATE High to (PWRGD – DRAIN) High
(LT4250L) Figures 1a, 5b
(LT4250H) Figures 1a, 5b
1.5
1.5
μs
μs
The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. (Note 2), VDD = 48V, VEE = 0V unless otherwise noted.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to VEE unless otherwise
specifi ed.
LT4250L/LT4250H
4
4250lhfa
TYPICAL PERFORMANCE CHARACTERISTICS
Gate Voltage vs Temperature
Current Limit Trip Voltage
vs Temperature
Gate Pull-Up Current
vs Temperature
Gate Pull-Down Current
vs Temperature
PWRGD Output Low Voltage
vs Temperature (LT4250L)
PWRGD Output Impedance
vs Temperature (LT4250H)
Supply Current vs Supply Voltage Supply Current vs Temperature Gate Voltage vs Supply Voltage
SUPPLY VOLTAGE (V)
0
SUPPLY CURRENT (mA)
1.3
1.4
1.5
60 100
4250 G01
1.2
1.1
020 40 80
1.6
1.7
1.8 TA = 25°C
TEMPERATURE (°C)
–50 –25
1.0
SUPPLY CURRENT (mA)
1.1
1.2
1.3
1.4
1.6
0255075
4250 G02
100
1.5
VDD = 48V
SUPPLY VOLTAGE (V)
0
6
GATE VOLTAGE (V)
7
9
10
11
40 80 100
15
4250 G03
8
20 60
12
13
14
TA = 25°C
TEMPERATURE (°C)
12.0
GATE VOLTAGE (V)
13.0
14.0
15.0
12.5
13.5
14.5
–25 0 75
4250 G04
100–50 25 50
VDD = 48V
TEMPERATURE (°C)
–50
48
TRIP VOLTAGE (mV)
49
51
52
53
55
250 50
4250 G05
50
54
100
–25 75
TEMPERATURE (°C)
–50
GATE PULL-UP CURRENT (μA)
48
47
46
45
44
43
42
41
40
75
4250 G06
–25 10050250
VGATE = 0V
TEMPERATURE (°C)
–50
GATE PULL-DOWN CURRENT (mA)
49
52
55
75
4250 G07
46
43
40 –25 0 25 50 100
VGATE = 2V
TEMPERATURE (°C)
–50
PWRGD OUTPUT LOW VOLTAGE (V)
0.3
0.4
0.5
75
4250 G08
0.2
0.1
0–25 25
050 100
IOUT = 1mA
TEMPERATURE (°C)
–50
2
OUTPUT IMPEDANCE (kΩ)
3
4
5
6
7
8
–25 2505075
4250 G09
100
VDRAIN – VEE > 2.4V
LT4250L/LT4250H
5
4250lhfa
PIN FUNCTIONS
for this pin is 1.5μs. Add an external capacitor to this pin
for additional filtering.
VEE (Pin 4): Negative Supply Voltage Input. Connect to
the lower potential of the power supply.
SENSE (Pin 5): Circuit Breaker Sense Pin. With a sense
resistor placed in the supply path between VEE and SENSE,
the overcurrent condition will pull down the GATE pin and
regulate the voltage across the resistor to be 50mV. If
the overcurrent condition exists for more than 500μs the
electronic circuit breaker will trip and turnoff the external
MOSFET.
If the current limit value is set to twice the normal operating
current, only 25mV is dropped across the sense resistor
during normal operation. To disable the current limit feature,
VEE and SENSE can be shorted together.
GATE (Pin 6): Gate Drive Output for the External N-channel
MOSFET. The GATE pin will go high when the following
start-up conditions are met: the UV pin is high, the OV pin
is low, (VSENSE – VEE) < 50mV and the VDD pin is greater
than VUVLOH. The GATE pin is pulled high by a 45μA cur-
rent source and pulled low with a 50mA current source.
During current limit the GATE pin is pulled low using a
100mA current source.
DRAIN (Pin 7): Analog Drain Sense Input. Connect this
pin to the drain of the external N-channel MOSFET and
the V– pin of the power module. When the DRAIN pin is
below VDL, the PWRGD/PWRGD pin will latch to indicate
the switch is on.
VDD (Pin 8): Positive Supply Voltage Input. Connect this
pin to the higher potential of the power supply inputs and
the V+ pin of the power module. An undervoltage lockout
circuit disables the chip until the VDD pin is greater than
the 16V VUVLOH threshold.
PWRGD/PWRGD (Pin 1): Power Good Output Pin. This pin
will latch a power good indication when VDRAIN is within
VDL of VEE and VGATE is within VGH of ΔVGATE. This pin
can be connected directly to the enable pin of a power
module.
When the DRAIN pin of the LT4250L is above VEE by more
than VDL or VGATE is more than VGH from ΔVGATE, the
PWRGD pin will be high impedance, allowing the pull-up
current of the module’s enable pin to pull the pin high and
turn the module off. When VDRAIN drops below VDL and
VGATE rises above VGH, the PWRGD pin sinks current to
VEE, pulling the enable pin low and turning on the module.
This condition is latched until the GATE pin is turned off
via the UV, OV, UVLO or the electronic circuit breaker.
When the DRAIN pin of the LT4250H is above VEE by more
than VDL or VGATE is more than VGH from ΔVGATE, the
PWRGD pin will sink current to the DRAIN pin which pulls
the module’s enable pin low, forcing it off. When VDRAIN
drops below VDL and VGATE rises above VGH, the PWRGD
sink current is turned off, allowing the module’s pull-up
current to pull the enable pin high and turn on the module.
This condition is latched until the GATE pin is turned off
via the UV, OV, UVLO or the electronic circuit breaker.
OV (Pin 2): Analog Overvoltage Input. When OV is pulled
above the 1.255V threshold, an overvoltage condition is
detected and the GATE pin will be immediately pulled low.
The GATE pin will remain low until OV drops below the
1.235V threshold.
UV (Pin 3): Analog Undervoltage Input. When UV is pulled
below the 1.125V threshold, an undervoltage condition
is detected and the GATE pin will be immediately pulled
low. The GATE pin will remain low until UV rises above
the 1.255 threshold.
The UV pin is also used to reset the electronic circuit
breaker. If the UV pin is cycled low and high following the
trip of the circuit breaker, the circuit breaker is reset and a
normal power-up sequence will occur. The response time
LT4250L/LT4250H
6
4250lhfa
BLOCK DIAGRAM
–
+
–
+
+
–
+
–
DRAIN
4250 BD
GATE
SENSEVEE
VEE
VDL
OUTPUT
DRIVE PWRGD/PWRGD
50mV
VCC
VDD
REF
REF
UV
OV
LOGIC
VCC AND
REFERENCE
GENERATOR
–
+
–
+
–
+
+
–
ΔVGATE
VGH
500μs
DELAY
GATE
DRIVER
UVLO
LT4250L/LT4250H
7
4250lhfa
TEST CIRCUIT
TIMING DIAGRAM
PWRGD/PWRGD VDD
V+
5V
OV
VDRAIN
48V
R
5k
DRAIN
LT4250L/LT4250H
UV GATE
VEE SENSE
VSENSE
4250 F01a
VUV
VOV
+
–
PWRGD/PWRGD VDD
OV 48V
20V
DRAIN
LT4250L/LT4250H
UV GATE
VEE SENSE
4250 F01b
VUV 0.1μF
+
–
+
–
10k
10Ω
10Ω
IRF530
Figure 1a. Test Circuit 1 Figure 1b. Test Circuit 2
2V
1V 4250 F02
tPHLOV
1.255V
0V
OV
GATE 1V
1.235V
tPLHOV
2V
1V 4250 F03
tPHLUV
1.125V
0V
UV
GATE 1V
1.255V
tPLHUV
1V
4250 F04a
tPHLSENSE
60mV
SENSE
GATE
100mV
VEE
1V
4250 F04b
tPHLCB
UV
GATE 1V
4250 F05a
VPWRGD – VDRAIN = 0V
DRAIN
PWRGD 1V
1.4V
VEE
DRAIN
PWRGD
1V
1.4V
tPHLDL
tPHLDL
VEE
VEE
4250 F05b
VPWRGD – VDRAIN = 0
GATE
PWRGD
1V
1.4V
1.4V
VEE
GATE
PWRGD
1V
tPHLGH
tPHLGH
ΔVGATE – VGATE = 0
ΔVGATE – VGATE = 0
Figure 2. OV to GATE Timing Figure 3. UV to GATE Timing
Figure 4a. SENSE to GATE Timing Figure 4b. Active Current Limit Timeout
Figure 5a. DRAIN to PWRGD/PWRGD Timing Figure 5b. GATE to PWRGD/PWRGD Timing
LT4250L/LT4250H
8
4250lhfa
APPLICATIONS INFORMATION
Figure 6a. Inrush Control Circuitry
Figure 6b. Inrush Control Waveforms
Hot Circuit Insertion
When circuit boards are inserted into a live –48V back-
plane, the bypass capacitors at the input of the board’s
power module or switching power supply can draw huge
transient currents as they charge up. The transient currents
can cause permanent damage to the board’s components
and cause glitches on the system power supply.
The LT4250 is designed to turn on a board’s supply volt-
age in a controlled manner, allowing the board to be safely
inserted or removed from a live backplane. The chip also
provides undervoltage, overvoltage and overcurrent pro-
tection while keeping the power module off until its input
voltage is stable and within tolerance.
Power Supply Ramping
The input to the power module on a board is controlled by
placing an external N-channel pass transistor (Q1) in the
power path (Figure 6a). R1 provides current fault detection
and R2 prevents high frequency oscillations. Resistors R4,
R5 and R6 provide undervoltage and over-voltage sensing.
By ramping the gate of Q1 up at a slow rate, the inrush
current charging load capacitors C3 and C4 can be limited
to a safe value when the board makes connection.
Resistor R3 and capacitor C2 act as a feedback network
to accurately control the inrush current. The C2 capacitor
can be calculated with the following equation:
C2 = (45μA • CL)/IINRUSH
where CL is the total load capacitance = C3 + C4 + module
input capacitance.
Capacitor C1 and resistor R3 prevent Q1 from momentarily
turning on when the power pins first make contact. Without
C1 and R3, capacitor C2 would pull the gate of Q1 up to
a voltage roughly equal to VEE • C2/CGS(Q1) before the
LT4250 could power up and actively pull the gate low. By
placing capacitor C1 in parallel with the gate capacitance
of Q1 and isolating them from C2 using resistor R3 the
problem is solved. The value of C1 is given by:
C1=VINMAX VTH
VTH
•C2+CGD
()
C1 ≅ 35 • C2 for VINMAX = 72V
where VTH is the MOSFET’s minimum gate threshold and
VINMAX is the maximum operating input voltage.
R3 should not exceed a value that produces an R3 • C2
time-constant of 150μs. A 1k value for R3 will ensure this
for C2 values up to 150nF.
The waveforms are shown in Figure 6b. When the power
pins make contact, they bounce several times. While the
contacts are bouncing, the LT4250 senses an undervoltage
condition and the GATE is immediately pulled low when
the power pins are disconnected.
Once the power pins stop bouncing, the GATE pin starts
to ramp up. When Q1 turns on, the GATE voltage is held
constant by the feedback network of R3 and C2. When the
+
VEE
VDD
LT4250H PWRGD
UV = 38.5V
OV = 71V
SENSE
C1
470nF
25V
C3
0.1μF
100V
C4
100μF
100V C5
100μF
16V
Q1
IRF530
R2
10Ω
5%
R3
1k, 5%
C2
15nF
100V
R4
549k
1%
R5
6.49k
1%
R6
10k
1%
R1
0.02Ω
5%
4
3
2OV
–48V RTN
–48V RTN
(SHORT PIN)
–48V
UV
56
8
7
1
GATE DRAIN
VICOR
VI-J30-CY
VOUT+
VOUT–
VIN+5V
4250 F06a
GATE IN
VIN–
+
*
* DIODES INC. SMAT70A
43
21
INRUSH
CURRENT
500mA/DIV
GATE –VEE
10V/DIV
DRAIN
50V/DIV
VEE
50V/DIV
25ms/DIV
4250 F06b
CONTACT
BOUNCE
MODULE
TURN-ON
MODULE
TURN-ON
CONTACT
BOUNCE
LT4250L/LT4250H
9
4250lhfa
DRAIN voltage has finished ramping, the GATE pin then
ramps to its final value.
Current Limit/Electronic Circuit Breaker
The LT4250 features a current limit function that protects
against short circuits or excessive supply currents. If the
current limit is active for more than 500μs the electronic
circuit breaker will trip. By placing a sense resistor between
the VEE and SENSE pin, the current limit will be activated
whenever the voltage across the sense resistor is greater
than 50mV.
Note that the current limit threshold should be set suffi-
ciently high to account for the sum of the load current
and the inrush current. The maximum value of the inrush
current is given by:
IINRUSH 0.8 • 40mV
RSENSE
–I
LOAD,
where the 0.8 factor is used as a worst case margin com-
bined with the minimum trip voltage (40mV).
In the case of a short circuit, the current limit circuitry
activates and immediately pulls the GATE low, servos the
SENSE voltage to 50mV, and starts a 500μs timer. The
MOSFET current is limited to 50mV/RSENSE (see Figure 7).
If the short circuit persists for more than 500μs, the circuit
breaker trips and pulls the GATE pin low, shutting off the
MOSFET. The circuit breaker is reset by pulling UV low,
or by cycling power to the part. If the short circuit clears
before the 500μs timing interval the current limit will
deactivate and release the GATE.
APPLICATIONS INFORMATION
Figure 7. Short-Circuit Protection Waveforms
DRAIN
50V/DIV
GATE
10V/DIV
ID (Q1)
5A/DIV
1ms/DIV
The LT4250 guards against voltage steps on the input
supply. A positive voltage step (increasing in magnitude)
on the input supply causes an inrush current that is
proportional to the voltage slew rate I = CL • ΔV/ΔT. If the
inrush exceeds 50mV/RSENSE, the current limit will activate
as shown in Figure 8. The GATE pin pulls low, limiting the
current to 50mV/RSENSE. At this level the MOSFET drain
will not follow the source as the input voltage rapidly
changes, but instead remains at the voltage stored on the
load capacitance. The load capacitance begins to charge
at a current of 50mV/RSENSE, but not for long. As the load
capacitance charges, C2 pushes back on the gate and limits
the MOSFET current in a manner identical to the initial start-
up condition which is less than the short circuit limiting
value of 50mV/RSENSE. Thus the circuit breaker does not
trip. To ensure correct operation under input voltage step
conditions, RSENSE must be chosen to provide a current
limit value greater than the sum of the load current and
the dynamic current in the load capacitance.
For C2 values less than 10nF a positive voltage step
increasing in magnitude on the input supply can result
in the Q1 turning off momentarily due to current limit
overshoot which can shut down the output. By adding an
additional resistor and diode, Q1 remains on during the
voltage step. This is shown as D1 and R7 in Figure 9. The
purpose of D1 is to shunt current around R7 when the
power pins first make contact and allow C1 to hold the
GATE low. The value of R7 should be sized to generate an
R7 • C1 time constant of 33μs.
Under some conditions, a short circuit at the output can
cause the input supply to dip below the UV threshold. The
LT4250 turns off once and then turns on until the electronic
circuit breaker is tripped. This can be minimized by adding
a deglitching delay to the UV pin with a capacitor from UV
to VEE. This capacitor forms an RC time constant with the
resistors at UV, allowing the input supply to recover before
the UV pin resets the circuit breaker.
LT4250L/LT4250H
10
4250lhfa
Figure 8. Voltage Step on Input Supply Waveforms
APPLICATIONS INFORMATION
Figure 9. Circuit for Input Steps with Small C2 (<10nF)
Figure 10. Automatic Restart After Current Fault
VEE AND
DRAIN
20V/DIV
ID(Q1)
5A/DIV
500μs/DIV 4250 08
VEE
VDD
LT4250H PWRGD
SENSE
C1
150nF
25V
C3
0.1μF
100V
C4
22μF
100V
Q1
IRF530
R2
10Ω
5%
R3
1k
5%
C2
3.3nF
100V
R4
549k
1%
R5
6.49k
1%
R6
10k
1%
R1
0.02Ω
5%
4
3
2
–48V RTN
–48V
OV
UV
56
8
1
GATE DRAIN
4250 F09
+
7
–48V RTN
(SHORT PIN)
*
* DIODES INC. SMAT70A
R7
220Ω
5%
43
21
D1
BAT85
VEE
VDD
LT4250L PWRGD
SENSE
C1
470nF
25V
C4
1μF
100V C3
100μF
100V
Q1
IRF530
R2
10Ω
5%
R8
510k
5%
R3
1k, 5%
C2
15nF
100V
R4
549k
1%
R7
1M
5%
R5
16.5k
1%
R9
10k
1%
R6
549k
1%
Q3
ZVN3310
Q2
2N2222
D1
1N4148
R1
0.02Ω
5%
4
3
2OV
–48V
UV
56
8
7
1
GATE DRAIN
4250 F10a
3
2
+
–48V RTN
–48V RTN
(SHORT PIN)
*
* DIODES INC. SMAT70A
43
21
NODE 2
50V/DIV
GATE
2V/DIV
1s/DIV 4250 F10
A circuit that automatically resets the circuit breaker after
a current fault is shown in Figure 10. Transistors Q2 and
Q3 along with R7, R8, C4 and D1 form a programmable
one-shot circuit. Before a short occurs, the GATE pin is
pulled high and Q3 is turned on, pulling node 2 to VEE.
Resistor R8 turns off Q2. When a short occurs, the GATE
pin is pulled low and Q3 turns off. Node 2 starts to charge
C4 and Q2 turns on, pulling the UV pin low and resetting
the circuit breaker. As soon as C4 is fully charged, R8 turns
off Q2, UV goes high and the GATE starts to ramp up. Q3
turns back on and quickly pulls node 2 back to VEE. Diode
D1 clamps node 3 one diode drop below VEE. The duty
cycle is set to 10% to prevent Q1 from overheating.
LT4250L/LT4250H
11
4250lhfa
APPLICATIONS INFORMATION
Undervoltage and Overvoltage Detection
The UV (Pin 3) and OV (Pin 2) pins can be used to detect
undervoltage and overvoltage conditions at the power sup-
ply input. The UV and OV pins are internally connected to
analog comparators with 130mV and 20mV of hysteresis
respectively. When the UV pin falls below its threshold or
the OV pin rises above its threshold, the GATE pin is im-
mediately pulled low. The GATE pin will be held low until
UV is high and OV is low.
The undervoltage and overvoltage trip voltages can be
programmed using a three resistor divider as shown in
Figure 11. With R4 = 549k, R5 = 6.49k and R6 = 10K, the
undervoltage threshold is set to 38.5V (with a 43V release
from undervoltage) and the overvoltage threshold is set
to 71V. The resistor divider will also gain up the hysteresis
at the UV pin and OV pin to 4.5V and 1.2V at the input
respectively.
PWRGD/PWRGD Output
The PWRGD/PWRGD output can be used to directly enable
a power module when the input voltage to the module is
within tolerance. The LT4250L has a PWRGD output for
modules with an active low enable input, and the LT4250H
has a PWRGD output for modules with an active high
enable input.
When the DRAIN voltage of the LT4250H is high with
respect to VEE (Figure 12) or the GATE voltage is low, the
internal transistor Q3 is turned off and I1 and Q2 clamp
the PWRGD pin one SAT drop (≈0.3V) above the DRAIN
pin.Transistor Q2 sinks the module’s pull-up current and
the module turns off.
When the DRAIN voltage drops below VDL and the GATE
voltage is high, Q3 will turn on, shorting the bottom of
I1 to DRAIN and turning Q2 off. The pull-up current in
the module pulls the PWRGD pin high and enables the
module.
When the DRAIN voltage of the LT4250L is high with
respect to VEE or the GATE voltage is low, the internal
pull-down transistor Q2 is off and the PWRGD pin is in a
high impedance state (Figure 13). The PWRGD pin will be
pulled high by the module’s internal pull-up current source,
turning the module off. When the DRAIN voltage drops
below VDL and the GATE voltage is high, Q2 will turn on
and the PWRGD pin will pull low, enabling the module.
The PWRGD signal can also be used to turn on an LED
oroptoisolator to indicate that the power is good as shown
in Figure 14.
Gate Pin Voltage Regulation
When the supply voltage to the chip is more than 18V,
the GATE pin voltage is regulated at 13.5V above VEE.
The gate voltage will be no greater than 18V for supply
voltages up to 80V.
VEE
VDD
LT4250L/LT4250H
R4
R5
R6
4
4250 F11
OV
–48V RTN
3
2
–48V
UV
8
VUV = 1.255 R4 + R5+ R6
R5 + R6
()
VOV = 1.255 R4 + R5+ R6
R6
()
–48V RTN
(SHORT PIN)
+
VEE
VDD
LT4250H
SENSE
C1
C3
Q1
R2 R3 C2
R4
R5
R6
R1
4
3
2OV
–48V RTN
–48V
UV
56
8
1
7
GATE
4250 F12
PWRGD
DRAIN
VEE
Q3
ACTIVE HIGH
ENABLE MODULE
VOUT+
VOUT–
VIN+
VIN–
ON/OFF
–48V RTN
(SHORT PIN)
*
* DIODES INC. SMAT70A
43
21
Q2
VDL
VGH
+
–
+
–
+
–
+
–
GATE
ΔVGATE
I1
Figure 11. Undervoltage and Overvoltage Sensing
Figure 12. Active High Enable Module
LT4250L/LT4250H
12
4250lhfa
APPLICATIONS INFORMATION
Figure 13. Active Low Enable Module
Figure 14. Using PWRGD to Drive an Optoisolator
VEE
LT4250L
SENSE
OV
UV
VDL
VGH
+
–
+
–
+
–
+
–
GATE
ΔVGATE
+
VDD
C1
C3
Q1
R2 R3 C2
R4
R5
R6
R1
4
3
2
–48V RTN
–48V
56
8
1
7
GATE
4250 F13
PWRGD
DRAIN
VEE
ACTIVE LOW
ENABLE MODULE
VOUT+
VOUT–
VIN+
VIN–
ON/OFF
–48V RTN
(SHORT PIN)
*
* DIODES INC. SMAT70A
43
21
Q2
VEE
VDD
LT4250L PWRGD
SENSE
C1
470nF
25V
C3
100μF
100V
Q1
IRF530
R2
10Ω
5%
R7
51k
5%
R3
1k, 5%
C2
15nF
100V
R4
549k
1%
R5
6.49k
1%
R6
10k
1%
R1
0.02Ω
5%
4
3
2OV
–48V RTN
–48V
UV
56
8
7
1MOC207
GATE DRAIN
4250 F14
PWRGD
+
–48V RTN
(SHORT PIN)
*
* DIODES INC. SMAT70A
43
21
LT4250L/LT4250H
13
4250lhfa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
PACKAGE DESCRIPTION
N8 Package
8-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510)
N8 1002
.065
(1.651)
TYP
.045 – .065
(1.143 – 1.651)
.130 ± .005
(3.302 ± 0.127)
.020
(0.508)
MIN
.018 ± .003
(0.457 ± 0.076)
.120
(3.048)
MIN 12 34
87 65
.255 ± .015*
(6.477 ± 0.381)
.400*
(10.160)
MAX
.008 – .015
(0.203 – 0.381)
.300 – .325
(7.620 – 8.255)
.325 +.035
–.015
+0.889
–0.381
8.255
()
NOTE:
1. DIMENSIONS ARE INCHES
MILLIMETERS
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)
.100
(2.54)
BSC
.016 – .050
(0.406 – 1.270)
.010 – .020
(0.254 – 0.508)× 45°
0°– 8° TYP
.008 – .010
(0.203 – 0.254)
SO8 0303
.053 – .069
(1.346 – 1.752)
.014 – .019
(0.355 – 0.483)
TYP
.004 – .010
(0.101 – 0.254)
.050
(1.270)
BSC
1234
.150 – .157
(3.810 – 3.988)
NOTE 3
8765
.189 – .197
(4.801 – 5.004)
NOTE 3
.228 – .244
(5.791 – 6.197)
.245
MIN .160 ±.005
RECOMMENDED SOLDER PAD LAYOUT
.045 ±.005
.050 BSC
.030 ±.005
TYP
INCHES
(MILLIMETERS)
NOTE:
1. DIMENSIONS IN
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
LT4250L/LT4250H
14
4250lhfa
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2001
LT 0309 REV A • PRINTED IN USA
RELATED PARTS
TYPICAL APPLICATION
PART NUMBER DESCRIPTION COMMENTS
LT C
®
1421 Dual Hot Swap Controller with Additional –12V Control Operates from 3V to 12V
LTC1422 Hot Swap Controller in SO-8 System Reset Output With Programmable Delay
LT1640AH/LT1640AL –48V Hot Swap Controller in SO-8 LT4250 is a Pin-Compatible Upgrade to LT1640
LT1641-1/LT1641-2 48V Hot Swap Controller in SO-8 Foldback Current Limit, 9V to 80V, Auto-Retry/Latch-Off
LTC1642 Fault Protected Hot Swap Controller Operates Up to 16.5V, Protected to 33V
LTC1643 PCI Hot Swap Controller 3.3V, 5V, 12V, –12V Supplies for PCI Bus
LTC1645 Dual Hot Swap Controller Operates from 1.2V to 12V, Power Sequencing
LTC1646 Dual CompactPCI Hot Swap Controller 3.3V, 5V Supplies With Precharge and Local PCI Reset Logic
LTC1647 Dual Hot Swap Controller Dual ON Pins for Supplies from 3V to 15V
LTC4211 Hot Swap Controller With Multifunction Current
Control
2.5V to 16.5V Supplies, Active Inrush Current Limiting
LTC4251 –48 Hot Swap Controller in SOT-23 Active Current Limiting, Fast Comparator for Catastrophic Faults
LTC4252 –48 Hot Swap Controller in MSOP Active Current Limiting, Fast Comparator for Catastrophic Faults, Separate
UV/0V Pins, Power-Good Output
Figure 15. Typical Application Using a Filter Module
+
VEE
VDD
LT4250L
PWRGD
SENSE
C1
470nF
25V
C2
15nF
100V
C3
0.1μF
100V
C4
0.1μF
100V
C6
0.1μF
100V
C5
100μF
100V
C7
100μF
16V
Q1
IRF530
R2
10Ω
5%
R3
1k
5%
R4
549k
1%
R5
6.49k
1%
R6
10k
1%
R1
0.02Ω
5%
4
OV
–48V RTN
3
2
–48V
UV
5
6
8
7
1
GATE
DRAIN
LUCENT
JW050A1-E
VOUT+
SENSE+
TRIM
SENSE–
VOUT–
VIN+95V
4250 F15
8
7
6
5
3
1
2
4
ON/OFF
CASE
VIN–
VOUT+
VOUT–
VIN+
CASE
VIN–
+
LUCENT
FLTR100V10
–48V RTN
(SHORT PIN)
*
* DIODES INC. SMAT70A
43
21
MOC207
R7
51k
5%
1N4003
Using an EMI Filter Module
Many applications place an EMI filter module in the
powerpath to prevent switching noise of the module
from being injected back onto the power supply. A typical
application using the Lucent FLTR100V10 filter module is
shown in Figure 15. When using a filter, an optoisolator
is required to prevent common mode transients from
destroying the PWRGD and ON/OFF pins.
