BQ24038RHLT - Texas Instruments - Datasheet.Directory

USB BAT

OUT

bq2403x

PACK+

PACK−

System

VDC

GND

VBUS

GND

D+

D −

USB Port

AC Adapter

Q2Q3

UDG−04082

40 mΩ

(2)

bq24030, bq24031

bq24032A, bq24035, bq24038

www.ti.com

............................................................................................................................................... SLUS618H –AUGUST 2004–REVISED OCTOBER 2009

SINGLE-CHIP CHARGE AND SYSTEM POWER-PATH MANAGEMENT IC (bqTINY™)

Check for Samples: bq24030, bq24031 bq24032A, bq24035, bq24038

1FEATURES APPLICATIONS

• Smart Phones and PDA

2• Small 3,5 mm × 4,5 mm QFN Package • MP3 Players

• Designed for Single-Cell Li-Ion- or • Digital Cameras Handheld Devices

Li-Polymer-Based Portable Applications • Internet Appliances

• Integrated Dynamic Power-Path Management

(DPPM) Feature Allowing the AC Adapter or DESCRIPTION

the USB Port to Simultaneously Power the

System and Charge the Battery The bqTINY™ III-series of devices are highly

• Power Supplement Mode Allows Battery to integrated Li-ion linear chargers and system

power-path management devices targeted at

Supplement the USB or AC Input Current space-limited portable applications. The bqTINY

• Autonomous Power Source Selection (AC III-series offer integrated USB-port and DC supply

Adapter or USB) (AC adapter), power-path management with

• Integrated USB Charge Control With autonomous power-source selection, power FETs

Selectable 100-mA and 500-mA Maximum and current sensors, high accuracy current and

Input Current Regulation Limits voltage regulation, charge status, and charge

termination, in a single monolithic device.

• Dynamic Total Current Management

for USB The bqTINY III-series powers the system while

independently charging the battery. This feature

• Supports Up to 2-A Total Current reduces the charge and discharge cycles on the

• 3.3-V Integrated LDO Output battery, allows for proper charge termination and

• Thermal Regulation for Charge Control allows the system to run with an absent or defective

battery pack. This feature also allows for the system

• Charge Status Outputs for LED or System to instantaneously turn on from an external power

Interface Indicates Charge and Fault source in the case of a deeply discharged battery

Conditions pack. The IC design is focused on supplying

• Reverse Current, Short-Circuit, and Thermal continuous power to the system when available from

Protection the AC, USB, or battery sources.

• Power Good (AC Adapter and USB Port

Present) Status Outputs

• Charge Voltage Options: 4.1V, 4.2V, or 4.36V

POWER FLOW DIAGRAM

(1) See Figure 2 and functional block diagram for more detailed feature information.

(2) P-FET back gate body diodes are disconnected to prevent body diode conduction.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2bqTINY is a trademark of Texas Instruments.

PRODUCTION DATA information current as of publication date.

Products conform to specifications per the terms of Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

bq24030, bq24031

bq24032A, bq24035, bq24038

SLUS618H –AUGUST 2004–REVISED OCTOBER 2009...............................................................................................................................................

www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

DESCRIPTION (CONTINUED)

The power select pin, PSEL, defines which input source is to be used first (primary source – AC or USB). If the

primary source is not available, then the IC automatically switches over to the other secondary source if available

or the battery as the last option. If the PSEL is set low, the USB input is selected first and if not available, the AC

line is selected (if available) but programmed to a USB input limiting rate (100 mA/500 mA max). This feature

allows the use of one input connector, where the host programs the PSEL pin according to what source is

connected (AC adaptor or USB port).

The bq24038 replaces USBPG with pin VBSEL, to enable user selection of the charge voltage. In addition, pin

ACPG was modified to PG. PG is active low when either ac power or USB power is detected.

The ISET1 pin programs the battery's fast charge constant current level with a resistor. During normal AC

operation, the input supply provides power to both the OUT (System) and BAT pins. For peak or excessive loads

(typically when operating from the USB power, PSEL = Low) that would cause the input source to enter current

limit (or Q3 - USB FET limiting current) and its source and system voltage (OUT pin) to drop, the dynamic

power-path management (DPPM) feature reduces the charging current attempting to prevent any further drop in

system voltage. This feature allows the selection of a lower current rated adaptor based on the average load

(ISYS-AVG + IBAT-PGM ) rather than a high peak transient load.

ORDERING INFORMATION(1)

BATTERY OUT PIN FOR AC PART PACKAGE

TAVOLTAGE (V) INPUT CONDITIONS (2) NUMBER (3) (4) MARKING

4.2 Regulated to 6 V(5) bq24030RHLR ANB

4.2 Regulated to 6 V(5) bq24030RHLT ANB

4.1 Regulated to 6 V(5) bq24031RHLR BZJ

4.1 Regulated to 6 V(5) bq24031RHLT BZJ

4.2 Regulated to 4.4 V(5) bq24032ARHLR BPE

–40°C to 125°C 4.2 Regulated to 4.4 V(5) bq24032ARHLT BPE

4.2 Cutoff for AC overvoltage(6) bq24035RHLR ANA

4.2 Cutoff for AC overvoltage(6) bq24035RHLT ANA

4.2/4.36 Selectable Regulated to 4.4 V bq24038RHLR BOW

4.2/4.36 Selectable Regulated to 4.4 V bq24038RHLT BOW

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

Web site at www.ti.com.

(2) When power is applied via the USB pin (PSEL=low), the input voltage is switched straight through to the OUT pin, unless the USB input

current limit is active, and then the OUT pin voltage will typically drop to the DPPM-OUT threshold or Battery voltage (which ever is

higher).

(3) The RHL package is available in the following options:

R - taped and reeled in quantities of 3,000 devices per reel.

T - taped and reeled in quantities of 250 devices per reel.

(4) This product is RoHS compatible, including a lead concentration that does not exceed 0.1% of total product weight, and is suitable for

use in specified lead-free soldering processes. In addition, this product uses package materials that do not contain halogens, including

bromine (Br) or antimony (Sb) above 0.1% of total product weight.

(5) If AC < VO(OUT-REG), the AC is connected to the OUT pin by a P-FET, (Q1).

(6) If AC > V(CUT-OFF) the P-FET disconnects the OUT pin from the AC.

Product Folder Link(s): bq24030, bq24031 bq24032A, bq24035, bq24038

bq24030, bq24031

bq24032A, bq24035, bq24038

www.ti.com

............................................................................................................................................... SLUS618H –AUGUST 2004–REVISED OCTOBER 2009

ABSOLUTE MAXIMUM RATINGS(1)

over operating free-air temperature range (unless otherwise noted) bq24030, bq24031, bq24032A,

bq24035, bq24038

AC (DC voltage wrt (with respect to) VSS) –0.3 V to 18 V

Input voltage USB (DC voltage wrt VSS) –0.3 V to 7 V

BAT, CE, DPPM, ACPG, PSEL, OUT, ISET1, ISET2, STAT1, –0.3 V to 7 V

STAT2, TS, USBPG , PG, VBSEL (all DC voltages wrt VSS)

Input voltage LDO (DC voltage wrt VSS) –0.3 V to VO(OUT) + 0.3 V

TMR –0.3 V to VO(LDO) + 0.3 V

AC 3.5 A

Input current USB 1000 mA

OUT 4 A

Output current BAT(2) –4 A to 3.5 A

Output source current (in LDO 30 mA

regulation at 3.3 V LDO)

Output sink current ACPG, STAT1, STAT2, USBPG, PG 15 mA

Storage temperature range, Tstg –65°C to 150°C

Junction temperature range, TJ–40°C to 150°C

Lead temperature (soldering, 10 seconds) 300°C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage

values are with respect to the network ground terminal unless otherwise noted.

(2) Negative current is defined as current flowing into the BAT pin.

RECOMMENDED OPERATING CONDITIONS MIN MAX UNIT

bq24030/31/32A/35, bq24038 (at VBSEL = LOW) 4.35 16

Supply voltage (from AC input)

VCC (1) (2) bq24038 (at VBSEL = HIGH) 4.55 16 V

VCC Supply voltage (from USB input) (1) 4.35 6

IAC Input current, AC 2 A

IUSB Input current, USB 0.5

TJOperating junction temperature range –40 125 °C

(1) VCC is defined as the greater of AC or USB input.

(2) Verify that power dissipation and junction temperatures are within limits at maximum VCC .

DISSIPATION RATINGS TA≤40°C DERATING FACTOR

PACKAGE θJA

POWER RATING TA> 40°C

20-pin RHL(1) 1.81 W 21 mW/°C 46.87 °C/W

(1) This data is based on using the JEDEC High-K board and the exposed die pad is connected to a Cu pad on the board. This is

connected to the ground plane by a 2×3 via matrix.

Product Folder Link(s): bq24030, bq24031 bq24032A, bq24035, bq24038

bq24030, bq24031

bq24032A, bq24035, bq24038

SLUS618H –AUGUST 2004–REVISED OCTOBER 2009...............................................................................................................................................

www.ti.com

ELECTRICAL CHARACTERISTICS

over junction temperature range (0°C ≤TJ≤125°C) and the recommended supply voltage range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

INPUT BIAS CURRENTS

ICC(SPLY) Active supply current, VCC VVCC > VVCC(min) 1 2 mA

V(AC) < V(BAT), V(USB) < V(BAT),

ICC(SLP) Sleep current (current into BAT pin) 2.6 V ≤VI(BAT) ≤VO(BAT-REG), 2 5

Excludes load on OUT pin

VI(AC) ≤6 V, Total current into AC pin with chip disabled,

ICC(AS-STDBY) AC standby current 200

Excludes all loads, CE=LOW, after t(CE-HOLDOFF) delay

ICC(USB- Total current into USB pin with chip disabled, Excludes all μA

USB standby current 200

STDBY) loads, CE=LOW, after t(CE-HOLDOFF) delay

Total current into BAT pin with AC and/or USB present

ICC(BAT- BAT standby current and chip disabled; Excludes all loads (OUT and LDO), 45 60

STDBY) CE=LOW, after t(CE-HOLDOFF) delay, 0°C ≤TJ≤85°C(1)

IIB(BAT) Charge done current, BAT Charge DONE, AC or USB supplying the load 1 5

HIGH AC CUTOFF MODE

VI(AC) > 6.8 V, AC FET (Q1) turns off, USB FET (Q3) turns

VCUT-OFF Input ac cutoff voltage, bq24035 on if USB power present, otherwise BAT FET (Q2) turns 6.1 6.4 6.8 V

on.

LDO OUTPUT

Active only if AC or USB is present,

VO(LDO) Output regulation voltage 3.3 V

VI(OUT) ≥VO(LDO) + (IO(LDO) × RDS(on))

Regulation accuracy(2) –5% 5%

IO(LDO) Output current 20 mA

RDS(on) On resistance OUT to LDO 50 Ω

C(OUT) (3) Output capacitance 1 μF

OUT PIN-VOLTAGE REGULATION(4)

bq24030/31 VI(AC) ≥6 V+VDO 6.0 6.3

Output

VO(OUT-REG) regulation bq24032A VI(AC) ≥4.4 V+VDO 4.4 4.5 V

voltage bq24038 VBSEL = HIGH or VBSEL = LOW, VI(AC) > 4.4 V+VDO 4.4 4.5

OUT PIN – DPPM REGULATION

V(DPPM-SET) DPPM set point(5) VDPPM-SET < VOUT 2.6 5 V

I(DPPM-SET) DPPM current source AC or USB present 95 100 105 μA

SF DPPM scale factor V(DPPM-REG)= V(DPPM-SET) × SF 1.139 1.150 1.162

(1) This includes the quiescent current for the integrated LDO.

(2) In standby mode (CE low) the accuracy is ±10%.

(3) LDO output capacitor not required but one with a value of 0.1 μF is recommended.

(4) When power is applied to the USB pin and PSEL is low, the USB input is switched straight through to the OUT pin (not regulated). This

voltage may drop to the DPPM-OUT threshold or battery voltage (which ever is higher) if the USB input current limit is active.

(5) V(DPPM-SET) is scaled up by the scale factor for controlling the output voltage V(DPPM-REG).

Product Folder Link(s): bq24030, bq24031 bq24032A, bq24035, bq24038

bq24030, bq24031

bq24032A, bq24035, bq24038

www.ti.com

............................................................................................................................................... SLUS618H –AUGUST 2004–REVISED OCTOBER 2009

ELECTRICAL CHARACTERISTICS (continued)

over junction temperature range (0°C ≤TJ≤125°C) and the recommended supply voltage range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

OUT PIN – FET (Q1, Q3, AND Q2) DROP-OUT VOLTAGE (RDSon)

VI(AC) ≥VCC(min), PSEL = High, II(AC) = 1 A,

V(ACDO) AC to OUT dropout voltage(6) 300 475

(IO(OUT)+ IO(BAT)), or no AC

VI(USB) ≥VCC(min), PSEL = Low, ISET2 = High, 140 180 mV

II(USB) = 0.4 A, (IO(OUT)+IO(BAT)), or no AC

V(USBDO) (7) USB to OUT dropout voltage VI(USB) ≥VCC(min), PSEL = Low, ISET2 = Low, 28 36

II(USB) = 0.08 A, (IO(OUT)+ IO(BAT))

BAT to OUT dropout voltage

V(BATDO) VI (BAT) ≥3 V, Ii(BAT)= 1.0 A, VCC < Vi(BAT) 40 100 mV

(discharging)

OUT PIN - BATTERY SUPPLEMENT MODE

Enter battery supplement mode VI(OUT)

VBSUP1 (battery supplements OUT current VI(BAT)> 2 V ≤VI(BAT)

in the presence of input source – 60 mV V

VI(OUT)

VBSUP2 Exit battery supplement mode VI(BAT)> 2 V ≥VI(BAT)

– 20 mV

OUT PIN - SHORT CIRCUIT

Current source between BAT to OUT for short-circuit

IOSH1 BAT to OUT short-circuit recovery 10 mA

recovery to VI(OUT) ≤VI(BAT) –200 mV

RSHAC AC to OUT short-circuit limit VI(OUT) ≤1 V 500 Ω

RSHVSB USB to OUT short-circuit limit VI(OUT) ≤1 V 500

BAT PIN CHARGING – PRECHARGE

Precharge to fast-charge transition

V(LOWV) Voltage on BAT 2.9 3 3.1 V

threshold

Deglitch time for fast-charge to tFALL = 100 ns, 10 mV overdrive,

TDGL(F) 22.5 ms

precharge transition(8) VI(BAT) decreasing below threshold

1 V < VI(BAT) < V(LOWV), t < t(PRECHG),

IO(PRECHG) Precharge range 10 150 mA

IO(PRECHG) = (K(SET)× V(PRECHG))/ RSET

V(PRECHG) Precharge set voltage 1 V < VI(BAT) < V(LOWV), t < t(PRECHG) 230 250 270 mV

BAT PIN CHARGING - CURRENT REGULATION

Vi (BAT) > V(LOWV), VI(OUT) - VI (BAT) > V(DO-MAX),

IO(BAT) AC battery charge current range (9) PSEL = High IOUT(BAT) = (K(SET) × V(SET) / RSET), 100 1000 1500 mA

VI(OUT) > VO(OUT-REG) + V(DO-MAX)

RPBAT BAT to OUT pullup Vi (BAT)< 1 V 1000

Ω

AC to OUT and USB to OUT

RPOUT VI(OUT) < 1 V 500

short-circuit pullup

Battery charge current set Voltage on ISET1, VVCC ≥4.35 V,

V(SET) 2.475 2.500 2.525 V

voltage(10) VI(OUT)- VI(BAT) > V(DO-MAX), VI(BAT) > V(LOWV)

100 mA ≤IO(BAT) ≤1 A 400 425 450

K(SET) Charge current set factor, BAT 10 mA ≤IO(BAT) ≤100 mA(11) 300 450 600

(6) VDO(max), dropout voltage is a function of the FET, RDS(on), and drain current. The dropout voltage increases proportionally to the

increase in current.

(7) RDS(on) of USB FET Q3 is calculated by: (VUSB – VOUT) / (IOUT + IBAT) when II(USB) ≤II(USB-MIN) (FET fully on, not in regulation).

(8) All deglitch periods are a function of the timer setting and is modified in DPPM or thermal regulation modes by the percentages that the

program current is reduced.

(9) When input current remains below 2 A, the battery charging current may be raised until the thermal regulation limits the charge current.

(10) For half-charge rate, V(SET) is 1.25 V ± 25 mV for bq24032A/38 only.

(11) Specification is for monitoring charge current via the ISET1 pin during voltage regulation mode, not for a reduced fast-charge level.

Product Folder Link(s): bq24030, bq24031 bq24032A, bq24035, bq24038

bq24030, bq24031

bq24032A, bq24035, bq24038

SLUS618H –AUGUST 2004–REVISED OCTOBER 2009...............................................................................................................................................

www.ti.com

ELECTRICAL CHARACTERISTICS (continued)

over junction temperature range (0°C ≤TJ≤125°C) and the recommended supply voltage range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

USB PIN INPUT CURRENT REGULATION

VI(BAT) > V(LOWV), VI(USB) - VI(BAT) > V(DO-MAX),100

ISET2= Low, PSEL = Low, or no AC (13)

USB input current range,

I(USB) mA

VI(BAT) > V(LOWV),

bq24030/32A/35/38(12) VI(USB) - VI(BAT) > V(DO-MAX), ISET2= High, 400 500

PSEL = Low, or no AC (12)

BAT PIN CHARGING VOLTAGE REGULATION, VO (BAT-REG) + V (DO-MAX) < VCC, ITERM < IBAT(OUT) ≤1 A

bq24030/32A/35 4.2

bq24031 4.1 V

Battery charge

voltage VBSEL = HI 4.36

VO(BAT-REG) bq24038 VBSEL = LO 4.2

TA= 25°C –0.5% 0.5%

Battery charge voltage regulation

accuracy –1% 1%

CHARGE TERMINATION DETECTION

I(TERM) Charge termination detection range VI(BAT) < V(RCH), I(TERM) = (K(SET) × V(TERM))/ RSET 10 150 mA

AC-charge termination detection

V(TERM-AC) VI(BAT) > V(RCH) , PSEL = High, ACPG = Low 235 250 265 mV

voltage, measured on ISET1

USB-charge termination detection VI(BAT) > V(RCH), PSEL = Low or

V(TAPER-USB) 95 100 130 mV

voltage, measured on ISET1 PSEL = High and ACPG = High

Deglitch time for termination tFALL = 100 ns, 10 mV overdrive,

TDGL(TERM) 22.5 ms

detection ICHG increasing above or decreasing below threshold

TEMPERATURE SENSE COMPARATORS

VLTF High voltage threshold Temp fault at V(TS) > VLTF 2.465 2.500 2.535 V

VHTF Low voltage threshold Temp fault at V(TS) < VHTF 0.485 0.500 0.515 V

ITS Temperature sense current source 94 100 106 μA

Deglitch time for temperature fault R(TMR) = 50 kΩ, VI(BAT) increasing or decreasing above and

TDGL(TF) 22.5 ms

detection(14) below; 100-ns fall time, 10-mv overdrive

BATTERY RECHARGE THRESHOLD

VO(BAT- VO(BAT- VO(BAT-

VRCH Recharge threshold voltage REG) REG) REG) V

–0.075 –0.100 –0.125

R(TMR) = 50 kΩ, VI(BAT) increasing

Deglitch time for recharge

TDGL(RCH) or decreasing below threshold, 22.5 ms

detection(14) 100-ns fall time, 10-mv overdrive

(12) With the PSEL= low, the bqTINY III-series defaults to USB charging. If USB input is ≤VBAT, then the bqTINY III-series charges from the

AC input at the USB charge rate. In this configuration, the specification is 400 mA (min) and 500 mA (max).

(13) With the PSEL= low, the bqTINY III-series defaults to USB charging. If USB input is ≤VBAT, then the bqTINY III-series charges from the

AC input at the USB charge rate. In this configuration, the specification is 80 mA (min) and 100 mA (max).

(14) All deglitch periods are a function of the timer setting and is modified in DPPM or thermal regulation modes by the percentages that the

program current is reduced.

Product Folder Link(s): bq24030, bq24031 bq24032A, bq24035, bq24038

bq24030, bq24031

bq24032A, bq24035, bq24038

www.ti.com

............................................................................................................................................... SLUS618H –AUGUST 2004–REVISED OCTOBER 2009

ELECTRICAL CHARACTERISTICS (continued)

over junction temperature range (0°C ≤TJ≤125°C) and the recommended supply voltage range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

STAT1, STAT2. ACPG AND USBPG, PG OPEN DRAIN (OD) OUTPUTS(15)

IOL = 5 mA, An external pullup

VOL Low-level output saturation voltage 0.25 V

resistor ≥1 K required.

ILKG Input leakage current 1 5 μA

ISET2, CE, VBSEL INPUTS

VIL Low-level input voltage 0 0.4 V

VIH High-level input voltage 1.4

IIL Low-level input current, CE –1

IIH High-level input current, CE 1

IIL Low-level input current, ISET2 VISET2 = 0 V –20 μA

IIH High-level input current, ISET2 VISET2 = VCC 40

IIL1 Low-level input current VBSEL = Low 6 1

IIH1 High-level input current VBSEL = High 15

t(CE-HLDOFF) Holdoff time, CE CE going low only 3.3 6.2 ms

PSEL INPUT

VIL Low-level input voltage Falling Hi→Low; 280 K ± 10% applied when low. 0.975 1 1.025 V

VIL +

VIH High-level input voltage Input RPSEL sets external hysteresis VIL + 0.01 V

0.024

IIL Low-level input current, PSEL –1 μA

IIH High-level input current, PSEL μA

TIMERS

K(TMR) Timer set factor t(CHG) = K(TMR) × R(TMR) 0.313 0.360 0.414 s/Ω

R(TMR) (16) External resistor limits 30 100 kΩ

0.09 × 0.10 × 0.11 ×

t(PRECHG) Precharge timer s

t(CHG) t(CHG) t(CHG)

Timer fault recovery pullup from

I(FAULT) 1 kΩ

OUT to BAT

CHARGER SLEEP THRESHOLDS (ACPG , PG, and USBPG THRESHOLDS, LOW →POWER GOOD)

VVCC ≤

V(SLPENT) V(UVLO) ≤VI(BAT) ≤VO(BAT-REG),

Sleep-mode entry threshold VI(BAT)

(17) No t(BOOT-UP) delay +125 mV V

VVCC ≥

V(SLPEXIT) V(UVLO) ≤VI(BAT) ≤VO(BAT-REG),

Sleep-mode exit threshold VI(BAT)

(17) No t(BOOT-UP) delay +190 mV

R(TMR) = 50 kΩ,

t(DEGL) Deglitch time for sleep mode(18) V(AC) or V(USB) or decreasing below threshold, 100-ns fall 22.5 ms

time, 10-mv overdrive

(15) See Charger Sleep mode for ACPG (VCC = VAC) and USBPG (VCC = VUSB) specifications.

(16) To disable the fast-charge safety timer and charge termination, tie TMR to the LDO pin. Tying the TMR pin high changes the timing

resistor from the external value to an internal 50 kΩ±25%, which can add an additional tolerance to any timed spectification. The TMR

pin normally regulates to 2.5 V when the charge current is not restricted by the DPPM or thermal feedback loops. If these loops become

active, the TMR pin voltage will be reduced proportionally to the reduction in charge current and the clock frequency will be reduced by

the same percentage (timed durations will count down slower, extending their time). The TMR pin is clamped at 0.80 V, for a maximum

time extension of 2.5 V ÷ 0.8 V × 100 = 310%.

(17) The IC is considered in sleep mode when both AC and USB are absent (ACPG = USBPG = OPEN DRAIN).

(18) Does not declare sleep mode until after the deglitch time and implement the needed power transfer immediately according to the

switching specification.

Product Folder Link(s): bq24030, bq24031 bq24032A, bq24035, bq24038

bq24030, bq24031

bq24032A, bq24035, bq24038

SLUS618H –AUGUST 2004–REVISED OCTOBER 2009...............................................................................................................................................

www.ti.com

ELECTRICAL CHARACTERISTICS (continued)

over junction temperature range (0°C ≤TJ≤125°C) and the recommended supply voltage range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

START-UP CONTROL and USB BOOT-UP

On the first application of USB input power or AC input

t(BOOT-UP) Boot-up time 120 150 180 ms

with PSEL Low

SWITCHING POWER SOURCE TIMING

Only AC power or USB power applied. Measure from:

Switching power source from inputs

tSW-BAT [xxPG: Lo →Hi to I(xx) > 5 mA], 50

(AC or USB) to battery xx = AC or USB I(OUT) = 100 mA, RTRM = 50 K

Switching from AC to USB, or, USB Measure from: μs

tSW-AC/USB 100

to AC by input source removal. (19) I(AC) < 5 mA to I(USB) > 5 mA or I(USB)

< 5 mA →I(AC) > 5 mA;

Switching from AC to USB, or USB I(OUT) = 100 mA, RTMR = 50 K,

tSW-PSEL 50 100

to AC by toggling PSEL ISET2 = hi, ROUT > 15 Ω, VDPPM = 2.5 V

THERMAL SHUTDOWN REGULATION(20)

T(SHTDWN) Temperature trip TJ(Q1 and Q3 only) 155

Thermal hysteresis TJ(Q1 and Q3 only) 30 °C

TJ(REG) Temperature regulation limit TJ(Q2) 115 135

UVLO

V(UVLO) Undervoltage lockout Decreasing VCC 2.45 2.50 2.65 V

Hysteresis 27 mV

(19) The power handoff is implemented once the PG pin goes high (removed sources PG) which is when the removed source drops to the

battery voltage. If the battery voltage is critically low, the system may lose power unless the system takes control of the PSEL pin and

switches to the available power source prior to shutdown. The USB source often has less current available; so, the system may have to

reduce its load when switching from AC to USB.

(20) Reaching thermal regulation reduces the charging current. Battery supplement current is not restricted by either thermal regulation or

shutdown. Input power FETs turn off during thermal shutdown. The battery FET is only protected by a short-circuit limit which typically

does not cause a thermal shutdown (input FETs turning off) by itself.

Product Folder Link(s): bq24030, bq24031 bq24032A, bq24035, bq24038

STAT1

STAT2

BAT

ISET2

PSEL

bq24030RHL − bq24038RHL

RHL PACKAGE

(TOP VIEW)

USBPG / VBSEL

ACPG / PG

OUT

TMR

DPPM

USB

LDO

VSS

ISET1

201

1110

bq24030, bq24031

bq24032A, bq24035, bq24038

www.ti.com

............................................................................................................................................... SLUS618H –AUGUST 2004–REVISED OCTOBER 2009

DEVICE INFORMATION

TERMINAL FUNCTIONS

TERMINAL I/O DESCRIPTION

NAME NO.

AC 4 I Charge input voltage from AC adapter

ACPG (1) 18 O AC power-good status output (open-drain)

BAT 5, 6 I/O Battery input and output.

CE 9 I Chip enable input (active high)

DPPM 13 I Dynamic power-path management set point (account for scale factor)

ISET1 10 I/O Charge current set point for AC input and precharge and termination set point for both AC and USB

ISET2 7 I Charge current set point for USB port. (High = 500 mA, Low = 100 mA)

LDO 1 O 3.3-V LDO regulator

OUT 15, 16, 17 O Output terminal to the system

PG (1) 18 O AC or USB power-good status output (open-drain)

PSEL 8 I Power source selection input (Low for USB, High for AC)

STAT1 2 O Charge status output 1 (open-drain)

STAT2 3 O Charge status output 2 (open-drain)

Timer program input programmed by resistor. Disable fast-charge safety timer and termination by tying

TMR 14 I/O TMR to LDO.

TS 12 I/O Temperature sense input

USB 20 I USB charge input voltage

USBPG (2) 19 O USB power-good status output (open-drain)

VBSEL(2) 19 I Battery charge voltage selection

Ground input (the thermal pad on the underside of the package) There is an internal electrical connection

between the exposed thermal pad and VSS pin of the device. The exposed thermal pad must be

VSS 11 – connected to the same potential as the VSS pin on the printed-circuit board. Do not use the thermal pad as

the primary ground input for the device. VSS pin must be connected to ground at all times.

(1) Pin 18 is PG for bq24038 and ACPG for bq24030/31/32A/35.

(2) Pin 19 is VBSEL for bq24038 and USBPG for bq24030/31/32A/35.

Product Folder Link(s): bq24030, bq24031 bq24032A, bq24035, bq24038

USB

Reference, Bias & UVLO

ISET2

Thermal

Shutdown

Precharge

Recharge

Term

STAT1

STAT2

PSEL

Suspend

Sleep (AC)

Sleep (USB)VSS

BAT Charge Enable

USB Charge Enable

500 mA/ 100 mA

*Signal Deglitched

UVLO

+1 V

DPPM

Power Source Selection

60 mV

200 mV

Disable−

Sleep

DPPM

Scaling

ISET1

BAT

3.3−V LDO LDO

OUT

AC Charge Enable

Short Circuit

Recovery

BAT

Short−Circuit

Recovery

USB

Charge

Enable

100 mA / 500 mA

BAT

Charge

Enable

Short−Circuit Recovery

USB

Charge

Enable

100 mA /

500 mA

TMR Oscillator

500 Ω

VO(OUT)

VO(LDO)

VI(BAT)

VI(ISET1)

VI(IUSB−SNS)

1 kΩ

500 Ω

VI(IUSB−SNS)

VO(OUT)

VO(OUT−REG)

VIO(AC) Charge

Enable

VI(IUSB−SNS)

VO(BAT−REG)

VI(BAT) VO(BAT−REG)

VI(BAT)

VI(ISET1)

Fast Precharge

VO(OUT)

I(DPPM) VSET

VSET

VDPPM

TJ(REG)

VSET

V(HTF)

V(LTF)

VO(BAT−REG)

VBAT

I(TS)

VI(ISET1)

VBAT

VAC

VBAT

VUSB

VI(BAT)

VO(OUT)

V(SET)

C/S − 100 mA

1C − 500 mA

Fast Precharge

ACPG

USBPG

Charge

Control

Timer

and

Display

Logic

UDG−04084

Recovery

Fault

10 mA

1 V

280 kΩ

bq24030, bq24031

bq24032A, bq24035, bq24038

SLUS618H –AUGUST 2004–REVISED OCTOBER 2009...............................................................................................................................................

www.ti.com

FUNCTIONAL BLOCK DIAGRAM FOR bq24030/31/32A/35 ONLY

(1) For bq24038 see bq24038 Differences in the Functional Descriptions section.

Product Folder Link(s): bq24030, bq24031 bq24032A, bq24035, bq24038

Pre-Conditioning

Phase Current Regulation Phase Voltage Regulation and Charge Termination Phase

Regulation

Voltage

Regulation

Current

Minimum

Charge

Voltage

Pre−

Conditioning

and Term

Detect

Charge

Current

Charge

Complete

UDG−04087

Charge

Voltage

USB

LDO

STAT2

TMR

ISET2

PACK+

PACK−

System

VDC

GND

VBUS

GND

D+

D −

USBPort

AC Adapter

2 STAT1

8PSEL

9CE

OUT 15

OUT 16

OUT 17

BAT

6BAT

DPPM

ISET1

VSS

TEMP

Battery P ack

10 µF

RTMR 1µF

RSET

USBPG

ACPG

RDPPM

Controland

Status Signals

bq24030/31/32A/35

10 µF

bq24030, bq24031

bq24032A, bq24035, bq24038

www.ti.com

............................................................................................................................................... SLUS618H –AUGUST 2004–REVISED OCTOBER 2009

FUNCTIONAL DESCRIPTIONS

CHARGE CONTROL

The bqTINY III-series supports a precision Li-ion or Li-polymer charging system suitable for single-cell portable

devices. See a typical charge profile, application circuit, and an operational flow chart in Figure 1 through

Figure 4, respectively.

Figure 1. Charge Profile

Figure 2. Typical Application Circuit

Product Folder Link(s): bq24030, bq24031 bq24032A, bq24035, bq24038

Vcc>V I(OUT)

checkedatall

VI(BAT) <V(LOWV) Yes

t(PRECHG)

Expired?

Yes

IndicateFault

Yes

t(CHG)

Expired?

IndicateCharge−

In−Progress

Regulate

IO(PRECHG)

IndicateCharge−

In−Progress

RegulateCurrent

orVoltage

ResetandStart

t(PRECHG)timer

POR

Yes

Resetalltimers,

Startt (CHG) timer

Yes

VI(OUT)<V(RCH)

VI(OUT)<V(LOWV)

FaultCondition

Yes

IndicateDONE

Turnoffcharge

IndicateSLEEP

MODE

SLEEP MODE

VI(OUT) <V(LOWV)

I(TERM)

detection?

Yes

VI(OUT)

>V(RCH)

EnableI(FAULT)

current

VI(OUT)>V(RCH)

Yes

DisableI(FAULT)

current

times?

bq24030, bq24031

bq24032A, bq24035, bq24038

SLUS618H –AUGUST 2004–REVISED OCTOBER 2009...............................................................................................................................................

www.ti.com

Figure 3. Charge Control Operational Flow Chart

Product Folder Link(s): bq24030, bq24031 bq24032A, bq24035, bq24038

bq24030, bq24031

bq24032A, bq24035, bq24038

www.ti.com

............................................................................................................................................... SLUS618H –AUGUST 2004–REVISED OCTOBER 2009

bq24038 Differences

The bq24038 replaces USBPG with pin VBSEL, to enable user selection of the charge voltage. In addition, pin

ACPG was modified to PG. PG is active low when either AC power or USB power is detected.

Autonomous Power Source Selection, PSEL Control Pin

The PSEL pin selects the priority of the input sources (high = AC, low = USB), if that primary source is not

available (based on ACPG, USBPG signal), then it uses the secondary source. If neither input source is

available, then the battery is selected as the source. With the PSEL input high, the bqTINY III-series attempts to

charge from the AC input. If AC input is not present, the USB is selected. If both inputs are available, the AC

adapter has priority. With the PSEL input low, the bqTINY III-series defaults to USB charging. If USB input is

grounded, then the bqTINY III-series charges from the AC input at the USB charge rate (as selected by ISET2).

This feature can be used in system where AC and USB power source selection is done elsewhere. The PSEL

function is summarized in Table 1.

Table 1. Power Source Selection Function Summary

PSEL STATE AC USB CHARGE MAXIMUM SYSTEM USB BOOT-UP

SOURCE CHARGE RATE (1) POWER FEATURE

SOURCE

Present(2) Absent AC ISET2 AC Enabled

Absent(3) Present USB ISET2 USB Enabled

Low Present Present USB ISET2 USB Enabled

Absent Absent N/A N/A Battery Disabled

Present Absent AC ISET1 AC Disabled

Absent Present USB ISET2 USB Disabled

High Present Present AC ISET1 AC Disabled

Absent Absent N/A N/A Battery Disabled

(1) Battery charge rate is always set by ISET1, but may be reduced by a limited input source (ISET2 USB mode) and IOUT system load.

(2) Present is defined as input being at a higher voltage than the BAT voltage (sources power good is low).

(3) AC Absent is defined as AC input not present (ACPG is High) or Q1 turned off due to overvoltage in bq24035.

Boot-Up Sequence

In order to facilitate the system start-up and USB enumeration, the bqTINY III-series offers a proprietary boot-up

sequence. On the first application of power to the bqTINY III-series, this feature enables the 100-mA USB charge

rate for a period of approximately 150 ms, (t(BOOT-UP)), ignoring the ISET2 and CE inputs setting. At the end of

this period, the bqTINY III-series implements CE and ISET2 inputs settings. Table 1 indicates when this feature

is enabled. See Figure 13.

Power-Path Management

The bqTINY III-series powers the system while independently charging the battery. This features reduces the

charge and discharge cycles on the battery, allows for proper charge termination, and allows the system to run

with an absent or defective battery pack. This feature gives the system priority on input power, allowing the

system to power up with a deeply discharged battery pack. This feature works as follows (note that PSEL is

assumed HIGH for this discussion).

Product Folder Link(s): bq24030, bq24031 bq24032A, bq24035, bq24038

USB BAT

OUT

bq2403x

PACK+

PACK−

System

VDC

GND

VBUS

GND

D+

D −

USB Port

AC Adapter

Q2Q3

UDG−04082

40 mΩ

(2)

bq24030, bq24031

bq24032A, bq24035, bq24038

SLUS618H –AUGUST 2004–REVISED OCTOBER 2009...............................................................................................................................................

www.ti.com

Figure 4. Power-Path Management

Case 1: AC Mode (PSEL = High)

System Power

In this case, the system load is powered directly from the AC adapter through the internal transistor Q1 (see

Figure 4). For bq24030/31, Q1 acts as a switch as long as the AC input remains at or below 6 V (VO(OUT-REG)).

Once the AC voltage goes above 6 V, Q1 starts regulating the output voltage at 6 V. For bq24035, once the AC

voltage goes above VCUT-OFF (~6.4 V), Q1 turns off. For bq24032A/38, the output is regulated at 4.4 V from the

AC input. Note that switch Q3 is turned off for both devices. If the system load exceeds the capacity of the

supply, the output voltage drops down to the battery's voltage.

Charge Control

When AC is present, the battery is charged through switch Q2 based on the charge rate set on the ISET1 input.

Dynamic Power-Path Management (DPPM)

This feature monitors the output voltage (system voltage) for input power loss due to brown outs, current limiting,

or removal of the input supply. If the voltage on the OUT pin drops to a preset value, V(DPPM-SET) × SF, due to a

limited amount of input current, then the battery charging current is reduced until the output voltage stops

dropping. The DPPM control tries to reach a steady-state condition where the system gets its needed current and

the battery is charged with the remaining current. No active control limits the current to the system; therefore, if

the system demands more current than the input can provide, the output voltage drops just below the battery

voltage and Q2 turns on which supplements the input current to the system. DPPM has three main advantages.

1. This feature allows the designer to select a lower power wall adapter, if the average system load is moderate

compared to its peak power. For example, if the peak system load is 1.75 A, average system load is 0.5 A

and battery fast-charge current is 1.25 A, the total peak demand could be 3 A. With DPPM, a 2-A adaptor

could be selected instead of a 3.25-A supply. During the system peak load of 1.75 A and charge load of 1.25

A, the smaller adaptor’s voltage drops until the output voltage reaches the DPPM regulation voltage

threshold. The charge current is reduced until there is no further drop on the output voltage. The system gets

its 1.75-A charge and the battery charge current is reduced from 1.25 A to 0.25 A. When the peak system

load drops to 0.5 A, the charge current returns to 1 A and the output voltage returns to its normal value.

2. Using DPPM provides a power savings compared to configurations without DPPM. Without DPPM, if the

system current plus charge current exceed the supply’s current limit, then the output is pulled down to the

battery. Linear chargers dissipate the unused power (VIN-VOUT) × ILOAD. The current remains high (at current

limit) and the voltage drop is large for maximum power dissipation. With DPPM, the voltage drop is less

(VIN-V(DPPM-REG)) to the system which means better efficiency. The efficiency for charging the battery is the

same for both cases. The advantages include less power dissipation, lower system temperature, and better

overall efficiency.

3. The DPPM sustains the system voltage no matter what causes it to drop, if at all possible. It does this by

reducing the noncritical charging load while maintaining the maximum power output of the adaptor.

Note that the DPPM voltage, V(DPPM-REG), is programmed as follows:

Product Folder Link(s): bq24030, bq24031 bq24032A, bq24035, bq24038

V(DPPM−REG) +I(DPPM) R(DPPM) SF

V(DPPM−REG) +V(DPPM−SET) SF

bq24030, bq24031

bq24032A, bq24035, bq24038

www.ti.com

............................................................................................................................................... SLUS618H –AUGUST 2004–REVISED OCTOBER 2009

(1)

where

R(DPPM) is the external resistor connected between the DPPM and VSS pins.

I(DPPM) is the internal current source.

SF is the scale factor as specified in the specification table.

The safety timer is dynamically adjusted while in DPPM mode. The voltage on the ISET1 pin is directly

proportional to the programmed charging current. When the programmed charging current is reduced, due to

DPPM, the ISET1 and TMR voltages are reduced and the timer’s clock is proportionally slowed, extending the

safety time. In normal operation, V(TMR) = 2.5 V; when the clock is slowed the voltage V(TMR) is reduced. For

example, if V(TMR) = 1.25 V, the safety timer has a value close to 2 times the normal operation timer value. See

Figure 5 through Figure 8.

Case 2: USB (PSEL = Low) bq24030/31/32A/38

System Power

In this case, the system load is powered directly from the USB port through the internal switch Q3 (see

Figure 14). Note in this case, Q3 regulates the total current to the 100 mA or 500 mA level, as selected on the

ISET2 input. Switch Q1 is turned off in this mode. If the system and battery load is less than the selected

regulated limit, then Q3 is fully on and VOUT is approximately (V(USB)-V(USB-DO)). The systems power management

is responsible for keeping its system load below the USB current level selected (if the battery is critically low or

missing). Otherwise, the output drops to the battery voltage; therefore, the system should have a low power

mode for USB power application. The DPPM feature keeps the output from dropping below its programmed

threshold, due to the battery charging current, by reducing the charging current.

Charge Control

When USB is present and selected, Q3 regulates the input current to the value selected by the ISET2 pin

(0.1/0.5 A). The charge current to the battery is set by the ISET1 resistor (typically > 0.5 A). Because the charge

current typically is programmed for more current than Q3 allows, the output voltage drops to the battery voltage

or DPPM voltage, whichever is higher. If the DPPM threshold is reached first, the charge current is reduced until

VOUT stops dropping. If VOUT drops to the battery voltage, the battery is able to supplement the input current to

the system.

Dynamic Power-Path Management (DPPM)

The theory of operation is the same as described in CASE 1, except that Q3 restricts the amount of input current

delivered to the output and battery instead of the input supply.

Note that the DPPM voltage, V(DPPM), is programmed as follows:

(2)

and

(3)

where

R(DPPM) is the external resistor connected between the DPPM and VSS pins.

I(DPPM) is the internal current source.

SF is the scale factor as specified in the specification table.

Feature Plots

The voltage on the DPPM pin, V(DPPM-SET) is determined by the external resistor, R(DPPM). The output voltage,

V(OUT), that the DPPM function regulates is V(DPPM-REG). For example, if R(DPPM) is 33 kΩ, then the

V(DPPM-SET)voltage on the DPPM pin is 3.3 V (I(DPPM-SET) = 100 μA, typical). The DPPM function attempts to keep

V(OUT) from dropping below the V(DPPM-REG) voltage, and is 3.795 V for this example (SF = 1.15, typical).

Figure 5 illustrates DPPM and battery supplement modes as the output current (IOUT) is increased; channel 1

Product Folder Link(s): bq24030, bq24031 bq24032A, bq24035, bq24038

T=4.26V, DPPMMode

Reg.@4.4V(bq24032A)

VOUT

VAC

ICHG

IOUT

VOUT

VDPPM − OU

VOUT VBAT

,BATSupplementMode

≈

bq24030, bq24031

bq24032A, bq24035, bq24038

SLUS618H –AUGUST 2004–REVISED OCTOBER 2009...............................................................................................................................................

www.ti.com

(CH1) VAC = 5.4 V; channel 2 (CH2) VOUT; channel 3 (CH3) IOUT = 0 to 2.2 A to 0 A; channel 4 (CH4) VBAT = 3.5

V; I(PGM-CHG) = 1 A. In typical operation, bq24032A (VOUT = 4.4 Vreg), through an AC adaptor overload condition

and recovery. The AC input is set for ~5.1 V (1.5 A current limit), I(CHG) =1A,V(DPPM-SET) = 3.7 V, V(DPPM-OUT) =

1.15 × V(DPPM-SET) = 4.26 V, VBAT = 3.5 V, PSEL = H, and USB input is not connected. The output load is

increased from 0 A to ~2.2 A and back to 0 A as shown in the bottom waveform. As the IOUT load reaches 0.5 A,

along with the 1-A charge current, the adaptor starts to current limit, the output voltage drops to the DPPM-OUT

threshold of 4.26 V. This is DPPM mode. The AC input tracks the output voltage by the dropout voltage of the

AC FET. The battery charge current is then adjusted back as necessary to keep the output voltage from falling

any further. Once the output load current exceeds the input current, the battery has to supplement the excess

current and the output voltage falls just below the battery voltage by the dropout voltage of the battery FET. This

is the battery supplement mode. When the output load current is reduced, the operation described is reversed as

shown. If V(DPPM-REG) was set below the battery voltage, during input current limiting, the output falls directly to

the battery's voltage.

Under USB operation, when the loads exceeds the programmed input current thresholds a similar pattern is

observed. If the output load exceeds the available USB current, the output instantly goes into the battery

supplement mode.

Figure 5. DPPM and Battery Supplement Modes

Figure 6 illustrates when PSEL is toggled low for 500 μs. Power transfers from AC to USB to AC; channel 1

(CH1) VAC = 5.4 V; channel 2 (CH2) V(USB) = 5 V; channel 3 (CH3) VOUT; output current, IOUT = 0.25 A; channel

4 (CH4) VBAT = 3.5 V; and I(PGM-CHG) = 1 A. When the PSEL went low (1st div), the AC FET opened, and the

output fell until the USB FET turned on. Turning off the active source before turning on the replacement source is

referred to as break-before-make switching. The rate of discharge on the output is a function of system

capacitance and load. Note the cable IR drop in the AC and USB inputs when they are under load. At the 4th

division, the output has reached steady-state operation at V(DPPM-REG) (charge current has been reduced due to

the limited USB input current). At the 6th division, the PSEL goes high and the USB FET turns off followed by the

AC FET turning on. The output returns to its regulated value, and the battery returns to its programmed current

level.

Product Folder Link(s): bq24030, bq24031 bq24032A, bq24035, bq24038

VAC

VUSB

VOUT

VBAT

Break Before Make

System Capacitance

Powering System

USB is Charging System Capacitance

DPPM Mode

Low

PSEL

VAC

VUSB

VOUT

VBAT

USB Input Current Limit is Reached.

DPPM Mode

AC Declared Not Present, USB Power Applied

bq24030, bq24031

bq24032A, bq24035, bq24038

www.ti.com

............................................................................................................................................... SLUS618H –AUGUST 2004–REVISED OCTOBER 2009

Figure 6. Toggle PSEL Low

Figure 7 illustrates when AC is removed, power transfers to USB; PSEL = H (AC primary source); channel 1

(CH1) VAC = 5.4 V; channel 2 (CH2) V(USB) = 5 V; channel 3 (CH3) VOUT; output current, IOUT = 0.25 A; channel

4 (CH4) VBAT = 3.5 V; and I(PGM-CHG) = 1 A. The power transfer from AC to USB only takes place after the primary

source (AC) is considered bad (too low, VAC<=VBAT + 125 mV) indicated by the ACPG FET turning off (open

drain not shown). Thus, the output drops down to the battery voltage before the USB source is connected (6th

div). The output starts to recover when the USB FET starts to limit the input current (7th div) and the output drops

to the V(DPPM-REG) threshold.

Figure 7. Remove AC – PWR XFER to USB

Product Folder Link(s): bq24030, bq24031 bq24032A, bq24035, bq24038

VAC

VUSB

VOUT

VBAT

DPPM Mode

BreakBeforeMake

VAC

VUSB

VOUT

VBAT

DPPMMode

VOUT ReturnstoRegulation(4.4V,bq24032A)

ChargingCurrentReturnstoI

pgm

bq24030, bq24031

bq24032A, bq24035, bq24038

SLUS618H –AUGUST 2004–REVISED OCTOBER 2009...............................................................................................................................................

www.ti.com

Figure 8 illustrates when AC (low battery) is removed, power transfers to USB; PSEL = H; channel 1 (CH1) VAC

= 5.4 V; channel 2 (CH2) V(USB) = 5 V; channel 3 (CH3) VOUT; output current, IOUT = 0.25 A; channel 4 (CH4)

VBAT = 2.25 V; and I(PGM-CHG) = 1 A. This figure is the same as where the battery has more capacity. Note that

the output drops to the battery voltage before switching to USB power. A resistor divider between AC and ground

tied to PSEL can toggle the power transfer earlier if necessary.

Figure 8. Remove AC (Low Battery) – PWR XFER to USB

Figure 9 illustrates when AC is applied, power transfers from USB to AC; PSEL = H; channel 1 (CH1) VAC = 5.4

V; channel 2 (CH2) V(USB) = 5 V; channel 3 (CH3) VOUT; output current, IOUT = 0.25 A; channel 4 (CH4) VBAT =

3.5 V; and I(PGM-CHG) = 1 A. The charger is set for AC priority but is running off USB until AC is applied. When AC

is applied (1st div) and the USB FET opens (2nd div), the AC FET closes (3rd div) and the output recovers from

the DPPM threshold (8th div).

Figure 9. Apply AC – PWR XFER From USB to AC

Product Folder Link(s): bq24030, bq24031 bq24032A, bq24035, bq24038

VAC

VUSB

VOUT

VBAT

DPPM Mode

USB Declared not Present

AC is Applied (USB Mode)

AC Hits USB (ISET2) limit

VAC

VUSB

VOUT

VBAT

Charging (Step) Followed by Charge Done

BAT PIN Capacitance Discharging to Refresh Threshold

bq24030, bq24031

bq24032A, bq24035, bq24038

www.ti.com

............................................................................................................................................... SLUS618H –AUGUST 2004–REVISED OCTOBER 2009

Figure 10 illustrates when USB is removed, power transfers from USB to AC; PSEL = L; channel 1 (CH1) VAC =

5.4 V; channel 2 (CH2) V(USB) = 5 V; channel 3 (CH3) VOUT; output current, IOUT = 0.25 A; channel 4 (CH4) VBAT

= 3.5 V; and I(PGM-CHG) = 1 A. The USB source is removed (2nd div) and the output drops to the battery voltage

(declares USB bad, 4th div) and switches to AC (in USB mode) and recovers similar to the figure that is switching

to USB power. This power transfer occurred with PSEL low, which means that the AC input is regulated as if it

were a USB.

Figure 10. Remove USB – PWR XFER From USB to AC

Figure 11 illustrates when the battery is absent, power transfers to USB; PSEL = H; channel 1 (CH1) VAC = 5.4

V; channel 2 (CH2) V(USB) = 5 V; channel 3 (CH3) VOUT; output current, IOUT = 0.25 A; channel 4 (CH4) VBAT;

I(PGM-CHG) = 1 A. Note the saw-tooth waveform due to cycling between charge done and refresh (new charge).

Figure 11. Battery Absent – PWR XFER to USB

Product Folder Link(s): bq24030, bq24031 bq24032A, bq24035, bq24038

VBAT

VOUT

bq24030, bq24031

bq24032A, bq24035, bq24038

SLUS618H –AUGUST 2004–REVISED OCTOBER 2009...............................................................................................................................................

www.ti.com

Figure 12 illustrates when a battery is inserted for power up; channel 1 (CH1) VAC = 0 V; channel 2 (CH2) VUSB

= 0 V; channel 3 (CH3) VOUT; output current, IOUT = 0.25 A for VOUT > 2 V; channel 4 (CH4) VBAT = 3.5 V; C(DPPM)

= 0 pF. When there are no power sources and the battery is inserted, the output tracks the battery voltage if

there is no load (<10 mA of load) on the output, as shown. If a load is present that keeps the output more than

200 mV below the battery, a short-circuit condition is declared. At this time, the load has to be removed to

recover. A capacitor can be placed on the DPPM pin to delay implementing the short-circuit mode and get

unrestricted (not limited) current.

Figure 12. Insert Battery – Power-Up Output via BAT

Figure 13 illustrates USB bootup and power-up via USB; channel 1 (CH1) V(USH) = 0 to 5 V; channel 2 (CH2)

USB input current (0.2 A/div); PSEL = Low; CE = High; ISET2 = High; VBAT = 3.85 V; V(DPPM) = 3.0 V (V(DPPM) ×

1.15 < VBAT, otherwise DPPM mode increases time duration). When a USB source is applied (if AC is not

present), the CE pin and ISET2 pin are ignored during the boot-up time and a maximum input current of 100 mA

is made available to the OUT or BAT pins. After the boot-up time, the bqTINY III-series implements the CE and

ISET2 pins as programmed.

Product Folder Link(s): bq24030, bq24031 bq24032A, bq24035, bq24038

VUSB

IUSB

bqTINYIII

LTF

HTF

BATTERY

PACK

PACK+

PACK−

NTC

TEMP

ITS

VLTF

VHTF

RT1

RT2

UDG−04086

bqTINYIII

LTF

HTF

BATTERY

PACK

PACK+

PACK−

NTC

ITS

VLTF

VHTF

UDG−04085

bq24030, bq24031

bq24032A, bq24035, bq24038

www.ti.com

............................................................................................................................................... SLUS618H –AUGUST 2004–REVISED OCTOBER 2009

Figure 13. USB Boot-Up Power-Up

Battery Temperature Monitoring

The bqTINY™ III-series continuously monitors battery temperature by measuring the voltage between the TS

and VSS pins. An internal current source (I(TS) = 100 μA, typical) provides the bias for most common 10-kΩ

negative-temperature coefficient thermistors (NTC) (see Figure 14). The device compares the voltage on the TS

pin against the internal V(LTF) , and V(HTF) thresholds (0.5 V and 2.5 V, respectively are typical) to determine if

charging is allowed. Once a temperature outside the V(LTF) and V(HTF) thresholds is detected, the device

immediately suspends the charge. The device suspends charge by turning off the power FET and holding the

timer value (i.e., timers are not reset). Charge is resumed when the temperature returns to the normal range. The

allowed temperature range for 103AT-type thermistor is 0°C to 45°C. However, the user may increase the range

by adding two external resistors. See Figure 15.

Figure 14. TS Pin Configuration Figure 15. TS Pin Thresholds

Battery Pre-Conditioning

During a charge cycle, if the battery voltage is below the V(LOWV) threshold (3.0 V, typical), the bqTINY III-series

applies a precharge current, IO(PRECHG), to the battery. This feature revives deeply discharged cells. The resistor

connected between the ISET1 and VSS, RSET, determines the precharge rate. The V(PRECHG) and

K(SET) parameters are specified in the specifications table. Note that this applies to both AC and USB charging.

Product Folder Link(s): bq24030, bq24031 bq24032A, bq24035, bq24038

IO (PRECHG) +V(PRECHG) K(SET)

RSET

IO (BAT) +V(SET) K(SET)

RSET

bq24030, bq24031

bq24032A, bq24035, bq24038

SLUS618H –AUGUST 2004–REVISED OCTOBER 2009...............................................................................................................................................

www.ti.com

(4)

The bqTINY III-series activates a safety timer, t(PRECHG), during the conditioning phase. If V(LOWV) threshold is not

reached within the timer period, the bqTINY III-series turns off the charger and enunciates FAULT on the STAT1

and STAT2 pins. The timeout is extended if the charge current is reduced by DPPM. See the Timer Fault

Recovery section for additional details.

Battery Charge Current

The bqTINY III-series offers on-chip current regulation with programmable set point. The resistor connected

between the ISET1 and VSS, RSET, determines the charge level. The charge level may be reduced to give the

system priority on input current (see DPPM). The V(SET) and K(SET) parameters are specified in the specifications

table.

(5)

When powered from a USB port, the input current available (0.1 A/0.5 A) is typically less than the programmed

(ISET1) charging current, and therefore, the DPPM feature attempts to keep the output from being pulled down

by reducing the charging current.

The charge level for the bq24032A/38, during AC operation only (PSEL = High), can be changed by a factor of 2

by setting the ISET2 pin high (full charge) or low (half charge). The voltage on the ISET1 pin, V(SET), is divided by

2 when in the half constant current charge mode. Note that with PSEL low, the ISET2 pin controls only the

0.1 A/0.5 A USB current level.

With ISET2 low the V(TMR) voltage remains at 2.5 V under normal operating conditions. In this case, the charge

rate is half the programmed current but the safety timer remains t(CHG). If the bqTINY III-series enters DPPM or

thermal regulation mode from this state, the safety timer immediately doubles and then the safety time is

adjusted (inversely proportionate) with the charge current.

See the section titled Power-Path Management for additional details.

Battery Voltage Regulation

The voltage regulation feedback is through the BAT pin. This input is tied directly to the positive side of the

battery pack. The bqTINY III-series monitors the battery-pack voltage between the BAT and VSS pins. When the

battery voltage rises to the VO(BAT-REG) threshold (4.1-V, 4.2-V, or 4.36-V versions), the voltage regulation phase

begins and the charging current begins to taper down.

If the battery is absent, the BAT pin cycles between charge done (VO(REG)) and charging (battery refresh

threshold, ~100 mV below VO(REG)). See Figure 11.

See Figure 12 for power up by battery insertion.

As a safety backup, the bqTINY III-series also monitors the charge time in the charge mode. If charge is not

terminated within this time period, t(CHG), the bqTINY III-series turns off the charger and enunciates FAULT on the

STAT1 and STAT2 pins. See the DPPM operation under Case 1 for information on extending the safety timer

during DPPM operation. See theTimer Fault Recovery section for additional details.

Power Handoff

The design goal of the bqTINY III-series is to keep the system powered at all times (OUT pin); first, by either AC

or USB input––priority chosen by PSEL, and lastly by the battery. The input power source is only considered

present if its power-good status is low. There is a break-before-make switching action when switching between

AC to USB or USB to AC, for tSW-AC/USB, where the system capacitance should hold up the system voltage. Note

that the transfer of power occurs when the sources power-good pin goes high (open-drain output high = power

not present), which is when the input source drops to the battery's voltage. If the battery is below a useable

voltage, the system may reset. Typically, prior to losing the input power, the battery would have some useable

capacity, and a system reset would be avoided. If the battery was dead or missing, the system would lose power

unless the PSEL pin was used to transfer power prior to shutdown.

Product Folder Link(s): bq24030, bq24031 bq24032A, bq24035, bq24038

t(CHG) +K(TMR) R(TMR)

t(CHG−TREG) +t(CHG) V(SET)

V(SET*REG)

bq24030, bq24031

bq24032A, bq24035, bq24038

www.ti.com

............................................................................................................................................... SLUS618H –AUGUST 2004–REVISED OCTOBER 2009

If this is a concern, there is a simple external solution. Externally toggling the PSEL (bq24030/31/5/8) pin

immediately starts the power-transfer process (does not wait for input to drop to the battery's voltage). This can

be implemented by a resistor divider between the AC input and ground with the PSEL pin tied between R1 (top

resistor) and R2 (resistor to ground). The resistor values are chosen such that the divider voltage will be at 1 V

(PSEL threshold) when the AC has dropped to its critical voltage (user defined). An internal ~280-kΩresistor is

applied when PSEL < 1 V, to provide hysteresis. Choose R2 between 10 kΩand 60 kΩand V(ac-critical) between

3.5 V and 4.5 V. R1 can be found using the following equation:

R1 = R2 (V(ac-critical) – 1 V); V(ac-reset) = 1 + R1 (R2+280 k)/(280 k × R2);

Example: If R2 = 30 kΩand V(ac-critical) =4V;R1=30kΩ(4 V – 1 V) = 90 kΩ, V(ac-reset) = 1+ 90k (30 k+280

k)/(280 k×30 k) = 4.32 V. Therefore, for a 90 kΩ/30 kΩdivider, the bias on PSEL would switch power from AC to

USB (USBPG = L) when the VAC dropped to 4 V (independent of VBAT) and switches back when the VAC

recovers to 4.32 V. See Figure 6 through Figure 10.

Temperature Regulation and Thermal Protection

In order to maximize charge rate, the bqTINY III-series features a junction temperature regulation loop. If the

power dissipation of the bqTINY III-series results in a junction temperature greater than the TJ(REG) threshold

(125°C, typical), the bqTINY III-series throttles back on the charge current in order to maintain a junction

temperature around the TJ(REG) threshold. To avoid false termination, the termination detect function is disabled

while in this mode. The reduced charge current results in a longer charge time so the safety timer, t(CHG) is

extended inversely. This means that if the temperature regulation loop reduces the current to half of the

programmed charge rate, then the safety timer t(CHG) doubles. See Charge Timer Operation for more detail.

The bqTINY III-series also monitors the junction temperature, TJ, of the die and disconnects the OUT pin from

AC or USB inputs if TJexceeds T(SHTDWN). This operation continues until TJfalls below T(SHTDWN) by the

hysteresis level specified in the specification table.

The battery supplement mode has no thermal protection. The Q2 FET continues to connect the battery to the

output (system), if input power is not sufficient; however, a short-circuit protection circuit limits the battery

discharge current such that the maximum power dissipation of the part is not exceeded under typical design

conditions.

Charge Timer Operation

As a safety backup, the bqTINY III-series monitors the charge time in the charge mode. If the termination

threshold is not detected within the time period, t(CHG), the bqTINY III-series turns off the charger and enunciates

FAULT on the STAT1 and STAT2 pins. The resistor connected between the TMR and VSS, RTMR, determines

the timer period. The K(TMR) parameter is specified in the specifications table. In order to disable the charge timer,

eliminate RTMR, connect the TMR pin directly to the LDO pin. Note that this action eliminates the fast-charge

safety timer (it does not disable or reset the pre-charge safety timer), disables termination, and also clears a

fast-charge timer fault. TMR pin should not be left floating.

(6)

While in the thermal regulation mode or DPPM mode, the bqTINY III-series dynamically adjusts the timer period

in order to provide the additional time needed to fully charge the battery. This proprietary feature is designed to

prevent against early or false termination. The maximum charge time in this mode, t(CHG-TREG), is calculated by

Equation 7.

(7)

Note that because this adjustment is dynamic and changes as the ambient temperature changes and the charge

level changes, the timer clock is adjusted. It is difficult to estimate a total safety time without integrating the

above equation over the charge cycle. Therefore, understanding the theory that the safety time is adjusted

inversely proportionately with the charge current and the battery is a current-hour rating, the safety time

dynamically adjusts appropriately.

The V(SET) parameter is specified in the specifications table. V(SET-TREG) is the voltage on the ISET pin during the

thermal regulation or DPPM mode and is a function of charge current. (Note that charge current is dynamically

adjusted during the thermal regulation or DPPM mode.)

Product Folder Link(s): bq24030, bq24031 bq24032A, bq24035, bq24038

V(SET−TREG) +I(OUT) R(SET)

K(SET)

I(TERM) +V(TERM) K(SET)

RSET

bq24030, bq24031

bq24032A, bq24035, bq24038

SLUS618H –AUGUST 2004–REVISED OCTOBER 2009...............................................................................................................................................

www.ti.com

(8)

All deglitch times also adjusted proportionally to t(CHG-TREG).

Charge Termination and Recharge

The bqTINY III-series monitors the voltage on the ISET1 pin, during voltage regulation, to determine when

termination should occur (C/10 – 250 mV, C/25 – 100 mV). Once the termination threshold, I(TERM), is detected

the bqTINY III-series terminates charge. The resistor connected between the ISET1 and VSS, RSET, programs

the fast charge current level (C level, VISET1 = 2.5 V) and thus the C/10 and C/25 current termination threshold

levels. The V(TERM) and K(SET) parameters are specified in the specifications table. Note that this applies to both

AC and USB charging.

(9)

After charge termination, the bqTINY III-series re-starts the charge once the voltage on the OUT pin falls below

the V(RCH) threshold (VO(BAT-REG) –100 mV, typical). This feature keeps the battery at full capacity at all times.

LDO Regulator

The bqTINY III-series provides a 3.3-V LDO regulator. This regulator is typically used to power USB transceiver

or drivers in portable applications. Note that this LDO is only enabled when either AC or USB inputs are present.

If the CE pin is low (chip disabled) and AC or USB is present, the LDO is powered by the battery. This is to

ensure low input current when the chip is disabled.

Sleep and Standby Modes

The bqTINY III-series charger circuitry enters the low-power sleep mode if both AC and USB are removed from

the circuit. This feature prevents draining the battery into the bqTINY III-series during the absence of input

supplies. Note that in sleep mode, Q2 remains on (i.e., battery connected to the OUT pin) in order for the battery

to continue supplying power to the system.

The bqTINY III-series enters the low-power standby mode if while AC or USB is present, the CE input is low. In

this suspend mode, internal power FETs Q1 and Q3 (see Figure 4) are turned off, the BAT input is used to

power the system through OUT pin, and the LDO remains on (powered from output). This feature is designed to

limit the power drawn from the input supplies (such as USB suspend mode).

Charge Status Outputs

The open-drain (OD) STAT1 and STAT2 outputs indicate various charger operations as shown in Table 2. These

status pins can be used to drive LEDs or communicate to the host processor. Note that OFF indicates the

open-drain transistor is turned off. Note that this assumes CE = High.

Table 2. Status Pins Summary

CHARGE STATE STAT1 STAT2

Precharge in progress ON ON

Fast charge in progress ON OFF

Charge done OFF ON

Charge suspend (temperature), timer fault, and sleep mode OFF OFF

ACPG, USBPG Outputs (Power Good), bq24030/31/32A/35

The two open-drain pins, ACPG, USBPG (AC and USB power good), indicate when the AC adapter or USB port

is present and above the battery voltage. The corresponding output turns ON (low) when exiting sleep mode

(input voltage above battery voltage). This output is turned off in the sleep mode (open drain). The ACPG,

USBPG pins can be used to drive an LED or communicate to the host processor. Note that OFF indicates the

open-drain transistor is turned off.

Product Folder Link(s): bq24030, bq24031 bq24032A, bq24035, bq24038

bq24030, bq24031

bq24032A, bq24035, bq24038

www.ti.com

............................................................................................................................................... SLUS618H –AUGUST 2004–REVISED OCTOBER 2009

PG Output (Power Good), bq24038

The open-drain pin PG indicates when either the AC adapter or USB port is present and above the battery

voltage. This output is turned off in sleep mode (open drain). The PG pin can be used to drive a LED or

communicate with the host processor.

CE Input (Chip Enable)

The CE (chip enable) digital input is used to disable or enable the bqTINY III-series. A high-level signal on this

pin enables the chip, and a low-level signal disables the device and initiates the standby mode. The bqTINY

III-series enters the low-power standby mode when the CE input is low with either AC or USB present. In this

suspend mode, internal power FETs Q1 and Q3 (see Figure 4) are turned off; the battery (BAT pin) is used to

power the system via Q2 and the OUT pin which also powers the LDO. This feature is designed to limit the

power drawn from the input supplies (such as USB suspend mode).

VBSEL Input (Battery Voltage Selection), bq24038

The VBSEL (battery voltage select) digital input pin can be used to set the charge voltage to 4.2 V typical

(VBSEL = low) or 4.36 V typical (VBSEL = high). If VBSEL is left open, an internal current source pulldown

ensures that the charge voltage is set to 4.2 V typical.

DPPM Used As A Charge Disable Function

The DPPM pin can be used to disable the charge process. The DPPM pin has an output current source that,

when used with a resistor, sets the DPPM threshold. If the chosen resistance is too high, then the "DPPM-OUT"

voltage is programmed higher than the OUT pin regulation voltage and the part is put in DPPM mode. In this

mode the charging current is reduced until the OUT pin recovers to the DPPM_OUT threshold. Since the OUT

pin is in voltage regulation (below the DPPM-OUT threshold) it does not increase in amplitude, and the charge

current turns completely off. In DPPM mode the charge termination is diabled.

Note that the OUT pin regulates at 4.4V ±0.1V, with an adaptor input, on the bq24032A/bq24038 ICs, is switched

straight through on the bq24030/5 ICs (up to 6V); and, on USB inputs (all ICs) is switched straight through from

the USB input to the OUT pin.

If the DPPM pin is floated (resistor disconnected) then the DPPM pin will be driven high and the charge current

will go to zero. Note that this applies to both AC and USB charging. Another way to disable the charging is to

externally drive the DPPM pin high (to the OUT pin voltage).

Timer Fault Recovery

As shown in Figure 3, bqTINY III-series provides a recovery method to deal with timer fault conditions. The

following summarizes this method:

Condition 1: Charge voltage above recharge threshold (V(RCH)) and timeout fault occurs.

Recovery Method: bqTINY III-series waits for the battery voltage to fall below the recharge threshold. This could

happen as a result of a load on the battery, self-discharge, or battery removal. Once the battery falls below the

recharge threshold, the bqTINY III-series clears the fault and starts a new charge cycle. A POR or CE toggle also

clears the fault.

Condition 2: Charge voltage below recharge threshold (V(RCH)) and timeout fault occurs.

Recovery Method: Under this scenario, the bqTINY III-series applies the I(FAULT) current. This small current is

used to detect a battery removal condition and remains on as long as the battery voltage stays below the

recharge threshold. If the battery voltage goes above the recharge threshold, then the bqTINY III-series disables

the I(FAULT) current and executes the recovery method described for condition 1. Once the battery falls below the

recharge threshold, the bqTINY III-series clears the fault and starts a new charge cycle. A POR or CE toggle also

clears the fault.

Short-Circuit Recovery

The output can experience two types of short-circuit protection, one associated with the input and one with the

battery.

Product Folder Link(s): bq24030, bq24031 bq24032A, bq24035, bq24038

bq24030, bq24031

bq24032A, bq24035, bq24038

SLUS618H –AUGUST 2004–REVISED OCTOBER 2009...............................................................................................................................................

www.ti.com

If the output drops below ~1 V, an output short-circuit condition is declared and the input FETs (AC and USB) are

turned off. To recover from this state, a 500-Ωpullup resistor from each input is applied (switched) to the output.

To recover, the load on the output has to be reduced {Rload > 1 V × 500 Ω/ (Vin–Vout)} such that the pullup

resistor is able to lift the output voltage above 1 V, for the input FETs to be turned back on.

If the output drops 200 mV below the battery voltage, the battery FET is considered in short circuit and the

battery FET turns off. To recover from this state, there is a 10-mA ±8 mA current source from the battery to the

output. Once the output load is reduced, such that the current source can pick up the output within 200 mV of the

battery, the FET turns back on (As Vout increases in voltage the current source's drive drops toward 2 mA).

If the short is removed, and the minimum system load is still too large [R<(VBat –200 mV / 2mA)], the

short-circuit protection can be temporarily defeated. The battery short-circuit protection can be disabled

(recommended only for a short time) if the voltage on the DPPM pin is less than 1 V. Pulsing this pin below 1 V,

for a few microseconds, should be enough to recover.

This short-circuit disable feature was implemented mainly for power up when inserting a battery. Because the

BAT input voltage rises much faster than the OUT voltage (Vout<Vbat-200 mV), with most any capacitive load on

the output, the part can get stuck in short-circuit mode. Placing a capacitor between the DPPM pin and ground

slows the VDPPM rise time, during power up, and delays the short-circuit protection. Too large a capacitance on

this pin (too much of a delay) could allow too-high currents if the output was shorted to ground. The

recommended capacitance is 1 nF to 10 nF. The VDPPM rise time is a function of the 100-µA DPPM current

source, the DPPM resistor, and the capacitor added.

Product Folder Link(s): bq24030, bq24031 bq24032A, bq24035, bq24038

qJA +TJ*TA

P+ƪǒVIN *VOUTǓ ǒIOUT )IBATǓƫ)ƪǒVOUT *VBATǓ ǒIBATǓƫ

bq24030, bq24031

bq24032A, bq24035, bq24038

www.ti.com

............................................................................................................................................... SLUS618H –AUGUST 2004–REVISED OCTOBER 2009

APPLICATION INFORMATION

Selecting the Input and Output Capacitors

In most applications, all that is needed is a high-frequency decoupling capacitor on each input (AC and USB). A

0.1-μF ceramic capacitor, placed in close proximity to AC and USB to VSS pins, works well. In some applications

depending on the power supply characteristics and cable length, it may be necessary to add an additional 10-μF

ceramic capacitor to each input.

The bqTINY III-series only requires a small output capacitor for loop stability. A 0.1-μF ceramic capacitor placed

between the OUT and VSS pin is typically sufficient.

The integrated LDO requires a maximum of 1-μF ceramic capacitor on its output. The output does not require a

capacitor for a steady-state load but a 0.1-μF minimum capacitance is recommended.

It is recommended to install a minimum of 33-μF capacitor between the BAT pin and VSS (in parallel with the

battery). This ensures proper hot plug power up with a no-load condition (no system load or battery attached).

Thermal Considerations

The bqTINY III-series is packaged in a thermally enhanced MLP package. The package includes a QFN thermal

pad to provide an effective thermal contact between the device and the printed-circuit board (PCB). Full PCB

design guidelines for this package are provided in the application note entitled QFN/SON PCB Attachment

(SLUA271). The power pad should be tied to the VSS plane. The most common measure of package thermal

performance is thermal impedance (θJA) measured (or modeled) from the chip junction to the air surrounding the

package surface (ambient).

The mathematical expression for θJA is:

(10)

where

TJ= chip junction temperature

TA= ambient temperature

P = device power dissipation

Factors that can greatly influence the measurement and calculation of θJA include:

• whether or not the device is board mounted

• trace size, composition, thickness, and geometry

• orientation of the device (horizontal or vertical)

• volume of the ambient air surrounding the device under test and airflow

• whether other surfaces are in close proximity to the device being tested

The device power dissipation, P, is a function of the charge rate and the voltage drop across the internal power

FET. It can be calculated from Equation 11:

(11)

Due to the charge profile of Li-xx batteries, the maximum power dissipation is typically seen at the beginning of

the charge cycle when the battery voltage is at its lowest. See Figure 1. Typically the Li-ion battery's voltage

quickly (< 2 V minutes) ramps to approximately 3.5 V, when entering fast charge (1-C charge rate and battery

above V(LOWV)). Therefore, it is customary to perform the steady-state thermal design using 3.5 V as the

minimum battery voltage because the system board and charging device does not have time to reach a

maximum temperature due to the thermal mass of the assembly during the early stages of fast charge. This

theory is easily verified by performing a charge cycle on a discharged battery while monitoring the battery voltage

and chargers power pad temperature.

Product Folder Link(s): bq24030, bq24031 bq24032A, bq24035, bq24038

bq24030, bq24031

bq24032A, bq24035, bq24038

SLUS618H –AUGUST 2004–REVISED OCTOBER 2009...............................................................................................................................................

www.ti.com

PCB Layout Considerations

It is important to pay special attention to the PCB layout. The following provides some guidelines:

• To obtain optimal performance, the decoupling capacitor from input terminals to VSS and the output filter

capacitors from OUT to VSS should be placed as close as possible to the bqTINY III-series, with short trace

runs to both signal and VSS pins.

• All low-current VSS connections should be kept separate from the high-current charge or discharge paths

from the battery. Use a single-point ground technique incorporating both the small signal ground path and the

power ground path.

• The high-current charge paths into AC and USB and from the BAT and OUT pins must be sized appropriately

for the maximum charge current in order to avoid voltage drops in these traces.

• The bqTINY III-series is packaged in a thermally enhanced MLP package. The package includes a QFN

thermal pad to provide an effective thermal contact between the device and the printed-circuit board. Full

PCB design guidelines for this package are provided in the application note entitled QFN/SON PCB

Attachment (SLUA271).

Product Folder Link(s): bq24030, bq24031 bq24032A, bq24035, bq24038

bq24030, bq24031

bq24032A, bq24035, bq24038

www.ti.com

............................................................................................................................................... SLUS618H –AUGUST 2004–REVISED OCTOBER 2009

Changes from Revision G (Sept 2007) to Revision H ..................................................................................................... Page

• Changed "safety timer" to "fast-charge safety timer" in footnote, and expanded footnote description. ............................... 7

• Changed "safety timer" to "fast-charge safety timer" for TMR description ........................................................................... 9

• Changed "all safety timers" to "the fast-charge safety timer" (and added parenthetical statement regarding the

pre-charge safety timer) in Charge Timer Operation paragraph. ....................................................................................... 23

Product Folder Link(s): bq24030, bq24031 bq24032A, bq24035, bq24038

PACKAGING INFORMATION

Orderable Device Status (1) Package

Type Package

Drawing Pins Package

Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)

BQ24030RHLR ACTIVE QFN RHL 20 3000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

BQ24030RHLRG4 ACTIVE QFN RHL 20 3000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

BQ24031RHLR ACTIVE QFN RHL 20 3000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

BQ24031RHLRG4 ACTIVE QFN RHL 20 3000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

BQ24031RHLT ACTIVE QFN RHL 20 250 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

BQ24031RHLTG4 ACTIVE QFN RHL 20 250 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

BQ24032ARHLR ACTIVE QFN RHL 20 3000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

BQ24032ARHLRG4 ACTIVE QFN RHL 20 3000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

BQ24032ARHLT ACTIVE QFN RHL 20 250 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

BQ24032ARHLTG4 ACTIVE QFN RHL 20 250 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

BQ24035RHLR ACTIVE QFN RHL 20 3000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

BQ24035RHLRG4 ACTIVE QFN RHL 20 3000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

BQ24038RHLR ACTIVE QFN RHL 20 3000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

BQ24038RHLRG4 ACTIVE QFN RHL 20 3000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

BQ24038RHLT ACTIVE QFN RHL 20 250 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

BQ24038RHLTG4 ACTIVE QFN RHL 20 250 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

PACKAGE OPTION ADDENDUM

www.ti.com 11-Aug-2009

Addendum-Page 1

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF BQ24030, BQ24031 :

•Automotive: BQ24030-Q1,BQ24031-Q1

NOTE: Qualified Version Definitions:

•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

PACKAGE OPTION ADDENDUM

www.ti.com 11-Aug-2009

Addendum-Page 2

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

BQ24030RHLR QFN RHL 20 3000 330.0 12.4 3.8 4.8 1.3 8.0 12.0 Q1

BQ24031RHLR QFN RHL 20 3000 330.0 12.4 3.8 4.8 1.6 8.0 12.0 Q1

BQ24031RHLT QFN RHL 20 250 180.0 12.4 3.8 4.8 1.6 8.0 12.0 Q1

BQ24032ARHLR QFN RHL 20 3000 330.0 12.4 3.8 4.8 1.3 8.0 12.0 Q1

BQ24032ARHLT QFN RHL 20 250 180.0 12.4 3.8 4.8 1.3 8.0 12.0 Q1

BQ24035RHLR QFN RHL 20 3000 330.0 12.4 3.8 4.8 1.6 8.0 12.0 Q1

BQ24035RHLR QFN RHL 20 3000 330.0 12.4 3.8 4.8 1.3 8.0 12.0 Q1

BQ24038RHLR QFN RHL 20 3000 330.0 12.4 3.8 4.8 1.6 8.0 12.0 Q1

BQ24038RHLR QFN RHL 20 3000 330.0 12.4 3.8 4.8 1.3 8.0 12.0 Q1

BQ24038RHLT QFN RHL 20 250 180.0 12.4 3.8 4.8 1.6 8.0 12.0 Q1

BQ24038RHLT QFN RHL 20 250 180.0 12.4 3.8 4.8 1.3 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 18-Aug-2012

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

BQ24030RHLR QFN RHL 20 3000 370.0 355.0 55.0

BQ24031RHLR QFN RHL 20 3000 367.0 367.0 35.0

BQ24031RHLT QFN RHL 20 250 210.0 185.0 35.0

BQ24032ARHLR QFN RHL 20 3000 370.0 355.0 55.0

BQ24032ARHLT QFN RHL 20 250 195.0 200.0 45.0

BQ24035RHLR QFN RHL 20 3000 367.0 367.0 35.0

BQ24035RHLR QFN RHL 20 3000 370.0 355.0 55.0

BQ24038RHLR QFN RHL 20 3000 367.0 367.0 35.0

BQ24038RHLR QFN RHL 20 3000 370.0 355.0 55.0

BQ24038RHLT QFN RHL 20 250 210.0 185.0 35.0

BQ24038RHLT QFN RHL 20 250 195.0 200.0 45.0

PACKAGE MATERIALS INFORMATION

www.ti.com 18-Aug-2012

Pack Materials-Page 2

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