74ABT240CSCX_NL - Fairchild Semiconductor

March 1994

Revised March 2005

74ABT240 Octal Buffer/Line Driver with 3-STATE Outputs

74ABT240

Octal Buffer/Line Driver with 3-STATE Outputs

General Descript ion

The ABT240 is an inverting octal buffer and line driver

designed to be employed as a memory address driver,

clock drive r and bu s oriented transmitter or receive r which

provide s imp rov ed PC boa rd densit y.

Features

■Output sink capability of 64 mA, source capability of

32 mA

■Guaranteed latchup protection

■High impedance glitch free bus loading during entire

power up and power down cycle

■Nondestructive hot insertion capability

Ordering Code:

Device a l s o av ailable in Tape and Reel. Specify by append ing suffix lette r “X” to the ordering co de.

Pb-Free package per JEDEC J-STD-020B.

Connection Diagram Pin Descriptions

Truth Tables

HIGH Voltage Leve l

LOW Voltage Lev el

Immaterial

High Impedance

Order Number Package Number Package Description

74ABT240CSC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

74ABT240CSJ M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74ABT240CMSA MSA20 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide

74ABT240CMTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Pin Names Description

OE1, OE23-STATE Output

Enable Inputs

I0–I7Inputs

O0–O7Outputs

Inputs Outputs

OE1In(Pins 12, 14, 16, 18)

LL H

LH L

HX Z

Inputs Outputs

OE2In(Pins 3, 5, 7, 9)

LL H

LH L

HX Z

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74ABT240

Absolute Maximum Ratings(No te 1) Recommended Operating

Conditions

Note 1: Absolute maximum ratings are values beyond which the device

may be damaged or have its useful life impaired. Functional operation

under th es e conditi ons is not im plied.

Note 2: Either voltage limit or current l imit is sufficient to protect inputs.

DC Electrical Characteristics

Note 3: Guaranteed, but not tested.

Note 4: For 8 bits toggling, ICCD



0.8 mA/M Hz.

Storage Temperature



C to



150

Junction Temperature under Bias



C to



150

VCC Pin Potential to Ground Pin



0.5V to



7.0V

Input Voltage (Note 2)



0.5V to



7.0V

Input Curr en t (Note 2)



30 mA to



5.0 mA

Voltage Applied to Any Output

in the Disab led or

Power-Off State



0.5V to 5.5V

in the HIGH State



0.5V to VCC

Current Applied to Output

in LOW S tate (Max) twice the rated IOL (mA)

DC Latchup Source Current

(Across Comm Operating Range)



150 mA

Over Voltage Latchup (I/O) 10V

Free Air Ambient Temperature



C to



Supply Voltage



4.5V to



5.5V

Minimum Input Edge Rate (

Data Input 50 mV/ns

Enable Input 20 mV/ns

Symbol Parameter Min Typ Max Units VCC Conditions

VIH Input HIGH Voltage 2.0 V Recognized HIGH Signal

VIL Input LOW Voltage 0.8 V Recognized LOW Signal

VCD Input Clamp Diode Voltage



1.2 V Min IIN



18 mA

VOH Output HIGH Voltage 2.5 V Min IOH



3 mA

2.0 V Min IOH



32 mA

VOL Output LOW Voltage 0.55 V Min IOL

64 mA

IIH Input HIGH Current 1

AMax

VIN

2.7V (Note 3)

VCC

IBVI Input HIGH Current Breakdown Test 7

AMaxV

7.0V

IIL Input LOW Current



AMax

VIN

0.5V (Note 3)



0.0V

VID Input Leakage Test 4.75 V 0.0 IID

1.9

All Other Pins Grounded

IOZH Output Leakage Current 10



5.5V VOUT

2.7V; OEn

2.0V

IOZL Output Leakage Current



5.5V VOUT

0.5V; OEn

2.0V

IOS Output Short-Circuit Current



100



275 mA Max VOUT

0.0V

ICEX Output HIGH Leakage Current 50

AMaxV

OUT

VCC

IZZ Bus Drainage Test 100

A0.0V

OUT

5.5V; All Others GND

ICCH Power Supply Current 50

A Max All Outputs HIGH

ICCL Power Supply Current 30 mA Max All Outputs LOW

ICCZ Power Supply Current 50

AMaxOE

VCC;

All Others at VCC or Ground

ICCT Additional ICC/Input Outputs Enabled 1.5 mA

Max

VCC



2.1V

Outputs 3-STATE 1.5 mA Enable Input VI

VCC



2.1V

Outputs 3-STATE 50

A Data Input VI

VCC



2.1V

All Others at VCC or Ground

ICCD Dynamic ICC No Load mA/ Max Outputs Open

(Note 3) 0.1 MHz OEn

GND, (Note 4)

One Bit Toggling, 50% Duty Cycle

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74ABT240

AC Electrical Characteristics

Capacitance

Note 5: COUT is meas ured at frequency f

1 MHz, per MIL-STD-883, Method 3012.





C to



125



C to



VCC



5V VCC

4.5V–5.5V VCC

4.5V–5.5V

Symbol Parameter CL

50 pF CL

50 pF Units

Min Typ Max Min Max Min Max

tPLH Propagation Delay 1.0 4.8 0.8 5.5 1.0 4.8 ns

tPHL Data to Outputs 1.6 4.8 1.0 5.5 1.6 4.8

tPZH Output Enable 1.1 6.2 0.8 7.5 1.1 6.2 ns

tPZL Time 1.1 6.2 0.8 7.7 1.1 6.2

tPHZ Output Disable 1.8 6.4 1.0 7.5 1.8 6.4 ns

tPLZ Time 1.6 5.8 1.0 7.2 1.6 5.8

Symbol Parameter Typ Units Conditions

CIN Input Capacitance 5.0 pF VCC

COUT (Note 5) Output Capacitance 9.0 pF VCC

5.0V

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74ABT240

AC Loading

*Inclu des jig an d probe capac it anc e

Standard AC Test Load Test Input Signal Levels

Test Input Signal Requirements

AC W aveforms

Propagation Delay ,

Pulse W idth Waveforms

3-STATE Output HIGH

and LOW Enable and Disable Times

Propagation Delay Waveforms for

Inverting and Non-Inverting Functions

Setup Time, Hold Time

and Recovery Time Waveforms

Amplitude Rep. Rate tWtrtf

3.0V 1 MHz 500 ns 2.5 ns 2.5 ns

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74ABT240

Physical Dimensions inches (millimeters) unless otherwise noted

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

Package Number M20B

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74ABT240

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M20D

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74ABT240

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide

Package Numb er MSA20

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74ABT240 Octal Buffer/Line Driver wit h 3-STATE Output s

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Package Number MTC20

Fairchild does no t assume any responsibility for use of any circui try described, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLI CY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life suppor t de vices o r systems a re devices or syste ms

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instructions for use provided in the labeling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A critical compon ent in any componen t of a life support

device or system whose failure to perform can be rea-

sonabl y ex pect ed to cause the fa ilu re of the li fe su pp ort

device or system, or to affect its safety or effectiveness.