PIC12CE5XX 8-Pin, 8-Bit CMOS Microcontroller with EEPROM Data Memory Devices Included in this Data Sheet: * PIC12CE518 * PIC12CE519 High-Performance RISC CPU: * Only 33 single word instructions to learn * All instructions are single cycle (1 us) except for program branches which are two-cycle * Operating speed: DC - 4 MHz clock input DC - 1 us instruction cycle Pin Diagram: PDIP, SOIC, Windowed CERDIP ( voo[]1 3 8[}+Vss GP5/OSC1/CLKIN@[] 9 a a 7 =~cPo apaosc2ee[]3 @O 6 []}++ap1 GP3/MCLRVepe[]4 = = 5 [> GP2/TOCKI Memory Device EPROM | RAM | EEPROM Program Data Data PIC12CE518| 512x12 25x 8 16x8 PIC12CE519| 1024x 12 41x8 16x8 * 12-bit wide instructions * 8-bit wide data path * Special function hardware registers * Two-level deep hardware stack * Direct, indirect and relative addressing modes for data and instructions Peripheral Features: * 8-bit real-time clock/counter (TMRO) with 8-bit programmable prescaler * 1,000,000 erase/write cycle EEPROM data memory * EEPROM data retention > 40 years Special Microcontroller Features: * In-Circuit Serial Programming (ICSP) of pro- gram memory (via two pins) * Internal 4 MHz RC oscillator with programmable calibration * Power-on Reset (POR) * Device Reset Timer (DRT) * Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation * Programmable code-protection * Power saving SLEEP mode * Wake-up from SLEEP on pin change * Internal weak pull-ups on I/O pins * Internal pull-up on MCLR pin * Selectable oscillator options: - INTRC: Internal 4 MHz RC oscillator - EXTRC: External low-cost RC oscillator - XT: Standard crystal/resonator - LP: Power saving, low frequency crystal CMOS Technology: + Low-power, high-speed CMOS EPROM/EEPROM technology * Fully static design + Wide temperature range: - Commercial: 0C to +70C - Industrial: -40C to +85C - Extended: -40C to +125C * Wide operating voltage range: -Commercial: 2.5V to 5.5V -Industrial: 2.5V to 5.5V -Extended: 2.5V to 5.5V + Low power consumption -<2 mA typical @ 5V, 4 MHz - 15 pA typical @ 3V, 32 kHz - <1 pA typical standby current 1998 Microchip Technology Inc. Breliyinary DS40172B-page 1PIC12CE5XX TABLE OF CONTENTS 1.0 General DeSCriPtion 0... ee en nee nr nee e retire tne teenie tite tite serene esnneeeeneesieeseesessiessessseeesiresnreseeessieesiteseeesiressneeeees 2.0 PIC12CE5XX Device Varieties 3.0 Architectural Overview ............... 4.0 Memory Organization 00... en nn nn enn nents ner ne tnd e een tnesneeecoiennneesireseieesneesireeeeneenneetiiesee 5.0 VO Port nsec eeccecccecceeeceeeeeeeneeceeeeeesaeescesaecseceeceecareeaecerecaeecrecaeecessaesaceaeeacerevaeceeeeeseresaeeceesareceeeeseaeeneeceesseareeesaneesesiteseesinenieentea 6.0 EEPROM Peripheral Operation........ 7.0 TimerO Module and TMRO Register . 8.0 Special Features of the CPU............ ve 9.0 Instruction Set SUMMATY 00... en nn enn ne ne nner ete cnn nnee fires cone tntsnneeseieesneesieeeseneenneetitesee 10.0 Development Support... nnn nee nts ieee nnr etnies cnee nite tiieecnnennneenneseirenitesiriee 11.0 Electrical Characteristics - PIC12CE5XX ve 12.0 DC and AC Characteristics - PICTACESXX ooo... en ne ne rn nnn ester etniennnennneetiieesieenneesnnessieenneetiteee Tf 13.0 Packaging Information ............ ccc cceeeceeceeeeecceeeeeeceeeeeseceeecaeceeeeaeececsaeececsaesasneessasneecaeceseceeesesarecessaeecescetceserevaesesevareeresireceeenteerenaees 81 INOX ooo eee eee eee ern renee cree teeter teen ne tne ects sees ete eee eens ecaee cae ecee ges aeseaeeseeeeeeesaeeseeeeecneesateceeeecsnessnesesseesieesareseseeccneesireseeeessiessneseneees 87 PIC1I2CE5XX Product Identification SySterm ..........ccceececeeeceeeceeeeseeeeeeeeceeeeceneceeceseeaeceeecaeeneecareceeaeseesciescesnresesereverseeesieenresireeesenrenrenaees 89 To Our Valued Customers Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please check our Worldwide Web site at: http:/Avww.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number. e.g., DS30000A is version A of document DS30000. Errata An errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and recommended workarounds. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revi- sion of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: + Microchips Worldwide Web site; http:/Avww.microchip.com * Your local Microchip sales office (see last page) + The Microchip Corporate Literature Center; U.S. FAX: (602) 786-7277 When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include liter- ature number) you are using. Corrections to this Data Sheet We constantly strive to improve the quality of all our products and documentation. We have spent a great deal of time to ensure that this document is correct. However, we realize that we may have missed a few things. If you find any information that is missing or appears in error, please: Fill out and mail in the reader response form in the back of this data sheet. + E-mail us at webmaster@microchip.com. We appreciate your assistance in making this a better document. DS40172B-page 2 Prelininary 1998 Microchip Technology Inc.PIC12CE5XX 1.0 GENERAL DESCRIPTION The 8-pin PIC12CE5XX from Microchip Technology is a family of low-cost, high performance, 8-bit, fully static, EPROM/EEPROM-based CMOS microcontrollers. It employs a RISC architecture with only 33 single word/ single cycle instructions. All instructions are single cycle (1 ws) except for program branches which take two cycles. The PIC12CE5xXX delivers performance an order of magnitude higher than its competitors in the same price category. The 12-bit wide instructions are highly symmetrical resulting in 2:1 code compression over other 8-bit microcontrollers in its class. The easy to use and easy to remember instruction set reduces development time significantly. The PIC12CE5XX products are equipped with special features that reduce system cost and power require- ments. The Power-On Reset (POR) and Device Reset Timer (DRT) eliminate the need for external reset cir- cuitry. There are four oscillator configurations to choose from, including INTRC internal oscillator mode and the power-saving LP (Low Power) oscillator mode. Power saving SLEEP mode, Watchdog Timer and code protection features improve system cost, power and reliability. The PIC12CE5XX are available in the cost-effective One-Time-Programmable (OTP) versions which are suitable for production in any volume. The customer can take full advantage of Microchips price leadership in OTP microcontrollers while benefiting from the OTPs flexibility. The PIC12CE5XX products are supported by a full-fea- tured macro assembler, a software simulator, an in-cir- cuit emulator, a C compiler, fuzzy logic support tools, a low-cost development programmer, and a full fea- tured programmer. All the tools are supported on IBM PC and compatible machines. 1.1 Applications The PIC12CE5XxX series fits perfectly in applications ranging from sensory systems, gas detectors and security systems to low-power remote transmitters/ receivers. The EPROM programming technology makes customizing application programs (transmitter codes, appliance settings, receiver frequencies, etc.) extremely fast and convenient. While the EEPROM data memory technology allows for the changing of cal- ibrations factors and security codes, the small footprint 8-pin packages, for through hole or surface mounting, make this microcontroller series perfect for applications with space limitations. Low-cost, low-power, high per- formance, ease of use and |/O flexibility make the PIC12CE5XxX series very versatile even in areas where no microcontroller use has been considered before (e.g., timer functions, replacement of glue logic and PLDs in larger systems, coprocessor applications). 1998 Microchip Technology Inc. Preiininary DS40172B-page 3PIC12CE5XX TABLE 1-1: PIC12CXXX & PIC12CEXXX FAMILY OF DEVICES PIC12C508(A) | PIC12C509(A) | PIC12CE518 | PIC12CE519} PIC12C671 | PIC12C672 | PIC12CE673 | PIC12CE674 Maximum 4 4 4 4 10 10 10 10 Frequency of Operation (MHz) EPROM 512 x12 1024 x 12 512x112 1024 x 12 1024 x 14 2048 x 14 1024 x 14 2048 x 14 Program Memory RAM Data 25 4 25 4 128 128 128 128 Memory (bytes) EEPROM _ _ 16 16 _ _ 16 16 Data Memory (bytes) Timer TMRO TMRO TMRO TMRO TMRO TMRO TMRO TMRO Module(s) A/D Con- _ _ _ 4 4 4 4 verter (8-bit) Channels yagi latte) Wake-up Yes Yes Yes Yes Yes Yes Yes Yes from SLEEP on pin change Interrupt _ _ 4 4 4 4 Sources etait \/O Pins 5 5 5 5 5 5 5 5 Input Pins os os os os os os os os Internal Yes Yes Yes Yes Yes Yes Yes Yes Pull-ups In-Circuit Yes Yes Yes Yes Yes Yes Yes Yes Serial Programming Number of 33 33 33 33 35 35 35 35 Instructions Packages 8-pin DIP, 8-pin DIP, 8-pin DIP, 8-pin DIP, 8-pin DIP, 8-pin DIP, 8-pin DIP, 8-pin DIP, JW, SOIC JW, SOIC JW, SOIC JW, SOIC JW, SOIC Jw, Soic [JW Jw All PIC12CXXX & PIC12CEXXX devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. All PIC12CXXX & PIC12CEXXX devices use serial programming with data pin GPO and clock pin GP1. meme meen DS40172B-page 4 Prelininary 1998 Microchip Technology Inc.PIC12CE5XX 2.0 PIC12CE5XX DEVICE VARIETIES A variety of packaging options are available. Depending on application and production requirements, the proper device option can be selected using the information in this section. When placing orders, please use the PIC12CE5XX Product Identification System at the back of this data sheet to specify the correct part number. 2.1 UV Erasable Devices The UV erasable version, offered in windowed cerdip package, is optimal for prototype development and pilot programs. The UV erasable version can be erased and reprogrammed to any of the configuration modes. Note: Please note that erasing the device will also erase the pre-programmed internal calibration value for the internal oscillator. The calibration value must be saved prior to erasing the part. Microchip's PICSTART PLUS and PRO MATE pro- grammers. all support programming of the PIC12CE5XxX. Third party programmers also are avail- able; refer to the Microchip Third Party Guide for a list of sources. 2.2 One-Time-Programmable (OTP) Devices The availability of OTP devices is especially useful for customers who need the flexibility for frequent code updates or small volume applications. The OTP devices, packaged in plastic packages permit the user to program them once. In addition to the program memory, the configuration bits must also be programmed. 2.3 Quick-Turnaround-Production (QTP) Devices Microchip offers a QTP Programming Service for factory production orders. This service is made available for users who choose not to program a medium to high quantity of units and whose code patterns have stabilized. The devices are identical to the OTP devices but with all EPROM locations and fuse options already programmed by the factory. Certain code and prototype verification procedures do apply before production shipments are available. Please con- tact your local Microchip Technology sales office for more details. 2.4 Serialized Quick-Turnaround Production (SQTP=) Devices Microchip offers a unique programming service where a few user-defined locations in each device are programmed with different serial numbers. The serial numbers may be random, pseudo-random or sequential. Serial programming allows each device to have a unique number which can serve as an entry-code, password or ID number. 1998 Microchip Technology Inc. Preiininary DS40172B-page 5PIC12CE5XX NOTES: DS40172B-page 6 Prelininary 1998 Microchip Technology Inc.PIC12CE5XX 3.0 ARCHITECTURAL OVERVIEW The high performance of the PIC12CE5XX family can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC12CE5XX uses a Harvard architecture in which program and data are accessed on separate buses. This improves bandwidth over traditional von Neumann architecture where program and data are fetched on the same bus. Separating program and data memory further allows instructions to be sized differently than the 8-bit wide data word. Instruction opcodes are 12-bits wide making it possible to have all single word instructions. A 12-bit wide program memory access bus fetches a 12-bit instruction in a single cycle. A two-stage pipeline overlaps fetch and execution of instructions. Consequently, all instructions (33) execute in a single cycle (1s @ 4MHz) except for program branches. The PIC12CE5XX can directly or indirectly address its register files and data memory. All special function registers including the program counter are mapped in the data memory. The PIC12CE5XX has a highly orthogonal (symmetrical) instruction set that makes it possible to carry out any operation on any register using any addressing mode. This symmetrical nature and lack of special optimal situations make programming with the PIC12CE5XX simple yet efficient. In addition, the learning curve is reduced significantly. The PIC12CE5XX contains a 16 X 8 EEPROM memory array for storing non-volatile information such as calibration data or security codes. This memory has an endurance of 1,000,000 erase/write cycles and a retention of 40+ years. The table below lists program memory (EPROM), data memory (RAM), and non-volatile (EEPROM) for each PIC12CE5XX device. Memory Device EPROM RAM EEPROM Program Data Data PIC12CE518 512x 12 25x 8 16x8 PIC12CE519 | 1024 X 12 41X8 16X8 The PIC12CE5XX device contains an 8-bit ALU and working register. The ALU is a general purpose arithmetic unit. It performs arithmetic and Boolean functions between data in the working register and any register file. The ALU is 8-bits wide and capable of addition, subtraction, shift and logical operations. Unless otherwise mentioned, arithmetic operations are two's complement in nature. In two-operand instructions, typically one operand is the W (working) register. The other operand is either a file register or an immediate constant. In single operand instructions, the operand is either the W register or a file register. The W register is an 8-bit working register used for ALU operations. It is not an addressable register. Depending on the instruction executed, the ALU may affect the values of the Carry (C), Digit Carry (DC), and Zero (Z) bits in the STATUS register. The C and DC bits operate as a borrow and digit borrow out bit, respectively, in subtraction. See the SUBWF and ADDWF instructions for examples. A simplified block diagram is shown in Figure 3-1, with the corresponding device pins described in Table 3-1. 1998 Microchip Technology Inc. Preiininary DS40172B-page 7PIC12CE5XX FIGURE 3-1: PIC12CE5XX BLOCK DIAGRAM 12 Data Bus GPIO EPROM Program Counter GPo 512 x 120r GP1 Dee RAM Ll GP2/TOCKI Memory STACK1 eer 4 l4[| GP3/MCLR/VeP STACK2 GP4/O0SC2 Regisiers GP5/OSC1/CLKIN Program 40 Bus 5 a / o Instruction reg | Direct Addr 7 16X8 EEPROM Data 8 Memory F 3. Device Reset V Timer Instruction Decode & MO Control Power-on eset Timin Watchd OSCI/CLKIN SS Generation Kk) timers OSCc2 Internal RC | OSC MCLR TimerO Vpbb, Vss f DS40172B-page 8 Prelininary 1998 Microchip Technology Inc.PIC12CE5XX TABLE 3-1: PIC12CE5XX PINOUT DESCRIPTION Name DIP Pin # solic Pin # VO/P Type Buffer Type Description GPO 7 7 VO TTL/ST Bi-directional I/O port/ serial programming data. Can be software programmed for internal weak pull-up and wake-up from SLEEP on pin change. This buffer is a Schmitt Trigger input when used in serial programming mode. GP1 VO TTL/ST Bi-directional I/O port/ serial programming clock. Can be software programmed for internal weak pull-up and wake-up from SLEEP on pin change. This buffer is a Schmitt Trigger input when used in serial programming mode. GP2/TOCKI VO ST Bi-directional I/O port. Can be configured as TOCKI. GP3/MCLR/VPpP TTL/ST Input port/master clear (reset) input/programming volt- age input. When configured as MCLR, this pin is an active low reset to the device. Voltage on MCLR/VPP must not exceed VDD during normal device operation. Can be software programmed for internal weak pull-up and wake-up from SLEEP on pin change. Weak pull- up always on if configured as MCLR. Input buffers are Schmitt Trigger when configured in MCLR mode. GP4/OSC2 VO TTL Bi-directional I/O port/oscillator crystal output. Con- nections to crystal or resonator in crystal oscillator mode (XT and LP modes only, GPIO in other modes). GP5/OSC1/CLKIN VO TTL/ST Bidirectional |O port/oscillator crystal input/external clock source input (GPIO in Internal RC mode only, OSC1 in all other oscillator modes). TTL input when GPIO, ST input in external RC oscillator mode. VDD ; ; P Positive supply for logic and I/O pins Vss 8 8 P Ground reference for logic and I/O pins Legend: | = input, O = output, I/O = input/output, P = power, = not used, TTL =TTL input, ST = Schmitt Trigger input 1998 Microchip Technology Inc. Preiininary DS40172B-page 9PIC12CE5XX 3.1 Clocking Scheme/Instruction Cycle The clock input (OSC1/CLKIN pin) is internally divided by four to generate four non-overlapping quadrature clocks namely Q1, Q2, Q3 and Q4. Internally, the program counter is incremented every Q1, and the instruction is fetched from program memory and latched into instruction register in Q4. It is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow is shown in Figure 3-2 and Example 3-1. 3.2 Instruction Flow/Pipelining An Instruction Cycle consists of four Q cycles (Q1, Q2, Q3 and @4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle while decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g., GOTO) then two cycles are required to complete the instruction (Example 3-1). A fetch cycle begins with the program counter (PC) incrementing in Q1. In the execution cycle, the fetched instruction is latched into the Instruction Register (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3, and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write). FIGURE 3-2: _CLOCK/INSTRUCTION CYCLE | Qt | Q2 | Q3 |] Q4 1 ai | G2] A] a4! at] GQ {asi} ast osct MUS LS VS LIAS VS VS AVI Tr Th Tr Fd Qi yo" yy \ y.CN | Q2 | fr | / \ | Tr | | Internal Qs " - , i" . pnase Q4 \ fh fh fo PC } PC { PC+14 ( PC+2 Fetch INST (PC) | | Execute INST (PC-1) Fetch INST (PC+1) | Execute INST (PC) Fetch INST (PC-+2) Execute INST (PC+1) EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW 1. MOVLW 03H Fetch 1 Execute 1 2. MOVWF GPIO Fetch 2 Execute 2 3. CALL SUB_1 Fetch 3 Execute 3 4. BSF GPIO, BITI Fetch 4 Flush Fetch SUB_1] Execute SUB_1 All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is flushed from the pipeline while the new instruction is being fetched and then executed. DS40172B-page 10 Prelininary 1998 Microchip Technology Inc.PIC12CE5XX 4.0 MEMORY ORGANIZATION FIGURE 4-1: PROGRAM MEMORY MAP . ws AND STACK FOR THE PIC12CE5XX memory is organized into program mem- PIC12CE5XX ory and data memory. For devices with more than 512 bytes of program memory, a paging scheme is used. PC<l10> Program memory pages are accessed using one STA- . . ; CALL, RETLW 12 TUS register bit. For the PIC12CE519 with a data memory register file of more than 32 registers, a bank- Stack Level 1 ing scheme is used. Data memory banks are accessed Stack Level 2 using the File Select Register (FSR). 4.1 Program Memory Organization T Reset Vector (note 1) o000h The PIC12CE5XX devices have a 12-bit Program Counter (PC) capable of addressing a 2K x 12 On-chip Program program memory space. Memory Only the first 512 x 12 (0000h-01FFh) for the = I PIC12CE518 and 1K x 12 (0000h-03FFh) for the 5 8 512 Word (PIC12CE518 PIC12CE519 are physically implemented. Refer to =o | {2 Word (PIC12CE518) | o1FFh Figure 4-1. Accessing a location above these a 0200h boundaries will cause a wrap-around within the first 512 x 12 space (PIC12CE518) or 1K x 12 space (PIC12CE519). The effective reset vector is at 000h, (see Figure 4-1). Location O1FFh (PIC12CE518) or location O3FFh (PIC12CE519), the hardwired reset y | 1024 Word (PIC12CE519) | ogFFh On-chip Program Memory vector location, contains the internal clock oscillator ~~ 0400h calibration value. This value is set at Microchip and should never be overwritten. Upon reset, the oo oO MOVLW XX is executed, the PC wraps to location DD 0000h, thus making 0000h the effective reset vector. oEFh Note 1: Address 0000h becomes the effective reset vector. Location 01FFh (PIC12CE518) or location O3FFh (PIC12CE519) contains the MOVLW XX INTRC oscillator calibration value. 1998 Microchip Technology Inc. Preliminary DS40172B-page 11PIC12CE5XX 4.2 Data Memory Organization Data memory is composed of registers, or bytes of RAM. Therefore, data memory for a device is specified by its register file. The register file is divided into two functional groups: special function registers and general purpose registers. The special function registers include the TMRO register, the Program Counter (PC), the Status Register, the I/O registers (ports), and the File Select Register (FSR). In addition, special purpose registers are used to control the I/O port configuration and prescaler options. The general purpose registers are used for data and control information under command of the instructions. For the PIC12CE518, the register file is composed of 7 special function registers and 25 general purpose registers (Figure 4-2). For the PIC12CE519, the register file is composed of 7 special function registers, 41 general purpose registers, and 16 general purpose registers that may be addressed using a banking scheme (Figure 4-3). 4.2.1 GENERAL PURPOSE REGISTER FILE The general purpose register file is accessed either directly or indirectly through the file select register FSR (Section 4.8). FIGURE 4-3: PIC12CE519 REGISTER FILE MAP FIGURE 4-2: PIC12CE518 REGISTER FILE MAP File Address 00h INDFO) Oth TMRO 02h PCL 03h STATUS 04h FSR 05h OSCCAL 06h GPIO O7h General Purpose Registers 1Fh Note 1: Nota physical register. See Indi- rect Data Addressing, Section 4.8. FSR<6:5> 00 O1 File Address INDFO | 00h Oth TMRO 02h PCL 03h STATUS 04h FSR 20h Addresses map back to addr 05h OSCCAL 06h GPIO O7h General Purpose OFh Registers in Bank 0. 2Fh 10h General 30h General Note 1: 1Fh Purpose Registers Purpose Registers 3Fh Bank 0 Bank 1 Not a physical register. See Indirect Data Addressing, Section 4.8. DS40172B-page 12 Prelhninary 1998 Microchip Technology Inc.PIC12CE5XX 4.2.2 The Special Function Registers (SFRs) are registers used by the CPU and peripheral functions to control the operation of the device (Table 4-1). SPECIAL FUNCTION REGISTERS The special registers can be classified into two sets. The special function registers associated with the core functions are described in this section. Those related to the operation of the peripheral features are described in the section for each peripheral feature. TABLE 4-1: SPECIAL FUNCTION REGISTER (SFR) SUMMARY Value on Value on Power-On all other Address| Name Bit7 | Bit | Bits | Bit4 | Bits Bit2 | Bit1 | Bito Reset Resets) N/A TRIS = _ GP5 | GP4 GP3 GP2 GP1 | GPO | --11 1111 --11 1111 Contains control bits to configure Timer0, TimerO/WDT prescaler, wake- N/A OPTION up on change, and weak pull-ups 1111 1111 1111 1111 00h INDF Uses contents of FSR to address data memory (not a physical register) XXKX XKXXK uuuu uuuu Oth TMRO 8-bit real-time clock/counter XXXX XXXX uuuu uuuu 02h = | PCL Low order 8 bits of PC 1111 1221 } 11112 1211 03h status | GPWUF | PAO | TO | PD | Z | DC | c | 0001 1xxx | goog quuu) FSR 04h (12CE518) |Indirect data memory address pointer llix xxxx T1lu uuuu FSR 04h (12CE519) | Indirect data memory address pointer 110x xxxx Tluu uuuu 05h OSCCAL CAL5 | CAL4 | CAL3 | CAL2} CAL1 CALO _ 1000 00-- uuuu uu-- 06h GPIO SCL SDA | GP5 | GP4 GP3 GP2 GP1 | GPO | lixx xxxx 1luu uuuu Legend: Shaded boxes = unimplemented or unused, = unimplemented, read as '0' (if applicable) Note 1: Note 2: Note 3: x = unknown, u = unchanged, gq = see the tables in Section 8.7 for possible values. The upper byte of the Program Counter is not directly accessible. See Section 4.6 for an explanation of how to access these bits. Other (non-power up) resets include external reset through MCLR, WDT, and wake-up on pin change reset. If reset was due to wake-up on pin change then bit 7 = 1. All other resets will cause bit 7 = 0. 1998 Microchip Technology Inc. Preiininary DS40172B-page 13PIC12CE5XX 4.2.3 EEPROM DATA MEMORY The PIC12CE518 and PIC12CE519 each have 16 bytes of EEPROM data memory. The EEPROM data memory supports a bi-directional 2-wire bus and data transmission protocol. Refer to Section 6.0 on EEPROM Peripherals. For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as 000u uluu (where u = unchanged). It is recommended, therefore, that only BCF BSF and MOVWF instructions be used to alter the STATUS register because these instructions do not affect the Z, DC or C bits from the STATUS register. For other instructions, which do affect STATUS bits, see 4.3 STATUS Register This register contains the arithmetic status of the ALU, the RESET status, and the page preselect bit for program memories larger than 512 words. Instruction Set Summary. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. FIGURE 4-4: STATUS REGISTER (ADDRESS:03h) RW-0 _R/W-0_sRYW-0=R- R-+4 RW-x R/W-x_R/W-x [apwuF| | Pao | TO | PD | z | oe | c R = Readable bit bit7 6 5 4 3 2 1 bito | W = Writable bit - n= Value at POR reset bit 7: GPWUF: GPIO reset bit 1 = Reset due to wake-up from SLEEP on pin change 0 = After power up or other reset bit 6: Unimplemented bit 5: PAO: Program page preselect bits 1 = Page 1 (200h - 3FFh) - PIC12CE519 0 = Page 0 (000h - 1FFh) - PIC12CE518 and PIC12CE519 Each page is 512 bytes. Using the PAO bit as a general purpose read/write bit in devices which do not use it for program page preselect is not recommended since this may affect upward compatibility with future products. TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = AWDT time-out occurred PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction Z: Zero bit 1 =The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 4: bit 3: bit 2: bit 1: DC: Digit carry/borrow bit (for ADDWF and SUBWF instructions) ADDWF 1 =Acarry from the 4th low order bit of the result occurred 0 =Acarry from the 4th low order bit of the result did not occur SUBWF 1 = A borrow from the 4th low order bit of the result did not occur 0 = A borrow from the 4th low order bit of the result occurred bit 0: C: Carry/borrow bit (for ADDWEF, SUBWF and RRF, RLF instructions) ADDWF SUBWF 1 =Acarry occurred 1 = A borrow did not occur 0 = Acarry did not occur 0 = A borrow occurred RRF or RLF Load bit with LSB or MSB, respectively DS40172B-page 14 Prelininary 1998 Microchip Technology Inc.PIC12CE5XX 4.4 OPTION Register . . ; ; ; Note: [f TRIS bit is set to 0, the wake-up on The OPTION register is a 8-bit wide, write-only change and pull-up functions are disabled register which contains various control bits to for that pin: i.e., note that TRIS overrides configure the Timer0/WDT prescaler and Timer0. OPTION control of GPPU and GPWU. By executing the OPTION instruction, the contents of Note: If the TOCS bit is set to 1. GP2 is forced to the W register will be transferred to the OPTION be an input even if TRIS GPe 0 register. A RESET sets the OPTION<7:0> bits. FIGURE 4-5: OPTION REGISTER W-1 W-1 W-1 W-1 W-1 W-1 W-1 W-1 | GPwu | GPPU | Tocs | TosE | PSA PS2 PS1 PSO W = Writable bit bit7 6 5 4 3 2 1 bitO U = Unimplemented bit bit 7: GPWU: Enable wake-up on pin change (GPO, GP1, GP3) 1 = Disabled 0 = Enabled bit 6: GPPU: Enable weak pull-ups (GPO, GP1, GP3) 1 = Disabled 0 = Enabled bit 5: TOCS: TimerO clock source select bit 1 = Transition on TOCKI pin 0 = Transition on internal instruction cycle clock, Fosc/4 bit 4: TOSE: TimerO source edge select bit 1 = Increment on high to low transition on the TOCKI pin 0 = Increment on low to high transition on the TOCKI pin bit 3: PSA: Prescaler assignment bit 1 = Prescaler assigned to the WDT 0 = Prescaler assigned to Timer0 bit 2-0: PS2:PS0: Prescaler rate select bits Bit Value TimerO Rate WDT Rate 000 1:2 1:1 001 1:4 1:2 010 1:8 1:4 011 1:16 1:8 100 1:32 1:16 101 1:64 1:32 110 1:128 1:64 111 1: 256 1:128 -n =Value at POR reset Reference Table 4-1 for other resets. 1998 Microchip Technology Inc. Preliminary DS40172B-page 15PIC12CE5XX 45 OSCCAL Register The Oscillator Calibration (OSCCAL) register is used to calibrate the internal 4 MHz oscillator. It contains six bits for calibration. Increasing the CAL value increases the frequency. FIGURE 4-6: _OSCCAL REGISTER (ADDRESS 05Fh) RW-1 RAW-0 RAW-0RYW-0RIW-0 RW U-0 U-0 | cats | cata | cats | cate | cai | cao | R_ = Readable bit bit7 bito |W = Writable bit U = Unimplemented bit, read as 0 -n = Value at POR reset bit 7-2: CAL<5:0>: Calibration bit 1-0: unimplemented DS40172B-page 16 Prelininary 1998 Microchip Technology Inc.PIC12CE5XX 4.6 Program Counter As a program instruction is executed, the Program Counter (PC) will contain the address of the next program instruction to be executed. The PC value is increased by one every instruction cycle, unless an instruction changes the PC. For a GOTO instruction, bits 8:0 of the PC are provided by the GoTo instruction word. The PC Latch (PCL) is mapped to PC<7:0>. Bit 5 of the STATUS register provides page information to bit 9 of the PC (Figure 4- 7). For a CALL instruction, or any instruction where the PCL is the destination, bits 7:0 of the PC again are provided by the instruction word. However, PC<8> does not come from the instruction word, but is always cleared (Figure 4-7). Instructions where the PCL is the destination, or Modify PCL instructions, include MoVWF PC, ADDWF PC, and BSF PC,5. Note: Because PC<8> is cleared in the CALL instruction, or any Modify PCL instruction, all subroutine calls or computed jumps are limited to the first 256 locations of any pro- gram memory page (512 words long). FIGURE 4-7: LOADING OF PC BRANCH INSTRUCTIONS - PIC12CE518/CE519 GOTO Instruction 1110 9 8 7 0 pel | | | | PCL | A A Instruction Word PAO 7 0 STATUS 4.6.1 EFFECTS OF RESET The Program Counter is set upon a RESET, which means that the PC addresses the last location in the last page i.e., the oscillator calibration instruction. After executing MOVLW XxX, the PC will roll over to location 00h, and begin executing user code. The STATUS register page preselect bits are cleared upon a RESET, which means that page 0 is pre- selected. Therefore, upon a RESET, a_ GoTo instruction will automatically cause the program to jump to page 0 until the value of the page bits is altered. 4.7 Stack PIC12CE5XX devices have a 12-bit wide hardware push/pop stack. A CALL instruction will push the current value of stack 1 into stack 2 and then push the current program counter value, incremented by one, into stack level 1. If more than two sequential CALLs are executed, only the most recent two return addresses are stored. A RETLW instruction will pop the contents of stack level 1 into the program counter and then copy stack level 2 contents into level 1. If more than two sequential RETLWs are executed, the stack will be filled with the address previously stored in level 2. Note that the W register will be loaded with the literal value specified in the instruction. This is particularly useful for the implementation of data look-up tables within the program memory. Note 1: There are no STATUS bits to indicate stack overflows or stack underflow conditions. Note 2: There are no. instructions mnemonics called PUSH nor POP. These are actions that occur from the execution of the CALL and RETLW instructions. CALL or Modify PCL Instruction 1110 9 87 0 poL{ | | | PCL | Toad Instruction Word Reset to 0 PAO 7 0 [2S TESS) STATUS 1998 Microchip Technology Inc. Preiininary DS40172B-page 17PIC12CE5XX 48 Indirect Data Addressing: INDF and FSR Registers The INDF register is not a physical register. Addressing INDF actually addresses the register whose address is contained in the FSR register (FSR is a pointer). This is indirect addressing. EXAMPLE 4-1: INDIRECT ADDRESSING * Register file 07 contains the value 10h * Register file 08 contains the value OAh * Load the value 07 into the FSR register * A read of the INDF register will return the value of 10h * Increment the value of the FSR register by one (FSR = 08) * A read of the INDR register now will return the value of OAh. Reading INDF itself indirectly (FSR = 0) will produce 00h. Writing to the INDF register indirectly results in a no-operation (although STATUS bits may be affected). A simple program to clear RAM locations 10h-1Fh using indirect addressing is shown in Example 4-2. EXAMPLE 4-2: HOWTO CLEAR RAM USING INDIRECT ADDRESSING moviw 0x10 ; initialize pointer movwt FSR ; to RAM NEXT clrf INDF ; clear INDF register incf FSR,F jinc pointer btfse FSR, 4 ;all done? goto NEXT ;NO, clear next CONTINUE ;YES, continue The FSR is a 5-bit wide register. It is used in conjunction with the INDF register to indirectly address the data memory area. The FSR<4:0> bits are used to select data memory addresses 00h to 1Fh. PIC12CE518: Does not use banking. FSR<7:5> are unimplemented and read as '1's. PIC12CE519: Uses FSR<5>. Selects between bank 0 and bank 1. FSR<7:6> is unimplemented, read as '1. Indirect Addressing 6 5 4 (FSR) O location select bank 01 Addr map back to addresses in Bank 0. 3Fh FIGURE 4-8: DIRECT/INDIRECT ADDRESSING Direct Addressing (FSR) 6 5 4 (opcode) 0 bank select __ location select \ | 00 00h Data OFh Memory) 10h 1Fh Bank 0 Note 2: PIC12CE519 only Note 1: For register map detail see Section 4.2. Bank 1@) DS40172B-page 18 Prelhninary 1998 Microchip Technology Inc.PIC12CE5XX 5.0 I/O PORT As with any other register, the I/O register can be written and read under program control. However, read instructions (.g., MOVF GPIO,W) always read the I/O pins independent of the pins input/output modes. On RESET, all GPIO ports are defined as input (inputs are at hi-impedance) since the I/O control registers are all set. 5.1 GPIO GPIO is an 8-bit I/O register. Only the low order 6 bits are used (GP5:GP0) for pin control. Bits 6 and 7 (SDA and SCL) are used by the EEPROM peripheral. Refer to Section 6.0 for use of SDA and SCL. Please note that GP3 is an input only pin. The configuration word can set several |/Os to alternate functions. When acting as alternate functions the pins will read as 0 during port read. Pins GPO, GP1, and GP3 can be configured with weak pull-ups and also with wake-up on change. The wake-up on change and weak pull-up functions are not pin selectable. If pin 4 is configured as MCLR, weak pull-up is always on and wake-up on change for this pin is not enabled. 5.2 TRIS Register The output driver control register is loaded with the contents of the W register by executing the TRIS f instruction. A 1' from a TRIS register bit puts the corresponding output driver in a hi-impedance mode. A O' puts the contents of the output data latch on the selected pins, enabling the output buffer. The exceptions are GP3 which is input only and GP2 which may be controlled by the option register, see Figure 4-5. Note: A read of the ports reads the pins, not the out- put data latches. That is, if an output driver on a pin is enabled and driven high, but the exter- nal system is holding it low, a read of the port will indicate that the pin is low. The TRIS registers are write-only and are set (output drivers disabled) upon RESET. 5.3 I/O Interfacing The equivalent circuit for an I/O port pin is shown in Figure 5-1. All port pins, except GP3 which is input only, may be used for both input and output operations. For input operations these ports are non-latching. Any input must be present until read by an input instruction (e.g., MOVF GPIO,W). The outputs are latched and remain unchanged until the output latch is rewritten. To use a port pin as output, the corresponding direction control bit in TRIS must be cleared (= 0). For use as an input, the corresponding TRIS bit must be set. Any I/O pin (except GP3) can be programmed individually as input or output. FIGURE 5-1: EQUIVALENT CIRCUIT FOR A SINGLE I/O PIN Data Bus D Q Data WR Latch Yoo Port =~ R in <9 D Q P TRIS Latch Vss TRIS f ck 8 Reset | (2) RD Port Note 1: I/O pins have protection diodes to VDD and Vss. Note 2: See Table 3-1 for buffer type. TABLE 5-1: SUMMARY OF PORT REGISTERS Value on Value on Power-On all other Address Name Bit 7 Bit 6 Bit5 Bit4 | Bit3 | Bit2 | Bit1 | Bito Reset Resets N/A TRIS _ _ \/O control registers --11 1111 --11 1111 N/A OPTION| GPWU | GPPU} TOCS | TOSE |. PSA PS2 PS1 PSO 1111 1111 1111 1111 03H STATUS | GPWUF| PAO TO PD Z DC Cc 0001 1xxx goog quuu 06h GPIO SCL SDA GP5 GP4 GP3 GP2 GP1 GPO llxx xxxx Tluu uuuu Legend: Shaded cells not used by Port Registers, read as 0, = unimplemented, read as '0', x = unknown, u = unchanged, q = see tables in Section 8.7 for possible values. Note 1: If reset was due to wake-up on pin change then bit 7 = 1. All other resets will cause bit 7 = 0. 1998 Microchip Technology Inc. Preiininary DS40172B-page 19PIC12CE5XX 5.4 1/O Programming Considerations 5.4.1 BI-DIRECTIONAL I/O PORTS Some instructions operate internally as read followed by write operations. The BCF and BSF instructions, for example, read the entire port into the CPU, execute the bit operation and re-write the result. Caution must be used when these instructions are applied to a port where one or more pins are used as input/outputs. For example, a BSF operation on bitS of GPIO will cause all eight bits of GPIO to be read into the CPU, bit5 to be set and the GPIO value to be written to the output latches. If another bit of GPIO is used as a bi- directional I/O pin (say bitO) and it is defined as an input at this time, the input signal present on the pin itself would be read into the CPU and rewritten to the data latch of this particular pin, overwriting the previous content. As long as the pin stays in the input mode, no problem occurs. However, if bitO is switched into output mode later on, the content of the data latch may now be unknown. Example 5-1 shows the effect of two sequential read- modify-write instructions (e.g., BCF, BSF etc.) on an I/O port. A pin actively outputting a high or a low should not be driven from external devices at the same time in order to change the level on this pin (wired-or, wired- and). The resulting high output currents may damage the chip. FIGURE 5-2: SUCCESSIVE I/O OPERATION EXAMPLE 5-1: READ-MODIFY-WRITE INSTRUCTIONS ON AN 1/0 PORT ; Initial GPIO Settings ; GPIO<5:3> Inputs ; GPIO<2:0> Outputs GPIO latch GPIO pins ' ' ' ' ' BCF GPIO, 5 ;--01 -ppp --11 pppp BCF GPIo, 4 ;--10 -ppp --11 pppp MOVLW 007h ; TRIS GPIO ;--10 -ppp --11 pppp ;Note that the user may have expected the pin jvalues to be --00 pppp. The 2nd BCF caused ;GP5 to be latched as the pin value (High). 5.4.2 SUCCESSIVE OPERATIONS ON I/O PORTS The actual write to an I/O port happens at the end of an instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cycle (Figure 5-2). Therefore, care must be exercised if a write followed by a read operation is carried out on the same I/O port. The sequence of instructions should allow the pin voltage to stabilize (load dependent) before the next instruction, which causes that file to be read into the CPU, is executed. Otherwise, the previous state of that pin may be read into the CPU rather than the new state. When in doubt, it is better to separate these instructions with a NoP or another instruction not accessing this I/O port. " Qt] G2] Q3] Q4* Qt] G2] Q3] Q4* Q1] Q2] Q3] Q4* Qt] Q2] _Q3] 4" _ PC K PC +1 X 1 PC+2 x PC+3 ' | This example shows a write to GPIO followed ns goned ' ' oy ' . | by aread from GPIO. ' MOVWF GPIO | MOVF GPIO,W Ss! 1 NOP ' NOP ' : ; ; my Data setup time = (0.25 Tcy TPD) GP5:GP0' ; vo ; ; where: TCY = instruction cycle. ' 1 st 1 1 TPD = propagation delay i i . i + ! 1 . : 1 ' Port pin 1 Port pin 1 ' | Therefore, at higher clock frequencies, a ' ' written here | sampled here: ' | write followed by a read may be problematic. Instruction ! ! ' ' ' executed | 1 MOVWF GPIO. 1 MOVFGPIO.W 1 NOP ' ' ' (Write to ' (Read ' ' ' ' GPIO) ' GPIO) ' ' DS40172B-page 20 Prelhninary 1998 Microchip Technology Inc.PIC12CE5XX 6.0 EEPROM PERIPHERAL OPERATION The PIC12CE518 and PIC12CE519 each have 16 bytes of EEPROM data memory. The EEPROM mem- ory has an endurance of 1,000,000 erase/write cycles and a data retention of greater than 40 years. The EEPROM data memory supports a bi-directional 2-wire bus and data transmission protocol. These two-wires are serial data (SDA) and serial clock (SCL), that are mapped to bit6 and bit7, respectively, of the GPIO reg- ister (SFR 06h). Unlike the GPO-GP5 that are con- nected to the I/O pins, SDA and SCL are only connected to the internal EEPROM peripheral. For most applications, all that is required is calls to the fol- lowing functions: ; Byte Write: Byte write routine ; Inputs: EEPROM Address EEADDR r EEPROM Data EEDATA ; Outputs: Return 01 in W if OK, else return 00 in W r ; Read Current: Read EEPROM at address currently held by EE device. i Inputs: NONE ; Outputs: EEPROM Data EEDATA ; Return 01 in W if OK, else return 00 in W r ; Read Random: Read EEPROM byte at supplied address ; Inputs: EEPROM Address EEADDR ; Outputs: EEPROM Data EEDATA ; Return 01 in W if OK, else return 00 in W The code for these functions is available on our website www.microchip.com. The code will be accessed by either including the source code FL51XINC.ASM or by linking FLASHSIX.ASM. It is very important to check the return codes when using these calls, and retry the operation if unsuccess- ful. Unsuccessful return codes occur when the EE dia memeory is busy with the previos write, which can take up to 4 ms. 6.0.1 SERIAL DATA SDA is a bi-directional pin used to transfer addresses and data into and data out of the device. For normal data transfer SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the START and STOP condi- tions. The EEPROM interface is a 2-wire bus protocol con- sisting of data (SDA) and a clock (SCL). Although these lines are mapped into the GPIO register, they are not accessible as external pins; only to the internal EEPROM peripheral. SDA and SCL operation is also slightly different than GPO-GP5 as listed below. Namely, to avoid code overhead in modifying the TRIS register, both SDA and SCL are always outputs. To read data from the EEPROM peripheral requires out- putting a 1 on SDA placing it in high-Z state, where only the internal 100K pull-up is active on the SDA line. SDA: Built-in 100K (typical) pull-up to VDD Open-drain (pull-down only) Always an output Outputs a 1 on reset SCL: Full CMOS output Always an output Outputs a 1 on reset The following example requires: * Code Space: 77 words * RAM Space: 5 bytes (4 are overlayable) * Stack Levels:1 (The call to the function itself. The functions do not call any lower level functions.) * Timing: - WRITE_BYTE takes 328 cycles - READ_CURRENT takes 212 cycles - READ _RANDOM takes 416 cycles. * IO Pins: 0 (No external IO pins are used) This code must reside in the lower half of a page. The code achieves its small size without additional calls through the use of a sequencing table. The table is a list of procedures that must be called in order. The table uses an ADDWF PCL,F instruction, effectively a computed goto, to sequence to the next procedure. However the ADDWF PCL,F instruction yields an 8 bit address, forcing the code to reside in the first 256 addresses of a page. 6.0.2 SERIAL CLOCK This SCL input is used to synchronize the data transfer from and to the device. 6.1 BUS CHARACTERISTICS The following bus protocol is to be used with the EEPROM data memory. * Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as a START or STOP condition. Accordingly, the following bus conditions have been defined (Figure 6-1). 6.1.1 BUS NOT BUSY (A) Both data and clock lines remain HIGH. 1998 Microchip Technology Inc. Preiininary DS40172B-page 21PIC12CE5XX 6.1.2 START DATA TRANSFER (B) A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a START condition. All commands must be preceded by a START condition. 6.1.3. STOP DATA TRANSFER (C) A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP condition. All operations must be ended with a STOP condition. 6.1.4 DATAVALID (D) The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one bit of data per clock pulse. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of the data bytes transferred between the START and STOP conditions is determined by the master device and is theoretically unlimited. 6.1.5 ACKNOWLEDGE Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this acknowledge bit. Note: Acknowledge bits are not generated if an internal programming cycle is in progress. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition (Figure 6-2). DS40172B-page 22 Prelhninary 1998 Microchip Technology Inc.