19-0378; Rev 3; 9/96 Quad/Octal, 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs The MAX520/MAX521 are quad/octal, 8-bit voltage-output digital-to-analog converters (DACs) with simple 2-wire serial interfaces that allow communication between multiple devices. They operate from a single +5V supply and their reference input range includes both supply rails. The MAX521 includes rail-to-rail output buffer amplifiers for reduced system size and component count when driving loads. The MAX520's unbuffered voltage outputs reduce the device's total supply current to 4A and provide increased accuracy at low output currents. The MAX520/MAX521 feature a serial interface and internal software protocol, allowing communication at data rates up to 400kbps. The interface, combined with the doublebuffered input configuration, allows the DAC registers to be updated individually or simultaneously. In addition, the devices can be put into a low-power shutdown mode that reduces supply current to 4A. Power-on reset ensures the DAC outputs are at 0V when power is initially applied. The MAX520 is available in 16-pin DIP and wide SO packages, as well as a space-saving 20-pin SSOP. The MAX521 comes in 20-pin DIP and 24-pin SO packages, as well as a space-saving 24-pin SSOP. ________________________Applications Minimum Component Analog Systems Digital Offset/Gain Adjustment Industrial Process Control Automatic Test Equipment Programmable Attenuators _________________Pin Configurations ____________________________Features Single +5V Supply Simple 2-Wire Serial Interface I2C Compatible Outputs Swing Rail to Rail: Unbuffered Outputs (MAX520) Buffered Outputs (MAX521) 1%-Accurate Trimmed Output Resistance (MAX520A) Ultra-Low 4A Supply Current (MAX520) Individual DACs Have Separate Reference Inputs Power-On Reset Clears All Latches 4A Power-Down Mode ______________Ordering Information TEMP. RANGE MAX520ACPE 0C to +70C 16 Plastic DIP 1 MAX520BCPE MAX520ACWE MAX520BCWE 0C to +70C 0C to +70C 0C to +70C 16 Plastic DIP 16 Wide SO 16 Wide SO 1 1 1 _______________Functional Diagrams SDA SCL REF1 8 8-BIT SHIFT REGISTER OUT1 1 16 OUT2 OUT0 2 15 OUT3 REF1 3 14 REF2 REF0 4 MAX520 ADDRESS COMPARATOR START/STOP DETECTOR 12 VDD DGND 6 11 AD2 SCL 7 10 AD1 SDA 8 9 REF0 INPUT LATCH 0 1 OUTPUT LATCH 0 DAC0 OUT0 INPUT LATCH 1 OUTPUT LATCH 1 DAC1 OUT1 OUTPUT LATCH 2 DAC2 OUT2 OUTPUT LATCH 3 DAC3 OUT3 1 13 REF3 AGND 5 PIN-PACKAGE Ordering Information continued at end of data sheet. MAX520 "A" grade parts include a 1%-accurate, factory-trimmed output resistance. MAX520 TOP VIEW TUE (LSB) PART INPUT LATCH 2 DECODE 4 1 INPUT LATCH 3 AD0 1 DIP/SO Pin Configurations continued at end of data sheet. AD0 AD2 REF2 REF3 AD1 Functional Diagrams continued at end of data sheet. ________________________________________________________________ Maxim Integrated Products 1 For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800 MAX520/MAX521 _______________General Description MAX520/MAX521 Quad/Octal, 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs ABSOLUTE MAXIMUM RATINGS VDD to DGND ...........................................................-0.3V to +6V VDD to AGND............................................................-0.3V to +6V OUT_ ..........................................................-0.3V to (VDD + 0.3V) REF_ ...........................................................-0.3V to (VDD + 0.3V) AD0, AD1, AD2...........................................-0.3V to (VDD + 0.3V) SCL, SDA to DGND ..................................................-0.3V to +6V AGND to DGND.....................................................-0.3V to +0.3V Maximum Current into Any Pin............................................50mA Continuous Power Dissipation (TA = +70C) 16-Pin Plastic DIP (derate 10.53mW/C above +70C)....842mW 20-Pin Plastic DIP (derate 11.11mW/C above +70C)....889mW 16-Pin Wide SO (derate 9.52mW/C above +70C) ......762mW 24-Pin Wide SO (derate 11.76mW/C above +70C) ....941mW 20-Pin SSOP (derate 8.00mW/C above +70C) .........640mW 24-Pin SSOP (derate 8.00mW/C above +70C) .........640mW 16-Pin CERDIP (derate 10.00mW/C above +70C)....800mW 20-Pin CERDIP (derate 11.11mW/C above +70C)....889mW Operating Temperature Ranges MAX520_C_ _/MAX521_C_ _ ..............................0C to +70C MAX520_E_ _/MAX521_E_ _ ...........................-40C to +85C MAX520_MJE/MAX521BMJP ........................-55C to +125C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10sec) .............................+300C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = 5V 10%, VREF_ = 4V, RL = (MAX520), RL = 10k (MAX521), CL = 0pF (MAX520), CL = 100pF (MAX521), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC ACCURACY Resolution 8 Total Unadjusted Error TUE Differential Nonlinearity DNL Bits MAX520_ 1 MAX521A 1.5 MAX521B Zero-Code Error ZCE 2 Guaranteed monotonic Code = 00 hex LSB 1.0 MAX520_ 8 MAX521_C 18 MAX521_E 20 MAX521BM LSB mV 20 Zero-Code-Error Supply Rejection Code = 00 hex 1 mV Zero-Code-Error Temperature Coefficient Code = 00 hex 10 V/C MAX520_ 8 MAX521_C 18 MAX521_E 20 Full-Scale Error Code = FF hex Full-Scale-Error Supply Rejection Code = FF hex, VDD = 5V 10% MAX521BM Full-Scale-Error Temperature Coefficient 2 mV 20 1 mV 10 V/C _______________________________________________________________________________________ Quad/Octal, 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs (VDD = 5V 10%, VREF_ = 4V, RL = (MAX520), RL = 10k (MAX521), CL = 0pF (MAX520), CL = 100pF (MAX521), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C) PARAMETER SYMBOL CONDITIONS MIN TYP 0 8 4 16 12 6 24 MAX UNITS VDD V REFERENCE INPUTS Input Voltage Range Input Resistance RIN Code = 55 hex (Note 1) Input Current PD = 1 Input Capacitance Code = FF hex (Note 2) Channel-to-Channel Isolation (Note 3) AC Feedthrough (Note 4) MAX520_ MAX521_ REF4 REF0-REF3 k 10 MAX520_ REF4 MAX521_ REF0-REF3 MAX520_ 30 120 30 -70 MAX521_ -60 A pF dB -70 dB DAC OUTPUTS Full-Scale Output Voltage 0 MAX520A Output Resistance (Note 5) 15.8 16 TA = TMIN to TMAX 15.6 16 MAX520B Output Load Regulation 8.4 V 16.2 16.4 k 16.4 MAX521_, OUT_ = 4V, 0mA to 2.5mA 0.25 MAX521_C/E, VREF_ = VDD, code = FF hex, 0A to 500A 1.5 MAX521BM, VREF_ = VDD, code = FF hex, 0A to 500A 2.0 MAX521_, OUT_ = 0V to VDD, PD = 1 Output Leakage Current VDD TA = +25C LSB 10 A DIGITAL INPUTS SCL, SDA Input High Voltage VIH Input Low Voltage VIL Input Current IIN Input Hysteresis Input Capacitance 0.7VDD 0V VIN VDD VHYST (Note 5) CIN (Note 5) V 0.3VDD V 10 A 10 pF 0.05VDD V DIGITAL INPUTS AD0, AD1 Input High Voltage VIH Input Low Voltage VIL Input Leakage IIN 2.4 V 0.8 V VIN = 0V to VDD 10 A ISINK = 3mA 0.4 ISINK = 6mA 0.6 VIN = 0V to VDD 10 A 10 pF DIGITAL OUTPUT SDA (Note 6) Output Low Voltage Three-State Leakage Current Three-State Output Capacitance VOL IL COUT (Note 5) V _______________________________________________________________________________________ 3 MAX520/MAX521 ELECTRICAL CHARACTERISTICS (continued) MAX520/MAX521 Quad/Octal, 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs ELECTRICAL CHARACTERISTICS (continued) (VDD = 5V 10%, VREF_ = 4V, RL = (MAX520), RL = 10k (MAX521), CL = 0pF (MAX520), CL = 100pF (MAX521), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DYNAMIC PERFORMANCE Voltage Output Slew Rate MAX521_C 1.0 Positive and negative MAX521_E 0.7 MAX521BM V/s 0.5 MAX520_, to 1/2LSB, no load 2 MAX521_, to 1/2LSB, 10k and 100pF load (Note 7) 6 Digital Feedthrough Code = 00 hex, all digital inputs from 0V to VDD 5 nV-s Digital-Analog Glitch Impulse Code 128 to 127 12 nV-s VREF_ = 4Vp-p at 1kHz, VDD = 5V, code = FF hex 87 dB Output Settling Time Signal to Noise + Distortion Ratio SINAD s Multiplying Bandwidth VREF_ = 4Vp-p, 3dB bandwidth 1 MHz Wideband Amplifier Noise MAX521_ 60 VRMS POWER REQUIREMENTS Supply Voltage Supply Current VDD IDD 4.5 5.5 V A Operating mode, out- MAX520_ put unloaded, all dig- MAX521_C ital inputs 0V or VDD MAX521_E/BM 4 20 10 20 10 24 Power-down mode (PD = 1) 4 20 mA A Note 1: Input resistance is code dependent. The lowest input resistance occurs at code = 55 hex. Note 2: Input capacitance is code dependent. The highest input capacitance occurs at code = FF hex. Note 3: VREF_ = 4Vp-p, 10kHz. Channel-to-channel isolation is measured by setting the code of one DAC to FF hex and setting the code of all other DACs to 00 hex. Note 4: VREF_ = 4Vp-p, 10kHz, DAC code = 00 hex. Note 5: Guaranteed by design. Note 6: I2C-compatible mode. Note 7: Output settling time is measured by taking the code from 00 hex to FF hex, and from FF hex to 00 hex. 4 _______________________________________________________________________________________ Quad/Octal, 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs MAX520/MAX521 TIMING CHARACTERISTICS (VDD = 5V 10%, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER SYMBOL Serial Clock Frequency Bus Free Time Between a STOP and a START Condition Hold Time, (Repeated) Start Condition CONDITIONS MIN TYP MAX UNITS 400 kHz fSCL 0 tBUF 1.3 s tHD, STA 0.6 s Low Period of the SCL Clock tLOW 1.3 s High Period of the SCL Clock tHIGH 0.6 s Setup Time for a Repeated START Condition tSU, STA Data Hold Time tHD, DAT Data Setup Time tSU, DAT 0.6 (Note 8) s 0 0.9 s 100 ns Rise Time of Both SDA and SCL Signals, Receiving tR (Note 9) 20 + 0.1Cb 300 ns Fall Time of Both SDA and SCL Signals, Receiving tF (Note 9) 20 + 0.1Cb 300 ns tF ISINK 6mA (Note 9) 20 + 0.1Cb 250 ns 400 pF 50 ns Fall Time of SDA Transmitting (Note 6) Setup Time for STOP Condition tSU, STO Capacitive Load for Each Bus Line Cb Pulse Width of Spike Suppressed tSP 0.6 (Notes 10, 11) s 0 Note 8: A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) in order to bridge the undefined region of SCL's falling edge. Note 9: Cb = total capacitance of one bus line in pF. tR and tf measured between 0.3VDD and 0.7VDD. Note 10: An input filter on the SDA and SCL input suppresses noise spikes less than 50ns. Note 11: Guaranteed by design. __________________________________________Typical Operating Characteristics (VDD = 5V, DAC outputs unloaded, TA = +25C, unless otherwise noted.) IDD (A) 7 6 5 4 3 2 1 0 VREF = 4V ONE REF INPUT DRIVEN 35 30 25 20 15 10 -30 0 30 60 90 TEMPERATURE (C) 120 150 0 VDD = 5V VREF = 4Vp-p SINE WAVE CENTERED AT 2.5V -2 -4 -6 -8 -10 -12 -14 5 -16 -18 0 -60 2 MAX520/521-03 8 40 MAX520/521-02 OPERATING MODE OR SHUTDOWN MODE RELATIVE OUTPUT (dB) MAX520/521-01 9 SHUTDOWN REFERENCE CURRENT (nA) 10 MAX520 REFERENCE VOLTAGE INPUT FREQUENCY RESPONSE MAX520 REFERENCE INPUT CURRENT vs. TEMPERATURE (SHUTDOWN MODE) MAX520 SUPPLY CURRENT vs. TEMPERATURE -60 -30 0 30 60 90 TEMPERATURE (C) 120 150 1k 10k 100k 1M 10M FREQUENCY (Hz) _______________________________________________________________________________________ 5 MAX520/MAX521 Quad/Octal, 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs ______________________________Typical Operating Characteristics (continued) (VDD = 5V, DAC outputs unloaded, TA = +25C, unless otherwise noted.) MAX520 NEGATIVE SETTLING TIME MAX520 POSITIVE SETTLING TIME OUT2 1V/div OUT2 1V/div 1s/div OUT2 = NO LOAD, REF2 = 4V, DAC CODE = FF HEX to 00 HEX 1s/div OUT2 = NO LOAD, REF2 = 4V, DAC CODE = 00 HEX to FF HEX MAX520 WORST-CASE 1LSB DIGITAL STEP CHANGE (CAPACITIVE LOAD = 25pF) MAX520 WORST-CASE 1LSB DIGITAL STEP CHANGE (CAPACITIVE LOAD < 5pF) OUT2 20mV/div AC COUPLED 500ns/div REF2 = 4V, DAC CODE = 7F HEX to 80 HEX 6 OUT2 20mV/div AC COUPLED 500ns/div REF2 = 4V, DAC CODE = 7F HEX to 80 HEX _______________________________________________________________________________________ Quad/Octal, 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs ALL DAC CODES FF HEX 6 4 MAX520/521-10 5 10 ALL REFERENCE INPUTS DRIVEN 8 4 ICC (mA) ICC (mA) 8 VDD = 5.5V ALL REF INPUTS = 0.6V ALL DIGITAL INPUTS to VDD MAX520/521-09 10 6 SHUTDOWN ICC (A) VDD = 5.5V ALL REF INPUTS = 0.6V ALL DIGITAL INPUTS to VDD MAX520/521-08 12 MAX521 SUPPLY CURRENT vs. REFERENCE VOLTAGE MAX521 SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE MAX521 SUPPLY CURRENT vs. TEMPERATURE 3 6 ALL DAC CODES = FF HEX 4 2 ALL DAC CODES 00 HEX 0 60 20 100 140 -20 20 60 100 TEMPERATURE (C) TEMPERATURE (C) MAX521 DAC OUTPUT HIGH VOLTAGE vs. OUTPUT SOURCE CURRENT MAX521 DAC OUTPUT LOW VOLTAGE vs. OUTPUT SINK CURRENT 1.0 0.4 0.2 0.6 0.4 0 0 2 4 6 8 10 2 0 -4 -6 16 4Vp-p SINE 2Vp-p SINE 1Vp-p SINE 0.5Vp-p SINE -8 -10 -12 VREF = SINE WAVE CENTERED AT 2.5V -18 0 14 0 OUTPUT SOURCE CURRENT (mA) 2 4 6 8 OUTPUT SINK CURRENT (mA) MAX521 POSITIVE SETTLING TIME 10 1k 10k 100k 1M 10M FREQUENCY (Hz) MAX521 NEGATIVE SETTLING TIME OUT1 1V/div 1s/div OUT1 LOADED WITH 10k II 100pF, REF1 = 4V, DAC CODE = 00 HEX to FF HEX 5 -2 -16 12 4 -14 0.2 VOUT = VREF x (255/256) 3 2 MAX521 REFERENCE VOLTAGE INPUT FREQUENCY RESPONSE RELATIVE OUTPUT (dB) VOUT (V) 0.6 1 REFERENCE VOLTAGE (V) VREF = 5V DAC CODE = 00 HEX LOAD to VDD 0.8 0 140 MAX520/521-12 VREF = 5V DAC CODE = FF HEX LOAD to AGND 0.8 -60 MAX520/521-11 1.0 -20 ALL DAC CODES = 00 HEX 0 0 -60 VDD - VOUT (V) 2 1 MAX520/521-13 2 OUT1 1V/div 1s/div OUT1 LOADED WITH 10k II 100pF, REF1 = 4V, DAC CODE = FF HEX to 00 HEX _______________________________________________________________________________________ 7 MAX520/MAX521 __________________________________________Typical Operating Characteristics (VDD = 5V, DAC outputs unloaded, TA = +25C, unless otherwise noted.) MAX520/MAX521 Quad/Octal, 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs ______________________________Typical Operating Characteristics (continued) (VDD = 5V, DAC outputs unloaded, TA = +25C, unless otherwise noted.) MAX521 WORST-CASE 1LSB DIGITAL STEP CHANGE OUT1 20mV/div AC COUPLED 500ns/div REF1 = 5V, DAC CODE = 80 HEX to 7F HEX REFERENCE FEEDTHROUGH AT 1kHz CLOCK FEEDTHROUGH A A B B A = SCL, 400kHz, 5V/div B = OUT1, 5mV/div A = REF1, 1V/div (4VP-P) B = OUT1, 50V/div, UNLOADED REF1 = 5V, DAC CODE = 7F HEX FILTER PASSBAND = 100Hz to 10kHz, DAC CODE = 00 HEX REFERENCE FEEDTHROUGH AT 10kHz REFERENCE FEEDTHROUGH AT 100kHz A A B 8 B A = REF1, 1V/div (4VP-P) B = OUT1, 50V/div, UNLOADED A = REF1, 1V/div (4VP-P) B = OUT1, 50V/div, UNLOADED FILTER PASSBAND = 1kHz to 100kHz, DAC CODE = 00 HEX FILTER PASSBAND = 10kHz to 1MHz, DAC CODE = 00 HEX _______________________________________________________________________________________ Quad/Octal, 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs PIN MAX520 MAX521 NAME FUNCTION DIP/SO SSOP DIP SO/SSOP 1 1 1 1 OUT1 DAC1 Voltage Output 2 2 2 2 OUT0 DAC0 Voltage Output 3 3 3 3 REF1 Reference Voltage Input for DAC1 4 5 4 4 REF0 Reference Voltage Input for DAC0 -- 4, 7, 14, 17 -- 7, 9, 16, 20 N.C. No Connect--not internally connected 6 8 5 5 DGND Digital Ground 5 6 6 6 AGND Analog Ground 7 9 7 8 SCL Serial Clock Input Serial Data Input 8 10 8 10 SDA -- -- 9 11 OUT4 DAC4 Voltage Output -- -- 10 12 OUT5 DAC5 Voltage Output -- -- 11 13 OUT6 DAC6 Voltage Output -- -- 12 14 OUT7 DAC7 Voltage Output 9 11 13 15 AD0 Address Input 0; sets IC's slave address 10 12 14 17 AD1 Address Input 1; sets IC's slave address 11 13 -- -- AD2 Address Input 2; sets IC's slave address 12 15 15 18 VDD Power Supply, +5V -- -- 16 19 REF4 Reference Voltage Input for DACs 4, 5, 6, and 7 13 16 17 21 REF3 Reference Voltage Input for DAC3 14 18 18 22 REF2 Reference Voltage Input for DAC2 15 19 19 23 OUT3 DAC3 Voltage Output 16 20 20 24 OUT2 DAC2 Voltage Output SDA tSU, DAT tBUF tSU, STA tHD, STA tLOW tSU, STO tHD, DAT SCL tHIGH tHD, STA tR tF START CONDITION REPEATED START CONDITION STOP CONDITION START CONDITION Figure 1. 2-Wire Serial-Interface Timing Diagram _______________________________________________________________________________________ 9 MAX520/MAX521 ______________________________________________________________Pin Description MAX520/MAX521 Quad/Octal, 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs _______________Detailed Description Serial Interface The MAX520/MAX521 use a simple 2-wire serial interface requiring only two I/O lines (2-wire bus) of a standard microprocessor (P) port. Figure 1 shows the timing diagram for signals on the 2-wire bus. Figure 2 shows the typical application of the MAX520/MAX521. The 2-wire bus can have several devices (in addition to the MAX520/MAX521) attached. The two bus lines (SDA and SCL) must be high when the bus is not in use. When in use, the port bits are toggled to generate the appropriate signals for SDA and SCL. External pull-up resistors are not required on these lines. The MAX520/MAX521 can be used in applications where pull-up resistors are required (such as in I2C systems) to maintain compatibility with the existing circuitry. The MAX520/MAX521 are receive-only devices and must be controlled by a bus master device. They operate at SCL rates up to 400kHz. A master device sends information to the devices by transmitting their address over the bus and then transmitting the desired information. Each transmission consists of a START condition, the MAX520/MAX521's programmable slave-address, one or more command-byte/output-byte pairs (or a command byte alone, if it is the last byte in the transmission), and finally, a STOP condition (Figure 3). The address byte and pairs of command and output bytes are transmitted between the START and STOP conditions. The SDA state is allowed to change only while SCL is low. SDA's state is sampled, and therefore must remain stable while SCL is high. The only exceptions to this are the START and STOP conditions. Data is transmitted in 8-bit bytes. Nine clock cycles are required to transfer the data bits to the MAX520/MAX521. Set SDA low during the 9th clock cycle as the MAX520/MAX521 pull SDA low during this time. RC (Figure 2) limits the current that flows during this time if SDA stays high for short periods of time. SLAVE ADDRESS BYTE C SDA SCL QUAD DAC RC 1k REF0 REF1 REF2 REF3 +1V +4V +5V OFFSET ADJUSTMENT OFFSET ADJUSTMENT GAIN ADJUSTMENT GAIN ADJUSTMENT OUT0 MAX520 OUT1 SCL SDA AD0 AD1 AD2 OUT2 OUT3 +5V +5V REF0 . . . OCTAL . DAC REF4 OUT0 MAX521 OUT1 OUT2 . SCL . . SDA AD0 OUT6 OUT7 AD1 BRIGHTNESS ADJUSTMENT CONTRAST ADJUSTMENT THRESHOLD ADJUSTMENTS +5V MOTOR +12V Figure 2. Typical Application Circuit COMMAND BYTE OUTPUT BYTE SDA MSB LSB ACK MSB LSB ACK MSB LSB ACK SCL START CONDITION Figure 3. A Complete Serial Transmission 10 ______________________________________________________________________________________ STOP CONDITION Quad/Octal, 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs Slave Address The MAX520/MAX521 each have a 7-bit-long slave address (Figure 5). The first four bits (MSBs) of the slave address have been factory programmed and are always 0101. In addition, the MAX521 has the next bit factory programmed to 0. The logic state of the address input pins (AD0, AD1, and AD2 of the MAX520; AD0 and AD1 of the MAX521) determine the least significant bits of the 7-bit slave address. These input pins may be connected to VDD or DGND, or they may be actively driven by TTL or CMOS logic levels. There are four possible slave addresses for the MAX521, and therefore a maximum of four such devices may be on the bus at one time. The MAX520 has eight possible slave addresses. The eighth bit (LSB) in the slave address byte should be low when writing to the MAX520/MAX521. The MAX520/MAX521 monitor the bus continuously, waiting for a START condition followed by its slave address. When a device recognizes its slave address, it is ready to accept data. Command Byte and Output Byte A command byte follows the slave address. Figure 6 shows the format for the command byte. A command byte is usually followed by an output byte unless it is the last byte in the transmission. If it is the last byte, all bits except PD and RST are ignored. If an output byte follows the command byte, A0-A2 of the command byte indicate the digital address of the DAC whose input data latch receives the digital output data. The data is transferred to the DAC's output latch during the STOP condition following the transmission. This allows all DACs to be updated and the new outputs to appear simultaneously (Figure 7). Setting the PD bit high powers down the MAX520/ MAX521 following a STOP condition (Figure 8a). If a command byte with PD set high is followed by an output byte, the addressed DAC's input latch will be updated and the data will be transferred to the DAC's output latch following the STOP condition (Figure 8b). If the transmission's last command byte has PD high, the voltage outputs will not reflect the newly entered data because the DAC will enter power-down mode when SDA SCL STOP CONDITION START CONDITION Figure 4. All communications begin with a START condition and end with a STOP condition, both generated by a bus master. SLAVE ADDRESS 0 1 0 1 0 or AD2 AD1 AD0 0 ACK SDA LSB SCL SLAVE ADDRESS BITS AD2, AD1, AND AD0 CORRESPOND TO THE LOGIC STATE OF THE ADDRESS INPUT PINS AD2, AD1, AND AD0. Figure 5. Address Byte R2 R1 R0 RST PD A2 A1 A0 ACK SDA MSB LSB SCL R2, R1, R0: RESERVED BITS. SET TO 0. RST: RESET BIT, SET TO 1 TO RESET ALL DAC REGISTERS. PD: POWER-DOWN BIT. SET TO 1 TO PLACE THE DEVICE IN THE 4A SHUTDOWN MODE. SET TO 0 TO RETURN TO THE NORMAL OPERATIONAL STATE. A2, A1, A0: ADDRESS BITS. DIGITAL ADDRESS FOR DAC0 TO DAC7. DETERMINES WHICH DAC'S INPUT LATCH RECEIVES THE 8 BITS OF DATA IN THE NEXT BYTE. A2 IS IGNORED BY THE MAX520. ACK: ACKNOWLEDGE BIT. THE MAX520/MAX521 PULL SDA LOW DURING THE 9TH CLOCK PULSE. Figure 6. Command Byte the STOP condition is detected. When in power-down, the MAX521's DAC outputs float, and the MAX520's unbuffered outputs look like a 16k resistor to AGND. In this mode, the supply current is a maximum of 20A. A command byte with the PD bit low returns the MAX520/MAX521 to normal operation following a STOP condition, and the voltage outputs reflect the current output-latch contents (Figures 9a and 9b). Because each subsequent command byte overwrites the previous PD bit, only the last command byte of a transmission affects the power-down state. ______________________________________________________________________________________ 11 MAX520/MAX521 START and STOP Conditions When the bus is not in use, both SCL and SDA must be high. A bus master signals the beginning of a transmission with a START condition by transitioning SDA from high to low while SCL is high (Figure 4). When the master has finished communicating with the slave, it issues a STOP condition by transitioning SDA from low to high while SCL is high. The bus is then free for another transmission. MAX520/MAX521 Quad/Octal, 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs 0 OR AD2 0 1 0 1 AD1 AD0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 0 SDA ADDRESS BYTE START CONDITION 1 1 1 1 1 COMMAND BYTE (ADDRESSING DAC0) ACK ACK OUTPUT BYTE (FULL SCALE) ACK ( 1 1 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 COMMAND BYTE (ADDRESSING DAC1) DAC0 INPUT LATCH SET TO FULL SCALE 0 0 0 ACK ) 0 SDA ACK OUTPUT BYTE (FULL SCALE) ( COMMAND BYTE (ADDRESSING DAC2) DAC1 INPUT LATCH SET TO FULL SCALE ACK OUTPUT BYTE STOP (HALF SCALE) CONDITION DAC2 INPUT LATCH SET TO HALF SCALE DAC OUTPUTS CHANGE HERE: DACS 0 AND 1 GO TO FULL SCALE, DAC 2 GOES TO HALF SCALE. ACK ) ( ) ( ) Figure 7. Setting DAC Outputs 0 OR AD2 (a) 0 1 0 1 AD1 AD0 0 0 (PD) 0 0 0 0 1 0 X SDA ADDRESS BYTE X X COMMAND BYTE ACK ACK STOP CONDITION START CONDITION 0 OR AD2 (b) 0 1 0 1 AD1 AD0 0 0 0 0 0 0 (PD) 1 0 0 0 0 1 ( 1 DEVICE ENTERS POWER-DOWN STATE 1 1 1 1 1 1 ) 0 SDA ADDRESS BYTE COMMAND BYTE (ADDRESSING DAC0) ACK START CONDITION ACK OUTPUT BYTE (FULL SCALE) ACK ( NOTE: X = DON'T CARE STOP CONDITION DAC 0 INPUT LATCH SET TO FULL SCALE DEVICE ENTERS POWER-DOWN STATE. DAC 0 OUTPUT LATCH SET TO FULL SCALE. ) ( ) Figure 8. Entering the Power-Down State 0 OR AD2 (a) 0 1 0 1 AD1 AD0 0 (PD) 0 0 0 0 0 0 0 X SDA ADDRESS BYTE X X COMMAND BYTE ACK START CONDITION 0 OR AD2 (b) 0 1 0 1 AD1 AD0 0 0 0 0 0 0 (PD) 0 0 1 1 ACK STOP CONDITION 0 0 0 ( DEVICE RETURNS TO NORMAL OPERATION 0 0 0 0 0 0 ) 0 SDA ADDRESS BYTE START CONDITION ACK COMMAND BYTE (ADDRESSING DAC3) NOTE: X = DON'T CARE ACK ACK OUTPUT BYTE STOP (SET TO 0) DAC3 OUTPUT CONDITION LATCH SET TO 0 DEVICE RETURNS TO NORMAL OPERATION. DAC 3 SET TO 0. ( ) ( Figure 9. Returning to Normal Operation from Power-Down 12 ______________________________________________________________________________________ ) Quad/Octal, 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs 0 1 0 1 AD1 AD0 0 0 (RST) 0 0 0 1 0 0 X SDA ADDRESS BYTE ( 0 OR AD2 0 1 0 1 AD1 AD0 0 0 0 0 ACK ) ALL INPUT LATCHES SET TO 0 (RST) 0 1 0 ADDRESS BYTE ACK START CONDITION NOTE: X = DON'T CARE STOP CONDITION ( ALL OUTPUTS SET TO 0 ) 0 X SDA X COMMAND BYTE ACK START CONDITION (b) X X COMMAND BYTE ( X 0 X X X X X X X X ALL INPUT LATCHES SET TO 0 ACK ADDITIONAL COMMAND BYTE/ OUTPUT BYTE PAIRS "DUMMY" OUTPUT BYTE ACK ) ( STOP CONDITION ) ALL DAC OUTPUTS SET TO 0 UNLESS CHANGED BY ADDITIONAL COMMAND BYTE/OUTPUT BYTE PAIRS Figure 10. Resetting DAC Outputs Setting the RST bit high clears all DAC input latches. The DAC outputs remain unchanged until a STOP condition is detected (Figure 10a). If a reset is issued, the following output byte is ignored. Subsequent pairs of command/output bytes overwrite the input latches (Figure 10b). All changes made during a transmission affect the MAX520/MAX521's outputs only when the transmission ends and a STOP has been recognized. The R0, R1, and R2 bits are reserved bits that must be set to zero. C 2 E PROM XICOR X24C04 SDA SCL SCL SDA QUAD DAC I2C Compatibility The MAX520/MAX521 are fully compatible with existing I2C systems. SCL and SDA are high-impedance inputs; SDA has an open drain which pulls the data line low during the 9th clock pulse. Figure 11 shows a typical I2C application. Additional START Conditions It is possible to interrupt a transmission to a MAX520/ MAX521 with a new START (repeated start) condition (perhaps addressing another device), which leaves the input latches with data that has not been transferred to the output latches (Figure 12). Only the currently addressed device will recognize a STOP condition and transfer data to its output latches. If the device is left with data in its input latches, the data can be transferred to the output latches the next time the device is addressed, as long as it receives at least one command byte and a STOP condition. SCL SDA AD0 AD1 AD2 MAX520 OCTAL DAC +5V SCL SDA AD0 AD1 MAX521 Figure 11. Typical I2C Application Circuit ______________________________________________________________________________________ 13 MAX520/MAX521 0 OR AD2 (a) MAX520/MAX521 Quad/Octal, 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 1 1 1 1 1 0 0 1 0 1 0 0 1 0 0 SDA ADDRESS BYTE (DEVICE 0) START CONDITION ACK COMMAND BYTE ADDRESSING DAC1 OUTPUT BYTE (FULL SCALE) ACK ( 0 0 0 0 0 0 1 0 0 1 1 1 1 1 1 1 1 ADDRESS BYTE (DEVICE 1) ACK DEVICE 0's DAC1 INPUT LATCH SET TO FULL SCALE ) ACK REPEATED START CONDITION 0 SDA COMMAND BYTE (ADDRESSING DAC2) OUTPUT BYTE (FULL SCALE) ACK ( ACK DEVICE 1's DAC2 INPUT LATCH SET TO FULL SCALE )( STOP CONDITION ONLY DEVICE 1's DAC2 OUTPUT LATCH SET TO FULL SCALE. DEVICE 0's OUTPUT LATCHES UNCHANGED. ) Figure 12. Repeated START Conditions 0 OR AD2 (a) 0 1 0 1 AD1 AD0 0 0 (RST) (PD) 0 0 0 1 1 0 SDA ADDRESS BYTE ACK START CONDITION INTERRUPTED COMMAND BYTE EARLY MAX520/MAX521's STATES STOP CONDITION REMAIN UNCHANGED ( 0 OR AD2 (b) 0 1 0 1 AD1 AD0 0 0 0 0 (PD) 0 RST 1 0 0 0 0 1 1 1 0 ) 0 SDA ADDRESS BYTE START CONDITION ACK COMMAND BYTE (POWER DOWN) ACK INTERRUPTED OUTPUT BYTE EARLY STOP CONDITION ( MAX520/MAX521 POWER DOWN; INPUT LATCHES UNCHANGED IF RST = 0, DAC OUTPUTS RESET IF RST = 1. ) Figure 13. Early STOP Conditions Early Stop Conditions The addressed device recognizes a STOP condition at any point in a transmission. If the STOP occurs during a command byte, all previous uninterrupted command and output byte pairs are accepted, the interrupted command byte is ignored, and the transmission ends (Figure 13a). If the STOP occurs during an output byte, all previous uninterrupted command and output byte pairs are accepted, the final command byte's PD and RST bits are accepted, the interrupted output byte is ignored, and the transmission ends (Figure 13b). Analog Section DAC Operation The MAX520 contains four matched voltage-output DACs, and the MAX521 contains eight. The DACs are inverted R-2R ladder networks that convert 8-bit digital 14 words into equivalent analog output voltages in proportion to the applied reference voltages. For both devices, DAC0-DAC3 each have separate reference inputs, while the MAX521's DAC4-DAC7 all share a common reference input. Figure 14 shows a simplified diagram of one DAC. Reference Inputs The MAX520/MAX521 can be used for multiplying applications. The reference accepts a 0V to VDD voltage, both DC and AC signals. The voltage at each REF input sets the full-scale output voltage for its respective DAC(s). The reference voltage must be positive. The DAC's input impedance is code dependent, with the lowest value occurring when the input code is 55 hex or 0101 0101, and the maximum value occurring when the input code is 00 hex. Since the REF input resistance ______________________________________________________________________________________ Quad/Octal, 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs OUT_ (MAX521) R 2R R R 2R 2R 2R 2R D0 D5 D6 D7 OUT_ (MAX520) REF_ AGND SHOWN FOR ALL 1s ON DAC Figure 14. DAC Simplified Circuit Diagram (RIN) is code dependent, it must be driven by a circuit with low output impedance (no more than RIN / 2000) to maintain output linearity. The REF input capacitance is also code dependent, with the maximum value occurring at code FF hex (typically 30pF for the MAX520/ MAX521's REF0-REF3, and 120pF for the MAX521's REF4). The output voltage for any DAC can be represented by a digitally programmable voltage source as: VOUT = (N x VREF) / 256, where N is the numerical value of the DAC's binary input code. Table 1 shows the unipolar code. Table 1. Unipolar Code Table DAC CONTENTS ANALOG OUTPUT 11111111 255 + VREF (------) 256 10000001 129 + VREF (------) 256 10000000 128 VREF + VREF (------) = ---- 256 2 01111111 127 + VREF (------) 256 00000001 1 + VREF (------) 256 00000000 0V DACs are often used in trimming applications to replace hardware potentiometers. Figure 15a shows a typical application, which requires a buffered output so that a precise current can be injected into the summing node through precision resistor RT. For this application, the MAX520A features a precise 1% (TA = +25C, 2.5% over temperature) factory-trimmed output resistance. Because the MAX520A's output resistance is precisely trimmed, there is no need for an internal buffer or external precision resistor (Figure 15b). For applications where the output resistance value is not critical, use the MAX520B. All DACs exhibit output glitches during code transitions. An output filter is sometimes used to reduce these glitches in sensitive applications. The MAX520 simplifies output filtering because its internal resistive ladder network serves as the "R" in an RC filter. Simply connect a small capacitor from the DAC output to ground. See the Typical Operating Characteristics for oscilloscope photos of the worst-case 1LSB step change both without and with 25pF of capacitance on the MAX520's output. MAX521 Output Buffer Amplifiers The MAX521 voltage outputs (OUT0-OUT7) are internally buffered precision unity-gain followers that slew up to 1V/s. The outputs can swing from 0V to VDD. With a 0V to 4V (or 4V to 0V) output transition, the amplifier outputs typically settle to 1/2LSB in 6s when loaded with 10k in parallel with 100pF. The buffer amplifiers are stable with any combination of resistive loads 2k and capacitive loads 300pF. ______________________________________________________________________________________ 15 MAX520/MAX521 MAX520 Unbuffered DAC Outputs The unbuffered DAC outputs (OUT0-OUT3) connect directly to the internal 16k R-2R network. The outputs swing from 0V to VDD. The MAX520 has no output buffer amplifiers, giving it very low supply current. The output-offset voltage is lower without the output buffer, and the output can also slew and settle faster if capacitive loading is minimized. Resistive loading should be very light for highest accuracy. Any output loading generates some gain error, increasing full-scale error. The R-2R ladder's output resistance is 16k, so a 1A output current creates a 16mV error. Linearity is not affected because the ladder output resistance does not change with DAC code. Ladder-resistance changes with temperature are also very small. MAX520/MAX521 Quad/Octal, 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs RF RIN RT DAC RF RIN DAC (1%) 16k (1%) MAX520A Figure 15a. Typical Trimming Circuit Figure 15b. MAX520A Trimming Circuit __________Applications Information SYSTEM GND Shutdown Mode In shutdown mode, the MAX520/MAX521 reference inputs are disconnected from the R-2R ladder inputs, which saves power when the reference is not powered down. In addition, the MAX521's output buffers are disabled, greatly reducing the supply current. The MAX520's operating supply current does not change in shutdown mode. The Command Byte and Output Byte section describes how to enter and exit shutdown mode. PIN1 OUT2 OUT1 OUT3 OUT0 REF2 REF1 REF3 REF0 Power-Supply Bypassing and Ground Management Bypass VDD with a 0.1F capacitor, located as close to V DD and DGND as possible. The analog ground (AGND) and digital ground (DGND) pins should be connected in a "star" configuration to the highest quality ground available, which should be located as close to the MAX521 as possible. Careful PC board layout minimizes crosstalk among DAC outputs, reference inputs, and digital inputs. Figure 16 shows the suggested PC board layout to minimize crosstalk. 16 Figure 16. PC Board Layout for Minimizing Crosstalk (MAX521 bottom view, DIP package) ______________________________________________________________________________________ Quad/Octal, 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs TOP VIEW OUT1 1 20 OUT2 OUT1 1 20 OUT2 OUT1 1 24 OUT2 OUT0 2 19 OUT3 OUT0 2 19 OUT3 OUT0 2 23 OUT3 REF1 3 18 REF2 REF1 3 18 REF2 REF1 3 22 REF2 17 REF3 REF0 4 21 REF3 N.C. 4 REF0 5 MAX520 AGND 6 17 N.C. REF0 4 16 REF3 DGND 5 16 REF4 DGND 5 15 VDD AGND 6 15 VDD AGND 6 18 VDD MAX521 MAX521 20 N.C. 19 REF4 N.C. 7 14 N.C. SCL 7 14 AD1 N.C. 7 DGND 8 13 AD2 SDA 8 13 AD0 SCL 8 17 AD1 SCL 9 12 AD1 OUT4 9 12 OUT7 N.C. 9 16 N.C. SDA 10 11 AD0 OUT5 10 11 OUT6 DIP SSOP SDA 10 15 AD0 OUT4 11 14 OUT7 OUT5 12 13 OUT6 SO/SSOP ________________________________________________Functional Diagrams (continued) SDA SCL REF2 INPUT LATCH 0 1 OUTPUT LATCH 0 DAC0 8 INPUT LATCH 1 1 OUTPUT LATCH 1 DAC1 8 INPUT LATCH 2 1 OUTPUT LATCH 2 DAC2 8 INPUT LATCH 3 1 OUTPUT LATCH 3 DAC3 OUTPUT LATCH 4 DAC4 OUTPUT LATCH 5 DAC5 OUTPUT LATCH 6 DAC6 OUTPUT LATCH 7 DAC7 ADDRESS COMPARATOR START/STOP DETECTOR OUT0 8 MAX521 8-BIT SHIFT REGISTER REF1 REF0 OUT1 OUT2 OUT3 1 8 DECODE 8 INPUT LATCH 4 OUT4 1 8 8 INPUT LATCH 5 OUT5 1 8 INPUT LATCH 6 OUT6 1 8 AD0 AD1 INPUT LATCH 7 OUT7 REF3 REF4 ______________________________________________________________________________________ 17 MAX520/MAX521 ___________________________________________________Pin Configurations (continued) MAX520/MAX521 Quad/Octal, 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs __Ordering Information (continued) _________________Chip Topographies MAX520 TUE (LSB) PART TEMP. RANGE PIN-PACKAGE MAX520ACAP MAX520BCAP MAX520AC/D MAX520BC/D MAX520AEPE MAX520BEPE 0C to +70C 0C to +70C 0C to +70C 0C to +70C -40C to +85C -40C to +85C 20 SSOP 20 SSOP Dice* Dice* 16 Plastic DIP 16 Plastic DIP 1 1 1 1 1 1 MAX520AEWE MAX520BEWE MAX520AEAP MAX520BEAP -40C to +85C -40C to +85C -40C to +85C -40C to +85C 16 Wide SO 16 Wide SO 20 SSOP 20 SSOP 1 1 1 1 MAX520AMJE MAX520BMJE MAX521ACPP MAX521BCPP -55C to +125C -55C to +125C 0C to +70C 0C to +70C 16 CERDIP 16 CERDIP 20 Plastic DIP 20 Plastic DIP 1 1 1 2 MAX521ACWG MAX521BCWG MAX521ACAG 0C to +70C 0C to +70C 0C to +70C 24 Wide SO 24 Wide SO 24 SSOP 1 2 1 MAX521BCAG MAX521BC/D MAX521AEPP MAX521BEPP 0C to +70C 0C to +70C -40C to +85C -40C to +85C 24 SSOP Dice* 20 Plastic DIP 20 Plastic DIP 2 2 1 2 MAX521AEWG MAX521BEWG MAX521AEAG -40C to +85C -40C to +85C -40C to +85C 24 Wide SO 24 Wide SO 24 SSOP 1 2 1 MAX521BEAG MAX521BMJP -40C to +85C -55C to +125C 24 SSOP 20 CERDIP 2 2 AGND DGND REF0 REF1 SCLK SDATA OUT0 OUT1 0.121" (3.073mm) OUT2 AD0 AD1 OUT3 AD2 REF2 V DD 0.098" (2.489mm) REF3 MAX521 REF1 OUT0 OUT1 OUT2 OUT3 REF2 REF0 REF3 DGND AGND * Dice are specified at TA = +25C, DC parameters only. MAX520 "A" grade parts include a 1%-accurate, factory-trimmed output resistance. 0.212" (5.385mm) SCL REF4 V DD AD1 SDA AD0 AGND OUT4 OUT5 OUT6 OUT7 0.125" (3.175mm) TRANSISTOR COUNT: 4518 SUBSTRATE CONNECTED TO VDD 18 ______________________________________________________________________________________ Quad/Octal, 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs D E DIM E1 A A1 A2 A3 B B1 C D1 E E1 e eA eB L A3 A A2 L A1 0 - 15 C e B1 eA B eB D1 Plastic DIP PLASTIC DUAL-IN-LINE PACKAGE (0.300 in.) INCHES MAX MIN 0.200 - - 0.015 0.175 0.125 0.080 0.055 0.022 0.016 0.065 0.045 0.012 0.008 0.080 0.005 0.325 0.300 0.310 0.240 - 0.100 - 0.300 0.400 - 0.150 0.115 PKG. DIM PINS P P P P P N D D D D D D 8 14 16 18 20 24 INCHES MIN MAX 0.348 0.390 0.735 0.765 0.745 0.765 0.885 0.915 1.015 1.045 1.14 1.265 MILLIMETERS MIN MAX - 5.08 0.38 - 3.18 4.45 1.40 2.03 0.41 0.56 1.14 1.65 0.20 0.30 0.13 2.03 7.62 8.26 6.10 7.87 2.54 - 7.62 - - 10.16 2.92 3.81 MILLIMETERS MIN MAX 8.84 9.91 18.67 19.43 18.92 19.43 22.48 23.24 25.78 26.54 28.96 32.13 21-0043A DIM D 0- 8 A e B 0.101mm 0.004in. A1 C L A A1 B C E e H L INCHES MAX MIN 0.104 0.093 0.012 0.004 0.019 0.014 0.013 0.009 0.299 0.291 0.050 0.419 0.394 0.050 0.016 DIM PINS E H Wide SO SMALL-OUTLINE PACKAGE (0.300 in.) D D D D D 16 18 20 24 28 INCHES MIN MAX 0.398 0.413 0.447 0.463 0.496 0.512 0.598 0.614 0.697 0.713 MILLIMETERS MIN MAX 2.35 2.65 0.10 0.30 0.35 0.49 0.23 0.32 7.40 7.60 1.27 10.00 10.65 0.40 1.27 MILLIMETERS MIN MAX 10.10 10.50 11.35 11.75 12.60 13.00 15.20 15.60 17.70 18.10 21-0042A ______________________________________________________________________________________ 19 MAX520/MAX521 ________________________________________________________Package Information MAX520/MAX521 Quad/Octal, 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs ___________________________________________Package Information (continued) DIM E H C L A A1 B C D E e H L INCHES MILLIMETERS MIN MAX MIN MAX 0.068 0.078 1.73 1.99 0.002 0.008 0.05 0.21 0.010 0.015 0.25 0.38 0.004 0.008 0.09 0.20 SEE VARIATIONS 0.205 0.209 5.20 5.38 0.0256 BSC 0.65 BSC 0.301 0.311 7.65 7.90 0.025 0.037 0.63 0.95 0 8 0 8 DIM PINS e SSOP SHRINK SMALL-OUTLINE PACKAGE A B A1 D D D D D 14 16 20 24 28 INCHES MILLIMETERS MAX MIN MAX MIN 6.33 0.239 0.249 6.07 6.33 0.239 0.249 6.07 7.33 0.278 0.289 7.07 8.33 0.317 0.328 8.07 0.397 0.407 10.07 10.33 21-0056A D Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 20 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 (c) 1996 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.