18 GHz Microwave PLL Synthesizer
Data Sheet
ADF41020
FEATURES
18 GHz maximum RF input frequency
Integrated SiGe prescaler
Software compatible with the ADF4106/ADF4107/ADF4108
family of PLLs
2.85 V to 3.15 V PLL power supply
Programmable dual-modulus prescaler
8/9, 16/17, 32/33, 64/65
Programmable charge pump currents
3-wire serial interface
Digital lock detect
Hardware and software power-down mode
4000 V HBM/1500 V CDM ESD performance
APPLICATIONS
Microwave point-to-point/multipoint radios
Wireless infrastructure
VSAT radios
Test equipment
Instrumentation
GENERAL DESCRIPTION
The ADF41020 frequency synthesizer can be used to implement
local oscillators as high as 18 GHz in the up conversion and
down conversion sections of wireless receivers and transmitters.
It consists of a low noise, digital phase frequency detector
(PFD), a precision charge pump, a programmable reference
divider, and high frequency programmable feedback dividers
(A, B, and P). A complete phase-locked loop (PLL) can be
implemented if the synthesizer is used with an external loop
filter and voltage controlled oscillator (VCO). The synthesizer
can be used to drive external microwave VCOs via an active
loop filter. Its very high bandwidth means a frequency doubler
stage can be eliminated, simplifying system architecture and
reducing cost. The ADF41020 is software-compatible with the
existing ADF4106/ADF4107/ADF4108 family of devices from
Analog Devices, Inc. Their pinouts match very closely with
the exception of the ADF41020’s single-ended RF input pin,
meaning only a minor layout change is required when updating
current designs.
FUNCTIONAL BLOCK DIAGRAM
Figure 1.
CLK
DATA
LE
REFIN
RFIN
24-BI T INP UT
REGISTER
AVDD DVDD
CEGND GND
R COUNTER
R COUNTER
LATCH
FUNCTION
LATCH
A, B CO UNTER
LATCH
P/P+ 1
N = 4(BP + A)
A AND B
M3 M2 M1
MUX
SDOUT
AVDD
HIGH-Z
MUXOUT
GND RSET
VP
CP
PHASE
FREQUENCY
DETECTOR
LOCK
DETECT
REFERENCE
CHARGE
PUMP
CURRENT
SETTING 1
ADF41020
CPI3 CPI2 CPI1 CPI6 CPI5 CPI4
CURRENT
SETTING 2
50Ω
3pF
COUNTERS
DIVIDE
BY 4
10304-001
Rev. C Document Feedback
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ADF41020 Data Sheet
Rev. C | Page 2 of 16
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Timing Characteristics ................................................................ 4
Absolute Maximum Ratings ............................................................ 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ............................. 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ........................................................................ 8
Reference Input Section ............................................................... 8
RF Input Stage ................................................................................8
Prescaler ..........................................................................................8
A Counter and B Counter ............................................................8
R Counter .......................................................................................9
PFD and Charge Pump .................................................................9
MUXOUT and Lock Detect .........................................................9
Input Shift Register .......................................................................9
The Function Latch .................................................................... 13
Applications Information .............................................................. 15
Interfacing ................................................................................... 15
PCB Design Guidelines ............................................................. 15
Outline Dimensions ....................................................................... 16
Ordering Guide .......................................................................... 16
REVISION HISTORY
12/14—Rev. B to Rev. C
Changes to Features Section............................................................ 1
Changes to Lock Detect Section ..................................................... 9
1/14—Rev. A to Rev. B
Changes to Figure 6 .......................................................................... 7
11/13—Rev. 0 to Rev. A
Changes to Features Section............................................................ 1
Changes to Absolute Maximum Ratings Section and Table 3 .... 5
10/12—Revision 0: Initial Version
Data Sheet ADF41020
SPECIFICATIONS
DVDD = AVDD = VP = 3.0 V ± 5%, GND = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω, TA = TMAX to TMIN, unless otherwise noted.
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
RF CHARACTERISTICS See Figure 1 for input circuit
RF Input Frequency (RFIN) 4.0 18.0 GHz
RF Input Sensitivity −10 +10 dBm
Maximum Allowable Prescaler
Output Frequency1
350 MHz
REFIN CHARACTERISTICS
REFIN Input Frequency 10 400 MHz For f < 10 MHz, ensure slew rate > 50 V/μs
REFIN Input Sensitivity 0.8 DVDD V p-p Biased at DVDD/2 when input is ac-coupled
REFIN Input Capacitance 10 pF
REFIN Input Current ±100 µA
PHASE DETECTOR
Phase Detector Frequency2 100 MHz
CHARGE PUMP Programmable, see Figure 17
ICP Sink/Source
High Value 5.0 mA With RSET = 5.1 kΩ
Low Value 625 µA
Absolute Accuracy 3 % With RSET = 5.1 kΩ
RSET 5.1 5.1 5.1 kΩ See Figure 17
ICP Three-State Leakage 1 2 nA TA = 25°C
Sink and Source Current Matching 2 % 0.5 V ≤ VCP ≤ VP − 0.5 V
ICP vs. VCP 1 % 0.5 V ≤ VCP ≤ VP − 0.5 V
ICP vs. Temperature 2 % VCP = VP/2
LOGIC INPUTS
V
IH
, Input High Voltage
1.4
V
The SPI interface is 1.8 V and 3 V logic compatible
VIL, Input Low Voltage 0.6 V
IINH, IINL, Input Current ±1 µA
CIN, Input Capacitance 10 pF
LOGIC OUTPUTS
VOH, Output High Voltage 1.4 V Open-drain output chosen, 1 kΩ pull-up resistor
to 1.8 V
VOH, Output High Voltage DVDD − 0.4 V CMOS output chosen
I
OH
, Output High Current
500
µA
VOL, Output Low Voltage 0.4 V
IOL, Output Low Current 500 µA
POWER SUPPLIES
AVDD 2.85 3.15 V
DVDD 2.85 3.15 V
VP 2.85 3.15 V
IDD3 27 30 mA TA = 25°C
IP3 4.5 5 mA TA = 25°C
Power-Down Mode 1 µA TA = 25°C
Rev. C | Page 3 of 16
ADF41020 Data Sheet
Parameter Min Typ Max Unit Test Conditions/Comments
NOISE CHARACTERISTICS
Normalized Phase Noise Floor4 −221 dBc/Hz PLL loop bandwidth = 500 kHz
Normalized 1/f Noise5 −118 dBc/Hz Normalized to 10 kHz offset at 1 GHz
Phase Noise Performance6 At VCO output
5.7 GHz
−89
dBc/Hz
At 1 kHz offset and 2.5 MHz PFD frequency with
20 kHz loop bandwidth
12.5 GHz7 −82 dBc/Hz At 3 kHz offset and 2.5 MHz PFD frequency with
20 kHz loop bandwidth
17.64 GHz −96 dBc/Hz At 100 kHz offset and 90 MHz PFD frequency with
700 kHz loop bandwidth
Spurious Signals
5.7 GHz −80/−86 dBc At 2.5 MHz/5 MHz and 2.5 MHz PFD frequency
12.5 GHz7 −98/<−110 dBc At 2.5 MHz/5 MHz and 2.5 MHz PFD frequency
17.64 GHz −109/−113 dBc At 90 MHz/180 MHz and 90 MHz PFD frequency
1 This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that
is less than this value.
2 Guaranteed by design. Sample tested to ensure compliance.
3 TA = 25°C; AVDD = DVDD = VP = 3.0 V; P = 16; fREFIN = 100 MHz; fPFD = 100 MHz; RFIN = 12.8 GHz.
4 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider
value) and 10 log fPFD. PNSYNTH = PNTOT − 10 log fPFD − 20 log N.
5 The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, fRF,
and at a frequency offset, f, is given by PN = PN1_f + 10 log(10 kHz/f) + 20 log(fRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in
ADIsimPLL.
6 The phase noise is measured with a Rohde & Schwarz FSUP spectrum analyzer. The reference is provided by a Rohde & Schwarz SMA100A.
7 The phase noise and spurious noise is measured with the EV-ADF41020EB1Z evaluation board and the Rohde & Schwarz FSUP spectrum analyzer.
TIMING CHARACTERISTICS
AVDD = DVDD = VP = 3.0 V, GN D = 0 V, R SET = 5.1 kΩ, dBm referred to 50 Ω, TA = TMAX to TMIN, unless otherwise noted.
Table 2.
Parameter Limit Unit Test Conditions/Comments
t1 10 ns min DATA to CLK setup time
t2 10 ns min DATA to CLK hold time
t3 25 ns min CLK high duration
t4 25 ns min CLK low duration
t5 10 ns min CLK to LE setup time
t6 20 ns min LE pulse width
Figure 2. Timing Diagram
CLK
DB22 DB2
DATA
LE
t
1
LE
DB23 (MS B)
t
2
DB1 (CO NTROL
BIT C2) DB0 (L S B)
(CO NTROL BI T C1)
t
3
t
4
t
6
t
5
10304-002
Rev. C | Page 4 of 16
Data Sheet ADF41020
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter Rating
AVDD to GND −0.3 V to +3.9 V
AVDD to DVDD −0.3 V to +0.3 V
VP to GND −0.3 V to +3.9 V
VP to AVDD −0.3 V to +0.3 V
Digital I/O Voltage, REFIN to GND −0.3 V to DVDD + 0.3 V
Analog I/O Voltage to GND −0.3 V to VP + 0.3 V
REF
IN
, RF
IN
to GND
−0.3 V to AV
DD
+ 0.3 V
Operating Temperature Range
Industrial −40°C to +85°C
Storage Temperature Range −65°C to +125°C
Maximum Junction Temperature 150°C
LFCSP θJA Thermal Impedance1
(Paddle Soldered)
62.82°C/W
Reflow Soldering
Peak Temperature 260°C
Time at Peak Temperature 40 sec
Transistor Count
CMOS 6610
Bipolar 358
ESD (Charged Device Model) 1500 V
ESD (Human Body Model) 4000 V
1 Two signal planes (that is, on the top and bottom surfaces of the board), two
buried planes, and four vias.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
Rev. C | Page 5 of 16
ADF41020 Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1, 2, 3, 5, 9, 10 GND Ground Pins.
4 RFIN Input to the RF Prescaler. This input is ac-coupled internally.
6, 7 AVDD Analog Power Supply. This may range from 2.85 V to 3.15 V. Decoupling capacitors to the ground plane
should be placed as close as possible to this pin. Pin 6 is the supply for the fixed divide-by-4 prescaler.
8 REFIN Reference Input. This is a CMOS input with a nominal threshold of DVDD/2 and a dc equivalent input
resistance of 100 kΩ (see Figure 9). This input can be driven from a TTL or CMOS crystal oscillator or it
can be ac-coupled.
11 CE Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into three-
state mode. Taking the pin high powers up the device, depending on the status of the power-down bit, PD1.
12 CLK Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into
the 24-bit shift register on the CLK rising edge. This is a high impedance CMOS input.
13 DATA Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This is a high
impedance CMOS input.
14 LE Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the
four latches with the latch being selected using the control bits.
15 MUXOUT This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference frequency to be
accessed externally.
16, 17 DVDD Digital Power Supply. This may range from 2.85 V to 3.15 V. Decoupling capacitors to the ground plane
should be placed as close as possible to this pin. DVDD must be the same value as AVDD.
18 VP Charge Pump Power Supply.
19 RSET Connecting a resistor between this pin and GND sets the maximum charge pump output current.
The nominal voltage potential at the RSET pin is 0.66 V. The relationship between ICP and RSET is
SET
MAXCP
R
I5.
25
=
So, with RSET = 5.1 kΩ, ICP MAX = 5.0 mA.
20
CP
Charge Pump Output. When enabled, this provides ±I
CP
to the external loop filter, which in turn drives the
external VCO.
EP Exposed Pad. The exposed pad must be connected to GND.
14
13
12
1
3
4
LE
15 MUXOUT
DATA
CLK
11 CE
GND
GND 2
GND
RFIN 5
GND
7
AVDD
6
AVDD
8
REFIN 9
GND 10
GND
19 RSET
20 CP
18 VP
17 DVDD
16 DVDD
TOP
VIEW
NOTES
1. THE EXPOSED PAD MUST BE
CONNE CTED T O G ND.
ADF41020
10304-003
Rev. C | Page 6 of 16
Data Sheet ADF41020
Rev. C | Page 7 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 4. RF Input Sensitivity
Figure 5. Charge Pump Output Characteristics
Figure 6. Closed-Loop Phase Noise, RF = 12.5 GHz, PFD = 2.5 MHz,
Loop Bandwidth = 20 kHz
Figure 7. REFIN Sensitivity
Figure 8. S-Parameters
–70
–60
–50
–40
–30
–20
–10
0
10
20
0 5 10 15 20 25
RF
IN
LEV
E
L (d B)
FRE Q U E NC Y ( GHz)
8/9 PRESCAL ER
16/17 PRESCALER
10304-004
–6
–5
–4
–3
–2
–1
0
1
2
3
4
5
6
0 0.5 1.0 1.5 2.0 2.5 3.0
I
CP
(mA)
V
CP
(V)
0.625mA
1.25mA
1.875mA
2.5mA
3.125mA
3.75mA
4.375mA
5.0mA
0.625mA
1.25mA
1.875mA
2.5mA
3.125mA
3.75mA
4.375mA
5.0mA
10304-005
–180
–160
–140
–120
–100
–80
–60
–40
–20
0
1k 10k 100k 1M 10M
PHASE NOISE (dBc/Hz)
FREQUENCY OFF SET (Hz)
10304-006
FRE QUENCY (M Hz)
10304-007
–25
–20
–15
–10
–5
0
5
10
0 100 200 300 400 500 600 700 800 900 1000
REFERENCE SENSITIVITY (dBm)
FREQ MAGS11 ANGS11 FREQ MAGS11 ANGS11
FREQ UNIT: GHz KEYWORD: R
PARAM TYPE: s
DATA FORMAT: M A
0.20099200
0.19669930
0.19140480
0.18317790
0.17232760
0.16071930
0.14943970
0.13791310
0.12839340
0.12090700
0.11516160
0.11252430
0.11213720
0.11236920
0.11323590
0.11401910
0.11361600
0.11225360
0.10909150
0.10484100
0.09871251
0.09258573
0.08667851
0.08075383
0.07542522
0.07048169
0.06751262
0.06561201
0.06308079
0.05995205
0.05666475
4.0
4.2
4.4
4.6
4.8
5.0
5.2
5.4
5.6
5.8
6.0
6.2
6.4
6.6
6.8
7.0
7.2
7.4
7.6
7.8
8.0
8.2
8.4
8.6
8.8
9.0
9.2
9.4
9.6
9.8
10.0
–133.9429000
–134.7069000
–135.0024000
–135.1249000
–135.0415000
–135.1840000
–136.0447000
–137.7694000
–140.5623000
–144.7454000
–149.8260000
–155.1801000
–160.0477000
–164.5794000
–168.1217000
–170.9163000
–173.2882000
–175.2539000
–176.9327000
–179.0774000
178.5525000
175.9697000
172.5878000
168.3692000
163.5676000
159.0954000
154.6976000
149.2087000
142.2284000
137.8226000
134.1730000
0.05542031
0.05306026
0.05123230
0.04471957
0.03846882
0.03402513
0.04456061
0.05158395
0.06039219
0.05580344
0.08402054
0.10374910
0.11639920
0.13647950
0.16700580
0.18309070
0.19458010
0.20377790
0.21170140
0.21883690
0.22280700
0.22498210
0.22589250
0.22572100
0.22596830
0.23197900
0.24339450
0.26023130
0.28636130
0.31905490
10.2
10.4
10.6
10.8
11.0
11.4
11.8
12.2
12.6
13.0
13.4
13.8
14.2
14.6
15.0
15.2
15.4
15.6
15.8
16.0
16.2
16.4
16.6
16.8
17.0
17.2
17.4
17.6
17.8
18.0
130.0581000
126.9556000
115.8988000
102.0333000
86.3895600
51.1515300
21.0829700
16.8124600
16.5178200
31.4631600
36.3540700
18.8428500
0.2817307
–15.4473000
–22.3273100
–24.3333900
–25.3870800
–25.0101800
–24.2554800
–23.4312200
–23.5596400
–24.411100
–26.5202700
–30.3773300
–36.2808700
–42.8398200
–50.7222200
–57.5844600
–63.0764200
–67.5389600
10304-008
ADF41020 Data Sheet
Rev. C | Page 8 of 16
THEORY OF OPERATION
REFERENCE INPUT SECTION
The reference input stage is shown in Figure 9. SW1 and SW2
are normally closed switches. SW3 is a normally open switch.
When power-down is initiated, SW3 is closed and SW1 and
SW2 are opened. This ensures that there is no loading of the
REFIN pin on power-down.
Figure 9. Reference Input Stage
RF INPUT STAGE
The RF input stage is shown in Figure 10. It is followed by a
buffer, which generates the differential CML levels needed for
the prescaler.
Figure 10. RF Input Stage
PRESCALER
The ADF41020 uses a two prescaler approach to achieve
operation up to 18 GHz. The first prescaler is a fixed
divide-by-4 block. The second prescaler, which takes its
input from the divide-by-4 output, is implemented as a dual-
modulus prescaler (P/P + 1), which allows finer frequency
resolution vs. a fixed prescaler. Along with the A counter and
B counter, this enables the large division ratio, N, to be realized
(N = 4(BP + A)). The dual-modulus prescaler, operating at
CML levels, takes the clock from the fixed prescaler stage and
divides it down to a manageable frequency for the CMOS A
counter and B counter. The second prescaler is programmable.
It can be set in software to 8/9, 16/17, 32/33, or 64/65. It is
based on a synchronous 4/5 core. There is a minimum divide
ratio possible for contiguous output frequencies. This minimum
is given by 4(P2 − P).
A COUNTER AND B COUNTER
The A counter and B counter combine with the two prescalers
to allow a wide ranging division ratio in the PLL feedback
counter. The counters are specified to work when the prescaler
output is 350 MHz or less.
Pulse Swallow Function
Because of the fixed divide-by-4 block, the generated output
frequencies are spaced by four times the reference frequency
divided by R. The equation for VCO frequency is
R
f
ABPf IN
REF
VCO
4
)(
where:
fVCO is the output frequency of the external voltage controlled
oscillator (VCO).
P is the preset modulus of the dual-modulus prescaler
(such as, 8/9, 16/17).
B is the preset divide ratio of the binary 13-bit counter
(2 to 8191).
A is the preset divide ratio of the binary 6-bit swallow
counter (0 to 63).
fREFIN is the external reference frequency oscillator.
Figure 11. Prescalers, A and B Counters that Make Up the N-Divide Value
REF
IN
SW1
SW2
SW3
100kΩ
NC
NO
NC
BUFFER
POWER-DOWN
CONTROL
TO R COUNTER
10304-009
50Ω
GND
RF
IN
AV
DD
3pF
BUFFER
TO DIVIDE BY 4
PRESCALER
10304-010
LOAD
LOAD
FROM RF INPUT
BUFFER
PRESCALER
P/P + 1
13-BIT B
COUNTER
TO PFD
6-BIT A
COUNTER
N DIVIDER
MODULUS
CONTROL
N = 4(BP + A)
DIVIDE BY 4
10304-011
Data Sheet ADF41020
R COUNTER
The 14-bit R counter allows the input reference frequency to
be divided down to produce the reference clock to the phase
frequency detector (PFD). Division ratios from 1 to 16,383
are allowed.
PFD AND CHARGE PUMP
The PFD takes inputs from the R counter and N counter and
produces an output proportional to the phase and frequency
difference between them. Figure 13 is a simplified schematic.
The PFD includes a fixed delay element that controls the
width of the antibacklash pulse. This pulse ensures that there
is no dead zone in the PFD transfer function and minimizes
phase noise and reference spurs. The charge pump converts the
PFD output to current pulses, which are integrated by the PLL
loop filter.
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF41020 allows the user
to access various internal points on the chip. The state of
MUXOUT is controlled by M3, M2, and M1 in the function
latch. Figure 17 shows the full truth table. Figure 12 shows
the MUXOUT section in block diagram form.
Lock Detect
MUXOUT can be programmed with digital lock detect.
Digital lock detect is active high. Digital lock detect is set high
when the phase error on five consecutive phase detector cycles
is less than 15 ns. It stays set high until a phase error of greater
than 25 ns is detected on any subsequent PD cycle.
Figure 12. MUXOUT Circuit
INPUT SHIFT REGISTER
The ADF41020 digital section includes a 24-bit input shift
register, a 14-bit R counter, and a 19-bit N counter, comprising
a 6-bit A counter and a 13-bit B counter. Data is clocked into
the 24-bit shift register on each rising edge of CLK. The data is
clocked in MSB first. Data is transferred from the shift register
to one of three latches on the rising edge of LE. The destination
latch is determined by the state of the two control bits (C2, C1)
in the shift register. C2 and C1 are the two LSBs, DB1 and DB0,
as shown in the timing diagram of Figure 2. The truth table for
these bits is shown in Table 5. Table 5 shows a summary of
how the latches are programmed. The SPI is both 1.8 V and
3 V compatible.
Table 5. C1, C2 Truth Table
Control Bits
Data Latch
C2 C1
0
0
R counter
0 1 N counter (A and B)
1 0 Function latch (including prescaler)
Figure 13. PFD Simplified Schematic
10304-013
GND
DV
DD
CONTROL
MUX
DIGITAL LOCK DETECT
R COUNT E R OUT P UT
N COUNT E R OUT P UT
SDOUT
MUXOUT
HIGH
HIGH
D1
D2
Q1
Q2
CLR2
CP
U1
U2
UP
DOWN
GND
U3
R DIVIDER
FIXED
DELAY
N DIVIDER
VPCHARGE
PUMP
CLR1
10304-012
Rev. C | Page 9 of 16
ADF41020 Data Sheet
Figure 14. Latch Summary
Figure 15. Reference Counter Latch Map
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C2 (0) C1 (0)R1R2R3R4R5
R6
R7R8R9R10R11R12R13R1410001
DB21
DB22DB23
0 01
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C2 (0) C1 (1)
A1A2A3A4A5B1B2B3B4B5B6B7B8B9B10B11B12B13 A6
DB21
DB22DB23
G100
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C2 (1) C1 (0)F1PD1M1M2M3F3P1P2 CPI1CPI2CPI5CPI6 TC4PD2 F2
CPI3CPI4
DB21
TC3 TC2 TC1
DB22DB23
F4F5
REF ERE NCE COUNT E R LAT CH
RESERVED 14-BIT RE FERENCE COUNT E R CONTROL
BITS
RESERVED 13-BIT B COUNTE R 6-BI T A COUNTER CONTROL
BITS
N COUNTER L ATCH
CP GAIN
FUNCTION L ATCH
PRESCALER
VALUE
POWER-
DOWN 2
CURRENT
SETTING
2
CURRENT
SETTING
1
TIMER COUNT E R
CONTROL
FAST LOCK
MODE
FAST LOCK
ENABLE
CP T HREE -
STATE
PD
POLARITY
MUXOUT
CONTROL
POWER-
DOWN 1
COUNTER
RESET
CONTROL
BITS
10304-014
R14 R13 R12 .......... R3 R2 R1
000.......... 0 0 1 1
000.......... 0 1 0 2
000.......... 0 1 1 3
000.......... 1 0 0 4
............. . . . .
............. . . . .
............. . . . .
111.......... 10016380
111.......... 10116381
111.......... 11016382
111.......... 11116383
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C2 (0) C1 (0)R1R2R3R4R5R6R7R8R9R10R11R12R13R1410001
DB21DB22DB23
0 01
RESERVED 14-BIT RE FERENCE COUNT E R CONTROL
BITS
DIVIDE RATI O
10304-015
Rev. C | Page 10 of 16
Data Sheet ADF41020
Figure 16. N (A, B) Counter Latch Map
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C2 (0) C1 (1)
A1A2
A3
A4A5
B1B2B3B4B5B6
B7B8
B9B10
B11
B12B13 A6
DB21
DB22
DB23
G1
0 0
01
10
F4 (FUNCT ION LAT CH)
FASTL OCK ENABL E
11
A6 A5 .......... A2 A1
00.......... 00 0
0 0 .......... 011
0 0 .......... 10 2
00.......... 1 1 3
. . .......... . . .
. . .......... . . .
. . .......... .. .
11.......... 0 0 60
11.......... 0161
11.......... 1 0 62
1 1 .......... 1163
00
B13 B12 B11 B3 B2 B1
00 0 .......... 00 0
00 0.......... 00 1
0 0 0.......... 0 1 0
00 0.......... 0 1 1 3
.. . .......... .. . .
. . ........... .. . .
.. ........... . . . .
1 1 1 .......... 1 0 0 8188
1 1 1 .......... 10 1 8189
1 1 1.......... 1 1 0 8190
11 1.......... 1 1 1 8191
RESERVED 13-BIT B COUNT E R 6-BIT A CO UNTER CONTROL
BITS
CP GAIN
A COUNT E R
DIVIDE RATIO
B COUNT E R DIVIDE RAT IO
NOT ALLOWED
NOT ALLOWED
2
OPERATIONCP GAIN
CHARGE P UM P CURRE NT
SETTING 1 IS PERMANENTLY USED.
CHARGE P UM P CURRE NT
SETTING 2 IS PERMANENTLY USED.
CHARGE P UM P CURRE NT
SETTING 1 IS USED.
CHARGE P UM P CURRE NT I S
SWITCHED TO SETTING 2. THE
TIME SPENT IN SETTING 2 IS
DEPENDE NT O N WHICH FAST LOCK
MODE IS USED. SEE FUNCTION
LAT CH DE S CRIPTION. N = 4(BP + A) , P IS A PRE S CALER V ALUE SE T I N THE F UNCTI ON
LAT CH. B MUS T BE G RE ATER THAN OR E QUAL TO A. F OR
CONT INUO US LY ADJACENT VALUES OF ( N × FREF ) , AT THE
OUTPUT, N MIN IS 4(P
2
– P).
BOTH OF THESE BITS
MUST BE SET TO 0 FOR
NORMAL O P E RATION.
10304-016
Rev. C | Page 11 of 16
ADF41020 Data Sheet
Figure 17. Function Latch Map
10304-017
P2 P1
0 0 8/9
0 1 16/17
1 0 32/33
1 1 64/65
PD2 PD1 MODE
00X
10 0
1 0 1
CPI6 CPI5 CPI4
CPI3 CPI2 CPI1
000
001
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
TC4 TC3 TC2 TC1
00003
000 1 7
0 0 1 0 11
0 0 1115
010019
010123
011027
011131
100035
100139
101043
101147
1 1 0 0 51
1 1 0 1 55
111059
1 1 1 1 63
F4
0
1
1
M3 M2 M1
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
F3
0
1
F2
0
1
F1
0
1
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C2 (1) C1 (0)
F1
PD1
M1
M2
M3
F3P1
P2 CPI1CPI2CPI5
CPI6 TC4PD2 F2CPI3CPI4
DB21
TC3 TC2 TC1
DB22DB23
F4
F5
F5
X
0
1
NEGATIVE
POSITIVE
PRESCALER
VALUE
POWER-
DOWN 2
CURRENT
SETTING
2
CURRENT
SETTING
1
TIMER COUNT E R
CONTROL
FAST LOCK
MODE
FAST LOCK
ENABLE
CP THREE-
STATE
MUXOUT
CONTROL
POWER-
DOWN 1
COUNTER
RESET
CONTROL
BITS
PHASE DETECTOR
POLARITYCOUNTER
OPERATION
NORMAL
R, A, B CO UNTERS
HEL D I N RE S E T
CHARGE P UMP
OUTPUT
NORMAL
THREE-STATE
FAS T LOCK DI S ABLED
FAS T LOCK MODE 1
FAS T LOCK MODE 2
FAS T LOCK MODE
THREE-STATE OUTPUT
DIGITAL L OCK DETECT
(ACT IVE HIG H)
N DIVIDER OUT P UT
DV
DD
R DIVIDER OUT P UT
RESERVED
SERIAL DATA OUTP UT
DGND
OUTPUT
TIMEOUT
(PFD CYCLES)
I
CP
(mA)
ASYNCHRO NOUS P OW E R- DOW N
NORMAL OPERATION
SOFTWARE POWER-DOW N
CE PIN
PRESCALER VALUE
PD
POLARITY
0.625
1.25
1.875
2.5
3.125
3.75
4.375
5.0
Rev. C | Page 12 of 16
Data Sheet ADF41020
THE FUNCTION LATCH
With C2 and C1 set to 1 and 0, respectively, the on-chip
function latch is programmed. Figure 17 shows the input
data format for programming the function latch.
Counter Reset
DB2 (F1) is the counter reset bit. When this is 1, the R counter
and the N (A, B) counter is reset. For normal operation, this bit
should be 0. When powering up, disable the F1 bit (set to 0).
The N counter then resumes counting in close alignment with
the R counter. (The maximum error is one prescaler cycle).
Power-Down
Bit DB3 (PD1) provides a software power-down mode to reduce
the overall current drawn by the device. It is enabled by the CE
pin. When the CE pin is low, the device is immediately disabled
regardless of the state of PD1.
In the programmed software power-down, the device powers
down immediately after latching 1 into the PD1 bit. PD2 is a
reserved bit and should be cleared to 0.
When a power-down is activated, the following events occur:
• All active dc current paths in the main synthesizer section
are removed. However, the RF divide-by-4 prescaler
remains active.
• The R, N, and timeout counters are forced to their load
state conditions.
• The charge pump is forced into three-state mode.
• The digital clock detect circuitry is reset.
• The RFIN input is debiased.
• The reference input buffer circuitry is disabled.
• The input register remains active and capable of loading
and latching data.
MUXOUT Control
The on-chip multiplexer is controlled by M3, M2, and M1 on
the ADF41020. Figure 17 shows the truth table.
Fast Lock Enable Bit
Bit DB9 (F4) of the function latch is the fast lock enable bit.
When this bit is 1, fast lock is enabled.
Fast Lock Mode Bit
Bit DB10 (F5)of the function latch is the fast lock mode bit.
When fast lock is enabled, this bit determines which fast lock
mode is used. If the fast lock mode bit is 0, then Fast Lock
Mode 1 is selected; and if the fast lock mode bit is 1, then Fast
Lock Mode 2 is selected.
Fast Lock Mode 1
The charge pump current is switched to the contents of Current
Setting 2. The device enters fast lock when 1 is written to the CP
gain bit in the N (A, B) counter latch. The device exits fast lock
when 0 is written to the CP gain bit in the N (A, B) counter latch.
Fast Lock Mode 2
The charge pump current is switched to the contents of Current
Setting 2. The device enters fast lock when 1 is written to the
CP gain bit in the N (A, B) counter latch. The device exits fast
lock under the control of the timer counter. After the timeout
period, which is determined by the value in TC4 to TC1, the CP
gain bit in the N (A, B) counter latch is automatically reset to 0,
and the device reverts to normal mode instead of fast lock. See
Figure 17 for the timeout periods.
Timer Counter Control
The user has the option of programming two charge pump
currents. The intent is that Current Setting 1 is used when the
RF output is stable and the system is in a static state. Current
Setting 2 is used when the system is dynamic and in a state of
change (that is, when a new output frequency is programmed).
The normal sequence of events follows.
The user initially decides what the preferred charge pump
currents are going to be. For example, the choice may be
0.85 mA as Current Setting 1 and 1.7 mA as Current Setting 2.
Simultaneously, the decision must be made as to how long the
secondary current stays active before reverting to the primary
current. This is controlled by the timer counter control bits,
DB14 to DB11 (TC4 to TC1), in the function latch. The truth
table is given in Figure 17.
To program a new output frequency, simply program the N (A, B)
counter latch with new values for A and B. Simultaneously, the
CP gain bit can be set to 1, which sets the charge pump with the
value in CPI6 to CPI4 for a period of time determined by TC4
to TC1. When this time is up, the charge pump current reverts
to the value set by CPI3 to CPI1. At the same time, the CP gain
bit in the N (A, B) counter latch is reset to 0 and is ready for the
next time the user wishes to change the frequency.
Note that there is an enable feature on the timer counter. It is
enabled when Fast Lock Mode 2 is chosen by setting the fast
lock mode bit (DB10) in the function latch to 1.
Charge Pump Currents
CPI3, CPI2, and CPI1 program Current Setting 1 for the charge
pump. CPI6, CPI5, and CPI4 program Current Setting 2 for the
charge pump. The truth table is given in Figure 17.
Prescaler Value
P2 and P1 in the function latch set the programmable P
prescaler value. The P value should be chosen so that the
prescaler output frequency is always less than or equal to
350 MHz.
PD Polarity
Bit DB7 (F2) sets the phase detector polarity bit. See Figure 17.
Rev. C | Page 13 of 16
ADF41020 Data Sheet
CP Three-State
Bit DB8 (F3) controls the CP output pin. With the bit set high,
the CP output is put into three-state. With the bit set low, the
CP output is enabled.
Device Programming After Initial Power-Up
After initial power up of the device, there are three methods for
programming the device: function latch, CE pin, and counter
reset.
Function Latch Method
1. Apply VDD.
2. Program the function latch load (10 in two LSBs of the
control word), making sure that the F1 bit is programmed
to a 0.
3. Do an R load (00 in two LSBs).
4. Do an N (A, B) load (01 in two LSBs).
CE Pin Method
1. Apply VDD.
2. Bring CE low to put the device into power-down. This is an
asychronous power-down in that it happens immediately.
3. Program the function latch (10).
4. Program the R counter latch (00).
5. Program the N (A, B) counter latch (01).
6. Bring CE high to take the device out of power-down. The
R and N (A, B) counters now resume counting in close
alignment.
Note that after CE goes high, a 1 µs duration may be required
for the prescaler band gap voltage and oscillator input buffer
bias to reach steady state.
CE can be used to power the device up and down to check
for channel activity. The input register does not need to be
reprogrammed each time the device is disabled and enabled
as long as it is programmed at least once after VDD is initially
applied.
Counter Reset Method
1. Apply VDD.
2. Do a function latch load (10 in two LSBs). As part of this,
load 1 to the F1 bit. This enables the counter reset.
3. Do an R counter load (00 in two LSBs).
4. Do an N (A, B) counter load (01 in two LSBs).
5. Do a function latch load (10 in two LSBs). As part of this,
load 0 to the F1 bit. This disables the counter reset.
This sequence provides direct control over the internal
counter reset.
Rev. C | Page 14 of 16
Data Sheet ADF41020
Rev. C | Page 15 of 16
APPLICATIONS INFORMATION
INTERFACING
The ADF41020 has a simple 1.8 V and 3 V SPI-compatible
serial interface for writing to the device. CLK, DATA, and
LE control the data transfer. When LE goes high, the 24 bits
clocked into the input register on each rising edge of CLK
are transferred to the appropriate latch. See Figure 2 for the
timing diagram and Table 5 for the latch truth table.
The maximum allowable serial clock rate is 20 MHz.
ADuC7020 Interface
Figure 18 shows the interface between the ADF41020 and the
ADuC7019 to ADuC7023 family of analog microcontrollers.
The ADuC70xx family is based on an AMR7 core, although the
same interface can be used with any 8051-based micro-
controller. The microcontroller is set up for SPI master mode
with CPHA = 0. To initiate the operation, the I/O port driving
LE is brought low. Each latch of the ADF41020 needs a 24-bit
word. This is accomplished by writing three 8-bit bytes from the
microcontroller to the device. When the third byte is written,
bring the LE input high to complete the transfer.
On first applying power to the ADF41020, it needs three writes
(one each to the function latch, R counter latch, and N counter
latch) for the output to become active.
I/O port lines on the microcontroller are also used to control
power-down (CE input) and to detect lock (MUXOUT
configured as lock detect and polled by the port input).
When operating in the mode described, the maximum SPI
transfer rate of the ADuC7023 is 20 Mbps. This means that
the maximum rate at which the output frequency can be
changed is 833 kHz. If using a faster SPI clock, ensure
adherence to the SPI timing requirements listed in Table 1.
Figure 18. ADuC70xx-to-ADF41020 Interface
Blackfin BF527 Interface
Figure 19 shows the interface between the ADF41020 and
the Blackfin® ADSP-BF527 digital signal processor (DSP). The
ADF41020 needs a 24-bit serial word for each latch write. The
easiest way to accomplish this using the Blackfin family is to
use the autobuffered transmit mode of operation with alternate
framing. This provides a means for transmitting an entire block
of serial data before an interrupt is generated. Set up the word
length for 8 bits and use three memory locations for each 24-bit
word. To program each 24-bit latch, store the three 8-bit bytes,
enable the autobuffered mode, and write to the transmit register
of the DSP. This last operation initiates the autobuffer transfer.
As in the microcontroller case, ensure the clock speeds are
within the maximum limits outlined in Table 1.
Figure 19. ADSP-BF527-to-ADF41020 Interface
PCB DESIGN GUIDELINES
The lands on the LFCSP (CP-20) are rectangular. The printed
circuit board (PCB) pad for these should be 0.1 mm longer than
the package land length and 0.05 mm wider than the package
land width. Center the land on the pad to ensure that the solder
joint size is maximized. The bottom of the LFCSP has a central
thermal pad.
The thermal pad on the PCB should be at least as large as the
exposed pad. To avoid shorting, on the PCB, provide a
clearance of at least 0.25 mm between the thermal pad and the
inner edges of the pad pattern.
Thermal vias may be used on the PCB thermal pad to improve
thermal performance of the package. If vias are used, they should
be incorporated in the thermal pad at 1.2 mm pitch grid. The
via diameter should be between 0.3 mm and 0.33 mm, and plate
the via barrel with 1 oz copper to plug the via.
Connect the PCB thermal pad to GND.
CLK
DATA
LE
CE
MUXOUT
(L OCK DE TECT)
MOSI
ADF41020
SCLOCK
I/O PORTS
ADuC70xx
10304-018
CLK
DATA
LE
CE
MUXOUT
(LOCK DET E CT)
MOSI
ADF41020
SCK
I/O FLAGS
ADSP-BF527 GPIO
10304-019
ADF41020 Data Sheet
Rev. C | Page 16 of 16
OUTLINE DIMENSIONS
Figure 20. 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Very Thin Quad
(CP-20-6)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
ADF41020BCPZ −40°C to +85°C 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-20-6
ADF41020BCPZ-RL7 −40°C to +85°C 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-20-6
EV-ADF41020EB1Z Evaluation Board
1 Z = RoHS Compliant Part.
0.50
BSC
0.65
0.60
0.55
0.30
0.25
0.18
COMPLIANT
TO
JEDEC STANDARDS MO-220-WGGD-1.
BOTTOM VIEWTOP VIEW
EXPOSED
PAD
PIN1
INDICATOR
4.10
4.00 SQ
3.90
SEATING
PLANE
0.80
0.75
0.70 0.05 MAX
0.02 NOM
0.20 REF
0.20 MIN
COPLANARITY
0.08
PIN 1
INDICATOR
2.30
2.10 SQ
2.00
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
1
20
6
10
11
1516
5
08-16-2010-B
©2012–2014 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10304-0-12/14(C)
