1998 Microchip Technology Inc. DS30289A-page 1

Microcontroller Core Features:

• Only 58 single word instructions to learn

• All single cycle instructions (121 ns) except for

program branches and table reads/writes which

are two-cycle

• Operating speed:

• 16 level deep hardware stack

• Direct, indirect, and relative addressing modes

• Internal/external program memory execution,

space

Peripheral Features:

• Up to 66 I/O pins with individual direction control

• 10-bit, multi-channel analog-to-digital converter

• High current sink/source for direct LED drive

• TMR2: 8-bit timer/counter

• TMR3: 16-bit timer/counter

• Two Universal Synchronous Asynchronous

dent baud rate generators

• Synchronous Serial Port (SSP) with SPI™ and

C™ modes (including I

C master mode)

and Oscillator Start-up Timer (OST)

oscillator for reliable operation

- 100

A typical @ 4.5V, 32 kHz

- < 1

VSS

VDD

80-Pin QFP

7.0 Memory Organization......................................................................................................................................41

8.0 Table Reads and Table Writes .......................................................................................................................57

9.0 Hardware Multiplier.........................................................................................................................................65

10.0 I/O Ports..........................................................................................................................................................69

11.0 Overview of Timer Resources.........................................................................................................................93

12.0 Timer0.............................................................................................................................................................95

13.0 Timer1, Timer2, Timer3, PWMs and Captures...............................................................................................99

14.0 Universal Synchronous Asynchronous Receiver Transmitter (USART) Modules.........................................115

15.0 Master Synchronous Serial Port (MSSP) Module.........................................................................................131

16.0 Analog-to-Digital Converter (A/D) Module ....................................................................................................177

Appendix A: Modifications..........................................................................................................................................283

Appendix B: Compatibility..........................................................................................................................................283

Appendix C: What’s New............................................................................................................................................284

Appendix D: What’s Changed....................................................................................................................................284

Appendix E: I

Appendix F: Status and Control Registers.................................................................................................................291

On-Line Support..........................................................................................................................................................321

Reader Response .......................................................................................................................................................322

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The last character of the literature number is the version number. e.g., DS30000A is version A of document DS30000.

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sion of silicon and revision of document to which it applies.

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We appreciate your assistance in making this a better document.

This data sheet covers the PIC17C7XX group of the

PIC17CXXX family of microcontrollers. The following

devices are discussed in this data sheet:

• PIC17C752

• PIC17C756A

• PIC17C762

Maximum Frequency

of Operation 33 MHz 33 MHz 33 MHz 33 MHz 33 MHz 33 MHz 33 MHz

Operating Voltage Range 2.5 - 6.0V 2.5 - 6.0V 2.5 - 6.0V 3.0 - 5.5V 3.0 - 5.5V 3.0 - 5.5V 3.0 - 5.5V

Program

Memory ( x16) (EPROM) 2K 4K 8K 8K 16K 8K 16K

Timer3 (16-bit) Yes Yes Yes Yes Yes Yes Yes

Capture inputs (16-bit) 2 2 24444

PWM outputs (up to 10-bit) 2 2 23333

A/D channels (10-bit) — — —12121616

SSP (SPI/I

mode) — — — Yes Yes Yes Yes

Power-on Reset Yes Yes Yes Yes Yes Yes Yes

ming — — — Yes Yes Yes Yes

I/O Pins 33 33 33 50 50 66 66

I/O High Cur-

rent Capability Source 25 mA 25 mA 25 mA 25 mA 25 mA 25 mA 25 mA

25 mA

25 mA

25 mA

P ackage Types 40-pin DIP

44-pin PLCC

44-pin PLCC

68-pin LCC

84-pin

84-pin

Each device has a variety of frequency ranges and

packaging options . Depending on application and pro-

duction requirements, the proper device option can be

sheet. When placing orders, please use the

“PIC17C7XX Product Identification System” at the back

of this data sheet to specify the correct part number.

When discussing the functionality of the device, mem-

ified in the middle characters of the part number.

and voltage range designators for a particular device.

These designators are in

TABLE 2-1: DEVICE MEMORY

Devices

Devices

cost option for high volume, mature products.

ROM devices do not allow serialization information in

the program memory space.

tact your regional sales office.

The high performance of the PIC17CXXX can be attrib-

found in RISC microprocessors. To begin with, the

word instructions. The full 16-bit wide program mem-

between program and data memory.

A simplified block diagram is shown in Figure 3-1. The

descriptions of the device pins are listed in Table 3-1.

(microprocessor mode) or both (extended microcon-

allow code protection.

LF 455 kHz

10 - 33 pF

16.0 MHz

22 - 68 pF

Higher capacitance increases the stability of the oscillator

but also increases the start-up time. These values are for

455 kHz Panasonic EFO-A455K04B ± 0.3%

2.0 MHz Murata Erie CSA2.00MG ± 0.5%

4.0 MHz Murata Erie CSA4.00MG ± 0.5%

8.0 MHz Murata Erie CSA8.00MT ± 0.5%

16.0 MHz Murata Erie CSA16.00MX ± 0.5%

FIGURE 4-3: CRYSTAL OPERATION,

OVERTONE CRYSTALS (XT

OSC CONFIGURATION)

T ABLE 4-2: CAPACITOR SELECTION FOR

CRYSTAL OSCILLATOR

LF 32 kHz(1)

16 MHz

25 MHz

47-100 pF

15-68 pF

15-47 pF

15-47 pF

10 pF

2: RS of 330Ω is required for a capacitor com-

L*C2 =(2πf)2

Where f = tank circuit resonant frequency. This should be

midway between the fundamental and the 3rd overtone

frequencies of the crystal.

C3 handles current during charging of tank circuit.

Clock from

CLKOUT

(FOSC/4)

RESONANT CRYSTAL

OSCILLATOR CIRCUIT

10 kΩ

330 Ω

330 Ω

quency is a function of the supply voltage, the resistor

temperature. In addition to this, oscillator frequency

will vary from unit to unit due to normal process param-

eter variation. Furthermore, the difference in lead

frame capacitance between package types will also

ately start its oscillations once the pin voltage levels

meet the input threshold specifications (parameter

tion section). The time required for the RC to start

oscillating depends on many factors. These include:

state”. The TO and PD bits are set or cleared diff erently

in different reset situations as indicated in Table 5-3.

These bits, in conjunction with the POR and BOR bits,

are used in software to determine the nature of the

reset. See Table 5-4 for a full description of the reset

states of all registers.

Note: While the device is in a reset state, the

execution will force the RE0/ALE pin as a

pins as high outputs.

FIGURE 5-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

SLEEP and OSC type is XT or LF)

† This RC oscillator is shared with the WDT

5.1.1 POWER-ON RESET (POR)

tions for details.

Figure 5-2 and Figure 5-3 show two possible POR cir-

cuits.

FIGURE 5-2: USING ON-CHIP POR

FIGURE 5-3: EXTERNAL POWER-ON

VDD

The Power-up Timer provides a fixed 96 ms time-out

oscillator. The chip is kept in RESET as long as the

PWRT is active. In most cases the PWRT delay allows

VDD to rise to an acceptable level.

or LF mode. The PWRT and OST operate in parallel.

The OST counts the oscillator pulses on the

OSC1/CLKIN pin. The counter only starts incrementing

after the amplitude of the signal reaches the oscillator

or resonator to stabilize before the device exits reset.

The length of the time-out is a function of the crys-

tal/resonator frequency.

Figure 5-4 shows the operation of the OST circuit. In

PWRT TIME_OUT

INTERNAL RESET

TPWRT

and PWRT timers start. In general the PWRT time-out

Figure 5-6 display these time-out sequences.

would be the case in higher frequency crystals. For

lower frequency crystals, (i.e., 32 kHz) TOST may be

DDRB 11h 1111 1111 1111 1111 uuuu uuuu

RCSTA1 13h 0000 -00x 0000 -00u uuuu -uuu

RCREG1 14h xxxx xxxx uuuu uuuu uuuu uuuu

TXSTA1 15h 0000 --1x 0000 --1u uuuu --uu

TXREG1 16h xxxx xxxx uuuu uuuu uuuu uuuu

SPBRG1 17h 0000 0000 0000 0000 uuuu uuuu

Prior to disabling any of the INTSTA enable bits, the

GLINTD bit should be set (disabled).

Note: All interrupt flag bits get set by their speci-

FIGURE 6-2: INTSTA REGISTER (ADDRESS: 07h, UNBANKED)

R - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0

interrupt logic forces program execution to address (20h) when a peripheral interrupt is pending.

1 =A peripheral interrupt is pending

0 =No peripheral interrupt is pending

This bit is cleared by hardware, when the interrupt logic forces program execution to address (18h).

1 =The software specified edge occurred on the RA1/T0CKI pin

0 =The software specified edge did not occur on the RA1/T0CKI pin

This bit is cleared by hardware, when the interrupt logic forces program execution to address (10h).

1 =TMR0 overflowed

1 =Enable peripheral interrupts

0 =Disable peripheral interrupts

1 =Enable software specified edge interrupt on the RA1/T0CKI pin

0 =Disable interrupt on the RA1/T0CKI pin

1 =Enable TMR0 overflow interrupt

0 =Disable TMR0 overflow interrupt

bit 7: RBIE: PORTB Interrupt on Change Enable bit

bit 6: TMR3IE: TMR3 Interrupt Enable bit

bit 5: TMR2IE: TMR2 Interrupt Enable bit

bit 2: CA1IE: Capture1 Interrupt Enable bit

bit 1: TX1IE: USART1 Transmit Interrupt Enable bit

bit 0: RC1IE: USART1 Receive Interrupt Enable bit

1 =Enable SSP Interrupt

0 = Disable SSP Interrupt

1 =Enable Bus Collision Interrupt

0 =Disable Bus Collision Interrupt

1 =Enable A/D Module Interrupt

0 =Disable A/D Module Interrupt

1 =Enable USART2 Transmit Buffer Empty Interrupt