ON Semiconductor TL071C,AC TL072C,AC TL074C,AC Low Noise, JFET Input Operational Amplifiers These low noise JFET input operational amplifiers combine two state-of-the-art analog technologies on a single monolithic integrated circuit. Each internally compensated operational amplifier has well matched high voltage JFET input device for low input offset voltage. The BIFET technology provides wide bandwidths and fast slew rates with low input bias currents, input offset currents, and supply currents. Moreover, the devices exhibit low noise and low harmonic distortion, making them ideal for use in high fidelity audio amplifier applications. These devices are available in single, dual and quad operational amplifiers which are pin-compatible with the industry standard MC1741, MC1458, and the MC3403/LM324 bipolar products. * * * * * * * LOW NOISE, JFET INPUT OPERATIONAL AMPLIFIERS SEMICONDUCTOR TECHNICAL DATA 8 1 8 1 Low Input Noise Voltage: 18 nV/ Hz Typ P SUFFIX PLASTIC PACKAGE CASE 626 Low Harmonic Distortion: 0.01% Typ D SUFFIX PLASTIC PACKAGE CASE 751 (SO-8) Low Input Bias and Offset Currents High Input Impedance: 1012 Typ PIN CONNECTIONS High Slew Rate: 13 V/s Typ 8 NC Offset Null 1 Wide Gain Bandwidth: 4.0 MHz Typ Inv + Input 2 Low Supply Current: 1.4 mA per Amp 7 VCC + Noninvt Input 3 6 Output VEE 4 5 Offset Null TL071 (Top View) Output A 1 8 2 Inputs A - + 3 - + VEE 4 VCC 7 Output B 6 Inputs B 5 TL072 (Top View) N SUFFIX PLASTIC PACKAGE CASE 646 (TL074 Only) 14 1 PIN CONNECTIONS 14 Output 4 Output 1 1 Inputs 1 Device Operating Temperature Range Inputs 2 Package TL071CD Single TL071ACP SO-8 TA = 0 to +70C Plastic DIP TL072CD Dual Quad TL072ACP TL074CN, ACN Semiconductor Components Industries, LLC, 2002 March, 2002 - Rev. 2 3 - + - 1 4 + 5 6 13 12 Inputs 4 11 VEE VCC 4 ORDERING INFORMATION Op Amp Function 2 + - 2 3 + - Output 2 7 10 9 Inputs 3 8 Output 3 TL074 (Top View) SO-8 TA = 0 to +70C TA = 0 to +70C Plastic DIP Plastic DIP 1 Publication Order Number: TL071C/D TL071C,AC TL072C,AC TL074C,AC MAXIMUM RATINGS Symbol Value Unit Supply Voltage Rating VCC VEE 18 -18 V Differential Input Voltage VID 30 V Input Voltage Range (Note 1) VIDR 15 V tSC Continuous PD 1.0/JA 680 10 mW mW/C Output Short Circuit Duration (Note 2) Power Dissipation Plastic Package (N, P) Derate above TA = 47C Operating Ambient Temperature Range TA 0 to +70 C Storage Temperature Range Tstg -65 to +150 C NOTES: 1. The magnitude of the input voltage must not exceed the magnitude of the supply voltage or 15 V, whichever is less. 2. The output may be shorted to ground or either supply. Temperature and/or supply voltages must be limited to ensure that power dissipation ratings are not exceeded. 3. ESD data available upon request. ELECTRICAL CHARACTERISTICS (VCC = 15 V, VEE = -15 V, TA = Thigh to Tlow [Note 1]) Characteristics Symbol Input Offset Voltage (RS 10 k, VCM = 0) TL071C, TL072C TL074C TL07_AC VIO Input Offset Current (VCM = 0) (Note 2) TL07_C TL07_AC IIO Input Bias Current (VCM = 0) (Note 2) TL07_C TL07_AC IIB Large-Signal Voltage Gain (VO = 10 V, RL 2.0 k) TL07_C TL07_AC Min Typ Max - - - - - - 13 13 7.5 - - - - 2.0 2.0 - - - - 7.0 7.0 15 25 - - - - 24 20 - - - - mV nA nA AVOL Output Voltage Swing (Peak-to-Peak) (RL 10 k) (RL 2.0 k) Unit V/mV VO V NOTES: 1. Tlow = 0C for TL071C,AC Thigh = 70C for TL071C,AC 0C for TL072C,AC Thigh = 70C for TL072C,AC 0C for TL074C,AC Thigh = 70C for TL074C,AC 2. Input Bias currents of JFET input op amps approximately double for every 10C rise in junction temperature as shown in Figure 3. To maintain junction temperature as close to ambient temperature as possible, pulse techniques must be used during testing. Figure 1. Unity Gain Voltage Follower Figure 2. Inverting Gain of 10 Amplifier 10 k 1.0 k Vin VO + RL = 2.0 k Vin CL = 100 pF - VO + RL http://onsemi.com 2 CL = 100 pF TL071C,AC TL072C,AC TL074C,AC ELECTRICAL CHARACTERISTICS (VCC = 15 V, VEE = -15 V, TA = 25C, unless otherwise noted.) Characteristics Symbol Min Typ Max - - - 3.0 3.0 3.0 10 10 6.0 - 10 - - - 5.0 5.0 50 50 - - 30 30 200 200 - 1012 - 10 11 15, -12 15, -12 - - 25 50 150 150 - - 24 28 - 70 80 100 100 - - 70 80 100 100 - - ID - 1.4 2.5 mA Unity Gain Bandwidth BW - 4.0 - MHz Slew Rate (See Figure 1) Vin = 10 V, RL = 2.0 k, CL = 100 pF SR - 13 - v/s tr - 0.1 - s Overshoot (Vin = 20 mV, RL = 2.0 k, CL = 100 pF) OS - 10 - % Equivalent Input Noise Voltage RS = 100 , f = 1000 Hz en - 18 - nV/ Hz Equivalent Input Noise Current RS = 100 , f = 1000 Hz in - 0.01 - pA/ Hz THD - 0.01 - % CS - 120 - dB Input Offset Voltage (RS 10 k, VCM = 0) TL071C, TL072C TL074C TL07_AC VIO VIO/T Average Temperature Coefficient of Input Offset Voltage RS = 50 , TA = Tlow to Thigh (Note 1) Input Offset Current (VCM = 0) (Note 2) TL07_C TL07_AC IIO Input Bias Current (VCM = 0) (Note 2) TL07_C TL07_AC IIB Input Resistance ri Common Mode Input Voltage Range TL07_C TL07_AC VICR Large-Signal Voltage Gain (VO = 10 V, RL 2.0 k) TL07_C TL07_AC AVOL Output Voltage Swing (Peak-to-Peak) (RL = 10 k) VO Common Mode Rejection Ratio (RS 10 k) TL07_C TL07_AC CMRR Supply Voltage Rejection Ratio (RS 10 k) TL07_C TL07_AC PSRR Supply Current (Each Amplifier) Rise Time (See Figure 1) Total Harmonic Distortion VO (RMS) = 10 V, RS 1.0 k, RL 2.0 k, f = 1000 Hz Channel Separation AV = 100 Unit mV V/C pA pA V V/mV V dB dB NOTES: 1. Tlow = 0C for TL071C,AC Thigh = 70C for TL071C,AC 0C for TL072C,AC Thigh = 70C for TL072C,AC 0C for TL074C,AC Thigh = 70C for TL074C,AC 2. Input Bias currents of JFET input op amps approximately double for every 10C rise in junction temperature as shown in Figure 3. To maintain junction temperature as close to ambient temperature as possible, pulse techniques must be used during testing. http://onsemi.com 3 TL071C,AC TL072C,AC TL074C,AC Figure 3. Input Bias Current versus Temperature Figure 4. Output Voltage Swing versus Frequency 10 35 VO, OUTPUT VOLTAGE SWING (Vpp ) IIB , INPUT BIAS CURRENT (nA) 100 VCC/VEE = 15 V 1.0 0.1 0.01 -100 -75 -50 -25 0 25 50 75 100 125 5.0 V 10 5.0 1.0 k 10 k 100 k 1.0 M 10 M 40 VO, OUTPUT VOLTAGE SWING (Vpp ) VO, OUTPUT VOLTAGE SWING (Vpp ) 15 Figure 6. Output Voltage Swing versus Supply Voltage VCC/VEE = 15 V TA = 25C (See Figure 2) 0.2 0.4 0.7 1.0 2.0 4.0 7.0 20 10 0 5.0 10 15 20 RL, LOAD RESISTANCE (k) VCC, |VEE| , SUPPLY VOLTAGE (V) Figure 7. Output Voltage Swing versus Temperature Figure 8. Supply Current per Amplifier versus Temperature ID , SUPPLY DRAIN CURRENT (mA) VCC/VEE = 15 V (See Figure 2) RL = 10 k 30 25 RL = 2.0 k 20 15 10 5.0 -50 RL = 2.0 k TA = 25C 30 0 10 40 VO, OUTPUT VOLTAGE SWING (Vpp ) 10 V Figure 5. Output Voltage Swing versus Load Resistance 5.0 0 -75 20 f, FREQUENCY (Hz) 10 35 25 TA, AMBIENT TEMPERATURE (C) 20 0 0.1 RL = 2.0 k TA = 25C (See Figure 2) VCC/VEE = 15 V 0 100 150 40 30 30 -25 0 25 50 75 100 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 -75 125 VCC/VEE = 15 V TA, AMBIENT TEMPERATURE (C) -50 -25 0 25 50 75 TA, AMBIENT TEMPERATURE (C) http://onsemi.com 4 100 125 TL071C,AC TL072C,AC TL074C,AC Figure 9. Large Signal Voltage Gain and Phase Shift versus Frequency Figure 10. Large Signal Voltage Gain versus Temperature 108 105 104 103 45 102 1.0 90 Phase Shift 101 1.0 0 Gain 10 100 1.0 k VVOL, VOLTAGE GAIN (V/mV) VVOL, OPEN-LOOP GAIN 106 PHASE SHIFT (DEGREES) 1000 VCC/VEE = 15 V RL = 2.0 k TA = 25C 107 VCC/VEE = 15 V VO = 10 V RL = 2.0 k 100 10 135 10 k 180 10 M 100 M 100 k 1.0 M 1.0 -100 -75 -50 en, EQUIVALENT INPUT NOISE VOLTAGE ( nV/ Hz ) Figure 11. Normalized Slew Rate versus Temperature 1.20 1.10 1.05 1.0 0.95 0.90 0.85 -25 0 25 50 75 100 125 TA, AMBIENT TEMPERATURE (C) 1.0 0.5 0.1 50 70 75 100 125 150 VCC/VEE = 15 Vdc AV = 10 RS = 100 TA = 25C 60 50 40 30 20 10 0 0.01 0.05 0.1 0.5 1.0 f, FREQUENCY (Hz) VCC/VEE = 15 V AV = 1.0 VO = 6.0 V (RMS) TA = 25C 0.05 0.01 0.005 0.001 0.1 25 Figure 12. Equivalent Input Noise Voltage versus Frequency Figure 13. Total Harmonic Distortion versus Frequency THD, TOTAL HARMONIC DISTORTION (%) NORMALIZED SLEW RATE 1.15 -50 0 TA, AMBIENT TEMPERATURE (C) f, FREQUENCY (Hz) 0.80 -75 -25 0.5 1.0 5.0 f, FREQUENCY (Hz) http://onsemi.com 5 10 50 100 5.0 10 50 100 TL071C,AC TL072C,AC TL074C,AC Representative Schematic Diagram (Each Amplifier) Bias Circuitry Common to All Amplifiers Output Q4 Q3 Q2 Q5 VCC Q1 Q6 Inputs + J1 J2 2.0 k Q17 Q20 Q15 10 pF Q14 24 Q21 Q13 Q12 Q10 J3 Q23 Q19 Q22 Q24 Q16 Q9 Q11 Q25 Q8 Q7 Offset Null (TL071 only) Q18 1.5 k 1.5 k VEE Figure 14. Audio Tone Control Amplifier Input 10 k 10 k 100 k 0.033 F 0.033 F 10 k VCC TL071 + 3.3 k 68 k 0.033 F 0.033 F VEE Turn-Over Frequency = 1.0 kHz Bass Boost/Cut 20 dB at 20 Hz Treble Boost/Cut 19 dB at 20 kHz 100 k Figure 15. High Q Notch Filter Input R R TL071 + C1 R1 C 1 350Hz 2RC R 2R1 1.5M C C1 300pF 2 f o C http://onsemi.com 6 Output TL071C,AC TL072C,AC TL074C,AC OUTLINE DIMENSIONS P SUFFIX PLASTIC PACKAGE CASE 626-05 ISSUE K 8 5 NOTES: 1. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 2. PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS). 3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. -B- 1 4 F DIM A B C D F G H J K L M N -A- NOTE 2 L C J -T- N SEATING PLANE D M K MILLIMETERS MIN MAX 9.40 10.16 6.10 6.60 3.94 4.45 0.38 0.51 1.02 1.78 2.54 BSC 0.76 1.27 0.20 0.30 2.92 3.43 7.62 BSC --10 0.76 1.01 INCHES MIN MAX 0.370 0.400 0.240 0.260 0.155 0.175 0.015 0.020 0.040 0.070 0.100 BSC 0.030 0.050 0.008 0.012 0.115 0.135 0.300 BSC --10 0.030 0.040 G H 0.13 (0.005) T A M M B M D SUFFIX PLASTIC PACKAGE CASE 751-05 (SO-8) ISSUE S D A 8 E 5 0.25 H 1 M B M 4 h B NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS ARE IN MILLIMETERS. 3. DIMENSION D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE MOLD PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. C e X 45 A C SEATING PLANE L 0.10 A1 B 0.25 M C B S A S http://onsemi.com 7 DIM A A1 B C D E e H h L MILLIMETERS MIN MAX 1.35 1.75 0.10 0.25 0.35 0.49 0.18 0.25 4.80 5.00 3.80 4.00 1.27 BSC 5.80 6.20 0.25 0.50 0.40 1.25 0 7 TL071C,AC TL072C,AC TL074C,AC OUTLINE DIMENSIONS N SUFFIX PLASTIC PACKAGE CASE 646-06 ISSUE M 14 8 1 7 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. B A F L N C -T- SEATING PLANE J K H G D 14 PL M 0.13 (0.005) DIM A B C D F G H J K L M N INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.290 0.310 --10 0.015 0.039 MILLIMETERS MIN MAX 18.16 18.80 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.37 7.87 --10 0.38 1.01 M ON Semiconductor is a trademark and is a registered trademark of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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