Linear Integrat
ed Systems
• 4042 C
lipper Court • Frem
ont, CA 94538 • Te
l: 510 490
-
9160 • Fax: 510 353
-
0261
2/13
/12
Rev#A5
ECN# PAD SERIES
FEATURES
DIRECT REPLACEMENT F
OR SILICONIX
PAD SERIES
REVERSE BREAKDOWN VOLTAGE
BV
R
≥
-
30V
REVERSE CAPACITANCE
C
rss
≤
2.0pF
ABSOLUTE MAXIMUM R
ATINGS
1
@ 25
°C (
unles
s ot
herwi
se s
tate
d)
Maximum T
emperatu
res
Storage Temperature
-5
5 to +150 °C
Oper
ating Junct
ion Temperature
-
55 to +1
50
°C
Maximum P
ower Di
ssipat
ion
Continuous
Power Diss
ipation
(PAD)
300mW
Continuous
Power Diss
ipation
(J/SSTPAD)
350mW
Maximum C
urrent
s
Forward Current (
PAD)
50mA
Forward Current (
J/SSTPAD)
10mA
COMMON ELECTRICAL CHARACTERISTI
CS @ 25 °C
(unless o
therwise st
ated)
SYMBOL
CHARACTERISTIC
MIN
TYP
MAX
UNITS
CONDITIONS
BV
R
Reverse Br
eakdown
Voltage
ALL PAD
-
45
V
I
R
=
-
1
µ
A
ALL SSTPAD
-
30
ALL JPAD
-
35
V
F
Forward Voltage
0.8
1.5
I
F
=
1
mA
C
rss
Total Reverse Capacit
ance
PAD1,5
0.5
0.8
pF
V
R
=
-
5V,
f
= 1MHz
All Others
1.5
2
SPECIFIC ELECTRICAL CHARACTERISTICS
@ 25 °C (unless
otherwise sta
ted)
SYMBOL
CHARACTERISTIC
PAD
JPAD
SSTPAD
UNITS
CONDITIONS
I
R
Maximum
Reverse
Leakage Current
PAD1
-1
pA
V
R
=
-
20V
PAD2
-2
(SST/J)PAD
5
-5
-5
-5
(SST/J)PAD
10
-
10
-
10
-
10
(SST/J)PAD
20
-
20
-
20
-
20
(SST/J)PAD
50
-
50
-
50
-
50
(SST/J)PAD
100
-
100
-
100
(SST/J)PAD
200
-
200
(SST/J)PAD
500
-
500
PAD SERIES
PICO AMPERE DIODES
PAD1,2,5
JPAD
SSTPAD
P
AD50
C
Case
13
TOP VIEW
TO-72
2
A
C
A & Case
1
TOP VIEW
TO-18
2
TOP VIEW
TO-92
1
C
A
2
1
2
3
SOT-23
TOP VIEW
K
A
K
1.
D
erate 2mW/°C above 25°C
2.
Der
ate 2.8mW/°C above 25°
C
C
C
Linear Integrat
ed Systems
• 4042 C
lipper Court • Frem
ont, CA 94538 • Te
l: 510 490
-
9160 • Fax: 510 353
-
0261
2/13
/12
Rev#A5
ECN# PAD SERIES
1.
Absolute maximum rat
ings are limit
ing values above whi
ch serviceabilit
y may be impaired.
2.
The PAD type number denotes its
maximum reverse current
value
in pico amperes. Devices with I
R
values
intermediate to those shown
are available upon request.
Information furnis
hed by Linear Integ
rated Systems is b
elieved to be accu
rate and reliable. Ho
wever, no respon
sibility is as
sumed for its
use; nor for any infr
ingement of patents or other r
ights of third parties
which may result from its use.
No license is granted by
implicat
ion or
otherwise under any patent or
patent rights of Linear I
ntegrated Systems.
Figure 1. Operati
onal Amplifier
Protection
Input Differen
tial Voltage lim
it
ed to 0.8V (typ)
by JPADs D
1
and D
2
. Common
Mode In
put v
oltage
limi
ted by
JPADs
D
3
and D
4
to ±15V.
Figure 2. Sample and
Hold Circuit
Typical Sample and Hol
d circuit
with clipping.
JPAD diodes reduce
offset
voltages fed capacit
ively from the JFET swit
ch
gate.
-15V
+15V
OP
-2
7
D1
D2
D3
D4
+
-
JPAD
2
0
FIGURE 1
2N4117A
R
2N4393
-V
+V
V
OUT
D2
D1
C
JP
AD5
CONT
RO
L
SIG
NAL
e
in
+V
FIGURE 2
0.210
0.170
1
2
3
SOT-23
DIMENSIONS IN
MILLIMETERS
0.89
1.03
1.78
2.05
1.20
1.40
2.10
2.64
0.37
0.51
2.80
3.04
0.89
1.12
0.013
0.100
0.085
0.180
0.55
TO
-
72
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