LP3985IM5-2.5 - NATIONAL SEMICONDUCTOR

LP3985

LP3985 Micropower, 150mA Low-Noise Ultra Low-Dropout CMOS Voltage Regulator

Literature Number: SNVS087AB

LP3985

November 14, 2011

Micropower, 150mA Low-Noise Ultra Low-Dropout CMOS

Voltage Regulator

General Description

The LP3985 is designed for portable and wireless applica-

tions with demanding performance and space requirements.

The LP3985 is stable with a small 1µF ±30% ceramic or high-

quality tantalum output capacitor. The micro SMD requires

the smallest possible PC board area - the total application

circuit area can be less than 2.0mm x 2.5mm, a fraction of a

1206 case size.

The LP3985's performance is optimized for battery powered

systems to deliver ultra low noise, extremely low dropout volt-

age and low quiescent current. Regulator ground current

increases only slightly in dropout, further prolonging the bat-

tery life.

An optional external bypass capacitor reduces the output

noise without slowing down the load transient response. Fast

startup time is achieved by utilizing an internal power-on cir-

cuit that actively pre-charges the bypass capacitor.

Power supply rejection is better than 50dB at low frequencies

and starts to roll off at 1kHz. High power supply rejection is

maintained down to low input voltage levels common to bat-

tery operated circuits.

The device is ideal for mobile phone and similar battery pow-

ered wireless applications. It provides up to 150mA, from a

2.5V to 6V input. The LP3985 consumes less than 1.5µA in

disable mode and has fast turn-on time less than 200µs.

The LP3985 is available in a 5-bump thin micro SMD and a

5-pin SOT-23 package. Performance is specified for −40°C

to +125°C temperature range and is available in 2.5V, 2.6V,

2.7V, 2.8V, 2.85V, 2.9V, 3.0V. 3.1V, 3.2V, 3.3V, 4.7V, 4.75V,

4.8V and 5.0V output voltages. For other output voltage op-

tions between 2.5V to 5.0V or for a dual LP3985, please

contact a Texas Instruments sales office.

Key Specifications

■2.5 to 6.0V input range

■150mA guaranteed output

■50dB PSRR at 1kHz @ VIN = VOUT + 0.2V

■≤1.5µA quiescent current when shut down

■Fast Turn-On time: 200µs (typ.)

■100mV maximum dropout with 150mA load

■30µVrms output noise (typ.) over 10Hz to 100kHz

■−40 to +125°C junction temperature range for operation

■2.5V, 2.6V, 2.7V, 2.8V, 2.85V, 2.9V, 3.0V, 3.1V, 3.2V,

3.3V, 4.7V, 4.75V, 4.8V and 5.0V outputs standard

Features

■Miniature 5-I/O micro SMD and SOT-23-5 package

■Logic controlled enable

■Stable with ceramic and high quality tantalum capacitors

■Fast turn-on

■Thermal shutdown and short-circuit current limit

Applications

■CDMA cellular handsets

■Wideband CDMA cellular handsets

■GSM cellular handsets

■Portable information appliances

Typical Application Circuit

10136402

Note: Pin Numbers in parenthesis indicate micro SMD package.

* Optional Noise Reduction Capacitor.

LP3985 Micropower, 150mA Low-Noise Ultra Low-Dropout CMOS Voltage Regulator

Block Diagram

10136401

Pin Descriptions

Name * micro SMD SOT Function

VEN A1 3 Enable Input Logic, Enable High

GND B2 2 Common Ground

VOUT C1 5 Output Voltage of the LDO

VIN C3 1 Input Voltage of the LDO

BYPASS A3 4 Optional Bypass Capacitor for Noise

Reduction

* The pin numbering scheme for the micro SMD package was revised in April 2002 to conform to JEDEC standard. Only the pin numbers were revised. No

changes to the physical location of the inputs/outputs were made. For reference purposes, the obsolete numbering scheme had VEN as pin 1, GND as pin 2,

VOUT as pin 3, VIN as pin 4, and BYPASS as pin 5.

Connection Diagrams

SOT 23-5 Package (MF)

10136407

Top View

See NS Package Number MF05A

5-Bump micro SMD Package (TLA05)

10136470

Top View

See NS Package Number TLA05

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LP3985

Ordering Information

TL refers to 0.300mm bump size, 0.600mm height for micro SMD Package

Output Voltage (V) Grade LP3985 Supplied as 250 Units, Tape and

Reel

LP3985 Supplied as 3000 Units, Tape

and Reel

2.5 STD LP3985ITL-2.5 LP3985ITLX-2.5

2.6 STD LP3985ITL-2.6 LP3985ITLX-2.6

2.7 STD LP3985ITL-2.7 LP3985ITLX-2.7

2.8 STD LP3985ITL-2.8 LP3985ITLX-2.8

2.85 STD LP3985ITL-285 LP3985ITLX-285

2.9 STD LP3985ITL-2.9 LP3985ITLX-2.9

3.0 STD LP3985ITL-3.0 LP3985ITLX-3.0

3.1 STD LP3985ITL-3.1 LP3985ITLX-3.1

3.2 STD LP3985ITL-3.2 LP3985ITLX-3.2

3.3 STD LP3985ITL-3.3 LP3985ITLX-3.3

4.75 STD LP3985ITL-4.75 LP3985ITLX-4.75

4.8 STD LP3985ITL-4.8 LP3985ITLX-4.8

5.0 STD LP3985ITL-5.0 LP3985ITLX-5.0

For SOT Package

Output Voltage

(V) Grade LP3985 Supplied as 1000 Units,

Tape and Reel

LP3985 Supplied as 3000 Units,

Tape and Reel Package Marking

2.5 STD LP3985IM5-2.5 LP3985IM5X-2.5 LCSB

2.6 STD LP3985IM5-2.6 LP3985IM5X-2.6 LCTB

2.7 STD LP3985IM5-2.7 LP3985IM5X-2.7 LCUB

2.8 STD LP3985IM5-2.8 LP3985IM5X-2.8 LCJB

2.85 STD LP3985IM5-285 LP3985IM5X-285 LCXB

2.9 STD LP3985IM5-2.9 LP3985IM5X-2.9 LCYB

3.0 STD LP3985IM5-3.0 LP3985IM5X-3.0 LCRB

3.1 STD LP3985IM5-3.1 LP3985IM5X-3.1 LCZB

3.2 STD LP3985IM5-3.2 LP3985IM5X-3.2 LDPB

3.3 STD LP3985IM5-3.3 LP3985IM5X-3.3 LDQB

4.7 STD LP3985IM5-4.7 LP3985IM5X-4.7 LDRB

5.0 STD LP3985IM5-5.0 LP3985IM5X-5.0 LDSB

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LP3985

Absolute Maximum Ratings (Note 1, Note

If Military/Aerospace specified devices are required,

please contact the Texas Instruments Sales Office/

Distributors for availability and specifications.

VIN, VEN −0.3 to 6.5V

VOUT −0.3 to (VIN+0.3) ≤ 6.5V

Junction Temperature 150°C

Storage Temperature −65°C to +150°C

Lead Temp. 235°C

Pad Temp. (Note 3) 235°C

Maximum Power Dissipation

SOT23-5 (Note 4)

micro SMD (Note 4)

364mW

314mW

ESD Rating(Note 5)

Human Body Model

Machine Model

2kV

150V

Operating Ratings (Note 1, Note 2)

VIN 2.5 to 6V

VEN 0 to (VIN+0.3) ≤ 6V

Junction Temperature −40°C to +125°C

Thermal Resistance

θJA (SOT23-5)

θJA (micro SMD)

220°C/W

255°C/W

Maximum Power Dissipation

SOT23-5 (Note 6)

micro SMD (Note 6)

250mW

216mW

Electrical Characteristics

Unless otherwise specified: VIN = VOUT(nom) + 0.5V, CIN = 1 µF, IOUT = 1mA, COUT = 1 µF, CBYPASS = 0.01µF. Typical values and

limits appearing in standard typeface are for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature

range for operation, −40°C to +125°C. (Note 7, Note 8)

Symbol Parameter Conditions Typ Limit Units

Min Max

ΔVOUT

Output Voltage

Tolerance

IOUT = 1mA −2

−3

% of VOUT

(nom)

Line Regulation Error VIN = (VOUT(nom) + 0.5V) to 6.0V,

For 4.7 to 5.0 options

For all other options

−0.19

−0.1

0.19

0.1

%/V

Load Regulation Error

(Note 9)

IOUT = 1 mA to 150 mA

LP3985IM5 (SOT23-5)

0.0025 0.005

%/mA

LP3985 (micro SMD) 0.0004 0.002

Output AC Line Regulation VIN = VOUT(nom) + 1V,

IOUT = 150 mA (Figure 1)

1.5 mVP-P

PSRR Power Supply Rejection Ratio

VIN = VOUT(nom) + 0.2V,

f = 1 kHz,

IOUT = 50 mA (Figure 2)

VIN = VOUT(nom) + 0.2V,

f = 10 kHz,

IOUT = 50 mA (Figure 2)

IQQuiescent Current VEN = 1.4V, IOUT = 0 mA

For 4.7 to 5.0 options

For all other options

100

165

150

µA

VEN = 1.4V, IOUT = 0 to 150 mA

For 4.7 to 5.0 options

For all other options

155

140

250

200

VEN = 0.4V 0.003 1.5

Dropout Voltage (Note 10) IOUT = 1 mA 0.4 2

IOUT = 50 mA 20 35

IOUT = 100 mA 45 70

IOUT = 150 mA 60 100

ISC Short Circuit Current Limit Output Grounded

(Steady State)

600 mA

IOUT(PK) Peak Output Current VOUT ≥ VOUT(nom) - 5% 550 300 mA

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LP3985

Symbol Parameter Conditions Typ Limit Units

Min Max

TON Turn-On Time

(Note 11)

CBYPASS = 0.01 µF 200 µs

enOutput Noise Voltage(Note 12) BW = 10 Hz to 100 kHz,

COUT = 1µF

30 µVrms

Output Noise Density CBP = 0 230 nV/

IEN Maximum Input Current at EN VEN = 0.4 and VIN = 6.0 ±1 nA

VIL Maximum Low Level Input Voltage

at EN

VIN = 2.5 to 6.0V 0.4 V

VIH Minimum High Level Input Voltage

at EN

VIN = 2.5 to 6.0V 1.4 V

TSD Thermal Shutdown Temperature 160 °C

Thermal Shutdown Hysteresis 20 °C

Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the

device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the

Electrical Characteristics tables.

Note 2: All voltages are with respect to the potential at the GND pin.

Note 3: Additional information on lead temperature and pad temperature can be found in National Semiconductor Application Note (AN-1112).

Note 4: The Absolute Maximum power dissipation depends on the ambient temperature and can be calculated using the formula: PD = (TJ - TA)/θJA,

where TJ is the junction temperature, TA is the ambient temperature, and θ JA is the junction-to-ambient thermal resistance. The 364mW rating for SOT23-5

appearing under Absolute Maximum Ratings results from substituting the Absolute Maximum junction temperature, 150°C, for TJ, 70°C for TA, and 220°C/W for

θJA. More power can be dissipated safely at ambient temperatures below 70°C . Less power can be dissipated safely at ambient temperatures above 70°C. The

Absolute Maximum power dissipation can be increased by 4.5mW for each degree below 70°C, and it must be derated by 4.5mW for each degree above 70°C.

Note 5: The human body model is 100pF discharged through 1.5kΩ resistor into each pin. The machine model is a 200 pF capacitor discharged directly into each

pin.

Note 6: Like the Absolute Maximum power dissipation, the maximum power dissipation for operation depends on the ambient temperature. The 250mW rating

for SOT23-5 appearing under Operating Ratings results from substituting the maximum junction temperature for operation, 125°C, for TJ, 70°C for TA, and 220°

C/W for θJA into (Note 4) above. More power can be dissipated at ambient temperatures below 70°C . Less power can be dissipated at ambient temperatures

above 70°C. The maximum power dissipation for operation can be increased by 4.5mW for each degree below 70°C, and it must be derated by 4.5mW for each

degree above 70°C.

Note 7: All limits are guaranteed. All electrical characteristics having room-temperature limits are tested during production with TJ = 25°C or correlated using

Statistical Quality Control (SQC) methods. All hot and cold limits are guaranteed by correlating the electrical characteristics to process and temperature variations

and applying statistical process control.

Note 8: The target output voltage, which is labeled VOUT(nom), is the desired voltage option.

Note 9: An increase in the load current results in a slight decrease in the output voltage and vice versa.

Note 10: Dropout voltage is the input-to-output voltage difference at which the output voltage is 100mV below its nominal value. This specification does not apply

for input voltages below 2.5V.

Note 11: Turn-on time is time measured between the enable input just exceeding VIH and the output voltage just reaching 95% of its nominal value.

Note 12: The output noise varies with output voltage option. The 30µVrms is measured with 2.5V voltage option. To calculate an approximated output noise for

other options, use the equation: (30µVrms)(X)/2.5, where X is the voltage option value.

Recommended Output Capacitor

Symbol Parameter Conditions Nominal

Value

Limit Units

Min Max

COUT Output Capacitor Capacitance(Note 13) 1.0 0.7 µF

ESR 5 500 mΩ

Note 13: The minimum value of capacitance for stability and correct operation is 0.7µF. The Capacitor tolerance should be ± 30% or better over the temperature

range. The full range of operating conditions for the capacitor in the application should be considered during device selection to ensure this minimum capacitance

specification is met. The recommended capacitor type is X7R to meet the full device temperature spec of -40ºC to 125ºC. See the capacitor section in Application

Hints.

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LP3985

Timing Diagrams

10136408

FIGURE 1. Line Transient Input Test Signal

10136409

FIGURE 2. PSRR Input Test Signal

Typical Performance Characteristics Unless otherwise specified, CIN = COUT = 1 µF Ceramic,

CBYPASS = 0.01 µF, VIN = VOUT + 0.2V, TA = 25°C, Enable pin is tied to VIN.

Output Voltage Change vs Temperature

10136441

Dropout Voltage vs Load Current

10136433

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LP3985

Ground Current vs Load Current

10136440

Ground Current vs VIN @ 25°C

10136435

Ground Current vs VIN @ −40°C

10136437

Ground Current vs VIN @ 125°C

10136439

Short Circuit Current (micro SMD)

10136445

Short Circuit Current (micro SMD)

10136446

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LP3985

Short Circuit Current (SOT)

10136447

Short Circuit Current (SOT)

10136448

Short Circuit Current (SOT)

10136449

Short Circuit Current (SOT)

10136450

Short Circuit Current (micro SMD)

10136451

Short Circuit Current (micro SMD)

10136452

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LP3985

Output Noise Spectral Density

10136410

Ripple Rejection (VIN = VOUT + 0.2V)

10136411

Ripple Rejection (VIN = VOUT + 1V)

10136412

Ripple Rejection (VIN = 5.0V)

10136413

Startup Time (VIN = VOUT + 0.2V)

10136414

Startup Time (VIN = 4.2V)

10136415

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LP3985

Startup Time (VIN = VOUT + 0.2V)

10136416

Startup Time (VIN = 4.2V)

10136417

Startup Time (VIN = VOUT + 0.2V)

10136418

Startup Time (VIN = 4.2V)

10136419

Line Transient Response

10136420

Line Transient Response

10136421

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LP3985

Load Transient Response (VIN = 3.2V)

10136423

Load Transient Response (VIN = 4.2V)

10136422

Load Transient Response (VIN = 3.2V)

10136424

Load Transient Response (VIN = 4.2V)

10136425

Enable Response (VIN = VOUT + 0.2V)

10136453

Enable Response (VIN = 4.2V)

10136454

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LP3985

Enable Response (VIN = VOUT + 0.2V)

10136455

Enable Response (VIN = 4.2V)

10136456

Output Impedance (VIN = 4.2V)

10136465

Output Impedance (VIN = VOUT + 0.2V)

10136466

Application Hints

EXTERNAL CAPACITORS

Like any low-dropout regulator, the LP3985 requires external

capacitors for regulator stability. The LP3985 is specifically

designed for portable applications requiring minimum board

space and smallest components. These capacitors must be

correctly selected for good performance.

INPUT CAPACITOR

An input capacitance of ≊ 1µF is required between the

LP3985 input pin and ground (the amount of the capacitance

may be increased without limit).

This capacitor must be located a distance of not more than

1cm from the input pin and returned to a clean analog ground.

A ceramic capacitor is recommended although a good quality

tantalum or film capacitor may be used at the input.

Important: Tantalum capacitors can suffer catastrophic fail-

ures due to surge current when connected to a low-

impedance source of power (like a battery or a very large

capacitor). If a tantalum capacitor is used at the input, it must

be guaranteed by the manufacturer to have a surge current

rating sufficient for the application.

There are no requirements for the ESR on the input capacitor,

but tolerance and temperature coefficient must be considered

when selecting the capacitor to ensure the capacitance will

remain within the operational range over the full range of tem-

perature and operating conditions.

OUTPUT CAPACITOR

Correct selection of the output capacitor is important to en-

sure stable operation in the intended application.

The output capacitor must meet all the requirements specified

in the recommended capacitor table over all conditions in the

application. These conditions include DC-bias, frequency and

temperature. Unstable operation will result if the capacitance

drops below the minimum specified value. (See the next sec-

tion Capacitor Characteristics).

The LP3985 is designed specifically to work with very small

ceramic output capacitors. A 1.0µF ceramic capacitor (dialec-

tric type X7R) with ESR between 5mΩ to 500mΩ is suitable

in the LP3985 application circuit. X5R capacitors may be used

but have a narrower temperature range. With these and other

capacitor types (Y5V, Z6U) that may be used, selection is

dependant on the range of operating conditions and temper-

ature range for that application. (see section on Capacitor

Characteristics).

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LP3985

It may also be possible to use tantalum or film capacitors at

the output, but these are not as attractive for reasons of size

and cost (see next section Capacitor Characteristics).

It is also recommended that the output capacitor be placed

within 1cm from the output pin and returned to a clean ground

line.

CAPACITOR CHARACTERISTICS

The LP3985 is designed to work with ceramic capacitors on

the output to take advantage of the benefits they offer: for

capacitance values in the range of 1µF to 4.7µF range, ce-

ramic capacitors are the smallest, least expensive and have

the lowest ESR values (which makes them best for eliminat-

ing high frequency noise). The ESR of a typical 1µF ceramic

capacitor is in the range of 20mΩ to 40mΩ, which easily

meets the ESR requirement for stability by the LP3985.

For both input and output capacitors careful interpretation of

the capacitor specification is required to ensure correct device

operation. The capacitor value can change greatly dependant

on the conditions of operation and capacitor type.

In particular the output capacitor selection should take ac-

count of all the capacitor parameters to ensure that the spec-

ification is met within the application. Capacitance value can

vary with DC bias conditions as well as temperature and fre-

quency of operation. Capacitor values will also show some

decrease over time due to aging. The capacitor parameters

are also dependant on the particular case size with smaller

sizes giving poorer performance figures in general. As an ex-

ample Figure 3 shows a typical graph showing a comparison

of capacitor case sizes in a Capacitance vs. DC Bias plot. As

shown in the graph, as a result of the DC Bias condition the

capacitance value may drop below the minimum capacitance

value given in the recommended capacitor table (0.7µF in this

case). Note that the graph shows the capacitance out of spec

for the 0402 case size capacitor at higher bias voltages. It is

therefore recommended that the capacitor manufacturers'

specifications for the nominal value capacitor are consulted

for all conditions as some capacitor sizes (e.g. 0402) may not

be suitable in the actual application.

10136467

FIGURE 3. Graph Showing A Typical Variation in

Capacitance vs DC Bias

The ceramic capacitor's capacitance can vary with tempera-

ture. The capacitor type X7R, which operates over a temper-

ature range of −55°C to +125°C, will only vary the capacitance

to within ±15%. The capacitor type X5R has a similar toler-

ance over a reduced temperature range of −55°C to +85°C.

Most large value ceramic capacitors (≊ 2.2µF) are manufac-

tured with Z5U or Y5V temperature characteristics. Their

capacitance can drop by more than 50% as the temperature

goes from 25°C to 85°C. Therefore X7R is recommended

over Z5U and Y5V in applications where the ambient tem-

perature will change significantly above or below 25°C.

Tantalum capacitors are less desirable than ceramic for use

as output capacitors because they are more expensive when

comparing equivalent capacitance and voltage ratings in the

1µF to 4.7µF range.

Another important consideration is that tantalum capacitors

have higher ESR values than equivalent size ceramics. This

means that while it may be possible to find a tantalum capac-

itor with an ESR value within the stable range, it would have

to be larger in capacitance (which means bigger and more

costly ) than a ceramic capacitor with the same ESR value. It

should also be noted that the ESR of a typical tantalum will

increase about 2:1 as the temperature goes from 25°C down

to −40°C, so some guard band must be allowed.

NOISE BYPASS CAPACITOR

Connecting a 0.01µF capacitor between the CBYPASS pin and

ground significantly reduces noise on the regulator output.

This cap is connected directly to a high impedance node in

the band gap reference circuit. Any significant loading on this

node will cause a change on the regulated output voltage. For

this reason, DC leakage current through this pin must be kept

as low as possible for best output voltage accuracy.

The types of capacitors best suited for the noise bypass ca-

pacitor are ceramic and film. High-quality ceramic capacitors

with either NPO or COG dielectric typically have very low

leakage. Polypropolene and polycarbonate film capacitors

are available in small surface-mount packages and typically

have extremely low leakage current.

Unlike many other LDO's, addition of a noise reduction ca-

pacitor does not effect the load transient response of the

device.

NO-LOAD STABILITY

The LP3985 will remain stable and in regulation with no ex-

ternal load. This is specially important in CMOS RAM keep-

alive applications.

ON/OFF INPUT OPERATION

The LP3985 is turned off by pulling the VEN pin low, and turned

on by pulling it high. If this feature is not used, the VEN pin

should be tied to VIN to keep the regulator output on at all time.

To assure proper operation, the signal source used to drive

the VEN input must be able to swing above and below the

specified turn-on/off voltage thresholds listed in the Electrical

Characteristics section under VIL and VIH.

FAST ON-TIME

The LP3985 output is turned on after Vref voltage reaches its

final value (1.23V nominal). To speed up this process, the

noise reduction capacitor at the bypass pin is charged with an

internal 70µA current source. The current source is turned off

when the bandgap voltage reaches approximately 95% of its

final value. The turn on time is determined by the time con-

stant of the bypass capacitor. The smaller the capacitor value,

the shorter the turn on time, but less noise gets reduced. As

a result, turn on time and noise reduction need to be taken

into design consideration when choosing the value of the by-

pass capacitor.

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LP3985

micro SMD MOUNTING

The micro SMD package requires specific mounting tech-

niques which are detailed in Texas Instruments Application

Note (AN-1112). Referring to the section Surface Mount

Technology (SMT) Assembly Considerations, it should be

noted that the pad style which must be used with the 5-bump

package is NSMD (non-solder mask defined) type.

For best results during assembly, alignment ordinals on the

PC board may be used to facilitate placement of the micro

SMD device.

micro SMD LIGHT SENSITIVITY

Exposing the micro SMD device to direct sunlight will cause

mis-operation of the device. Light sources such as halogen

lamps can effect electrical performance if brought near to the

device.

The wavelengths which have most detrimental effect are reds

and infra-reds, which means that the fluorescent lighting used

inside most buildings has very little effect on performance. A

micro SMD test board was brought to within 1cm of a fluo-

rescent desk lamp and the effect on the regulated output

voltage was negligible, showing a deviation of less than 0.1%

from nominal.

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LP3985

Physical Dimensions inches (millimeters) unless otherwise noted

5-Lead Small Outline Package (MF)

NS Package Number MF05A

thin micro SMD, 5 Bump, Package (TLA05)

NS Package Number TLA05AEA

The dimensions for X1, X2 and X3 are as given:

X1 = 1.006 ± 0.03mm

X2 = 1.463 ± 0.03mm

X3 = 0.6 ± 0.075mm

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LP3985

Notes

LP3985 Micropower, 150mA Low-Noise Ultra Low-Dropout CMOS Voltage Regulator

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