STw4141 Single Coil Dual Output Step Down DC/DC Converter for Digital Base Band and Multimedia Processor Supply PRELIMINARY DATA Features Single coil dual output switching converter for digital core supply & digital I/Os supply - Digital I/O supply:VOUT1 @ 200 mA - CPU CORE supply:VOUT2 @ 400 mA Wide range of fixed output voltage configurations available High efficiency synchronous step down converter with up to 92 % for the entire device Size and cost optimized application board (7x8 mm, height 1.2mm) three capacitors and only one inductor necessary for both outputs 2.7 V to 5.5 V battery input range 100mV output voltage accuracy full range in PWM (Including Line and Load Transients) 900 kHz fixed frequency PWM operation PFM mode operation at light load current PWM/PFM switch can be done automatically or forced by setting external pins (AUTO and MODE/SYNC) MODE/SYNC input pin for external clock synchronization from 600 kHz to 1.5 MHz VSEL input pin for VOUT2/VOUT2(red.) selection Ultra low shutdown current (Iq<1 A) Short circuit and thermal shutdown protections Solution size 7 x 8 mm TFBGA 3x3mm 16 bumps 0.5 mm pitch Applications Mobile phones PDAs and hand held terminals Portable media players Digital still camera WLAN and Bluetooth applications Description The STw4141 is a single coil dual output synchronous step down DC/DC converter that requires only four standard external components. It operates at a fixed 900 kHz switching frequency in PWM mode. The device can operate in PFM mode to maintain high efficiency over the full range of output currents. The STw4141 application requires a very small PCB area and offers a very efficient, accurate, space and cost saving solution to fulfill the requirements of digital baseband or multimedia processor supply (CORE & I/O). Application Test Circuit L 4.7 H VLX1 VIN=2.7V to 5.5V PVDD CIN 10 F 6.3 V VLX2 A2 B1 A4 D3 D1 VDD EN FB1 COUT1 22 F 6.3 V D4 AUTO STw4141 C2 VSEL VOUT1=1.8V VOUT1 A3 B4 C3 D2 MODE/SYNC C1 A1 C4 PGND GND B2 VOUT2=1.0V/1.2V VOUT2 FB2 STATE COUT2 22 F 6.3 V B3 T_MODE December 2005 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. Rev 1 1/27 www.st.com 2 STw4141 Order Codes Table 1. STw4141 ordering information Output voltage options(1) Part number Package type Package marking VOUT1(2) (I/O) VOUT2 (CORE) VOUT2reduced (CORE) Supplied as STw41411 STA1 1.8 V 1.2 V 1.0 V Tray STw41411/T STA1 1.8 V 1.2 V 1.0 V Tapes/Reels STw41412 STA2 1.8 V 1.3 V 1.0 V Tray STw41412/T STA2 1.8 V 1.3 V 1.0 V Tapes/Reels STw41413 STA3 1.5 V 1.3 V 1.0 V Tray STA3 1.5 V 1.3 V 1.0 V Tapes/Reels STA4 1.8 V 1.5 V 1.3 V Tray STw41414/T STA4 1.8 V 1.5 V 1.3 V Tapes/Reels STw41415 STA5 1.8 V 1.35 V 1.0 V Tray STw41415/T STA5 1.8 V 1.35 V 1.0 V Tapes/Reels STw41416 STA6 1.8 V 1.25 V 1.0 V Tray STw41416/T STA6 1.8 V 1.25 V 1.0 V Tapes/Reels STw41413/T STw41414 TFBGA 3x3x1.2 16 balls 1. The output configuration which will be introduced in production will be only those related to customer design-in. 2. VOUT1 VOUT2 THIS CONDITION MUST BE ALWAYS VALID. 2/27 STw4141 Contents 1 STw4141 Pinout 2 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 4 .............................................. 5 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 Dynamic electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.5 Soft start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.6 Settling time of VOUT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.7 Line transients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.8 Load transients in AUTO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.9 Load transients in PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.10 Switching between PFM and PWM in FORCED MODE . . . . . . . . . . . . . . . . 13 2.11 Efficiency in PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.12 Efficiency in AUTO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.13 Output voltages versus output currents in PWM and PFM . . . . . . . . . . . . . . 16 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.2 PWM and PFM mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3 Current limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.4 Short circuit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.5 Thermal shutdown protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.1 User mode details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2 Automatic PWM/PFM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.3 User selected PWM/PFM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.4 External clock synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.5 Checking Transient response versus external components . . . . . . . . . . . . . 20 4.6 Bill of Material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.6.1 Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3/27 STw4141 4.7 4.6.2 Input capacitor (CIN selection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.6.3 Output capacitors (COUT selection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.6.4 Capacitors selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 PCB layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.7.1 PCB layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.7.2 TFBGA16 internal bumps access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5 Package Outline and Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4/27 STw4141 1 1 STw4141 Pinout STw4141 Pinout Figure 1. Pin assignment in TFBGA 3x3 mm - 16 bumps 0.5 mm pitch 11 22 33 44 44 33 AA PGND VLX1 VLX2 VOUT1 VOUT1 BB PVDD STATE T_MODE VOUT2 CC MODE/ SYNC AUTO VSEL DD FB1 FB2 VDD 22 11 VLX2 VLX1 PGND AA VOUT2 T_MODE STATE PVDD BB GND GND VSEL AUTO MODE/ SYNC EN EN VDD FB2 FB1 STw4141 pin description Pin Symbol Description A1 PGND Power ground B1 PVDD Power supply voltage C1 MODE/SYNC MODE/SYNC = High to forced PWM mode MODE/SYNC = Low to forced PFM mode MODE/SYNC = 600 kHz - 1.5 MHz external clock synchronization in PWM D1 FB1 Feedback 1 A2 VLX1 External inductor connection pin 1 STATE Output STATE pin allow the user to monitor operation mode of the product STATE = High - PFM mode STATE = Low - PWM mode If not used must be left unconnected. C2 AUTO PWM/PFM automatic switch control pin AUTO = High - PWM/PFM mode automatic switch ENABLED AUTO = Low - PWM/PFM mode automatic switch DISABLED PWM/PFM mode controlled by MODE/SYNC pin) D2 FB2 Feedback 2 A3 VLX2 External inductor connection pin 2 B3 T_MODE Input signal for test mode selection. This pin must be connected to GND. C3 VSEL Voltage selection input VSEL = High - VOUT1 = 1.8V, VOUT2 = 1.2V (valid for STA1) VSEL = Low - VOUT1 = 1.8V, VOUT2 = 1.0V (valid for STA1) (For other voltage options see Table 1: STw4141 ordering information) D3 VDD Signal supply voltage A4 VOUT1 Output voltage 1 B2 DD Bottom view Top view Table 2. CC 5/27 STw4141 1 STw4141 Pinout Table 2. STw4141 pin description Pin Symbol Description B4 VOUT2 Output voltage 2 C4 GND Signal ground EN Enable Input: EN = Low - Device in shutdown mode, EN = High - Enable device This pin must be connected either to VDD or GND. D4 PGND pin This is the ground pin related to power signal. This pin should be connected to the board ground plane by short and wide track or multiply vias to reduce impedance and EMI. GND pins This is the ground pin related to analog signal. This pin is designed to provide power to the device. This path leads high currents. It should be wide and short to minimize track impedance to reduce losses and EMI. This pin is designed to provide signal supply voltage to the device. There is no specific VDD pin requirement for its related track design. VLX1/VLX2 pins External coil is connected on those pins. It should be placed as closed as possible to the device in order minimize resistances which cause looses. These paths lead high currents. It is the first output voltage of this device. This path leads high currents. It should be wide and VOUT1 pin3 short to minimize track impedance to reduce losses and EMI. It is the second output voltage of this device. This path leads high currents. It should be wide and VOUT2 pin short to minimize track impedance to reduce losses and EMI. PVDD pin FB1 pin Intended to measure VOUT1 voltage in order to ensure the regulation of this output. FB2 pin Intended to measure VOUT2 voltage in order to ensure the regulation of this output. This is the enable pin of the device. Pulling this pin to ground, forces the device into shutdown mode. Pulling this pin to VDD enables the device. This pin must be terminated. MODE/SYNC pin The MODE/SYNC pin is a multipurpose pin which provides mode selection and frequency synchronization. The device can also be synchronized to an external clock signal from 600 kHz to 1.5 MHz by the MODE/SYNC pin. During synchronization, the mode is forced to PWM mode and the top switch turn-on is synchronized to the rising edge of the external clock. This pin allows the device to automatically switch from PWM to PFM mode following load on both AUTO pin 2 outputs. ENABLE pin STATE pin This output pin informs user in which state the device is working: PWM or PFM mode. VSEL pin This pin is used to reduce VOUT2 (CORE) output voltage in order to reduce the processor power consumption when entering into sleep mode. 6/27 STw4141 2 Electrical Characteristics 2 Electrical Characteristics 2.1 Absolute maximum ratings Absolute maximum ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All voltages are referenced to GND. Table 3. Absolute maximum ratings Symbol 2.2 Parameter Value Unit PVDD Power Supply Voltage -0.3 to 6 V VDD Signal Supply Voltage -0.3 to 6 V VEN Enable Input -0.3 to VDD V VSEL Voltage Selection -0.3 to VDD V VMODE/SYNC Operating Mode Selection/Synchronization Input -0.3 to VDD V VAUTO PWM/PFM automatic switch selection -0.3 to VDD V VT_MODE Test mode selection -0.3 to VDD V VSTATE Operating mode information -0.3 to VOUT1 V VOUT1,FB1 Output Voltage 1, Feedback 1 -0.3 to 3.3 V VOUT2, FB2 Output Voltage 2, Feedback 2 -0.3 to 3.3 V VLX1 External Inductor Connection Pin 1 -0.3 to VDD V VLX2 External Inductor Connection Pin 2 -0.3 to 3.3 V TA Operating Temperature Range -40 to 85 C TJ Maximum Operating Junction Temperature 150 C TSTG Storage Temperature Range -65 to 150 C Value Unit 150 C/W Thermal data Table 4. Symbol RthJA Thermal data Parameter Thermal Resistance Junction-Ambient TFBGA 3x3 mm - 16 bumps - 0.5 mm pitch 7/27 STw4141 2 Electrical Characteristics 2.3 DC electrical characteristics Characteristics measured over recommended operating conditions unless otherwise is noted. All typical values are referred to TA = 25C, PVDD = 3.6V, VDD = 3.6V. Table 5. DC electrical characteristics Symbol Parameter PVDD Power supply voltage ILIM Peak current limit VOUT1(1) Output voltage 1(2) Test Conditions Min. Typ 2.7 Max. Unit 5.5 V 1.6 A -3 +3 % Output voltage 2(2) VSEL = VDD, MODE/SYNC = VDD -3 +3 % Output voltage 2(2) VSEL = GND, MODE/SYNC = VDD -3 +3 % VOUT2 IOUT1 Output current 1 200 mA IOUT2 Output current 2 400 mA Iq Quiescent Current (PWM) IOUT1 = 0 mA, IOUT2 = 0 mA EN = VDD, VSEL = VDD MODE/SYNC = VDD, AUTO = GND 600 A Quiescent Current (PFM) IOUT1 = 0 mA, IOUT2 = 0 mA EN = VDD, VSEL = VDD MODE/SYNC = GND, AUTO = GND 90 A Shutdown Current EN = GND, VSEL = GND MODE/SYNC = GND, AUTO = GND 1 5 A Enable functions VENH Enable Threshold High VENL Enable Threshold Low 0.9 V 0.4 V Mode/sync functions VM/SH MODE/SYNC Threshold High VM/SL MODE/SYNC Threshold Low 0.9 V 0.4 V VSEL functions VSELH Voltage Selection Threshold High VSELL Voltage Selection Threshold Low 8/27 0.9 V 0.4 V STw4141 Table 5. 2 Electrical Characteristics DC electrical characteristics Symbol Parameter Test Conditions Min. Typ Max. Unit Auto functions VAUTOH Voltage Selection Threshold High VAUTOL Voltage Selection Threshold Low 0.9 V 0.4 V State functions VSTATEH Voltage Selection Threshold High RLmax = 100k, CLmax = 10pF VSTATEL Voltage Selection Threshold Low RLmax = 100k, CLmax = 10pF 1. 0.7VOUT1 V 0.3 VOUT1 V VOUT1 VOUT2 . This condition must always be valid. 2. Output voltage accuracy excludes line and load transients 2.4 Dynamic electrical characteristics Characteristics measured over recommended operating conditions unless otherwise is noted. All typical values are referred to TA = 25C, PVDD = 3.6V, VDD = 3.6V. Table 6. Symbol Dynamic electrical characteristics Parameter Test Conditions Min. Typ Max. Unit fSW Switching frequency fSYNC Sync mode frequency Ts Settling time (soft start) 400 s TS2 Settling time VSEL change from GND to VDD VOUT2 (reduced)/VOUT2 80 s 900 600 kHz 1500 kHz 9/27 2 Electrical Characteristics 2.5 STw4141 Soft start To avoid spikes on battery during STw4141 start-up sequence, a smooth start-up is implemented. Reference voltage grows up less than 600 s until it achieves is final target. Therefore, STw4141 start up is smooth and secure for the overall mobile phone. Figure 2. 2.6 Settling time of VOUT2 Figure 3. 10/27 Smooth start-up sequence VIN = 3.6V, VOUT1 = 1.8V@ 200mA, VOUT2 =1.2V@400mA Settling time of VOUT2, IOUT1 = 200mA, IOUT2 = 400mA STw4141 2.7 Line transients Figure 4. 2.8 2 Electrical Characteristics Line transient, VOUT1 = 1.8V @ 100mA, VOUT2 = 1.2V @ 100mA Load transients in AUTO mode Figure 5. Load transient in AUTO mode VIN = 3.6V, VOUT1 = 1.8V, VOUT2 = 1.2V 11/27 2 Electrical Characteristics 2.9 STw4141 Load transients in PWM mode Figure 6: Load transient in PWM mode, IOUT1 = 1mA to 200mA, IOUT2 = 1mA to 400mA Load transient related to in-phase switching VIN = 3.6V, VOUT1 = 1.8V, VOUT2 = 1.2V Load transient output 2 leading output 1 VIN = 3.6V, VOUT1 = 1.8V, VOUT2 = 1.2V 12/27 Load transient output 1 leading output 2 VIN = 3.6V, VOUT1 = 1.8V, VOUT2 = 1.2V Load transient related to anti-phase switching VIN = 3.6V, VOUT1 = 1.8V, VOUT2 = 1.2V STw4141 2.10 2 Electrical Characteristics Switching between PFM and PWM in FORCED MODE Figure 7. Switching between PFM to PWM operation modes VIN = 3.6V, IOUT1 = 10mA, IOUT2 = 10mA Figure 8. Switching between PWM to PFM operation modes VIN = 3.6V, IOUT1 = 10mA, IOUT2 = 10mA 13/27 STw4141 2 Electrical Characteristics 2.11 Efficiency in PWM The efficiency of a switching regulator is equal to the total output power divided by the input. STw4141 has high efficiency up to 92% (for the 2 outputs). Efficiency curve is flat over the output current range. Figure 9. Switching regulator efficiency in PWM mode Efficiency in PWM mode @ VIN=2.7V, TA= 25C Efficiency in PWM mode @ VIN=3.6V, TA= 25C 100 100 90 90 80 80 70 70 60 60 40 20 1 400 360 320 80 280 400 360 320 280 240 10 IOUT1 (mA) IOUT2 (mA) Efficiency vs IOUT1@IOUT2 PWM mode, TA=25C IOUT2 (mA) Efficiency vs IOUT1@IOUT2 PWM mode, TA=25C 100 100 VIN = 3.6V VIN = 2.7V IOUT2 = 200 mA IOUT2 = 200 mA 80 80 70 EFFICIENCY (%) VOUT2 = 1.2V 60 50 40 IOUT2 = 400 mA VOUT1 = 1.8V VOUT2 = 1.2V IOUT2 = 400 mA VOUT1 = 1.8V 70 IOUT2 = 0 mA 90 IOUT2 = 0 mA 90 EFFICIENCY (%) 90-100 80-90 70-80 60-70 50-60 40-50 30-40 20-30 10-20 0-10 0 40 120 200 180 160 140 120 100 1 1 1 40 20 80 40 160 60 200 80 IOUT1 (mA) Efficiency (%) 40 30 240 10 0 50 20 200 200 180 160 140 120 100 70-80 60-70 50-60 40-50 30-40 20-30 10-20 0-10 160 20 90-100 80-90 120 30 60 Efficiency (%) 80 50 40 60 50 40 30 30 20 20 10 10 0 0 1 10 100 1 1000 10 100 1000 IOUT1 (mA) IOUT1 (mA) Efficiency vs IOUT2@IOUT1, PWM mode, TA=25C Efficiency vs IOUT2@IOUT1, PWM mode, TA=25C 100 VIN = 3.6V 100 VIN = 2.7V IOUT1 = 0 mA 90 IOUT1 = 0 mA 90 80 80 IOUT1 = 100 mA IOUT1 = 100 mA IOUT1 = 200 mA VOUT1 = 1.8V VOUT2 = 1.2V 60 50 40 70 EFFICIENCY (%) EFFICIENCY (%) 70 IOUT1 = 200 mA VOUT1 = 1.8V VOUT2 = 1.2V 60 50 40 30 30 20 20 10 10 0 0 1 1 10 100 IOUT2 (mA) 14/27 1000 10 100 IOUT2 (mA) 1000 STw4141 2.12 2 Electrical Characteristics Efficiency in AUTO The efficiency of a switching regulator is equal to the total output power divided by the input. STw4141 has high efficiency up to 92% (both outputs) and always higher than 70% for output currents higher than 1mA. Figure 10. Switching regulator efficiency in auto mode Efficiency VS output currents IOUT1 and IOUT2, VIN = 2.7V, AUTO mode Efficiency VS output currents IOUT1 and IOUT2, VIN = 3.6V, AUTO mode 100 100 90 90 80 80 70 70 60 80 160 10 160 40 1 Efficiency VS IOUT1@IOUT2, AUTO mode, TA = 25C IOUT2 (mA) 100 VIN = 2.7V VIN = 3.6V IOUT2 = 0 mA 90 IOUT2 = 0 mA 90 IOUT2 = 200 mA IOUT2 = 200 mA 80 80 IOUT2 = 400 mA VOUT1 = 1.8V 70 IOUT2 = 400 mA 70 VOUT2 = 1.2V EFFICIENCY (%) EFFICIENCY (%) 90-100 80-90 70-80 60-70 50-60 40-50 30-40 20-30 10-20 0-10 Efficiency VS IOUT1@IOUT2, AUTO mode, TA = 25C 100 60 50 40 VOUT1 = 1.8V VOUT2 = 1.2V 60 50 40 30 30 20 20 10 10 0 0 1 10 100 1 1000 10 100 1000 IOUT1 (mA) IOUT1 (mA) Efficiency VS IOUT2@IOUT1, AUTO mode, TA = 25C Efficiency VS IOUT2@IOUT1, AUTO mode, TA = 25C 100 100 VIN = 2.7V VIN = 3.6V IOUT1 = 0 mA 90 IOUT1 = 0 mA 90 80 80 IOUT1 = 100 mA 70 IOUT1 = 100 mA 70 IOUT1 = 200 mA EFFICIENCY (%) EFFICIENCY (%) 400 320 80 IOUT1 (mA) IOUT2 (mA) 360 0 120 280 400 360 320 20 200 40 1 1 40 30 120 60 240 IOUT1 (mA) 200 90 280 120 30 240 0 150 50-60 40-50 30-40 20-30 10-20 0-10 Efficiency (%) 40 200 20 10 180 90-100 80-90 70-80 60-70 160 30 50 120 40 60 Efficiency (%) 80 50 60 VOUT1 = 1.8V VOUT2 = 1.2V 50 40 VOUT1 = 1.8V VOUT2 = 1.2V 50 40 30 30 20 20 10 10 0 IOUT1 = 200 mA 60 0 1 10 100 IOUT2 (mA) 1000 1 10 100 1000 IOUT2 (mA) 15/27 STw4141 2 Electrical Characteristics 2.13 Output voltages versus output currents in PWM and PFM Figure 11. Output voltages versus output currents in PWM and PFM VOUT1 VS IOUT1 @ IOUT1 - PWM mode VOUT2 VS IOUT2 @ IOUT1 - PWM mode 1.830 1.230 VIN = 3.6V V IN = 3.6V 1.820 1.220 IOUT1 = 0 mA IOUT2 = 0 mA 1.210 IOUT2 = 200 mA 1.800 VOUT2 (V) VOUT1 (V) 1.810 IOUT2 = 400 mA IOUT1 = 200 mA 1.790 1.190 1.780 1.180 1.770 IOUT1 = 100 mA 1.200 1.170 1 10 100 1000 1 10 IOUT1 (mA) 100 VOUT1 VS IOUT1 @ IOUT2 - PFM mode VOUT2 VS IOUT2 @ IOUT1 - PFM mode 1.230 1.830 VIN = 3.6V VIN = 3.6V 1.220 1.820 IOUT1 = 0 mA IOUT2 = 0 mA 1.210 IOUT2 = 20 mA IOUT1 = 10 mA IOUT2 = 40 mA VOUT2 (V) VOUT1 (V) 1.810 1.800 IOUT1 = 20 mA 1.200 1.790 1.190 1.780 1.180 1.170 1.770 1 10 IOUT1 (mA) 16/27 1000 IOUT2 (mA) 100 1 10 IOUT2 (mA) 100 STw4141 3 Functional Description 3.1 Introduction 3 Functional Description The STw4141 is an easy to use, single coil dual outputs step down DC/DC converter optimized to supply low-voltage to CPUs or DSPs in cell phones and other miniature devices powered by single cell lithium-ion or 3 cell NiMH/NiCd batteries. It provides two different output voltages with high efficiency operation in a wide range of output currents. The device offers high DC voltage regulation accuracy and load transient response to satisfy demanding processor core supply. The converter is based on voltage mode buck architecture using PWM and PFM operation modes. At light load currents, the device can operate in PFM mode to maintain high efficiency over the entire load current range. Switching between PWM and PFM modes can be done automatically or can be forced by external pins (AUTO and MODE/SYNC). Externally synchronized or fixed frequency (internal oscillator) PWM mode offers full output current capability while minimizing interference to sensitive RF and data acquisition circuits. 3.2 PWM and PFM mode operation PWM (Pulse Width Modulation) mode is intended for normal load to high load currents. Energy is delivered to the load with an accurate and defined frequency of 900 kHz. PFM (Pulse Frequency Modulation) mode is intended for low load currents to maintain high efficiency conversion. Forced mode: When AUTO pin is LOW, the operating mode is selectable by the user itself. It means that system controls the behavior of the STw4141 according to processor needs. STw4141 is switched from PWM to PFM mode using MODE/SYNC pin (refer to User mode details" section). Automatic PWM / PFM switch: When AUTO pin is HIGH, the operating mode is directly controlled by internal digital circuit according to processor needs. The device switches from PWM to PFM by itself if sum of output currents is lower than approximately 100 mA during at least 16 clock cycles. The device can be forced to PWM mode connecting MODE/SYNC to HIGH level. (see Section 2.8 and Section 2.9). 3.3 Current limiter This protection limits the current flowing through coil. As soon as ILIM is detected, the duty cycle is terminated and prevents the coil current against rising above peak current limit. There is no reset of device. 3.4 Short circuit protection It protects the device against short-circuit at output terminals. When one or both output voltages are decreased by 0.7 V below their nominal output values the device enters into reset followed by soft start sequence. 17/27 STw4141 4 Application information 3.5 Thermal shutdown protection Thermal shutdown protects the device against damage due to overheating when maximum operating junction temperature is exceeded. The device is kept in reset until junction temperature decreases by 25C approximately. 4 Application information 4.1 User mode details The following table describes the different user modes available. Depending on the application constraints (processor I/O pins available) and expected efficiency, PWM or PFM mode are forced or automatically controlled by STw4141 internal digital gates. Table 7. STw4141 available user modes EN AUTO MODE/ SYNC Shutdown L X X Forced PFM H L L Forced PWM H L H Forced PWM and synchronized external clock H L CLK Auto mode H H L Forced PWM H H H Forced PWM and synchronized external clock H H CLK Mode OFF FORCED AUTO Table 8. 18/27 User mode / pins Operating mode information (STATE pin - digital output) Operation mode State pin voltage level PFM VOUT1 PWM GND STw4141 4.2 4 Application information Automatic PWM/PFM mode This user mode is designed to allow STw4141 to switch automatically between PWM and PFM modes. This feature improves the application efficiency because STw4141 enters in PFM mode according to application processor current consumption. Figure 12. Automatic PWM/PFM switch schematic example L 4.7 H VLX1 VIN=2.7V to 5.5V CIN 10 F 6.3 V PVDD VLX2 A2 B1 A4 D3 D1 VDD EN AUTO VSEL VOUT1 A3 APE I/O FB1 COUT1 22 F 6.3 V C1 100 nF COUT2 22 F 6.3 V C2 100 nF D4 STw4141 C2 B4 C3 D2 MODE/SYNC C1 A1 C4 PGND GND VOUT2 APE CORE FB2 STATE B2 APPLICATION PROCESSOR B3 T_MODE MODE_INFO SLEEP 4.3 GND User selected PWM/PFM mode STw4141 PWM/PFM mode can also be controlled by the application processor. This feature is accessible through MODE/SYNC pin state. It is useful to users who want to use STw4141 with the modem digital processor. Therefore, MODE/SYNC pin is connected to SLEEP mobile phone signal. Figure 13. PWM/PFM forced mode schematic example L 4.7 H VLX1 VIN=2.7V to 5.5V CIN 10 F 6.3 V PVDD VLX2 A2 B1 A4 D3 D1 VDD EN AUTO VSEL VOUT1 A3 APE I/O FB1 COUT1 22 F 6.3 V C1 100 nF COUT2 22 F 6.3 V C2 100 nF D4 STw4141 C2 B4 C3 D2 MODE/SYNC C1 A1 C4 PGND GND VOUT2 APE CORE FB2 B2 STATE APPLICATION PROCESSOR B3 T_MODE MODE_INFO PWR_EN SLEEP GND 19/27 STw4141 4 Application information 4.4 External clock synchronization Figure 14. Application using external clock synchronization L 4.7 H VLX1 VIN=2.7V to 5.5V PVDD VLX2 A2 B1 CIN 10 F 6.3 V A4 VDD D1 D3 EN VOUT1 A3 APE I/O FB1 COUT1 22 F 6.3 V C1 100 nF COUT2 22 F 6.3 V C2 100 nF D4 AUTO STw4141 C2 VSEL B4 C3 D2 MODE/SYNC C1 A1 C4 PGND GND VOUT2 APE CORE FB2 B2 STATE APPLICATION PROCESSOR B3 T_MODE MODE_INFO CLK SLEEP 4.5 GND Checking Transient response versus external components The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT is immediately shifted by an amount equal to ILOAD x ESR, where ESR is the equivalent series resistance of COUT. ILOAD also begins to charge or discharge COUT generating a feedback error signal used by the regulator to return VOUT to its steady-state value. In order to improve the transient response, it is better to use two 10 F ceramic capacitors on each output to reduce ESR. 4.6 Bill of Material 4.6.1 Inductor selection The choice of which inductor to use depends on the price and size versus performance required with the STw4141 application. Table 9 shows some typical surface mount inductors that work well in STw4141 applications. Table 9. Bill of material: inductor selection Part number 20/27 Supplier Value (H) DCR ( max) Max DC current (mA) Size (mm) WxLxH VFL4012A-4R7M1R1 TDK 4.7 0.14 1100 3.5 x 3.7 x 1.2 VFL3012A-4R7MR74 TDK 4.7 0.16 740 2.6 x 2.8 x 1.2 744031004 WUERTH 4.7 0.085 900 3.8 x 3.8 x 1.8 STw4141 4.6.2 4 Application information Input capacitor (CIN selection) Input capacitor of 10 F ceramic low ESR capacitor should be used to reduce switching losses. It should be placed as close as possible to supply pins VDD and PVDD. The connection traces should be wide and short to minimize impedance. 4.6.3 Output capacitors (COUT selection) The selection of COUT is driven by the required ESR to minimize voltage ripple and load step transients. There are two possibilities for output capacitors: either a 22 F is connected to ground or two 10 F ceramic are used to reduce ESR and switching losses. The capacitor should be placed as close as possible to VOUTx pins. The connection traces should be wide and short to minimize impedance. 4.6.4 Capacitors selection Table 10. Bill of Material: capacitor selection Component CIN Supplier Part number Case size TDK C1608X5R0J106MT 10 F, 6.3V 0603 TDK C2012X5R0J106MT 10 F, 6.3V 0805 TAIYO YUDEN JMK212BJ106MG-T 10 F, 6.3V 0805 C1608X5R0J106MT 2 x 10 F, 6.3V 2 x 0603 C2012X5R0J106MT 2 x 10 F, 6.3V 2 x 0805 C2012X5R0J226MT 22 F, 6.3V 0805 JMK212BJ106MG-T 2 x 10 F, 6.3V 2 x 0805 JMK212BJ226MG-T 22 F, 6.3V 0805 TDK COUT1, COUT2 TAIYO YUDEN 4.7 Value PCB layout considerations The Printed Circuit Board layout must include the following consideration: Current paths carrying high currents (bold lines in Figure 15) must be wide and short to minimize impedance in order to reduce looses and EMI. Small currents flow through voltage paths. No specific care is requested about voltage paths but it is recommended to follow the general rules for PCB routing to reduce influence of external and internal interferences. 21/27 STw4141 4 Application information Figure 15. Board layout track length and width L 4.7 H HIGH CURRENT PATH VLX1 VIN=2.7V to 5.5V PVDD CIN 10 F 6.3 V VLX2 A2 A4 D3 D1 VDD EN STw4141 C2 B4 C3 D2 MODE/SYNC C1 A1 C4 PGND GND 4.7.1 FB1 COUT1 22 F 6.3 V D4 AUTO VSEL VOUT1=1.8V VOUT1 A3 B1 B2 VOUT2=1.0V/1.2V VOUT2 FB2 STATE COUT2 22 F 6.3 V B3 T_MODE PCB layout Figure 16 and Figure 17 show the PCB layout. All components are on the top side of the board. Figure 16. Demoboard top layer 22/27 Figure 17. Demoboard assembled with 2x10F output capacitors STw4141 4.7.2 4 Application information TFBGA16 internal bumps access Pad centers are at 500 m distance. Pad diameter is 275 m. The distance between two adjacent pad edges is only 225 m. We recommend a distance for lead-out signals from the center of pad matrix by 75 m wide trace. Isolation distance in this case is 75 m (see Figure 18 and Figure 19). Figure 18. TFBGA16 ball pad spacing and track parameters to internal pads Grid dot distance : with A = 500m B = 275m C = 75m Figure 19. PCB routing example using TFBGA16 23/27 STw4141 5 Package Outline and Mechanical Data 5 Package Outline and Mechanical Data Table 11: TFBGA 3x3x1.20 16 F4x4 0.50. Package code: L0 - JEDEC/EAIJ reference number: N/A Ref Min. A 1.01 A1 0.15 A2 Typ. Max. 1.20 (Note 1) 0.82 b 0.25 0.30 0.35 D 2.85 3.00 3.15 D1 E 1.50 2.85 3.00 E1 1.50 e 0.50 ddd 0.85 3.15 0.08 eee 0.15 fff 0.05 Note: 1 Max mounted height is 1.12 mm. Based on a 0.28 mm ball pad diameter. Solder paste is 0.15 mm thickness and 0.28 mm diameter. 2 TFBGA stands for Thin Profile Fine Pitch Ball Grid Array. Thin profile: The total profile height (DIm A) is measured from the seating plane to the top of the component. A = 1.01 to 1.20 mm Fine pitch < 1.00 mm pitch. 3 The tolerance of position that controls the location of the pattern of balls with respect to datums A and B. For each ball there is a cylindral tolerance zone eee perpendicular to datum C and located on true position with respect to datums A and B as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone. 4 The tolerance of position that controls the location of the balls within the matrix with respect to each other. For each ball there is a cylindrical tolerance zone fff perpendicular to datum C and located on true position as defined by e. The axis perpendicular to datum C of each ball must lie within the tolerance zone. Each tolerance zone fff in the array is contained entirely in the respective above eee zone above. The axis of each ball must be simultaneously in both tolerance zones. 5 Leadfree package according to JEDEC JESD-020-C 24/27 STw4141 5 Package Outline and Mechanical Data Figure 20. TFBGA 3x3x1.20 16 F4x4 0.50 25/27 STw4141 6 Revision history 6 Revision history Date 8-Dec-2005 26/27 Revision 1 Changes Initial release STw4141 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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