PRELIMINARY DATA
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
Rev 1
December 2005 1/27
2
STw4141
Single Coil Dual Output Step Down DC/DC Converter
for Digital Base Band and Multimedia Processor Supply
Features
■Single coi l dua l output switchi ng co nve r ter for
digital core supply & digital I/Os supply
– Digit al I/O suppl y:VOUT1 @ 200 mA
– CPU CORE supply:VOUT2 @ 400 mA
■Wide range of fixed output voltage
configurations avail abl e
■High efficiency synchronous step down
converter with up to 92 % for the entire device
■Size and cost optimized application board
(7x8 mm, height 1.2mm) three capacitors and
only one inductor necessary for both outputs
■2.7 V to 5.5 V battery input range
■±100mV output voltage accuracy full range in
PWM (Including Line and Load Transients)
■900 kHz fixed fr eque nc y PW M operati on
■PFM mode operation at light load current
■PWM/PFM switch can be done automatically or
forced by se ttin g exte rnal pin s (A UTO and
MODE/SYNC)
■MODE/SYNC input pin for external clock
synchronization from 600 kHz to 1.5 MHz
■VSEL input pin for VOUT2/VOUT2(red.) selection
■Ultra low shutdown current (Iq<1 µA)
■Short circuit and thermal shutdown protections
Applications
■Mobile phones
■PDAs and hand held terminals
■Portable media players
■Digital still camera
■WLAN and Bluetooth applications
Description
The STw4141 is a single coil dual output
synchronous step down DC/DC converter that
requires only four standard external components.
It operates at a fixed 900 kHz switching frequency
in PWM mode. The device can operate in PFM
mode to maintain high efficiency over the full
range of output currents.
The STw4141 application requires a very small
PCB area and offers a very efficient, accurate,
space and cost saving solution to fulfill the
requirements of digital baseband or multimedia
processor supply (CORE & I/O).
Application Test Circuit
TFBGA 3x3mm
16 bumps 0.5 mm pitch
Solution size
7 x 8 mm
VOUT1
FB1
VOUT1=1.8V
COUT1
22 µF
6.3 V
VOUT2
FB2
VOUT2=1.0V/1.2V
COUT2
22 µF
6.3 V
PVDD
VIN=2.7V to 5.5V
CIN
10 µF
6.3 V
PGND
VDD
EN
VLX1 VLX2
GND
MODE/SYNC
T_MODE
AUTO
L 4.7 µH
STw4141
VSEL
STATE
B1
D3
D4
C2
C3
C1
A4
D1
B4
D2
B2
A2 A3
A1 B3
C4
VOUT1
FB1
VOUT1=1.8V
COUT1
22 µF
6.3 V
VOUT2
FB2
VOUT2=1.0V/1.2V
COUT2
22 µF
6.3 V
PVDD
VIN=2.7V to 5.5V
CIN
10 µF
6.3 V
PGND
VDD
EN
VLX1 VLX2
GND
MODE/SYNC
T_MODE
AUTO
L 4.7 µH
STw4141
VSEL
STATE
B1
D3
D4
C2
C3
C1
A4
D1
B4
D2
B2
A2 A3
A1 B3
C4
www.st.com
STw4141
2/27
Order Codes
Table 1. STw4141 ordering information
Part number Package type Package
marking
Output voltage options(1)
1. The output configuration which will be introduced in production will be only those related to customer design-in.
Supplied as
VOUT1(2)
(I/O)
2. THIS CONDITION MUST BE ALWAYS VALID.
VOUT2
(CORE)
VOUT2reduced
(CORE)
STw41411
TFBGA
3x3x1.2
16 balls
STA1 1.8 V 1.2 V 1.0 V Tray
STw41411/T STA1 1.8 V 1.2 V 1.0 V Tapes/Reels
STw41412 STA2 1.8 V 1.3 V 1.0 V Tray
STw41412/T STA2 1.8 V 1.3 V 1.0 V Tapes/Reels
STw41413 STA3 1.5 V 1.3 V 1.0 V Tray
STw41413/T STA3 1.5 V 1.3 V 1.0 V Tapes/Reels
STw41414 STA4 1.8 V 1.5 V 1.3 V Tray
STw41414/T STA4 1.8 V 1.5 V 1.3 V Tapes/Reels
STw41415 STA5 1.8 V 1.35 V 1.0 V Tray
STw41415/T STA5 1.8 V 1.35 V 1.0 V Tapes/Reels
STw41416 STA6 1.8 V 1.25 V 1.0 V Tray
STw41416/T STA6 1.8 V 1.25 V 1.0 V Tapes/Reels
VOUT1 VOUT2≥
STw4141
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Contents
1 STw4141 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 Dynamic electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.5 Soft start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.6 Settling time of VOUT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.7 Line transients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.8 Load transients in AUTO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.9 Load transients in PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.10 Switching between PFM and PWM in FORCED MODE . . . . . . . . . . . . . . . . 13
2.11 Efficiency in PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.12 Efficiency in AUTO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.13 Output voltages versus output currents in PWM and PFM . . . . . . . . . . . . . . 16
3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.2 PWM and PFM mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3 Current limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4 Short circuit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.5 Thermal shutdown protecti on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1 User mode details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.2 A utomatic PWM/PFM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.3 User selected PWM/PFM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.4 External clock synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.5 Checking Transient response versus external components . . . . . . . . . . . . . 20
4.6 Bill of Material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.6.1 Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
STw4141
4/27
4.6.2 Input capacitor (CIN selection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.6.3 Output capacitors (COUT selection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.6.4 Capacitors selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.7 PCB lay o ut considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.7.1 PCB layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.7.2 TFBGA16 internal bumps access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5 Package Outline and Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
STw4141 1 STw4141 Pinout
5/27
1 STw4141 Pinout
Figure 1. Pin assignment in TFBGA 3x3 mm - 16 bumps 0.5 mm pitch
Table 2. STw4141 pin description
Pin Symbol Description
A1 PGND Power ground
B1 PVDD Power supply voltage
C1 MODE/SYNC MODE/SYNC = High to forced PWM mode
MODE/SYNC = Low to forced PFM mode
MODE/SYNC = 600 kHz - 1.5 MHz external clock synchronization in PWM
D1 FB1 Feedback 1
A2 VLX1 External inductor co nne cti on pin 1
B2 STATE
Output STATE pin allow the user to monitor operation mode of the product
STATE = High - PFM mode
STATE = Low - PWM mode
If not used must be left unconnected.
C2 AUTO
PWM/PFM automatic switch control pin
AUTO = High - PWM/PFM mode automatic switch ENABLED
AUTO = Low - PWM/PFM mode automatic switch DISABLED
PWM/PFM mode controlled by MODE/SYNC pin)
D2 FB2 Feedback 2
A3 VLX2 External inductor co nne cti on pin 2
B3 T_MODE Input signal for test mode selection. This pin must be connected to GND.
C3 VSEL
Voltage selection input
VSEL = High - VOUT1 = 1.8V, VOUT2 = 1.2V (valid for STA1)
VSEL = Low - VOUT1 = 1.8V, VOUT2 = 1.0V (valid for STA1)
(For other voltage options see
Table 1: STw4141 ordering information
)
D3 VDD Signal supply voltage
A4 VOUT1 Output voltag e 1
PGND
PVDD
MODE/
SYNC
FB1
VLX1
STATE
AUTO
FB2
VLX2
VSEL
VDD
VOUT1
VOUT2
GND
EN
A
B
C
D
1
2
3
4
T_MODE
PGND
PVDD
MODE
/
SYNC
FB1
VLX1
STATE
AUTO
FB2
VLX2
VSEL
VDD
VOUT1
VOUT2
GND
EN
1
2
3
4
A
B
C
D
T_MODE
Top view Bottom view
12 34
A
B
C
D
A
B
C
D
4321
1 STw4141 Pinout STw4141
6/27
B4 VOUT2 Output voltag e 2
C4 GND Signal ground
D4 EN
Enable Input:
EN = Low - Device in shutdown mode,
EN = High - Enable device
This pin must be connected either to VDD or GND.
PGND pin This is the g round pin related to power signal. Thi s p in sh oul d b e c on nec ted to the board groun d
plane by short and wide track or multiply vias to reduce impedance and EMI.
GND pins Thi s is the g roun d pin related to analog signal.
PVDD pin This pin is designed to provide power to the device. This path leads high currents. It should be
wide and short to minimize track impedance to reduce losses and EMI.
VDD pin This pin is designed to provide signal supply voltage to the device. There is no specific
requirement for its related track design.
VLX1/VLX2 pins External coil is connected on those pins. It should be placed as closed as possible to the device
in order minimize resistances which cause looses. These paths lead high currents.
VOUT1 pin3 It is the first output voltage of this device. This path leads high currents. It should be wide and
short to minimize track impedance to reduce losses and EMI.
VOUT2 pin It is the seco nd out put v olta ge of t his d e vic e. This p ath le ads h igh c urrents . It shou ld be wide and
short to minimize track impedance to reduce losses and EMI.
FB1 pin Intended to measure VOUT1 voltage in order to ensure the regulation of this output.
FB2 pin Intended to measure VOUT2 voltage in order to ensure the regulation of this output.
ENABLE pin This is the enable pin of the device. Pulling this pin to ground, forces the device into shutdown
mode. Pulling this pin to VDD enables the device. This pin must be terminated.
MODE/SYNC pin The MODE/SYNC pin is a multipurpose pin which provides mode selection and frequency
synchronization.
The device can also be syn chronized to a n external clock sign al from 600 k H z t o 1 . 5 MHz by the
MODE/SYNC pin. During synchronization, the mode is forced to PWM mode and the top switch
turn-on is synchronized to the rising edge of the external clock.
AUTO pin This pin al low s the de vice to automati cally s witc h from PWM to PFM mo de f ollo wing load on both
2 output s.
STATE pin This output pin informs user in which state the device is working: PWM or PFM mode.
VSEL pin This pin is us ed to redu ce VOUT2 (CORE) output v o ltag e in ord er to r edu ce the proc essor power
consumption when entering into sleep mode.
Table 2. STw4141 pin description
Pin Symbol Description
STw4141 2 Electrical Characte ristics
7/27
2 Electrical Characteristics
2.1 Absolute maximum ratings
Absolute maximum ratings are those values beyond which damage to the device may occur.
Functional operation under these conditions is not implied. All voltages are referenced to GND.
2.2 Thermal data
Table 3. Absolute maximum ratings
Symbol Parameter Value Unit
PVDD Power Supply Voltage -0.3 to 6 V
VDD Signal Supply Voltage -0.3 to 6 V
VEN Enable Input -0.3 to VDD V
VSEL Volta ge Sele ction -0.3 to VDD V
VMODE/SYNC Operating Mode Selection/Synchronization Input -0.3 to VDD V
VAUTO PWM/PFM automati c swit ch sele ction -0.3 to VDD V
VT_MODE Test mode selecti on -0.3 to VDD V
VSTATE Operating mode information -0.3 to VOUT1 V
VOUT1,FB1Output Voltage 1, Feedback 1 -0.3 to 3.3 V
VOUT2, FB2Output Voltage 2, Feedback 2 -0.3 to 3.3 V
VLX1External Inductor Connection Pin 1 -0.3 to VDD V
VLX2External Inductor Connection Pin 2 -0.3 to 3.3 V
TAOperating Temperature Range -40 to 85 °C
TJMaximum Operating Junction Temperature 150 °C
TSTG Storage Temperature Range -65 to 150 °C
Table 4. Thermal data
Symbol Parameter Value Unit
RthJA Thermal Resistance Junction-Ambient
TFBGA 3x3 mm – 16 bumps - 0.5 mm pitch 150 °C/W
2 Electrical Characteristics STw4141
8/27
2.3 DC electrical characteristics
Characteristics measured over recommended operating conditions unless otherwise is noted.
All typical values are referred to TA= 25°C, PVDD = 3.6V, VDD = 3.6V.
Table 5. DC electrical characteristics
Symbol Parameter Test Conditions Min. Typ Max. Unit
PVDD Power supply voltage 2.7 5.5 V
ILIM Peak current limit 1.6 A
VOUT1(1) O utp ut voltag e 1(2) -3 +3 %
VOUT2
Output voltag e 2(2) VSEL = VDD,
MODE/SYNC = VDD -3 +3 %
Output voltag e 2(2) VSEL = GND,
MODE/SYNC = VDD -3 +3 %
IOUT1 Output cur rent 1 200 mA
IOUT2 Output cur rent 2 400 mA
Iq
Quiescent Current
(PWM)
IOUT1 = 0 mA, IOUT2 = 0 mA
EN = VDD, VSEL = VDD
MODE/SYNC = VDD,
AUTO = GND
600 µA
Quiescent Current
(PFM)
IOUT1 = 0 mA, IOUT2 = 0 mA
EN = VDD, VSEL = VDD
MODE/SYNC = GND,
AUTO = GND
90 µA
Shutdown Current
EN = GND,
VSEL = GND
MODE/SYNC = GND,
AUTO = GND
15µA
Enable functions
VENHEnable Threshold High 0.9 V
VENLEnable Threshold Low 0.4 V
Mode/sync functions
VM/SHMODE/SYNC
Threshold High 0.9 V
VM/SLMODE/SYNC
Threshold Low 0.4 V
VSEL functions
VSELHVoltage Selection
Threshold High 0.9 V
VSELLVoltage Selection
Threshold Low 0.4 V
STw4141 2 Electrical Characte ristics
9/27
2.4 Dynamic electrical characteristics
Characteristics measured over recommended operating conditions unless otherwise is noted.
All typical values are referred to TA= 25°C, PVDD = 3.6V, VDD = 3.6V.
Auto functions
VAUTOHVoltage Selection
Threshold High 0.9 V
VAUTOLVoltage Selection
Threshold Low 0.4 V
State functions
VSTATEHVoltage Selection
Threshold High RLmax = 100k, CLmax = 10pF 0.7VOUT1 V
VSTATELVoltage Selection
Threshold Low RLmax = 100k, CLmax = 10pF 0.3 VOUT1 V
1. . This condition must always be valid.
2. Output voltage accuracy excludes line and load transients
Table 6. Dynamic electrical characteristics
Symbol Parameter Test Conditions Min. Typ Max. Unit
fSW Switching frequency 900 kHz
fSYNC Sync mode frequency 600 1500 kHz
Ts Settling time (soft star t) 400 µs
TS2 Settling tim e
VOUT2 (reduced)/VOUT2 VSEL change from GND to VDD 80 µs
Table 5. DC electrical characteristics
Symbol Parameter Test Conditions Min. Typ Max. Unit
VOUT1 VOUT2≥
2 Electrical Characteristics STw4141
10/27
2.5 Soft start
To avoid spikes on battery during STw4141 start-up sequence, a smooth start-up is
implemented. Reference voltage grows up less than 600 µs until it achieves is final target.
Therefore, STw4141 start up is smooth and secure for the overall mobile phone.
Figure 2. Smooth start-up sequence VIN = 3.6V, VOUT1 = 1.8V@ 200mA,
VOUT2 =1.2V@400mA
2.6 Settling time of VOUT2
Figure 3. Settling time of VOUT2, IOUT1 = 200mA, IOUT2 = 400mA
STw4141 2 Electrical Characte ristics
11/27
2.7 Line transients
Figure 4. Line transient, VOUT1 = 1.8V @ 100mA, VOUT2 = 1.2V @ 100mA
2.8 Load transients in AUTO mode
Figure 5. Load transient in AUTO mode VIN = 3.6V, VOUT1 = 1.8V, VOUT2 = 1.2V
2 Electrical Characteristics STw4141
12/27
2.9 Load transients in PWM mode
Figure 6: Load transient in PWM mode, IOUT1 = 1mA to 200mA, IOUT2 = 1mA to 400mA
Load transient related to in-phase switching
VIN = 3.6V, VOUT1 = 1.8V, VOUT2 = 1.2V Load transient output 1 leading output 2
VIN = 3.6V, VOUT1 = 1.8V, VOUT2 = 1.2V
Load transient output 2 leading output 1
VIN = 3.6V, VOUT1 = 1.8V, VOUT2 = 1.2V Load transient related to anti-phase switching
VIN = 3.6V, VOUT1 = 1.8V, VOUT2 = 1.2V
STw4141 2 Electrical Characte ristics
13/27
2.10 Switching between PFM and PWM in FORCED MODE
Figure 7. Switching between PFM to PWM operation modes VIN = 3.6V, IOUT1 = 10mA,
IOUT2 = 10mA
Figure 8. Switching between PWM to PFM operation modes VIN = 3.6V, IOUT1 = 10mA,
IOUT2 = 10mA
2 Electrical Characteristics STw4141
14/27
2.11 Efficiency in PWM
The efficiency of a s witching regulator is equal to the total output power divided by the input.
STw4141 has high efficiency up to 92% (for the 2 outputs). Efficiency curve is flat over the
output current range.
Figure 9. Switching regulator efficiency in PWM mode
1
40
80
120
160
200
240
280
320
360
400
1
20
40
60
80
100
120
140
160
180
200
0
10
20
30
40
50
60
70
80
90
100
Efficiency (%)
IOUT2 (mA)
IOUT1 (mA)
90-100
80-90
70-80
60-70
50-60
40-50
30-40
20-30
10-20
0-10
Efficiency in PWM mode @ VIN=2.7V, TA= 25°C
1
40
80
120
160
200
240
280
320
360
400
1
20
40
60
80
100
120
140
160
180
200
0
10
20
30
40
50
60
70
80
90
100
Efficiency (%)
IOUT2 (mA)
IOUT1 (mA)
90-100
80-90
70-80
60-70
50-60
40-50
30-40
20-30
10-20
0-10
Efficiency in PWM mode @ VIN=3.6V, TA= 25°C
0
10
20
30
40
50
60
70
80
90
100
1 10 100 1000
IOUT1 (mA)
EFFICIENCY (%)
VIN = 2.7V
VOUT1 = 1.8V
VOUT2 = 1.2V
IOUT2 = 0 mA
IOUT2 = 200 mA
IOUT2 = 400 mA
Efficiency vs IOUT1@IOUT2 PW M mode, TA=25°C
0
10
20
30
40
50
60
70
80
90
100
1 10 100 1000
IOUT1 (mA)
EFFICIENCY (%)
VIN = 3.6V
VOUT1 = 1.8V
VOUT2 = 1.2V
IOUT2 = 0 mA
IOUT2 = 200 mA
IOUT2 = 400 mA
Efficiency vs IOUT1@IOUT2 PWM mode , TA=25°C
0
10
20
30
40
50
60
70
80
90
100
1 10 100 1000
IOUT2 (mA)
EFFICIENCY (%)
VIN = 2.7V
VOUT1 = 1.8V
VOUT2 = 1.2V
IOUT1 = 0 mA
IOUT1 = 100 mA
IOUT1 = 200 mA
Efficiency vs IOUT2@IOUT1, PWM mode, TA=25°C
0
10
20
30
40
50
60
70
80
90
100
1 10 100 1000
IOUT2 (mA)
EFFICIENCY (%)
VIN = 3.6V
VOUT1 = 1.8 V
VOUT2 = 1.2 V
IOUT1 = 0 mA
IOUT1 = 100 mA
IOUT1 = 200 mA
Efficiency vs IOUT2@IOUT1, PWM mode, TA=25°C
STw4141 2 Electrical Characte ristics
15/27
2.12 Efficiency in AUTO
The efficiency of a s witching regulator is equal to the total output power divided by the input.
STw4141 has high efficiency up to 92% (both outputs) and always higher than 70% for output
currents higher than 1mA.
Figure 10. Switching regulator efficiency in auto mode
1
40
80
120
160
200
240
280
320
360
400
1
30
60
90
120
150
180 0
10
20
30
40
50
60
70
80
90
100
Efficiency (%
)
IOUT2 (mA)
IOUT1 (mA)
90-100
80-90
70-80
60-70
50-60
40-50
30-40
20-30
10-20
0-10
Efficiency VS output currents IOUT1 and IOUT2, VIN = 2.7V, A UTO mode
4
0
80
120
160
200
240
280
320
360
400
1
40
80
120
160
200
0
10
20
30
40
50
60
70
80
90
100
Efficiency (%)
IOUT2 (mA)
IOUT1 (mA)
90-100
80-90
70-80
60-70
50-60
40-50
30-40
20-30
10-20
0-10
Efficiency VS output currents IOUT1 and IOUT2, VIN = 3.6V, A UTO mode
0
10
20
30
40
50
60
70
80
90
100
1 10 100 1000
I
OUT1
(
mA
)
EFFICIENCY (%)
VIN = 2.7V
VOUT1 = 1.8V
VOUT2 = 1.2V
IOUT2 = 0 mA
IOUT2 = 200 mA
IOUT2 = 400 mA
Efficiency VS IOUT1@IOUT2, A UTO mode, TA = 25°C
0
10
20
30
40
50
60
70
80
90
100
1 10 100 1000
I
OUT1
(
mA
)
EFFICIENCY (%)
VIN = 3.6V
VOUT1 = 1.8V
VOUT2 = 1.2V
IOUT2 = 0 mA
IOUT2 = 200 mA
IOUT2 = 400 mA
Efficiency VS IOUT1@IOUT2, AUTO mode, TA = 25°C
0
10
20
30
40
50
60
70
80
90
100
1 10 100 1000
IOUT2 (mA)
EFFICIENCY (%)
VIN = 2.7V
VOUT1 = 1.8V
VOUT2 = 1.2V
IOUT 1 = 0 mA
IOUT1 = 100 mA
IOUT1 = 200 mA
Efficiency VS IOUT2@IOUT1, A UTO mode, TA = 25°C
0
10
20
30
40
50
60
70
80
90
100
1101001000
IOUT2 (mA)
EFFICIENCY (%)
VIN = 3.6V
VOUT1 = 1.8V
VOUT2 = 1.2V
IOUT1 = 0 mA
IOUT1 = 100 mA
IOUT1 = 200 mA
Efficiency VS IOUT2@IOUT1, A UTO mode, TA = 25°C
2 Electrical Characteristics STw4141
16/27
2.13 Output voltages versus output currents in PWM and PFM
Figure 11. Output voltages versus output currents in PWM and PFM
1.770
1.780
1.790
1.800
1.810
1.820
1.830
1 10 100 1000
IOUT1 (mA)
VOUT1 (V)
VIN = 3.6V
IOUT 2 = 0 mA
IOUT 2 = 200 mA
IOUT2 = 400 mA
VOUT1 VS IOUT1 @ IOUT1 - PWM mode
1.170
1.180
1.190
1.200
1.210
1.220
1.230
1 10 100 1000
IOUT2 (mA)
VOUT2 (V)
VIN = 3.6V
IOUT1 = 0 mA
IOUT1 = 100 mA
IOUT1 = 200 mA
VOUT2 VS IOUT2 @ IOUT1 - PWM mode
1.770
1.780
1.790
1.800
1.810
1.820
1.830
110100
IOUT1 (mA)
VOUT1 (V)
VIN = 3.6V
IOUT2 = 0 mA
IOUT2 = 20 mA
IOUT2 = 40 mA
VOUT1 VS IOUT1 @ IOUT2 - PFM mode
1.170
1.180
1.190
1.200
1.210
1.220
1.230
110100
IOUT2 (mA)
VOUT2 (V)
VIN = 3.6V
IOUT1 = 0 mA
IOUT1 = 10 mA
IOUT1 = 20 mA
VOUT2 VS IOUT2 @ IOUT1 - PFM mode
STw4141 3 Functi ona l Des c ription
17/27
3 Functional Description
3.1 Introduction
The STw4141 is an easy to use, single coil dual outputs step down DC/DC converter optimized
to supply low-voltage to CPUs or DSPs in cell phones and other miniature devices powered by
single cell lithium-ion or 3 cell NiMH/NiCd batteries. It provides two different output voltages
with high efficiency operation in a wide range of output currents. The device offers high DC
voltage regulation accuracy and load transient response to satisfy demanding processor core
supply. The converter is based on voltage mode buck architecture using PWM and PFM
operation modes.
At light load currents, the device can operate in PFM mode to maintain high efficiency over the
entire load current range. Switching between PWM and PFM modes can be done automatically
or can be forced by external pins (AUTO and MODE/SYNC). Externally synchronized or fixed
frequency (internal oscillator) PWM mode offers full output current capability while minimizing
interference to sensitive RF and data acquisition circuits.
3.2 PWM and PFM mode operation
PWM (Pulse Width Modulation) mode is intended for normal load to high load currents. Energy
is delivered to the load with an accurate and defined frequency of 900 kHz.
PFM (Pulse Frequency Modulation) mode is intended for low load currents to maintain high
efficiency conversion.
Forced mode: When AUTO pin is LOW, the operating mode is selectable by the user itself. It
means that system controls the behavior of the STw4141 according to processor needs.
STw4141 is switched from PWM to PFM mode using MODE/SYNC pin (refer to
User mode
details
” section).
Automatic PWM / PFM switch: When AUTO pin is HIGH, the operating mode is directly
controlled by internal digital circuit according to processor needs. The device switches from
PWM to PFM by itself if sum of output currents is lower than approximately 100 mA during at
least 16 clock cycles. The device can be forced to PWM mode connecting MODE/SYNC to
HIGH level. (see
Section 2.8
and
Section 2.9
).
3.3 Current limiter
This protection limits the current flowing through coil. As soon as ILIM is detected, the duty
cycle is terminated and prevents the coil current against rising above peak current limit. There
is no reset of device.
3.4 Short circuit protection
It protects the device against short-circuit at output terminals. When one or both output
voltages are decreased by 0.7 V below their nominal output values the device enters into reset
followed by soft start sequence.
4 Application information STw4141
18/27
3.5 Thermal shutdown protection
Thermal shutdown protects the device against damage due to overheating when maximum
operating junction temperature is exceeded. The device is kept in reset until junction
temperature decreases by 25°C approximately.
4 Application information
4.1 User mode details
The following table describes the different user modes available. Depending on the application
constraints (processor I/O pins available) and expected efficiency, PWM or PFM mode are
forced or automatically controlled by STw4141 internal digital gates.
Table 7. STw4141 available user modes
Mode User mode / pins EN AUTO MODE/
SYNC
OFF Shutdown L X X
FORCED
Forced PFM H L L
Forced PWM H L H
Forced PWM and synchronized external clock H L CLK
AUTO
Auto mode H H L
Forced PWM H H H
Forced PWM and synchronized external clock H H CLK
Table 8. Operating mode information (STATE pin - digital output)
Operation mode State pin voltage level
PFM VOUT1
PWM GND
STw4141 4 Application information
19/27
4.2 Automatic PWM/PFM mode
This user mode is designed to allow STw4141 to switch automatically between PWM and PFM
modes. This feature improv es the application efficiency because STw4141 enters in PFM mode
according to application processor current consumption.
Figure 12. Automatic PWM/PFM switch schematic example
4.3 User selected PWM/PFM mode
STw4141 PWM/PFM mode can also be controlled by the application processor. This feature is
accessible through MODE/SYNC pin state. It is useful to users who want to use STw4141 with
the modem digital processor. Therefore, MODE/SYNC pin is connected to SLEEP mobile
phone signal.
Figure 13. PWM/PFM forced mode schematic example
VIN=2.7V to 5.5V VOUT1
FB1 COUT1
22 µF
6.3 V
VOUT2
FB2 COUT2
22 µF
6.3 V
PVDD
CIN
10 µF
6.3 V
PGND
VDD
EN
VLX1 VLX2
GND
MODE/SYNC
T_MODE
L 4.7 µH
STw4141
VSEL
STATE
B1
D3
D4
C2
C3
C1
A4
D1
B4
D2
B2
A2 A3
A1 B3
C4
APE I/O
APE CORE
GND
APPLICATION
PROCESSOR
MODE_INFO
SLEEP
AUTO
C1
100 nF
C2
100 nF
VIN=2.7V to 5.5V VOUT1
FB1 COUT1
22 µF
6.3 V
VOUT2
FB2 COUT2
22 µF
6.3 V
PVDD
CIN
10 µF
6.3 V
PGND
VDD
EN
VLX1 VLX2
GND
MODE/SYNC
T_MODE
L 4.7 µH
STw4141
VSEL
STATE
B1
D3
D4
C2
C3
C1
A4
D1
B4
D2
B2
A2 A3
A1 B3
C4
APE I/O
APE CORE
GND
APPLICATION
PROCESSOR
MODE_INFO
SLEEP
AUTO
C1
100 nF
C2
100 nF
VIN=2.7V to 5.5V VOUT1
FB1 COUT1
22 µF
6.3 V
VOUT2
FB2 COUT2
22 µF
6.3 V
PVDD
CIN
10 µF
6.3 V
PGND
VDD
EN
VLX1 VLX2
GND
MODE/SYNC
T_MODE
L 4.7 µH
STw4141
VSEL
STATE
B1
D3
D4
C2
C3
C1
A4
D1
B4
D2
B2
A2 A3
A1 B3
C4
APE I/O
APE CORE
GND
APPLICATION
PROCESSOR
MODE_INFO
SLEEP
AUTO
PWR_EN
C1
100 nF
C2
100 nF
VIN=2.7V to 5.5V VOUT1
FB1 COUT1
22 µF
6.3 V
VOUT2
FB2 COUT2
22 µF
6.3 V
PVDD
CIN
10 µF
6.3 V
PGND
VDD
EN
VLX1 VLX2
GND
MODE/SYNC
T_MODE
L 4.7 µH
STw4141
VSEL
STATE
B1
D3
D4
C2
C3
C1
A4
D1
B4
D2
B2
A2 A3
A1 B3
C4
APE I/O
APE CORE
GND
APPLICATION
PROCESSOR
MODE_INFO
SLEEP
AUTO
PWR_EN
C1
100 nF
C2
100 nF
4 Application information STw4141
20/27
4.4 External clock synchronization
Figure 14. Application using external clock synchronization
4.5 Checking Transient response versus external components
The regulator loop response can be checked by looking at the load transient response.
Switching regulators take several cycles to respond to a step in load current. When a load step
occurs, VOUT is immediately shifted by an amount equal to ILOAD x ESR, where ESR is the
equivalent series resistance of COUT. ILOAD also begins to charge or discharge COUT
generating a feedback error signal used by the regulator to return VOUT to its steady-state
value. In order to improve the transient response, it is better to use two 10 µF ceramic
capacitors on each output to reduce ESR.
4.6 Bill of Material
4.6.1 Inductor selection
The choice of which inductor to use depends on the price and size versus performance
required with the STw4141 application.
Table 9
shows some typical surface mount inductors
that work well in STw4141 applications.
Table 9. Bill of material: inductor selection
Part number Supplier Value
(µH)
DCR
( max)
Max DC
current (mA)
Size (mm)
W x L x H
VFL4012A-4R7M1R1 TDK 4.7 0.14 1100 3.5 x 3.7 x 1.2
VFL3012A-4R7MR74 TDK 4.7 0.16 740 2.6 x 2.8 x 1.2
744031004 WUERTH 4.7 0.085 900 3.8 x 3.8 x 1.8
VIN=2.7V to 5.5V VOUT1
FB1 COUT1
22 µF
6.3 V
VOUT2
FB2 COUT2
22 µF
6.3 V
PVDD
CIN
10 µF
6.3 V
PGND
VDD
EN
VLX1 VLX2
GND
MODE/SYNC
T_MODE
L 4.7 µH
STw4141
VSEL
STATE
B1
D3
D4
C2
C3
C1
A4
D1
B4
D2
B2
A2 A3
A1 B3
C4
APE I/O
APE CORE
GND
APPLICATION
PROCESSOR
C1
100 nF
C2
100 nF
MODE_INFO
CLK
SLEEP
AUTO
VIN=2.7V to 5.5V VOUT1
FB1 COUT1
22 µF
6.3 V
VOUT2
FB2 COUT2
22 µF
6.3 V
PVDD
CIN
10 µF
6.3 V
PGND
VDD
EN
VLX1 VLX2
GND
MODE/SYNC
T_MODE
L 4.7 µH
STw4141
VSEL
STATE
B1
D3
D4
C2
C3
C1
A4
D1
B4
D2
B2
A2 A3
A1 B3
C4
APE I/O
APE CORE
GND
APPLICATION
PROCESSOR
C1
100 nF
C2
100 nF
MODE_INFO
CLK
SLEEP
AUTO
STw4141 4 Application information
21/27
4.6.2 Input capacitor (CIN selection)
Input capacitor of 10 µF ceramic low ESR capacitor should be used to reduce switching losses.
It should be placed as close as possible to supply pins VDD and PVDD. The connection traces
should be wide and short to minimize impedance.
4.6.3 Output capacitors (COUT selection)
The selection of COUT is driven by the required ESR to minimize voltage ripple and load step
transients. There are two possibilities for output capacitors: either a 22 µF is connected to
ground or two 10 µF ceramic are used to reduce ESR and switching losses. The capacitor
should be placed as close as possible to V OUTx pins. The connection traces should be wide and
short to minimize impedance.
4.6.4 Capacitors selection
4.7 PCB layout considerations
The Printed Circuit Board layout must include the following consideration:
Current paths carrying high currents (bold lines in
Figure 15
) must be wide and short to
minimize impedance in order to reduce looses and EMI.
Small currents flow through voltage paths. No specific care is requested about voltage paths
but it is recommended to f ollow the general rules for PCB routing to reduce influence of external
and internal interferences.
Table 10. Bill of Material: capacitor selection
Component Supplier Part number Value Case size
CIN
TDK C1608X5R0J106MT 10 µF, 6.3V 0603
TDK C2012X5R0J106MT 10 µF, 6.3V 0805
TAIYO YUDEN JMK212BJ106MG-T 10 µF, 6.3V 0805
COUT1, COUT2
TDK
C1608X5R0J106MT 2 x 10 µF, 6.3V 2 x 0603
C2012X5R0J106MT 2 x 10 µF, 6.3V 2 x 0805
C2012X5R0J226MT 22 µF, 6.3V 0805
TAIYO YUDEN JMK212BJ106MG-T 2 x 10 µF, 6.3V 2 x 0805
JMK212BJ226MG-T 22 µF, 6.3V 0805
4 Application information STw4141
22/27
Figure 15. Board layout track length and width
4.7.1 PCB layout
Figure 16
and
Figure 17
show the PCB lay out. All components are on the top side of the board.
Figure 16. Demoboard top layer Figure 17. Demoboard assembled with 2x10µF
output capacitors
VOUT1
FB1
VOUT1=1.8V
COUT1
22 µF
6.3 V
VOUT2
FB2
VOUT2=1.0V/1.2V
COUT2
22 µF
6.3 V
PVDD
VIN=2.7V to 5 .5V
CIN
10 µF
6.3 V
PGND
VDD
EN
VLX1 VLX2
GND
MODE/SYNC
T_MODE
AUTO
L 4.7 µH
STw4141
VSEL
STATE
B1
D3
D4
C2
C3
C1
A4
D1
B4
D2
B2
A2 A3
A1 B3
C4
HIGH CURRENT PATH
VOUT1
FB1
VOUT1=1.8V
COUT1
22 µF
6.3 V
VOUT2
FB2
VOUT2=1.0V/1.2V
COUT2
22 µF
6.3 V
PVDD
VIN=2.7V to 5 .5V
CIN
10 µF
6.3 V
PGND
VDD
EN
VLX1 VLX2
GND
MODE/SYNC
T_MODE
AUTO
L 4.7 µH
STw4141
VSEL
STATE
B1
D3
D4
C2
C3
C1
A4
D1
B4
D2
B2
A2 A3
A1 B3
C4
HIGH CURRENT PATH
STw4141 4 Application information
23/27
4.7.2 TFBGA16 internal bumps access
Pad centers are at 500 µm distance. Pad diameter is 275 µm. The distance between two
adjacent pad edges is only 225 µm. We recommend a distance for lead-out signals from the
center of pad matrix by 75 µm wide trace. Isolation distance in this case is 75 µm (see
Figure 18
and
Figure 19
).
Figure 18. TFBGA16 ball pad spacing and track parameters to internal pads
Figure 19. PCB routing example using TFBGA16
Grid dot distance : with
A = 500µm
B = 275µm
C = 75 µm
5 Package Outline and Mechanical Data STw4141
24/27
5 Package Outline and Mechanical Data
Note: 1 Max mounted height is 1.12 mm. Based on a 0.28 mm ball pad diameter.
Solder paste is 0.15 mm thickness and 0.28 mm diameter.
2 TFBGA stands for Thin Profile Fine Pitch Ball Grid Array.
Thin profile: The total profile height (DIm A) is measured from the seating plane to the top of the
component.
A = 1.01 to 1.20 mm
Fine pitch < 1.00 mm pitch.
3 The tolerance of position that controls the location of the pattern of balls with respect to datums
A and B.
For each ball there is a cylindral tolerance zone eee perpendicular to datum C and located on
true position with respect to datums A and B as defined by e. The axis perpendicular to datum
C of each ball must lie within this tolerance zone.
4 The tolerance of position that controls the location of the balls within the matrix with respect to
each other. For each ball there is a cylindrical tolerance zone perpendicular to datum C and
located on true position as defined by e. The axis perpendicular to datum C of each ball must
lie within the tol erance zone.
Each tolerance zone fff in the array is contained entirely in the respective above eee zone
above.
The axis of each ball must be simultaneously in both tolerance zones.
5 Leadfree package according to JEDEC JESD-020-C
Table 11: TFBGA 3x3x1.20 16 F4x4 0.50. Package code: L0 - JEDEC/EAIJ reference
number: N/A
Ref Min. Typ. Max.
A 1.01 1.20 (
Note 1
)
A1 0.15
A2 0.82
b 0.25 0.30 0.35
D 2.85 3.00 3.15
D1 1.50
E 2.85 3.00 3.15
E1 1.50
e0.50
ddd 0.85 0.08
eee 0.15
fff 0.05
STw4141 5 Package Outline and Mechanical Data
25/27
Figure 20. TFBGA 3x3x1.20 16 F4x4 0.50
6 Revision history STw4141
26/27
6 Revision history
Date Revision Changes
8-Dec-2005 1Initial release
STw4141
27/27
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of us e of such information no r for any infringement of patent s or other rights of third p arties which ma y result from its u se. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This pub lication supersedes and replaces all info rmation previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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